dce_i2c_hw.c

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25#include "resource.h"
 26#include "dce_i2c.h"
 27#include "dce_i2c_hw.h"
 28#include "reg_helper.h"
 29#include "include/gpio_service_interface.h"
 30
 31#define CTX \
 32	dce_i2c_hw->ctx
 33#define REG(reg)\
 34	dce_i2c_hw->regs->reg
 35
 36#undef FN
 37#define FN(reg_name, field_name) \
 38	dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
 39
 40static void execute_transaction(
 41	struct dce_i2c_hw *dce_i2c_hw)
 42{
 43	REG_UPDATE_N(SETUP, 5,
 44		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
 45		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
 46		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
 47		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
 48		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
 49
 50
 51	REG_UPDATE_5(DC_I2C_CONTROL,
 52		     DC_I2C_SOFT_RESET, 0,
 53		     DC_I2C_SW_STATUS_RESET, 0,
 54		     DC_I2C_SEND_RESET, 0,
 55		     DC_I2C_GO, 0,
 56		     DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1);
 57
 58	/* start I2C transfer */
 59	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
 60
 61	/* all transactions were executed and HW buffer became empty
 62	 * (even though it actually happens when status becomes DONE)
 63	 */
 64	dce_i2c_hw->transaction_count = 0;
 65	dce_i2c_hw->buffer_used_bytes = 0;
 66}
 67
 68static enum i2c_channel_operation_result get_channel_status(
 69	struct dce_i2c_hw *dce_i2c_hw,
 70	uint8_t *returned_bytes)
 71{
 72	uint32_t i2c_sw_status = 0;
 73	uint32_t value =
 74		REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
 75	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
 76		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
 77	else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
 78		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
 79	else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
 80		return I2C_CHANNEL_OPERATION_TIMEOUT;
 81	else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
 82		return I2C_CHANNEL_OPERATION_FAILED;
 83	else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
 84		return I2C_CHANNEL_OPERATION_SUCCEEDED;
 85
 86	/*
 87	 * this is the case when HW used for communication, I2C_SW_STATUS
 88	 * could be zero
 89	 */
 90	return I2C_CHANNEL_OPERATION_SUCCEEDED;
 91}
 92
 93static uint32_t get_hw_buffer_available_size(
 94	const struct dce_i2c_hw *dce_i2c_hw)
 95{
 96	return dce_i2c_hw->buffer_size -
 97			dce_i2c_hw->buffer_used_bytes;
 98}
 99
100static void process_channel_reply(
101	struct dce_i2c_hw *dce_i2c_hw,
102	struct i2c_payload *reply)
103{
104	uint32_t length = reply->length;
105	uint8_t *buffer = reply->data;
106
107	REG_SET_3(DC_I2C_DATA, 0,
108		 DC_I2C_INDEX, dce_i2c_hw->buffer_used_write,
109		 DC_I2C_DATA_RW, 1,
110		 DC_I2C_INDEX_WRITE, 1);
111
112	while (length) {
113		/* after reading the status,
114		 * if the I2C operation executed successfully
115		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
116		 * should read data bytes from I2C circular data buffer
117		 */
118
119		uint32_t i2c_data;
120
121		REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
122		*buffer++ = i2c_data;
123
124		--length;
125	}
126}
127
128static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
129{
130	unsigned int arbitrate;
131	unsigned int i2c_hw_status;
132
133	REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
134	if (i2c_hw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW)
135		return false;
136
137	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
138	if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
139		return false;
140
141	return true;
142}
143
144static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
145{
146	uint32_t i2c_sw_status = 0;
147
148	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
149	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
150		return false;
151
152	if (is_engine_available(dce_i2c_hw))
153		return false;
154
155	return true;
156}
157
158static bool process_transaction(
159	struct dce_i2c_hw *dce_i2c_hw,
160	struct i2c_request_transaction_data *request)
161{
162	uint32_t length = request->length;
163	uint8_t *buffer = request->data;
164
165	bool last_transaction = false;
166	uint32_t value = 0;
167
168	if (is_hw_busy(dce_i2c_hw)) {
169		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
170		return false;
171	}
172
173	last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
174			(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
175			(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
176
177
178	switch (dce_i2c_hw->transaction_count) {
179	case 0:
180		REG_UPDATE_5(DC_I2C_TRANSACTION0,
181				 DC_I2C_STOP_ON_NACK0, 1,
182				 DC_I2C_START0, 1,
183				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
184				 DC_I2C_COUNT0, length,
185				 DC_I2C_STOP0, last_transaction ? 1 : 0);
186		break;
187	case 1:
188		REG_UPDATE_5(DC_I2C_TRANSACTION1,
189				 DC_I2C_STOP_ON_NACK0, 1,
190				 DC_I2C_START0, 1,
191				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
192				 DC_I2C_COUNT0, length,
193				 DC_I2C_STOP0, last_transaction ? 1 : 0);
194		break;
195	case 2:
196		REG_UPDATE_5(DC_I2C_TRANSACTION2,
197				 DC_I2C_STOP_ON_NACK0, 1,
198				 DC_I2C_START0, 1,
199				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
200				 DC_I2C_COUNT0, length,
201				 DC_I2C_STOP0, last_transaction ? 1 : 0);
202		break;
203	case 3:
204		REG_UPDATE_5(DC_I2C_TRANSACTION3,
205				 DC_I2C_STOP_ON_NACK0, 1,
206				 DC_I2C_START0, 1,
207				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
208				 DC_I2C_COUNT0, length,
209				 DC_I2C_STOP0, last_transaction ? 1 : 0);
210		break;
211	default:
212		/* TODO Warning ? */
213		break;
214	}
215
216	/* Write the I2C address and I2C data
217	 * into the hardware circular buffer, one byte per entry.
218	 * As an example, the 7-bit I2C slave address for CRT monitor
219	 * for reading DDC/EDID information is 0b1010001.
220	 * For an I2C send operation, the LSB must be programmed to 0;
221	 * for I2C receive operation, the LSB must be programmed to 1.
222	 */
223	if (dce_i2c_hw->transaction_count == 0) {
224		value = REG_SET_4(DC_I2C_DATA, 0,
225				  DC_I2C_DATA_RW, false,
226				  DC_I2C_DATA, request->address,
227				  DC_I2C_INDEX, 0,
228				  DC_I2C_INDEX_WRITE, 1);
229		dce_i2c_hw->buffer_used_write = 0;
230	} else
231		value = REG_SET_2(DC_I2C_DATA, 0,
232			  DC_I2C_DATA_RW, false,
233			  DC_I2C_DATA, request->address);
234
235	dce_i2c_hw->buffer_used_write++;
236
237	if (!(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)) {
238		while (length) {
239			REG_SET_2(DC_I2C_DATA, value,
240				  DC_I2C_INDEX_WRITE, 0,
241				  DC_I2C_DATA, *buffer++);
242			dce_i2c_hw->buffer_used_write++;
243			--length;
244		}
245	}
246
247	++dce_i2c_hw->transaction_count;
248	dce_i2c_hw->buffer_used_bytes += length + 1;
249
250	return last_transaction;
251}
252
253static inline void reset_hw_engine(struct dce_i2c_hw *dce_i2c_hw)
254{
255	REG_UPDATE_2(DC_I2C_CONTROL,
256		     DC_I2C_SW_STATUS_RESET, 1,
257		     DC_I2C_SW_STATUS_RESET, 1);
258}
259
260static void set_speed(
261	struct dce_i2c_hw *dce_i2c_hw,
262	uint32_t speed)
263{
264	uint32_t xtal_ref_div = 0, ref_base_div = 0;
265	uint32_t prescale = 0;
266	uint32_t i2c_ref_clock = 0;
267
268	if (speed == 0)
269		return;
270
271	REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
272		XTAL_REF_DIV, &xtal_ref_div);
273
274	if (xtal_ref_div == 0)
275		xtal_ref_div = 2;
276
277	if (ref_base_div == 0)
278		i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2);
279	else
280		i2c_ref_clock = ref_base_div * 1000;
281
282	prescale = (i2c_ref_clock / xtal_ref_div) / speed;
283
284	if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
285		REG_UPDATE_N(SPEED, 3,
286			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
287			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
288			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
289	else
290		REG_UPDATE_N(SPEED, 2,
291			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
292			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
293}
294
295static bool acquire_engine(struct dce_i2c_hw *dce_i2c_hw)
296{
297	uint32_t arbitrate = 0;
298
299	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
300	switch (arbitrate) {
301	case DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW:
302		return true;
303	case DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW:
304		return false;
305	case DC_I2C_STATUS__DC_I2C_STATUS_IDLE:
306	default:
307		break;
308	}
309
310	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, true);
311	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
312	if (arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
313		return false;
314
315	return true;
316}
317
318static bool setup_engine(
319	struct dce_i2c_hw *dce_i2c_hw)
320{
321	// Deassert soft reset to unblock I2C engine registers
322	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, false);
323
324	uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
325	uint32_t  reset_length = 0;
326
327	if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
328		if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
329			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
330			REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
331		}
332	}
333
334	if (dce_i2c_hw->masks->DC_I2C_DDC1_CLK_EN)
335		REG_UPDATE_N(SETUP, 1,
336			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN), 1);
337
338	if (!acquire_engine(dce_i2c_hw))
339		return false;
340
341	/*set SW requested I2c speed to default, if API calls in it will be override later*/
342	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
343
344	if (dce_i2c_hw->setup_limit != 0)
345		i2c_setup_limit = dce_i2c_hw->setup_limit;
346
347	/* Program pin select */
348	REG_UPDATE_5(DC_I2C_CONTROL,
349		     DC_I2C_GO, 0,
350		     DC_I2C_SEND_RESET, 0,
351		     DC_I2C_SW_STATUS_RESET, 1,
352		     DC_I2C_TRANSACTION_COUNT, 0,
353		     DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
354
355	/* Program time limit */
356	if (dce_i2c_hw->send_reset_length == 0) {
357		/*pre-dcn*/
358		REG_UPDATE_N(SETUP, 2,
359			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
360			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
361	} else {
362		reset_length = dce_i2c_hw->send_reset_length;
363		REG_UPDATE_N(SETUP, 3,
364			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
365			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
366			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
367	}
368	/* Program HW priority
369	 * set to High - interrupt software I2C at any time
370	 * Enable restart of SW I2C that was interrupted by HW
371	 * disable queuing of software while I2C is in use by HW
372	 */
373	REG_UPDATE(DC_I2C_ARBITRATION,
374			DC_I2C_NO_QUEUED_SW_GO, 0);
375
376	return true;
377}
378
379/**
380 * cntl_stuck_hw_workaround - Workaround for I2C engine stuck state
381 * @dce_i2c_hw: Pointer to dce_i2c_hw structure
382 *
383 * If we boot without an HDMI display, the I2C engine does not get initialized
384 * correctly. One of its symptoms is that SW_USE_I2C does not get cleared after
385 * acquire. After setting SW_DONE_USING_I2C on release, the engine gets
386 * immediately reacquired by SW, preventing DMUB from using it.
387 *
388 * This function checks the I2C arbitration status and applies a release
389 * workaround if necessary.
390 */
391static void cntl_stuck_hw_workaround(struct dce_i2c_hw *dce_i2c_hw)
392{
393	uint32_t arbitrate = 0;
394
395	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
396	if (arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
397		return;
398
399	// Still acquired after release, release again as a workaround
400	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);
401	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
402	ASSERT(arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW);
403}
404
405static void release_engine(
406	struct dce_i2c_hw *dce_i2c_hw)
407{
408	bool safe_to_reset;
409
410
411	/* Reset HW engine */
412	{
413		uint32_t i2c_sw_status = 0;
414
415		REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
416		/* if used by SW, safe to reset */
417		safe_to_reset = (i2c_sw_status == 1);
418	}
419
420	if (safe_to_reset)
421		REG_UPDATE_2(DC_I2C_CONTROL,
422			     DC_I2C_SOFT_RESET, 1,
423			     DC_I2C_SW_STATUS_RESET, 1);
424	else
425		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
426	/* HW I2c engine - clock gating feature */
427	if (!dce_i2c_hw->engine_keep_power_up_count)
428		REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
429
430	/*for HW HDCP Ri polling failure w/a test*/
431	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);
432	// Release I2C engine so it can be used by HW or DMCU, automatically clears SW_USE_I2C
433	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);
434	cntl_stuck_hw_workaround(dce_i2c_hw);
435
436	if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
437		if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL)
438			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
439	}
440}
441
442struct dce_i2c_hw *acquire_i2c_hw_engine(
443	struct resource_pool *pool,
444	struct ddc *ddc)
445{
446	uint32_t counter = 0;
447	enum gpio_result result;
448	struct dce_i2c_hw *dce_i2c_hw = NULL;
449
450	if (!ddc)
451		return NULL;
452
453	if (ddc->hw_info.hw_supported) {
454		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
455
456		if (line < pool->res_cap->num_ddc)
457			dce_i2c_hw = pool->hw_i2cs[line];
458	}
459
460	if (!dce_i2c_hw)
461		return NULL;
462
463	if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw))
464		return NULL;
465
466	do {
467		result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
468			GPIO_DDC_CONFIG_TYPE_MODE_I2C);
469
470		if (result == GPIO_RESULT_OK)
471			break;
472
473		/* i2c_engine is busy by VBios, lets wait and retry */
474
475		udelay(10);
476
477		++counter;
478	} while (counter < 2);
479
480	if (result != GPIO_RESULT_OK)
481		return NULL;
482
483	dce_i2c_hw->ddc = ddc;
484
485	if (!setup_engine(dce_i2c_hw)) {
486		release_engine(dce_i2c_hw);
487		return NULL;
488	}
489
490	pool->i2c_hw_buffer_in_use = true;
491	return dce_i2c_hw;
492}
493
494static enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result(struct dce_i2c_hw *dce_i2c_hw,
495										    uint32_t timeout,
496										    enum i2c_channel_operation_result expected_result)
497{
498	enum i2c_channel_operation_result result;
499	uint32_t i = 0;
500
501	if (!timeout)
502		return I2C_CHANNEL_OPERATION_SUCCEEDED;
503
504	do {
505
506		result = get_channel_status(
507				dce_i2c_hw, NULL);
508
509		if (result != expected_result)
510			break;
511
512		udelay(1);
513
514		++i;
515	} while (i < timeout);
516	return result;
517}
518
519static void submit_channel_request_hw(
520	struct dce_i2c_hw *dce_i2c_hw,
521	struct i2c_request_transaction_data *request)
522{
523	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
524
525	if (!process_transaction(dce_i2c_hw, request))
526		return;
527
528	if (is_hw_busy(dce_i2c_hw)) {
529		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
530		return;
531	}
532	reset_hw_engine(dce_i2c_hw);
533
534	execute_transaction(dce_i2c_hw);
535
536
537}
538
539static uint32_t get_transaction_timeout_hw(
540	const struct dce_i2c_hw *dce_i2c_hw,
541	uint32_t length,
542	uint32_t speed)
543{
544	uint32_t period_timeout;
545	uint32_t num_of_clock_stretches;
546
547	if (!speed)
548		return 0;
549
550	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
551
552	num_of_clock_stretches = 1 + (length << 3) + 1;
553	num_of_clock_stretches +=
554		(dce_i2c_hw->buffer_used_bytes << 3) +
555		(dce_i2c_hw->transaction_count << 1);
556
557	return period_timeout * num_of_clock_stretches;
558}
559
560static bool dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw *dce_i2c_hw,
561					     struct i2c_payload *payload,
562					     bool middle_of_transaction,
563					     uint32_t speed)
564{
565
566	struct i2c_request_transaction_data request;
567
568	uint32_t transaction_timeout;
569
570	enum i2c_channel_operation_result operation_result;
571
572	bool result = false;
573
574	/* We need following:
575	 * transaction length will not exceed
576	 * the number of free bytes in HW buffer (minus one for address)
577	 */
578
579	if (payload->length >=
580			get_hw_buffer_available_size(dce_i2c_hw)) {
581		return false;
582	}
583
584	if (!payload->write)
585		request.action = middle_of_transaction ?
586			DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT :
587			DCE_I2C_TRANSACTION_ACTION_I2C_READ;
588	else
589		request.action = middle_of_transaction ?
590			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT :
591			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;
592
593
594	request.address = (uint8_t) ((payload->address << 1) | (payload->write ? 0 : 1));
595	request.length = payload->length;
596	request.data = payload->data;
597
598	/* obtain timeout value before submitting request */
599
600	transaction_timeout = get_transaction_timeout_hw(
601		dce_i2c_hw, payload->length + 1, speed);
602
603	submit_channel_request_hw(
604		dce_i2c_hw, &request);
605
606	if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
607		(request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY))
608		return false;
609
610	/* wait until transaction proceed */
611
612	operation_result = dce_i2c_hw_engine_wait_on_operation_result(
613		dce_i2c_hw,
614		transaction_timeout,
615		I2C_CHANNEL_OPERATION_ENGINE_BUSY);
616
617	/* update transaction status */
618
619	if (operation_result == I2C_CHANNEL_OPERATION_SUCCEEDED)
620		result = true;
621
622	if (result && (!payload->write))
623		process_channel_reply(dce_i2c_hw, payload);
624
625	return result;
626}
627
628bool dce_i2c_submit_command_hw(
629	struct resource_pool *pool,
630	struct ddc *ddc,
631	struct i2c_command *cmd,
632	struct dce_i2c_hw *dce_i2c_hw)
633{
634	uint8_t index_of_payload = 0;
635	bool result;
636
637	set_speed(dce_i2c_hw, cmd->speed);
638
639	result = true;
640
641	while (index_of_payload < cmd->number_of_payloads) {
642		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
643
644		struct i2c_payload *payload = cmd->payloads + index_of_payload;
645
646		if (!dce_i2c_hw_engine_submit_payload(
647				dce_i2c_hw, payload, mot, cmd->speed)) {
648			result = false;
649			break;
650		}
651
652		++index_of_payload;
653	}
654
655	pool->i2c_hw_buffer_in_use = false;
656
657	release_engine(dce_i2c_hw);
658	dal_ddc_close(dce_i2c_hw->ddc);
659
660	dce_i2c_hw->ddc = NULL;
661
662	return result;
663}
664
665void dce_i2c_hw_construct(
666	struct dce_i2c_hw *dce_i2c_hw,
667	struct dc_context *ctx,
668	uint32_t engine_id,
669	const struct dce_i2c_registers *regs,
670	const struct dce_i2c_shift *shifts,
671	const struct dce_i2c_mask *masks)
672{
673	dce_i2c_hw->ctx = ctx;
674	dce_i2c_hw->engine_id = engine_id;
675	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
676	dce_i2c_hw->regs = regs;
677	dce_i2c_hw->shifts = shifts;
678	dce_i2c_hw->masks = masks;
679	dce_i2c_hw->buffer_used_bytes = 0;
680	dce_i2c_hw->transaction_count = 0;
681	dce_i2c_hw->engine_keep_power_up_count = 1;
682	dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED;
683	dce_i2c_hw->send_reset_length = 0;
684	dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
685	dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE;
686}
687
688void dce100_i2c_hw_construct(
689	struct dce_i2c_hw *dce_i2c_hw,
690	struct dc_context *ctx,
691	uint32_t engine_id,
692	const struct dce_i2c_registers *regs,
693	const struct dce_i2c_shift *shifts,
694	const struct dce_i2c_mask *masks)
695{
696	dce_i2c_hw_construct(dce_i2c_hw,
697			ctx,
698			engine_id,
699			regs,
700			shifts,
701			masks);
702	dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE100;
703}
704
705void dce112_i2c_hw_construct(
706	struct dce_i2c_hw *dce_i2c_hw,
707	struct dc_context *ctx,
708	uint32_t engine_id,
709	const struct dce_i2c_registers *regs,
710	const struct dce_i2c_shift *shifts,
711	const struct dce_i2c_mask *masks)
712{
713	dce100_i2c_hw_construct(dce_i2c_hw,
714			ctx,
715			engine_id,
716			regs,
717			shifts,
718			masks);
719	dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
720}
721
722void dcn1_i2c_hw_construct(
723	struct dce_i2c_hw *dce_i2c_hw,
724	struct dc_context *ctx,
725	uint32_t engine_id,
726	const struct dce_i2c_registers *regs,
727	const struct dce_i2c_shift *shifts,
728	const struct dce_i2c_mask *masks)
729{
730	dce112_i2c_hw_construct(dce_i2c_hw,
731			ctx,
732			engine_id,
733			regs,
734			shifts,
735			masks);
736	dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
737}
738
739void dcn2_i2c_hw_construct(
740	struct dce_i2c_hw *dce_i2c_hw,
741	struct dc_context *ctx,
742	uint32_t engine_id,
743	const struct dce_i2c_registers *regs,
744	const struct dce_i2c_shift *shifts,
745	const struct dce_i2c_mask *masks)
746{
747	dcn1_i2c_hw_construct(dce_i2c_hw,
748			ctx,
749			engine_id,
750			regs,
751			shifts,
752			masks);
753	dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9;
754	if (ctx->dc->debug.scl_reset_length10)
755		dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
756}