dce_clock_source.c

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27
  28
  29#include "dc_types.h"
  30#include "core_types.h"
  31
  32#include "include/grph_object_id.h"
  33#include "include/logger_interface.h"
  34
  35#include "dce_clock_source.h"
  36#include "clk_mgr.h"
  37#include "dccg.h"
  38
  39#include "reg_helper.h"
  40
  41#define REG(reg)\
  42	(clk_src->regs->reg)
  43
  44#define CTX \
  45	clk_src->base.ctx
  46
  47#define DC_LOGGER \
  48	calc_pll_cs->ctx->logger
  49#define DC_LOGGER_INIT() \
  50	struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll
  51
  52#undef FN
  53#define FN(reg_name, field_name) \
  54	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
  55
  56#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
  57#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
  58#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
  59
  60#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
  61
  62static const struct spread_spectrum_data *get_ss_data_entry(
  63		struct dce110_clk_src *clk_src,
  64		enum signal_type signal,
  65		uint32_t pix_clk_khz)
  66{
  67
  68	uint32_t entrys_num;
  69	uint32_t i;
  70	struct spread_spectrum_data *ss_parm = NULL;
  71	struct spread_spectrum_data *ret = NULL;
  72
  73	switch (signal) {
  74	case SIGNAL_TYPE_DVI_SINGLE_LINK:
  75	case SIGNAL_TYPE_DVI_DUAL_LINK:
  76		ss_parm = clk_src->dvi_ss_params;
  77		entrys_num = clk_src->dvi_ss_params_cnt;
  78		break;
  79
  80	case SIGNAL_TYPE_HDMI_TYPE_A:
  81		ss_parm = clk_src->hdmi_ss_params;
  82		entrys_num = clk_src->hdmi_ss_params_cnt;
  83		break;
  84
  85	case SIGNAL_TYPE_LVDS:
  86		ss_parm = clk_src->lvds_ss_params;
  87		entrys_num = clk_src->lvds_ss_params_cnt;
  88		break;
  89
  90	case SIGNAL_TYPE_DISPLAY_PORT:
  91	case SIGNAL_TYPE_DISPLAY_PORT_MST:
  92	case SIGNAL_TYPE_EDP:
  93	case SIGNAL_TYPE_VIRTUAL:
  94		ss_parm = clk_src->dp_ss_params;
  95		entrys_num = clk_src->dp_ss_params_cnt;
  96		break;
  97
  98	default:
  99		ss_parm = NULL;
 100		entrys_num = 0;
 101		break;
 102	}
 103
 104	if (ss_parm == NULL)
 105		return ret;
 106
 107	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
 108		if (ss_parm->freq_range_khz >= pix_clk_khz) {
 109			ret = ss_parm;
 110			break;
 111		}
 112	}
 113
 114	return ret;
 115}
 116
 117/**
 118 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
 119 *                                          feedback dividers values
 120 *
 121 * @calc_pll_cs:	    Pointer to clock source information
 122 * @target_pix_clk_100hz:   Desired frequency in 100 Hz
 123 * @ref_divider:            Reference divider (already known)
 124 * @post_divider:           Post Divider (already known)
 125 * @feedback_divider_param: Pointer where to store
 126 *			    calculated feedback divider value
 127 * @fract_feedback_divider_param: Pointer where to store
 128 *			    calculated fract feedback divider value
 129 *
 130 * return:
 131 * It fills the locations pointed by feedback_divider_param
 132 *					and fract_feedback_divider_param
 133 * It returns	- true if feedback divider not 0
 134 *		- false should never happen)
 135 */
 136static bool calculate_fb_and_fractional_fb_divider(
 137		struct calc_pll_clock_source *calc_pll_cs,
 138		uint32_t target_pix_clk_100hz,
 139		uint32_t ref_divider,
 140		uint32_t post_divider,
 141		uint32_t *feedback_divider_param,
 142		uint32_t *fract_feedback_divider_param)
 143{
 144	uint64_t feedback_divider;
 145
 146	feedback_divider =
 147		(uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
 148	feedback_divider *= 10;
 149	/* additional factor, since we divide by 10 afterwards */
 150	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
 151	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
 152
 153/*Round to the number of precision
 154 * The following code replace the old code (ullfeedbackDivider + 5)/10
 155 * for example if the difference between the number
 156 * of fractional feedback decimal point and the fractional FB Divider precision
 157 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
 158
 159	feedback_divider += 5ULL *
 160			    calc_pll_cs->fract_fb_divider_precision_factor;
 161	feedback_divider =
 162		div_u64(feedback_divider,
 163			calc_pll_cs->fract_fb_divider_precision_factor * 10);
 164	feedback_divider *= (uint64_t)
 165			(calc_pll_cs->fract_fb_divider_precision_factor);
 166
 167	*feedback_divider_param =
 168		div_u64_rem(
 169			feedback_divider,
 170			calc_pll_cs->fract_fb_divider_factor,
 171			fract_feedback_divider_param);
 172
 173	if (*feedback_divider_param != 0)
 174		return true;
 175	return false;
 176}
 177
 178/**
 179 * calc_fb_divider_checking_tolerance - Calculates Feedback and
 180 *                                      Fractional Feedback divider values
 181 *		                        for passed Reference and Post divider,
 182 *                                      checking for tolerance.
 183 * @calc_pll_cs:	Pointer to clock source information
 184 * @pll_settings:	Pointer to PLL settings
 185 * @ref_divider:	Reference divider (already known)
 186 * @post_divider:	Post Divider (already known)
 187 * @tolerance:		Tolerance for Calculated Pixel Clock to be within
 188 *
 189 * return:
 190 *  It fills the PLLSettings structure with PLL Dividers values
 191 *  if calculated values are within required tolerance
 192 *  It returns	- true if error is within tolerance
 193 *		- false if error is not within tolerance
 194 */
 195static bool calc_fb_divider_checking_tolerance(
 196		struct calc_pll_clock_source *calc_pll_cs,
 197		struct pll_settings *pll_settings,
 198		uint32_t ref_divider,
 199		uint32_t post_divider,
 200		uint32_t tolerance)
 201{
 202	uint32_t feedback_divider;
 203	uint32_t fract_feedback_divider;
 204	uint32_t actual_calculated_clock_100hz;
 205	uint32_t abs_err;
 206	uint64_t actual_calc_clk_100hz;
 207
 208	calculate_fb_and_fractional_fb_divider(
 209			calc_pll_cs,
 210			pll_settings->adjusted_pix_clk_100hz,
 211			ref_divider,
 212			post_divider,
 213			&feedback_divider,
 214			&fract_feedback_divider);
 215
 216	/*Actual calculated value*/
 217	actual_calc_clk_100hz = (uint64_t)feedback_divider *
 218					calc_pll_cs->fract_fb_divider_factor +
 219							fract_feedback_divider;
 220	actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10;
 221	actual_calc_clk_100hz =
 222		div_u64(actual_calc_clk_100hz,
 223			ref_divider * post_divider *
 224				calc_pll_cs->fract_fb_divider_factor);
 225
 226	actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
 227
 228	abs_err = (actual_calculated_clock_100hz >
 229					pll_settings->adjusted_pix_clk_100hz)
 230			? actual_calculated_clock_100hz -
 231					pll_settings->adjusted_pix_clk_100hz
 232			: pll_settings->adjusted_pix_clk_100hz -
 233						actual_calculated_clock_100hz;
 234
 235	if (abs_err <= tolerance) {
 236		/*found good values*/
 237		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
 238		pll_settings->reference_divider = ref_divider;
 239		pll_settings->feedback_divider = feedback_divider;
 240		pll_settings->fract_feedback_divider = fract_feedback_divider;
 241		pll_settings->pix_clk_post_divider = post_divider;
 242		pll_settings->calculated_pix_clk_100hz =
 243			actual_calculated_clock_100hz;
 244		pll_settings->vco_freq =
 245			div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
 246		return true;
 247	}
 248	return false;
 249}
 250
 251static bool calc_pll_dividers_in_range(
 252		struct calc_pll_clock_source *calc_pll_cs,
 253		struct pll_settings *pll_settings,
 254		uint32_t min_ref_divider,
 255		uint32_t max_ref_divider,
 256		uint32_t min_post_divider,
 257		uint32_t max_post_divider,
 258		uint32_t err_tolerance)
 259{
 260	uint32_t ref_divider;
 261	uint32_t post_divider;
 262	uint32_t tolerance;
 263
 264/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
 265 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
 266	tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
 267									100000;
 268	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
 269		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
 270
 271	for (
 272			post_divider = max_post_divider;
 273			post_divider >= min_post_divider;
 274			--post_divider) {
 275		for (
 276				ref_divider = min_ref_divider;
 277				ref_divider <= max_ref_divider;
 278				++ref_divider) {
 279			if (calc_fb_divider_checking_tolerance(
 280					calc_pll_cs,
 281					pll_settings,
 282					ref_divider,
 283					post_divider,
 284					tolerance)) {
 285				return true;
 286			}
 287		}
 288	}
 289
 290	return false;
 291}
 292
 293static uint32_t calculate_pixel_clock_pll_dividers(
 294		struct calc_pll_clock_source *calc_pll_cs,
 295		struct pll_settings *pll_settings)
 296{
 297	uint32_t err_tolerance;
 298	uint32_t min_post_divider;
 299	uint32_t max_post_divider;
 300	uint32_t min_ref_divider;
 301	uint32_t max_ref_divider;
 302
 303	if (pll_settings->adjusted_pix_clk_100hz == 0) {
 304		DC_LOG_ERROR(
 305			"%s Bad requested pixel clock", __func__);
 306		return MAX_PLL_CALC_ERROR;
 307	}
 308
 309/* 1) Find Post divider ranges */
 310	if (pll_settings->pix_clk_post_divider) {
 311		min_post_divider = pll_settings->pix_clk_post_divider;
 312		max_post_divider = pll_settings->pix_clk_post_divider;
 313	} else {
 314		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
 315		if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
 316						calc_pll_cs->min_vco_khz * 10) {
 317			min_post_divider = calc_pll_cs->min_vco_khz * 10 /
 318					pll_settings->adjusted_pix_clk_100hz;
 319			if ((min_post_divider *
 320					pll_settings->adjusted_pix_clk_100hz) <
 321						calc_pll_cs->min_vco_khz * 10)
 322				min_post_divider++;
 323		}
 324
 325		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
 326		if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
 327				> calc_pll_cs->max_vco_khz * 10)
 328			max_post_divider = calc_pll_cs->max_vco_khz * 10 /
 329					pll_settings->adjusted_pix_clk_100hz;
 330	}
 331
 332/* 2) Find Reference divider ranges
 333 * When SS is enabled, or for Display Port even without SS,
 334 * pll_settings->referenceDivider is not zero.
 335 * So calculate PPLL FB and fractional FB divider
 336 * using the passed reference divider*/
 337
 338	if (pll_settings->reference_divider) {
 339		min_ref_divider = pll_settings->reference_divider;
 340		max_ref_divider = pll_settings->reference_divider;
 341	} else {
 342		min_ref_divider = ((calc_pll_cs->ref_freq_khz
 343				/ calc_pll_cs->max_pll_input_freq_khz)
 344				> calc_pll_cs->min_pll_ref_divider)
 345			? calc_pll_cs->ref_freq_khz
 346					/ calc_pll_cs->max_pll_input_freq_khz
 347			: calc_pll_cs->min_pll_ref_divider;
 348
 349		max_ref_divider = ((calc_pll_cs->ref_freq_khz
 350				/ calc_pll_cs->min_pll_input_freq_khz)
 351				< calc_pll_cs->max_pll_ref_divider)
 352			? calc_pll_cs->ref_freq_khz /
 353					calc_pll_cs->min_pll_input_freq_khz
 354			: calc_pll_cs->max_pll_ref_divider;
 355	}
 356
 357/* If some parameters are invalid we could have scenario when  "min">"max"
 358 * which produced endless loop later.
 359 * We should investigate why we get the wrong parameters.
 360 * But to follow the similar logic when "adjustedPixelClock" is set to be 0
 361 * it is better to return here than cause system hang/watchdog timeout later.
 362 *  ## SVS Wed 15 Jul 2009 */
 363
 364	if (min_post_divider > max_post_divider) {
 365		DC_LOG_ERROR(
 366			"%s Post divider range is invalid", __func__);
 367		return MAX_PLL_CALC_ERROR;
 368	}
 369
 370	if (min_ref_divider > max_ref_divider) {
 371		DC_LOG_ERROR(
 372			"%s Reference divider range is invalid", __func__);
 373		return MAX_PLL_CALC_ERROR;
 374	}
 375
 376/* 3) Try to find PLL dividers given ranges
 377 * starting with minimal error tolerance.
 378 * Increase error tolerance until PLL dividers found*/
 379	err_tolerance = MAX_PLL_CALC_ERROR;
 380
 381	while (!calc_pll_dividers_in_range(
 382			calc_pll_cs,
 383			pll_settings,
 384			min_ref_divider,
 385			max_ref_divider,
 386			min_post_divider,
 387			max_post_divider,
 388			err_tolerance))
 389		err_tolerance += (err_tolerance > 10)
 390				? (err_tolerance / 10)
 391				: 1;
 392
 393	return err_tolerance;
 394}
 395
 396static bool pll_adjust_pix_clk(
 397		struct dce110_clk_src *clk_src,
 398		struct pixel_clk_params *pix_clk_params,
 399		struct pll_settings *pll_settings)
 400{
 401	uint32_t actual_pix_clk_100hz = 0;
 402	uint32_t requested_clk_100hz = 0;
 403	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
 404							0 };
 405	enum bp_result bp_result;
 406	switch (pix_clk_params->signal_type) {
 407	case SIGNAL_TYPE_HDMI_TYPE_A: {
 408		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 409		if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
 410			switch (pix_clk_params->color_depth) {
 411			case COLOR_DEPTH_101010:
 412				requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
 413				break; /* x1.25*/
 414			case COLOR_DEPTH_121212:
 415				requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
 416				break; /* x1.5*/
 417			case COLOR_DEPTH_161616:
 418				requested_clk_100hz = requested_clk_100hz * 2;
 419				break; /* x2.0*/
 420			default:
 421				break;
 422			}
 423		}
 424		actual_pix_clk_100hz = requested_clk_100hz;
 425	}
 426		break;
 427
 428	case SIGNAL_TYPE_DISPLAY_PORT:
 429	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 430	case SIGNAL_TYPE_EDP:
 431		requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
 432		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 433		break;
 434
 435	default:
 436		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 437		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 438		break;
 439	}
 440
 441	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
 442	bp_adjust_pixel_clock_params.
 443		encoder_object_id = pix_clk_params->encoder_object_id;
 444	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
 445	bp_adjust_pixel_clock_params.
 446		ss_enable = pix_clk_params->flags.ENABLE_SS;
 447	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
 448			clk_src->bios, &bp_adjust_pixel_clock_params);
 449	if (bp_result == BP_RESULT_OK) {
 450		pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
 451		pll_settings->adjusted_pix_clk_100hz =
 452			bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
 453		pll_settings->reference_divider =
 454			bp_adjust_pixel_clock_params.reference_divider;
 455		pll_settings->pix_clk_post_divider =
 456			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
 457
 458		return true;
 459	}
 460
 461	return false;
 462}
 463
 464/*
 465 * Calculate PLL Dividers for given Clock Value.
 466 * First will call VBIOS Adjust Exec table to check if requested Pixel clock
 467 * will be Adjusted based on usage.
 468 * Then it will calculate PLL Dividers for this Adjusted clock using preferred
 469 * method (Maximum VCO frequency).
 470 *
 471 * \return
 472 *     Calculation error in units of 0.01%
 473 */
 474
 475static uint32_t dce110_get_pix_clk_dividers_helper (
 476		struct dce110_clk_src *clk_src,
 477		struct pll_settings *pll_settings,
 478		struct pixel_clk_params *pix_clk_params)
 479{
 480	uint32_t field = 0;
 481	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
 482	DC_LOGGER_INIT();
 483	/* Check if reference clock is external (not pcie/xtalin)
 484	* HW Dce80 spec:
 485	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
 486	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
 487	REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
 488	pll_settings->use_external_clk = (field > 1);
 489
 490	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
 491	 * (we do not care any more from SI for some older DP Sink which
 492	 * does not report SS support, no known issues) */
 493	if ((pix_clk_params->flags.ENABLE_SS) ||
 494			(dc_is_dp_signal(pix_clk_params->signal_type))) {
 495
 496		const struct spread_spectrum_data *ss_data = get_ss_data_entry(
 497					clk_src,
 498					pix_clk_params->signal_type,
 499					pll_settings->adjusted_pix_clk_100hz / 10);
 500
 501		if (NULL != ss_data)
 502			pll_settings->ss_percentage = ss_data->percentage;
 503	}
 504
 505	/* Check VBIOS AdjustPixelClock Exec table */
 506	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
 507		/* Should never happen, ASSERT and fill up values to be able
 508		 * to continue. */
 509		DC_LOG_ERROR(
 510			"%s: Failed to adjust pixel clock!!", __func__);
 511		pll_settings->actual_pix_clk_100hz =
 512				pix_clk_params->requested_pix_clk_100hz;
 513		pll_settings->adjusted_pix_clk_100hz =
 514				pix_clk_params->requested_pix_clk_100hz;
 515
 516		if (dc_is_dp_signal(pix_clk_params->signal_type))
 517			pll_settings->adjusted_pix_clk_100hz = 1000000;
 518	}
 519
 520	/* Calculate Dividers */
 521	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
 522		/*Calculate Dividers by HDMI object, no SS case or SS case */
 523		pll_calc_error =
 524			calculate_pixel_clock_pll_dividers(
 525					&clk_src->calc_pll_hdmi,
 526					pll_settings);
 527	else
 528		/*Calculate Dividers by default object, no SS case or SS case */
 529		pll_calc_error =
 530			calculate_pixel_clock_pll_dividers(
 531					&clk_src->calc_pll,
 532					pll_settings);
 533
 534	return pll_calc_error;
 535}
 536
 537static void dce112_get_pix_clk_dividers_helper (
 538		struct dce110_clk_src *clk_src,
 539		struct pll_settings *pll_settings,
 540		struct pixel_clk_params *pix_clk_params)
 541{
 542	uint32_t actual_pixel_clock_100hz;
 543
 544	actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
 545	/* Calculate Dividers */
 546	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
 547		switch (pix_clk_params->color_depth) {
 548		case COLOR_DEPTH_101010:
 549			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
 550			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
 551			break;
 552		case COLOR_DEPTH_121212:
 553			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
 554			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
 555			break;
 556		case COLOR_DEPTH_161616:
 557			actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
 558			break;
 559		default:
 560			break;
 561		}
 562	}
 563	pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
 564	pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
 565	pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 566}
 567
 568static uint32_t dce110_get_pix_clk_dividers(
 569		struct clock_source *cs,
 570		struct pixel_clk_params *pix_clk_params,
 571		struct pll_settings *pll_settings)
 572{
 573	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 574	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
 575	DC_LOGGER_INIT();
 576
 577	if (pix_clk_params == NULL || pll_settings == NULL
 578			|| pix_clk_params->requested_pix_clk_100hz == 0) {
 579		DC_LOG_ERROR(
 580			"%s: Invalid parameters!!\n", __func__);
 581		return pll_calc_error;
 582	}
 583
 584	memset(pll_settings, 0, sizeof(*pll_settings));
 585
 586	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
 587			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
 588		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 589		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 590		pll_settings->actual_pix_clk_100hz =
 591					pix_clk_params->requested_pix_clk_100hz;
 592		return 0;
 593	}
 594
 595	pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
 596			pll_settings, pix_clk_params);
 597
 598	return pll_calc_error;
 599}
 600
 601static uint32_t dce112_get_pix_clk_dividers(
 602		struct clock_source *cs,
 603		struct pixel_clk_params *pix_clk_params,
 604		struct pll_settings *pll_settings)
 605{
 606	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 607	DC_LOGGER_INIT();
 608
 609	if (pix_clk_params == NULL || pll_settings == NULL
 610			|| pix_clk_params->requested_pix_clk_100hz == 0) {
 611		DC_LOG_ERROR(
 612			"%s: Invalid parameters!!\n", __func__);
 613		return -1;
 614	}
 615
 616	memset(pll_settings, 0, sizeof(*pll_settings));
 617
 618	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
 619			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
 620		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 621		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 622		pll_settings->actual_pix_clk_100hz =
 623					pix_clk_params->requested_pix_clk_100hz;
 624		return -1;
 625	}
 626
 627	dce112_get_pix_clk_dividers_helper(clk_src,
 628			pll_settings, pix_clk_params);
 629
 630	return 0;
 631}
 632
 633static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
 634{
 635	enum bp_result result;
 636	struct bp_spread_spectrum_parameters bp_ss_params = {0};
 637
 638	bp_ss_params.pll_id = clk_src->base.id;
 639
 640	/*Call ASICControl to process ATOMBIOS Exec table*/
 641	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
 642			clk_src->bios,
 643			&bp_ss_params,
 644			false);
 645
 646	return result == BP_RESULT_OK;
 647}
 648
 649static bool calculate_ss(
 650		const struct pll_settings *pll_settings,
 651		const struct spread_spectrum_data *ss_data,
 652		struct delta_sigma_data *ds_data)
 653{
 654	struct fixed31_32 fb_div;
 655	struct fixed31_32 ss_amount;
 656	struct fixed31_32 ss_nslip_amount;
 657	struct fixed31_32 ss_ds_frac_amount;
 658	struct fixed31_32 ss_step_size;
 659	struct fixed31_32 modulation_time;
 660
 661	if (ds_data == NULL)
 662		return false;
 663	if (ss_data == NULL)
 664		return false;
 665	if (ss_data->percentage == 0)
 666		return false;
 667	if (pll_settings == NULL)
 668		return false;
 669
 670	memset(ds_data, 0, sizeof(struct delta_sigma_data));
 671
 672	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
 673	/* 6 decimal point support in fractional feedback divider */
 674	fb_div  = dc_fixpt_from_fraction(
 675		pll_settings->fract_feedback_divider, 1000000);
 676	fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
 677
 678	ds_data->ds_frac_amount = 0;
 679	/*spreadSpectrumPercentage is in the unit of .01%,
 680	 * so have to divided by 100 * 100*/
 681	ss_amount = dc_fixpt_mul(
 682		fb_div, dc_fixpt_from_fraction(ss_data->percentage,
 683					100 * (long long)ss_data->percentage_divider));
 684	ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
 685
 686	ss_nslip_amount = dc_fixpt_sub(ss_amount,
 687		dc_fixpt_from_int(ds_data->feedback_amount));
 688	ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
 689	ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
 690
 691	ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
 692		dc_fixpt_from_int(ds_data->nfrac_amount));
 693	ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
 694	ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
 695
 696	/* compute SS_STEP_SIZE_DSFRAC */
 697	modulation_time = dc_fixpt_from_fraction(
 698		pll_settings->reference_freq * (uint64_t)1000,
 699		pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz);
 700
 701	if (ss_data->flags.CENTER_SPREAD)
 702		modulation_time = dc_fixpt_div_int(modulation_time, 4);
 703	else
 704		modulation_time = dc_fixpt_div_int(modulation_time, 2);
 705
 706	ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
 707	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
 708	ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
 709	ds_data->ds_frac_size =  dc_fixpt_floor(ss_step_size);
 710
 711	return true;
 712}
 713
 714static bool enable_spread_spectrum(
 715		struct dce110_clk_src *clk_src,
 716		enum signal_type signal, struct pll_settings *pll_settings)
 717{
 718	struct bp_spread_spectrum_parameters bp_params = {0};
 719	struct delta_sigma_data d_s_data;
 720	const struct spread_spectrum_data *ss_data = NULL;
 721
 722	ss_data = get_ss_data_entry(
 723			clk_src,
 724			signal,
 725			pll_settings->calculated_pix_clk_100hz / 10);
 726
 727/* Pixel clock PLL has been programmed to generate desired pixel clock,
 728 * now enable SS on pixel clock */
 729/* TODO is it OK to return true not doing anything ??*/
 730	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
 731		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
 732			bp_params.ds.feedback_amount =
 733					d_s_data.feedback_amount;
 734			bp_params.ds.nfrac_amount =
 735					d_s_data.nfrac_amount;
 736			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
 737			bp_params.ds_frac_amount =
 738					d_s_data.ds_frac_amount;
 739			bp_params.flags.DS_TYPE = 1;
 740			bp_params.pll_id = clk_src->base.id;
 741			bp_params.percentage = ss_data->percentage;
 742			if (ss_data->flags.CENTER_SPREAD)
 743				bp_params.flags.CENTER_SPREAD = 1;
 744			if (ss_data->flags.EXTERNAL_SS)
 745				bp_params.flags.EXTERNAL_SS = 1;
 746
 747			if (BP_RESULT_OK !=
 748				clk_src->bios->funcs->
 749					enable_spread_spectrum_on_ppll(
 750							clk_src->bios,
 751							&bp_params,
 752							true))
 753				return false;
 754		} else
 755			return false;
 756	}
 757	return true;
 758}
 759
 760static void dce110_program_pixel_clk_resync(
 761		struct dce110_clk_src *clk_src,
 762		enum signal_type signal_type,
 763		enum dc_color_depth colordepth)
 764{
 765	REG_UPDATE(RESYNC_CNTL,
 766			DCCG_DEEP_COLOR_CNTL1, 0);
 767	/*
 768	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 769	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 770	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 771	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 772	 */
 773	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
 774		return;
 775
 776	switch (colordepth) {
 777	case COLOR_DEPTH_888:
 778		REG_UPDATE(RESYNC_CNTL,
 779				DCCG_DEEP_COLOR_CNTL1, 0);
 780		break;
 781	case COLOR_DEPTH_101010:
 782		REG_UPDATE(RESYNC_CNTL,
 783				DCCG_DEEP_COLOR_CNTL1, 1);
 784		break;
 785	case COLOR_DEPTH_121212:
 786		REG_UPDATE(RESYNC_CNTL,
 787				DCCG_DEEP_COLOR_CNTL1, 2);
 788		break;
 789	case COLOR_DEPTH_161616:
 790		REG_UPDATE(RESYNC_CNTL,
 791				DCCG_DEEP_COLOR_CNTL1, 3);
 792		break;
 793	default:
 794		break;
 795	}
 796}
 797
 798static void dce112_program_pixel_clk_resync(
 799		struct dce110_clk_src *clk_src,
 800		enum signal_type signal_type,
 801		enum dc_color_depth colordepth,
 802		bool enable_ycbcr420)
 803{
 804	uint32_t deep_color_cntl = 0;
 805	uint32_t double_rate_enable = 0;
 806
 807	/*
 808	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 809	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 810	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 811	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 812	 */
 813	if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
 814		double_rate_enable = enable_ycbcr420 ? 1 : 0;
 815
 816		switch (colordepth) {
 817		case COLOR_DEPTH_888:
 818			deep_color_cntl = 0;
 819			break;
 820		case COLOR_DEPTH_101010:
 821			deep_color_cntl = 1;
 822			break;
 823		case COLOR_DEPTH_121212:
 824			deep_color_cntl = 2;
 825			break;
 826		case COLOR_DEPTH_161616:
 827			deep_color_cntl = 3;
 828			break;
 829		default:
 830			break;
 831		}
 832	}
 833
 834	if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
 835		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
 836				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
 837				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
 838	else
 839		REG_UPDATE(PIXCLK_RESYNC_CNTL,
 840				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
 841
 842}
 843
 844static bool dce110_program_pix_clk(
 845		struct clock_source *clock_source,
 846		struct pixel_clk_params *pix_clk_params,
 847		enum dp_link_encoding encoding,
 848		struct pll_settings *pll_settings)
 849{
 850	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 851	struct bp_pixel_clock_parameters bp_pc_params = {0};
 852
 853	/* First disable SS
 854	 * ATOMBIOS will enable by default SS on PLL for DP,
 855	 * do not disable it here
 856	 */
 857	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
 858			!dc_is_dp_signal(pix_clk_params->signal_type) &&
 859			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
 860		disable_spread_spectrum(clk_src);
 861
 862	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 863	bp_pc_params.controller_id = pix_clk_params->controller_id;
 864	bp_pc_params.pll_id = clock_source->id;
 865	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 866	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
 867	bp_pc_params.signal_type = pix_clk_params->signal_type;
 868
 869	bp_pc_params.reference_divider = pll_settings->reference_divider;
 870	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
 871	bp_pc_params.fractional_feedback_divider =
 872			pll_settings->fract_feedback_divider;
 873	bp_pc_params.pixel_clock_post_divider =
 874			pll_settings->pix_clk_post_divider;
 875	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
 876					pll_settings->use_external_clk;
 877
 878	switch (pix_clk_params->color_depth) {
 879	case COLOR_DEPTH_101010:
 880		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
 881		break;
 882	case COLOR_DEPTH_121212:
 883		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
 884		break;
 885	case COLOR_DEPTH_161616:
 886		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
 887		break;
 888	default:
 889		break;
 890	}
 891
 892	if (clk_src->bios->funcs->set_pixel_clock(
 893			clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
 894		return false;
 895	/* Enable SS
 896	 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
 897	 * based on HW display PLL team, SS control settings should be programmed
 898	 * during PLL Reset, but they do not have effect
 899	 * until SS_EN is asserted.*/
 900	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
 901			&& !dc_is_dp_signal(pix_clk_params->signal_type)) {
 902
 903		if (pix_clk_params->flags.ENABLE_SS)
 904			if (!enable_spread_spectrum(clk_src,
 905							pix_clk_params->signal_type,
 906							pll_settings))
 907				return false;
 908
 909		/* Resync deep color DTO */
 910		dce110_program_pixel_clk_resync(clk_src,
 911					pix_clk_params->signal_type,
 912					pix_clk_params->color_depth);
 913	}
 914
 915	return true;
 916}
 917
 918static bool dce112_program_pix_clk(
 919		struct clock_source *clock_source,
 920		struct pixel_clk_params *pix_clk_params,
 921		enum dp_link_encoding encoding,
 922		struct pll_settings *pll_settings)
 923{
 924	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 925	struct bp_pixel_clock_parameters bp_pc_params = {0};
 926
 927	/* First disable SS
 928	 * ATOMBIOS will enable by default SS on PLL for DP,
 929	 * do not disable it here
 930	 */
 931	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
 932			!dc_is_dp_signal(pix_clk_params->signal_type) &&
 933			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
 934		disable_spread_spectrum(clk_src);
 935
 936	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 937	bp_pc_params.controller_id = pix_clk_params->controller_id;
 938	bp_pc_params.pll_id = clock_source->id;
 939	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 940	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
 941	bp_pc_params.signal_type = pix_clk_params->signal_type;
 942
 943	if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 944		bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
 945						pll_settings->use_external_clk;
 946		bp_pc_params.flags.SET_XTALIN_REF_SRC =
 947						!pll_settings->use_external_clk;
 948		if (pix_clk_params->flags.SUPPORT_YCBCR420) {
 949			bp_pc_params.flags.SUPPORT_YUV_420 = 1;
 950		}
 951	}
 952	if (clk_src->bios->funcs->set_pixel_clock(
 953			clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
 954		return false;
 955	/* Resync deep color DTO */
 956	if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
 957		dce112_program_pixel_clk_resync(clk_src,
 958					pix_clk_params->signal_type,
 959					pix_clk_params->color_depth,
 960					pix_clk_params->flags.SUPPORT_YCBCR420);
 961
 962	return true;
 963}
 964
 965static bool dcn31_program_pix_clk(
 966		struct clock_source *clock_source,
 967		struct pixel_clk_params *pix_clk_params,
 968		enum dp_link_encoding encoding,
 969		struct pll_settings *pll_settings)
 970{
 971	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 972	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
 973	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
 974	const struct pixel_rate_range_table_entry *e =
 975			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
 976	struct bp_pixel_clock_parameters bp_pc_params = {0};
 977	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
 978
 979	// Apply ssed(spread spectrum) dpref clock for edp and dp
 980	if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&
 981		dc_is_dp_signal(pix_clk_params->signal_type) &&
 982		encoding == DP_8b_10b_ENCODING)
 983		dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;
 984
 985	// For these signal types Driver to program DP_DTO without calling VBIOS Command table
 986	if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
 987		if (e) {
 988			/* Set DTO values: phase = target clock, modulo = reference clock*/
 989			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
 990			REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
 991		} else {
 992			/* Set DTO values: phase = target clock, modulo = reference clock*/
 993			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
 994			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
 995		}
 996		/* Enable DTO */
 997		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
 998			if (encoding == DP_128b_132b_ENCODING)
 999				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1000						DP_DTO0_ENABLE, 1,
1001						PIPE0_DTO_SRC_SEL, 2);
1002			else
1003				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1004						DP_DTO0_ENABLE, 1,
1005						PIPE0_DTO_SRC_SEL, 1);
1006		else
1007			REG_UPDATE(PIXEL_RATE_CNTL[inst],
1008					DP_DTO0_ENABLE, 1);
1009	} else {
1010
1011		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1012			REG_UPDATE(PIXEL_RATE_CNTL[inst],
1013					PIPE0_DTO_SRC_SEL, 0);
1014
1015		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1016		bp_pc_params.controller_id = pix_clk_params->controller_id;
1017		bp_pc_params.pll_id = clock_source->id;
1018		bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1019		bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1020		bp_pc_params.signal_type = pix_clk_params->signal_type;
1021
1022		// Make sure we send the correct color depth to DMUB for HDMI
1023		if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1024			switch (pix_clk_params->color_depth) {
1025			case COLOR_DEPTH_888:
1026				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1027				break;
1028			case COLOR_DEPTH_101010:
1029				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1030				break;
1031			case COLOR_DEPTH_121212:
1032				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1033				break;
1034			case COLOR_DEPTH_161616:
1035				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1036				break;
1037			default:
1038				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1039				break;
1040			}
1041			bp_pc_params.color_depth = bp_pc_colour_depth;
1042		}
1043
1044		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1045			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1046							pll_settings->use_external_clk;
1047			bp_pc_params.flags.SET_XTALIN_REF_SRC =
1048							!pll_settings->use_external_clk;
1049			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1050				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1051			}
1052		}
1053		if (clk_src->bios->funcs->set_pixel_clock(
1054				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1055			return false;
1056		/* Resync deep color DTO */
1057		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1058			dce112_program_pixel_clk_resync(clk_src,
1059						pix_clk_params->signal_type,
1060						pix_clk_params->color_depth,
1061						pix_clk_params->flags.SUPPORT_YCBCR420);
1062	}
1063
1064	return true;
1065}
1066
1067static bool dcn401_program_pix_clk(
1068		struct clock_source *clock_source,
1069		struct pixel_clk_params *pix_clk_params,
1070		enum dp_link_encoding encoding,
1071		struct pll_settings *pll_settings)
1072{
1073	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1074	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1075	const struct pixel_rate_range_table_entry *e =
1076			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1077	struct bp_pixel_clock_parameters bp_pc_params = {0};
1078	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1079	struct dp_dto_params dto_params = { 0 };
1080
1081	dto_params.otg_inst = inst;
1082	dto_params.signal = pix_clk_params->signal_type;
1083
1084	// all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table
1085	if (!dc_is_tmds_signal(pix_clk_params->signal_type)) {
1086		long long dtbclk_p_src_clk_khz;
1087
1088		dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1089		dto_params.clk_src = DPREFCLK;
1090
1091		if (e) {
1092			dto_params.pixclk_hz = e->target_pixel_rate_khz;
1093			dto_params.pixclk_hz *= e->mult_factor;
1094			dto_params.refclk_hz = dtbclk_p_src_clk_khz;
1095			dto_params.refclk_hz *= e->div_factor;
1096		} else {
1097			dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz;
1098			dto_params.pixclk_hz *= 100;
1099			dto_params.refclk_hz = dtbclk_p_src_clk_khz;
1100			dto_params.refclk_hz *= 1000;
1101		}
1102
1103		/* enable DP DTO */
1104		clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
1105				clock_source->ctx->dc->res_pool->dccg,
1106				&dto_params);
1107
1108	} else {
1109		if (pll_settings->actual_pix_clk_100hz > 6000000UL)
1110			return false;
1111
1112		/* disables DP DTO when provided with TMDS signal type */
1113		clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
1114				clock_source->ctx->dc->res_pool->dccg,
1115				&dto_params);
1116
1117		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1118		bp_pc_params.controller_id = pix_clk_params->controller_id;
1119		bp_pc_params.pll_id = clock_source->id;
1120		bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1121		bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1122		bp_pc_params.signal_type = pix_clk_params->signal_type;
1123
1124		// Make sure we send the correct color depth to DMUB for HDMI
1125		if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1126			switch (pix_clk_params->color_depth) {
1127			case COLOR_DEPTH_888:
1128				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1129				break;
1130			case COLOR_DEPTH_101010:
1131				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1132				break;
1133			case COLOR_DEPTH_121212:
1134				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1135				break;
1136			case COLOR_DEPTH_161616:
1137				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1138				break;
1139			default:
1140				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1141				break;
1142			}
1143			bp_pc_params.color_depth = bp_pc_colour_depth;
1144		}
1145
1146		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1147			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1148							pll_settings->use_external_clk;
1149			bp_pc_params.flags.SET_XTALIN_REF_SRC =
1150							!pll_settings->use_external_clk;
1151			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1152				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1153			}
1154		}
1155		if (clk_src->bios->funcs->set_pixel_clock(
1156				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1157			return false;
1158		/* Resync deep color DTO */
1159		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1160			dce112_program_pixel_clk_resync(clk_src,
1161						pix_clk_params->signal_type,
1162						pix_clk_params->color_depth,
1163						pix_clk_params->flags.SUPPORT_YCBCR420);
1164	}
1165
1166	return true;
1167}
1168
1169static bool dce110_clock_source_power_down(
1170		struct clock_source *clk_src)
1171{
1172	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
1173	enum bp_result bp_result;
1174	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
1175
1176	if (clk_src->dp_clk_src)
1177		return true;
1178
1179	/* If Pixel Clock is 0 it means Power Down Pll*/
1180	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
1181	bp_pixel_clock_params.pll_id = clk_src->id;
1182	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
1183
1184	/*Call ASICControl to process ATOMBIOS Exec table*/
1185	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
1186			dce110_clk_src->bios,
1187			&bp_pixel_clock_params);
1188
1189	return bp_result == BP_RESULT_OK;
1190}
1191
1192static bool get_pixel_clk_frequency_100hz(
1193		const struct clock_source *clock_source,
1194		unsigned int inst,
1195		unsigned int *pixel_clk_khz)
1196{
1197	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1198	unsigned int clock_hz = 0;
1199	unsigned int modulo_hz = 0;
1200	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1201
1202	if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1203		clock_hz = REG_READ(PHASE[inst]);
1204
1205		if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1206			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1207			/* NOTE: In case VBLANK syncronization is enabled, MODULO may
1208			 * not be programmed equal to DPREFCLK
1209			 */
1210			modulo_hz = REG_READ(MODULO[inst]);
1211			if (modulo_hz)
1212				*pixel_clk_khz = div_u64((uint64_t)clock_hz*
1213					dp_dto_ref_khz*10,
1214					modulo_hz);
1215			else
1216				*pixel_clk_khz = 0;
1217		} else {
1218			/* NOTE: There is agreement with VBIOS here that MODULO is
1219			 * programmed equal to DPREFCLK, in which case PHASE will be
1220			 * equivalent to pixel clock.
1221			 */
1222			*pixel_clk_khz = clock_hz / 100;
1223		}
1224		return true;
1225	}
1226
1227	return false;
1228}
1229
1230/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1231const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1232	// /1.001 rates
1233	{25170, 25180, 25200, 1000, 1001},	//25.2MHz   ->   25.17
1234	{59340, 59350, 59400, 1000, 1001},	//59.4Mhz   ->   59.340
1235	{74170, 74180, 74250, 1000, 1001},	//74.25Mhz  ->   74.1758
1236	{89910, 90000, 90000, 1000, 1001},	//90Mhz     ->   89.91
1237	{125870, 125880, 126000, 1000, 1001},	//126Mhz    ->  125.87
1238	{148350, 148360, 148500, 1000, 1001},	//148.5Mhz  ->  148.3516
1239	{167830, 167840, 168000, 1000, 1001},	//168Mhz    ->  167.83
1240	{222520, 222530, 222750, 1000, 1001},	//222.75Mhz ->  222.527
1241	{257140, 257150, 257400, 1000, 1001},	//257.4Mhz  ->  257.1429
1242	{296700, 296710, 297000, 1000, 1001},	//297Mhz    ->  296.7033
1243	{342850, 342860, 343200, 1000, 1001},	//343.2Mhz  ->  342.857
1244	{395600, 395610, 396000, 1000, 1001},	//396Mhz    ->  395.6
1245	{409090, 409100, 409500, 1000, 1001},	//409.5Mhz  ->  409.091
1246	{445050, 445060, 445500, 1000, 1001},	//445.5Mhz  ->  445.055
1247	{467530, 467540, 468000, 1000, 1001},	//468Mhz    ->  467.5325
1248	{519230, 519240, 519750, 1000, 1001},	//519.75Mhz ->  519.231
1249	{525970, 525980, 526500, 1000, 1001},	//526.5Mhz  ->  525.974
1250	{545450, 545460, 546000, 1000, 1001},	//546Mhz    ->  545.455
1251	{593400, 593410, 594000, 1000, 1001},	//594Mhz    ->  593.4066
1252	{623370, 623380, 624000, 1000, 1001},	//624Mhz    ->  623.377
1253	{692300, 692310, 693000, 1000, 1001},	//693Mhz    ->  692.308
1254	{701290, 701300, 702000, 1000, 1001},	//702Mhz    ->  701.2987
1255	{791200, 791210, 792000, 1000, 1001},	//792Mhz    ->  791.209
1256	{890100, 890110, 891000, 1000, 1001},	//891Mhz    ->  890.1099
1257	{1186810, 1186820, 1188000, 1000, 1001},//1188Mhz   -> 1186.8131
1258
1259	// *1.001 rates
1260	{27020, 27030, 27000, 1001, 1000}, //27Mhz
1261	{54050, 54060, 54000, 1001, 1000}, //54Mhz
1262	{108100, 108110, 108000, 1001, 1000},//108Mhz
1263};
1264
1265const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1266		unsigned int pixel_rate_khz)
1267{
1268	int i;
1269
1270	for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
1271		const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1272
1273		if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1274			return e;
1275		}
1276	}
1277
1278	return NULL;
1279}
1280
1281static bool dcn20_program_pix_clk(
1282		struct clock_source *clock_source,
1283		struct pixel_clk_params *pix_clk_params,
1284		enum dp_link_encoding encoding,
1285		struct pll_settings *pll_settings)
1286{
1287	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1288	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1289
1290	dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1291
1292	if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1293			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1294		/* NOTE: In case VBLANK syncronization is enabled,
1295		 * we need to set modulo to default DPREFCLK first
1296		 * dce112_program_pix_clk does not set default DPREFCLK
1297		 */
1298		REG_WRITE(MODULO[inst],
1299			clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);
1300	}
1301	return true;
1302}
1303
1304static bool dcn20_override_dp_pix_clk(
1305		struct clock_source *clock_source,
1306		unsigned int inst,
1307		unsigned int pixel_clk,
1308		unsigned int ref_clk)
1309{
1310	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1311
1312	REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
1313	REG_WRITE(PHASE[inst], pixel_clk);
1314	REG_WRITE(MODULO[inst], ref_clk);
1315	REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1316	return true;
1317}
1318
1319static const struct clock_source_funcs dcn20_clk_src_funcs = {
1320	.cs_power_down = dce110_clock_source_power_down,
1321	.program_pix_clk = dcn20_program_pix_clk,
1322	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1323	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
1324	.override_dp_pix_clk = dcn20_override_dp_pix_clk
1325};
1326
1327static bool dcn3_program_pix_clk(
1328		struct clock_source *clock_source,
1329		struct pixel_clk_params *pix_clk_params,
1330		enum dp_link_encoding encoding,
1331		struct pll_settings *pll_settings)
1332{
1333	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1334	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1335	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1336	const struct pixel_rate_range_table_entry *e =
1337			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1338
1339	// For these signal types Driver to program DP_DTO without calling VBIOS Command table
1340	if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1341		if (e) {
1342			/* Set DTO values: phase = target clock, modulo = reference clock*/
1343			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1344			REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1345		} else {
1346			/* Set DTO values: phase = target clock, modulo = reference clock*/
1347			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1348			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1349		}
1350		/* Enable DTO */
1351		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1352			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1353					DP_DTO0_ENABLE, 1,
1354					PIPE0_DTO_SRC_SEL, 1);
1355		else
1356			REG_UPDATE(PIXEL_RATE_CNTL[inst],
1357					DP_DTO0_ENABLE, 1);
1358	} else
1359		// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1360		dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1361
1362	return true;
1363}
1364
1365static uint32_t dcn3_get_pix_clk_dividers(
1366		struct clock_source *cs,
1367		struct pixel_clk_params *pix_clk_params,
1368		struct pll_settings *pll_settings)
1369{
1370	unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0;
1371	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
1372
1373	DC_LOGGER_INIT();
1374
1375	if (pix_clk_params == NULL || pll_settings == NULL
1376			|| pix_clk_params->requested_pix_clk_100hz == 0) {
1377		DC_LOG_ERROR(
1378			"%s: Invalid parameters!!\n", __func__);
1379		return -1;
1380	}
1381
1382	memset(pll_settings, 0, sizeof(*pll_settings));
1383	/* Adjust for HDMI Type A deep color */
1384	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1385		switch (pix_clk_params->color_depth) {
1386		case COLOR_DEPTH_101010:
1387			actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1388			break;
1389		case COLOR_DEPTH_121212:
1390			actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1391			break;
1392		case COLOR_DEPTH_161616:
1393			actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1394			break;
1395		default:
1396			break;
1397		}
1398	}
1399	pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1400	pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1401	pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1402
1403	return 0;
1404}
1405
1406static const struct clock_source_funcs dcn3_clk_src_funcs = {
1407	.cs_power_down = dce110_clock_source_power_down,
1408	.program_pix_clk = dcn3_program_pix_clk,
1409	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1410	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1411};
1412
1413static const struct clock_source_funcs dcn31_clk_src_funcs = {
1414	.cs_power_down = dce110_clock_source_power_down,
1415	.program_pix_clk = dcn31_program_pix_clk,
1416	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1417	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1418};
1419
1420static const struct clock_source_funcs dcn401_clk_src_funcs = {
1421	.cs_power_down = dce110_clock_source_power_down,
1422	.program_pix_clk = dcn401_program_pix_clk,
1423	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1424	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1425};
1426
1427/*****************************************/
1428/* Constructor                           */
1429/*****************************************/
1430
1431static const struct clock_source_funcs dce112_clk_src_funcs = {
1432	.cs_power_down = dce110_clock_source_power_down,
1433	.program_pix_clk = dce112_program_pix_clk,
1434	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1435	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1436};
1437static const struct clock_source_funcs dce110_clk_src_funcs = {
1438	.cs_power_down = dce110_clock_source_power_down,
1439	.program_pix_clk = dce110_program_pix_clk,
1440	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1441	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1442};
1443
1444
1445static void get_ss_info_from_atombios(
1446		struct dce110_clk_src *clk_src,
1447		enum as_signal_type as_signal,
1448		struct spread_spectrum_data *spread_spectrum_data[],
1449		uint32_t *ss_entries_num)
1450{
1451	enum bp_result bp_result = BP_RESULT_FAILURE;
1452	struct spread_spectrum_info *ss_info;
1453	struct spread_spectrum_data *ss_data;
1454	struct spread_spectrum_info *ss_info_cur;
1455	struct spread_spectrum_data *ss_data_cur;
1456	uint32_t i;
1457	DC_LOGGER_INIT();
1458	if (ss_entries_num == NULL) {
1459		DC_LOG_SYNC(
1460			"Invalid entry !!!\n");
1461		return;
1462	}
1463	if (spread_spectrum_data == NULL) {
1464		DC_LOG_SYNC(
1465			"Invalid array pointer!!!\n");
1466		return;
1467	}
1468
1469	spread_spectrum_data[0] = NULL;
1470	*ss_entries_num = 0;
1471
1472	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1473			clk_src->bios,
1474			as_signal);
1475
1476	if (*ss_entries_num == 0)
1477		return;
1478
1479	ss_info = kcalloc(*ss_entries_num,
1480			  sizeof(struct spread_spectrum_info),
1481			  GFP_KERNEL);
1482	ss_info_cur = ss_info;
1483	if (ss_info == NULL)
1484		return;
1485
1486	ss_data = kcalloc(*ss_entries_num,
1487			  sizeof(struct spread_spectrum_data),
1488			  GFP_KERNEL);
1489	if (ss_data == NULL)
1490		goto out_free_info;
1491
1492	for (i = 0, ss_info_cur = ss_info;
1493		i < (*ss_entries_num);
1494		++i, ++ss_info_cur) {
1495
1496		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1497				clk_src->bios,
1498				as_signal,
1499				i,
1500				ss_info_cur);
1501
1502		if (bp_result != BP_RESULT_OK)
1503			goto out_free_data;
1504	}
1505
1506	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1507		i < (*ss_entries_num);
1508		++i, ++ss_info_cur, ++ss_data_cur) {
1509
1510		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1511			DC_LOG_SYNC(
1512				"Invalid ATOMBIOS SS Table!!!\n");
1513			goto out_free_data;
1514		}
1515
1516		/* for HDMI check SS percentage,
1517		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1518		if (as_signal == AS_SIGNAL_TYPE_HDMI
1519				&& ss_info_cur->spread_spectrum_percentage > 6){
1520			/* invalid input, do nothing */
1521			DC_LOG_SYNC(
1522				"Invalid SS percentage ");
1523			DC_LOG_SYNC(
1524				"for HDMI in ATOMBIOS info Table!!!\n");
1525			continue;
1526		}
1527		if (ss_info_cur->spread_percentage_divider == 1000) {
1528			/* Keep previous precision from ATOMBIOS for these
1529			* in case new precision set by ATOMBIOS for these
1530			* (otherwise all code in DCE specific classes
1531			* for all previous ASICs would need
1532			* to be updated for SS calculations,
1533			* Audio SS compensation and DP DTO SS compensation
1534			* which assumes fixed SS percentage Divider = 100)*/
1535			ss_info_cur->spread_spectrum_percentage /= 10;
1536			ss_info_cur->spread_percentage_divider = 100;
1537		}
1538
1539		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1540		ss_data_cur->percentage =
1541				ss_info_cur->spread_spectrum_percentage;
1542		ss_data_cur->percentage_divider =
1543				ss_info_cur->spread_percentage_divider;
1544		ss_data_cur->modulation_freq_hz =
1545				ss_info_cur->spread_spectrum_range;
1546
1547		if (ss_info_cur->type.CENTER_MODE)
1548			ss_data_cur->flags.CENTER_SPREAD = 1;
1549
1550		if (ss_info_cur->type.EXTERNAL)
1551			ss_data_cur->flags.EXTERNAL_SS = 1;
1552
1553	}
1554
1555	*spread_spectrum_data = ss_data;
1556	kfree(ss_info);
1557	return;
1558
1559out_free_data:
1560	kfree(ss_data);
1561	*ss_entries_num = 0;
1562out_free_info:
1563	kfree(ss_info);
1564}
1565
1566static void ss_info_from_atombios_create(
1567	struct dce110_clk_src *clk_src)
1568{
1569	get_ss_info_from_atombios(
1570		clk_src,
1571		AS_SIGNAL_TYPE_DISPLAY_PORT,
1572		&clk_src->dp_ss_params,
1573		&clk_src->dp_ss_params_cnt);
1574	get_ss_info_from_atombios(
1575		clk_src,
1576		AS_SIGNAL_TYPE_HDMI,
1577		&clk_src->hdmi_ss_params,
1578		&clk_src->hdmi_ss_params_cnt);
1579	get_ss_info_from_atombios(
1580		clk_src,
1581		AS_SIGNAL_TYPE_DVI,
1582		&clk_src->dvi_ss_params,
1583		&clk_src->dvi_ss_params_cnt);
1584	get_ss_info_from_atombios(
1585		clk_src,
1586		AS_SIGNAL_TYPE_LVDS,
1587		&clk_src->lvds_ss_params,
1588		&clk_src->lvds_ss_params_cnt);
1589}
1590
1591static bool calc_pll_max_vco_construct(
1592			struct calc_pll_clock_source *calc_pll_cs,
1593			struct calc_pll_clock_source_init_data *init_data)
1594{
1595	uint32_t i;
1596	struct dc_firmware_info *fw_info;
1597	if (calc_pll_cs == NULL ||
1598			init_data == NULL ||
1599			init_data->bp == NULL)
1600		return false;
1601
1602	if (!init_data->bp->fw_info_valid)
1603		return false;
1604
1605	fw_info = &init_data->bp->fw_info;
1606	calc_pll_cs->ctx = init_data->ctx;
1607	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1608	calc_pll_cs->min_vco_khz =
1609			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1610	calc_pll_cs->max_vco_khz =
1611			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1612
1613	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1614		calc_pll_cs->max_pll_input_freq_khz =
1615			init_data->max_override_input_pxl_clk_pll_freq_khz;
1616	else
1617		calc_pll_cs->max_pll_input_freq_khz =
1618			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1619
1620	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1621		calc_pll_cs->min_pll_input_freq_khz =
1622			init_data->min_override_input_pxl_clk_pll_freq_khz;
1623	else
1624		calc_pll_cs->min_pll_input_freq_khz =
1625			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1626
1627	calc_pll_cs->min_pix_clock_pll_post_divider =
1628			init_data->min_pix_clk_pll_post_divider;
1629	calc_pll_cs->max_pix_clock_pll_post_divider =
1630			init_data->max_pix_clk_pll_post_divider;
1631	calc_pll_cs->min_pll_ref_divider =
1632			init_data->min_pll_ref_divider;
1633	calc_pll_cs->max_pll_ref_divider =
1634			init_data->max_pll_ref_divider;
1635
1636	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1637		init_data->num_fract_fb_divider_decimal_point_precision >
1638				init_data->num_fract_fb_divider_decimal_point) {
1639		DC_LOG_ERROR(
1640			"The dec point num or precision is incorrect!");
1641		return false;
1642	}
1643	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1644		DC_LOG_ERROR(
1645			"Incorrect fract feedback divider precision num!");
1646		return false;
1647	}
1648
1649	calc_pll_cs->fract_fb_divider_decimal_points_num =
1650				init_data->num_fract_fb_divider_decimal_point;
1651	calc_pll_cs->fract_fb_divider_precision =
1652			init_data->num_fract_fb_divider_decimal_point_precision;
1653	calc_pll_cs->fract_fb_divider_factor = 1;
1654	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1655		calc_pll_cs->fract_fb_divider_factor *= 10;
1656
1657	calc_pll_cs->fract_fb_divider_precision_factor = 1;
1658	for (
1659		i = 0;
1660		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1661				calc_pll_cs->fract_fb_divider_precision);
1662		++i)
1663		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1664
1665	return true;
1666}
1667
1668bool dce110_clk_src_construct(
1669	struct dce110_clk_src *clk_src,
1670	struct dc_context *ctx,
1671	struct dc_bios *bios,
1672	enum clock_source_id id,
1673	const struct dce110_clk_src_regs *regs,
1674	const struct dce110_clk_src_shift *cs_shift,
1675	const struct dce110_clk_src_mask *cs_mask)
1676{
1677	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1678	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1679
1680	clk_src->base.ctx = ctx;
1681	clk_src->bios = bios;
1682	clk_src->base.id = id;
1683	clk_src->base.funcs = &dce110_clk_src_funcs;
1684
1685	clk_src->regs = regs;
1686	clk_src->cs_shift = cs_shift;
1687	clk_src->cs_mask = cs_mask;
1688
1689	if (!clk_src->bios->fw_info_valid) {
1690		ASSERT_CRITICAL(false);
1691		goto unexpected_failure;
1692	}
1693
1694	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1695
1696	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1697	calc_pll_cs_init_data.bp = bios;
1698	calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1699	calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1700			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1701	calc_pll_cs_init_data.min_pll_ref_divider =	1;
1702	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
1703	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1704	calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
1705	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1706	calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz =	0;
1707	/*numberOfFractFBDividerDecimalPoints*/
1708	calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1709			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1710	/*number of decimal point to round off for fractional feedback divider value*/
1711	calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1712			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1713	calc_pll_cs_init_data.ctx =	ctx;
1714
1715	/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1716	calc_pll_cs_init_data_hdmi.bp = bios;
1717	calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1718	calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1719			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1720	calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1721	calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1722	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1723	calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1724	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1725	calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1726	/*numberOfFractFBDividerDecimalPoints*/
1727	calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1728			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1729	/*number of decimal point to round off for fractional feedback divider value*/
1730	calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1731			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1732	calc_pll_cs_init_data_hdmi.ctx = ctx;
1733
1734	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1735
1736	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1737		return true;
1738
1739	/* PLL only from here on */
1740	ss_info_from_atombios_create(clk_src);
1741
1742	if (!calc_pll_max_vco_construct(
1743			&clk_src->calc_pll,
1744			&calc_pll_cs_init_data)) {
1745		ASSERT_CRITICAL(false);
1746		goto unexpected_failure;
1747	}
1748
1749
1750	calc_pll_cs_init_data_hdmi.
1751			min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1752	calc_pll_cs_init_data_hdmi.
1753			max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1754
1755
1756	if (!calc_pll_max_vco_construct(
1757			&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1758		ASSERT_CRITICAL(false);
1759		goto unexpected_failure;
1760	}
1761
1762	return true;
1763
1764unexpected_failure:
1765	return false;
1766}
1767
1768bool dce112_clk_src_construct(
1769	struct dce110_clk_src *clk_src,
1770	struct dc_context *ctx,
1771	struct dc_bios *bios,
1772	enum clock_source_id id,
1773	const struct dce110_clk_src_regs *regs,
1774	const struct dce110_clk_src_shift *cs_shift,
1775	const struct dce110_clk_src_mask *cs_mask)
1776{
1777	clk_src->base.ctx = ctx;
1778	clk_src->bios = bios;
1779	clk_src->base.id = id;
1780	clk_src->base.funcs = &dce112_clk_src_funcs;
1781
1782	clk_src->regs = regs;
1783	clk_src->cs_shift = cs_shift;
1784	clk_src->cs_mask = cs_mask;
1785
1786	if (!clk_src->bios->fw_info_valid) {
1787		ASSERT_CRITICAL(false);
1788		return false;
1789	}
1790
1791	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1792
1793	return true;
1794}
1795
1796bool dcn20_clk_src_construct(
1797	struct dce110_clk_src *clk_src,
1798	struct dc_context *ctx,
1799	struct dc_bios *bios,
1800	enum clock_source_id id,
1801	const struct dce110_clk_src_regs *regs,
1802	const struct dce110_clk_src_shift *cs_shift,
1803	const struct dce110_clk_src_mask *cs_mask)
1804{
1805	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1806
1807	clk_src->base.funcs = &dcn20_clk_src_funcs;
1808
1809	return ret;
1810}
1811
1812bool dcn3_clk_src_construct(
1813	struct dce110_clk_src *clk_src,
1814	struct dc_context *ctx,
1815	struct dc_bios *bios,
1816	enum clock_source_id id,
1817	const struct dce110_clk_src_regs *regs,
1818	const struct dce110_clk_src_shift *cs_shift,
1819	const struct dce110_clk_src_mask *cs_mask)
1820{
1821	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1822
1823	clk_src->base.funcs = &dcn3_clk_src_funcs;
1824
1825	return ret;
1826}
1827
1828bool dcn31_clk_src_construct(
1829	struct dce110_clk_src *clk_src,
1830	struct dc_context *ctx,
1831	struct dc_bios *bios,
1832	enum clock_source_id id,
1833	const struct dce110_clk_src_regs *regs,
1834	const struct dce110_clk_src_shift *cs_shift,
1835	const struct dce110_clk_src_mask *cs_mask)
1836{
1837	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1838
1839	clk_src->base.funcs = &dcn31_clk_src_funcs;
1840
1841	return ret;
1842}
1843
1844bool dcn401_clk_src_construct(
1845	struct dce110_clk_src *clk_src,
1846	struct dc_context *ctx,
1847	struct dc_bios *bios,
1848	enum clock_source_id id,
1849	const struct dce110_clk_src_regs *regs,
1850	const struct dce110_clk_src_shift *cs_shift,
1851	const struct dce110_clk_src_mask *cs_mask)
1852{
1853	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1854
1855	clk_src->base.funcs = &dcn401_clk_src_funcs;
1856
1857	return ret;
1858}
1859bool dcn301_clk_src_construct(
1860	struct dce110_clk_src *clk_src,
1861	struct dc_context *ctx,
1862	struct dc_bios *bios,
1863	enum clock_source_id id,
1864	const struct dce110_clk_src_regs *regs,
1865	const struct dce110_clk_src_shift *cs_shift,
1866	const struct dce110_clk_src_mask *cs_mask)
1867{
1868	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1869
1870	clk_src->base.funcs = &dcn3_clk_src_funcs;
1871
1872	return ret;
1873}