dce_audio.c

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "reg_helper.h"
  27#include "dce_audio.h"
  28#include "dce/dce_11_0_d.h"
  29#include "dce/dce_11_0_sh_mask.h"
  30
  31#define DCE_AUD(audio)\
  32	container_of(audio, struct dce_audio, base)
  33
  34#define CTX \
  35	aud->base.ctx
  36
  37#define DC_LOGGER_INIT()
  38
  39#define REG(reg)\
  40	(aud->regs->reg)
  41
  42#undef FN
  43#define FN(reg_name, field_name) \
  44	aud->shifts->field_name, aud->masks->field_name
  45
  46#define IX_REG(reg)\
  47	ix ## reg
  48
  49#define AZ_REG_READ(reg_name) \
  50		read_indirect_azalia_reg(audio, IX_REG(reg_name))
  51
  52#define AZ_REG_WRITE(reg_name, value) \
  53		write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
  54
  55static void write_indirect_azalia_reg(struct audio *audio,
  56	uint32_t reg_index,
  57	uint32_t reg_data)
  58{
  59	struct dce_audio *aud = DCE_AUD(audio);
  60
  61	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  62	REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  63			AZALIA_ENDPOINT_REG_INDEX, reg_index);
  64
  65	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  66	REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
  67			AZALIA_ENDPOINT_REG_DATA, reg_data);
  68}
  69
  70static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
  71{
  72	struct dce_audio *aud = DCE_AUD(audio);
  73
  74	uint32_t value = 0;
  75
  76	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  77	REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  78			AZALIA_ENDPOINT_REG_INDEX, reg_index);
  79
  80	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  81	value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
  82
  83	return value;
  84}
  85
  86static bool is_audio_format_supported(
  87	const struct audio_info *audio_info,
  88	enum audio_format_code audio_format_code,
  89	uint32_t *format_index)
  90{
  91	uint32_t index;
  92	uint32_t max_channe_index = 0;
  93	bool found = false;
  94
  95	if (audio_info == NULL)
  96		return found;
  97
  98	/* pass through whole array */
  99	for (index = 0; index < audio_info->mode_count; index++) {
 100		if (audio_info->modes[index].format_code == audio_format_code) {
 101			if (found) {
 102				/* format has multiply entries, choose one with
 103				 *  highst number of channels */
 104				if (audio_info->modes[index].channel_count >
 105		audio_info->modes[max_channe_index].channel_count) {
 106					max_channe_index = index;
 107				}
 108			} else {
 109				/* format found, save it's index */
 110				found = true;
 111				max_channe_index = index;
 112			}
 113		}
 114	}
 115
 116	/* return index */
 117	if (found && format_index != NULL)
 118		*format_index = max_channe_index;
 119
 120	return found;
 121}
 122
 123/*For HDMI, calculate if specified sample rates can fit into a given timing */
 124static void check_audio_bandwidth_hdmi(
 125	const struct audio_crtc_info *crtc_info,
 126	uint32_t channel_count,
 127	union audio_sample_rates *sample_rates)
 128{
 129	uint32_t samples;
 130	uint32_t  h_blank;
 131	bool limit_freq_to_48_khz = false;
 132	bool limit_freq_to_88_2_khz = false;
 133	bool limit_freq_to_96_khz = false;
 134	bool limit_freq_to_174_4_khz = false;
 135	if (!crtc_info)
 136		return;
 137
 138	/* For two channels supported return whatever sink support,unmodified*/
 139	if (channel_count > 2) {
 140
 141		/* Based on HDMI spec 1.3 Table 7.5 */
 142		if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
 143		(crtc_info->v_active <= 576) &&
 144		!(crtc_info->interlaced) &&
 145		!(crtc_info->pixel_repetition == 2 ||
 146		crtc_info->pixel_repetition == 4)) {
 147			limit_freq_to_48_khz = true;
 148
 149		} else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
 150				(crtc_info->v_active <= 576) &&
 151				(crtc_info->interlaced) &&
 152				(crtc_info->pixel_repetition == 2)) {
 153			limit_freq_to_88_2_khz = true;
 154
 155		} else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
 156				(crtc_info->v_active <= 576) &&
 157				!(crtc_info->interlaced)) {
 158			limit_freq_to_174_4_khz = true;
 159		}
 160	}
 161
 162	/* Also do some calculation for the available Audio Bandwidth for the
 163	 * 8 ch (i.e. for the Layout 1 => ch > 2)
 164	 */
 165	h_blank = crtc_info->h_total - crtc_info->h_active;
 166
 167	if (crtc_info->pixel_repetition)
 168		h_blank *= crtc_info->pixel_repetition;
 169
 170	/*based on HDMI spec 1.3 Table 7.5 */
 171	h_blank -= 58;
 172	/*for Control Period */
 173	h_blank -= 16;
 174
 175	samples = h_blank * 10;
 176	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
 177	 * of Audio samples per line multiplied by 10 - Layout 1)
 178	 */
 179	samples /= 32;
 180	samples *= crtc_info->v_active;
 181	/*Number of samples multiplied by 10, per second */
 182	samples *= crtc_info->refresh_rate;
 183	/*Number of Audio samples per second */
 184	samples /= 10;
 185
 186	/* @todo do it after deep color is implemented
 187	 * 8xx - deep color bandwidth scaling
 188	 * Extra bandwidth is avaliable in deep color b/c link runs faster than
 189	 * pixel rate. This has the effect of allowing more tmds characters to
 190	 * be transmitted during blank
 191	 */
 192
 193	switch (crtc_info->color_depth) {
 194	case COLOR_DEPTH_888:
 195		samples *= 4;
 196		break;
 197	case COLOR_DEPTH_101010:
 198		samples *= 5;
 199		break;
 200	case COLOR_DEPTH_121212:
 201		samples *= 6;
 202		break;
 203	default:
 204		samples *= 4;
 205		break;
 206	}
 207
 208	samples /= 4;
 209
 210	/*check limitation*/
 211	if (samples < 88200)
 212		limit_freq_to_48_khz = true;
 213	else if (samples < 96000)
 214		limit_freq_to_88_2_khz = true;
 215	else if (samples < 176400)
 216		limit_freq_to_96_khz = true;
 217	else if (samples < 192000)
 218		limit_freq_to_174_4_khz = true;
 219
 220	if (sample_rates != NULL) {
 221		/* limit frequencies */
 222		if (limit_freq_to_174_4_khz)
 223			sample_rates->rate.RATE_192 = 0;
 224
 225		if (limit_freq_to_96_khz) {
 226			sample_rates->rate.RATE_192 = 0;
 227			sample_rates->rate.RATE_176_4 = 0;
 228		}
 229		if (limit_freq_to_88_2_khz) {
 230			sample_rates->rate.RATE_192 = 0;
 231			sample_rates->rate.RATE_176_4 = 0;
 232			sample_rates->rate.RATE_96 = 0;
 233		}
 234		if (limit_freq_to_48_khz) {
 235			sample_rates->rate.RATE_192 = 0;
 236			sample_rates->rate.RATE_176_4 = 0;
 237			sample_rates->rate.RATE_96 = 0;
 238			sample_rates->rate.RATE_88_2 = 0;
 239		}
 240	}
 241}
 242static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate)
 243{
 244	switch (link_rate) {
 245	case LINK_RATE_LOW:
 246		return dc_fixpt_from_int(162); /* 162 MHz */
 247	case LINK_RATE_HIGH:
 248		return dc_fixpt_from_int(270); /* 270 MHz */
 249	case LINK_RATE_HIGH2:
 250		return dc_fixpt_from_int(540); /* 540 MHz */
 251	case LINK_RATE_HIGH3:
 252		return dc_fixpt_from_int(810); /* 810 MHz */
 253	case LINK_RATE_UHBR10:
 254		return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */
 255	case LINK_RATE_UHBR13_5:
 256		return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */
 257	case LINK_RATE_UHBR20:
 258		return dc_fixpt_from_int(625); /* 625 MHz */
 259	default:
 260		/* Unexpected case, this requires debug if encountered. */
 261		ASSERT(0);
 262		return dc_fixpt_from_int(0);
 263	}
 264}
 265
 266struct dp_audio_layout_config {
 267	uint8_t layouts_per_sample_denom;
 268	uint8_t symbols_per_layout;
 269	uint8_t max_layouts_per_audio_sdp;
 270};
 271
 272static void get_audio_layout_config(
 273	uint32_t channel_count,
 274	enum dp_link_encoding encoding,
 275	struct dp_audio_layout_config *output)
 276{
 277	/* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP,
 278	 * with each layout being the same size (8ch layout).
 279	 */
 280	if (encoding == DP_8b_10b_ENCODING) {
 281		if (channel_count == 2) {
 282			output->layouts_per_sample_denom = 4;
 283			output->symbols_per_layout = 40;
 284			output->max_layouts_per_audio_sdp = 1;
 285		} else if (channel_count == 8 || channel_count == 6) {
 286			output->layouts_per_sample_denom = 1;
 287			output->symbols_per_layout = 40;
 288			output->max_layouts_per_audio_sdp = 1;
 289		}
 290	} else if (encoding == DP_128b_132b_ENCODING) {
 291		if (channel_count == 2) {
 292			output->layouts_per_sample_denom = 4;
 293			output->symbols_per_layout = 10;
 294			output->max_layouts_per_audio_sdp = 1;
 295		} else if (channel_count == 8 || channel_count == 6) {
 296			output->layouts_per_sample_denom = 1;
 297			output->symbols_per_layout = 10;
 298			output->max_layouts_per_audio_sdp = 1;
 299		}
 300	}
 301}
 302
 303static uint32_t get_av_stream_map_lane_count(
 304	enum dp_link_encoding encoding,
 305	enum dc_lane_count lane_count,
 306	bool is_mst)
 307{
 308	uint32_t av_stream_map_lane_count = 0;
 309
 310	if (encoding == DP_8b_10b_ENCODING) {
 311		if (!is_mst)
 312			av_stream_map_lane_count = lane_count;
 313		else
 314			av_stream_map_lane_count = 4;
 315	} else if (encoding == DP_128b_132b_ENCODING) {
 316		av_stream_map_lane_count = 4;
 317	}
 318
 319	ASSERT(av_stream_map_lane_count != 0);
 320
 321	return av_stream_map_lane_count;
 322}
 323
 324static uint32_t get_audio_sdp_overhead(
 325	enum dp_link_encoding encoding,
 326	enum dc_lane_count lane_count,
 327	bool is_mst)
 328{
 329	uint32_t audio_sdp_overhead = 0;
 330
 331	if (encoding == DP_8b_10b_ENCODING) {
 332		if (is_mst)
 333			audio_sdp_overhead = 16; /* 4 * 2 + 8 */
 334		else
 335			audio_sdp_overhead = lane_count * 2 + 8;
 336	} else if (encoding == DP_128b_132b_ENCODING) {
 337		audio_sdp_overhead = 10; /* 4 x 2.5 */
 338	}
 339
 340	ASSERT(audio_sdp_overhead != 0);
 341
 342	return audio_sdp_overhead;
 343}
 344
 345static uint32_t calculate_required_audio_bw_in_symbols(
 346	const struct audio_crtc_info *crtc_info,
 347	const struct dp_audio_layout_config *layout_config,
 348	uint32_t channel_count,
 349	uint32_t sample_rate_hz,
 350	uint32_t av_stream_map_lane_count,
 351	uint32_t audio_sdp_overhead)
 352{
 353	/* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */
 354	struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);
 355	struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(
 356			crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10);
 357	struct fixed31_32 samples_per_line;
 358	struct fixed31_32 layouts_per_line;
 359	struct fixed31_32 symbols_per_sdp_max_layout;
 360	struct fixed31_32 remainder;
 361	uint32_t num_sdp_with_max_layouts;
 362	uint32_t required_symbols_per_hblank;
 363
 364	samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000);
 365	samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz);
 366	layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom);
 367
 368	num_sdp_with_max_layouts = dc_fixpt_floor(
 369			dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp));
 370	symbols_per_sdp_max_layout = dc_fixpt_from_int(
 371			layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout);
 372	symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead);
 373	symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin);
 374	required_symbols_per_hblank = num_sdp_with_max_layouts;
 375	required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) /
 376			av_stream_map_lane_count) *	av_stream_map_lane_count;
 377
 378	if (num_sdp_with_max_layouts !=	dc_fixpt_ceil(
 379			dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) {
 380		remainder = dc_fixpt_sub_int(layouts_per_line,
 381				num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp);
 382		remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout);
 383		remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead);
 384		remainder = dc_fixpt_mul(remainder, audio_sdp_margin);
 385		required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) /
 386				av_stream_map_lane_count) * av_stream_map_lane_count;
 387	}
 388
 389	return required_symbols_per_hblank;
 390}
 391
 392/* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST.
 393 */
 394static uint32_t calculate_available_hblank_bw_in_symbols(
 395	const struct audio_crtc_info *crtc_info,
 396	const struct audio_dp_link_info *dp_link_info)
 397{
 398	uint64_t hblank = crtc_info->h_total - crtc_info->h_active;
 399	struct fixed31_32 hblank_time_msec =
 400			dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz);
 401	struct fixed31_32 lsclkfreq_mhz =
 402			get_link_symbol_clk_freq_mhz(dp_link_info->link_rate);
 403	struct fixed31_32 average_stream_sym_bw_frac;
 404	struct fixed31_32 peak_stream_bw_kbps;
 405	struct fixed31_32 bits_per_pixel;
 406	struct fixed31_32 link_bw_kbps;
 407	struct fixed31_32 available_stream_sym_count;
 408	uint32_t available_hblank_bw = 0; /* in stream symbols */
 409
 410	if (crtc_info->dsc_bits_per_pixel) {
 411		bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16);
 412	} else {
 413		switch (crtc_info->color_depth) {
 414		case COLOR_DEPTH_666:
 415			bits_per_pixel = dc_fixpt_from_int(6);
 416			break;
 417		case COLOR_DEPTH_888:
 418			bits_per_pixel = dc_fixpt_from_int(8);
 419			break;
 420		case COLOR_DEPTH_101010:
 421			bits_per_pixel = dc_fixpt_from_int(10);
 422			break;
 423		case COLOR_DEPTH_121212:
 424			bits_per_pixel = dc_fixpt_from_int(12);
 425			break;
 426		default:
 427			/* Default to commonly supported color depth. */
 428			bits_per_pixel = dc_fixpt_from_int(8);
 429			break;
 430		}
 431
 432		bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3);
 433
 434		if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 435			bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3);
 436			bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2);
 437		} else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 438			bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2);
 439		}
 440	}
 441
 442	/* Use simple stream BW calculation because mainlink overhead is
 443	 * accounted for separately in the audio BW calculations.
 444	 */
 445	peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10);
 446	peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel);
 447	link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps);
 448	average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps);
 449
 450	available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000);
 451	available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz);
 452	available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac);
 453	available_hblank_bw = dc_fixpt_floor(available_stream_sym_count);
 454	available_hblank_bw *= dp_link_info->lane_count;
 455	available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */
 456
 457	if (available_hblank_bw < dp_link_info->hblank_min_symbol_width)
 458		/* Each symbol takes 4 frames */
 459		available_hblank_bw = 4 * dp_link_info->hblank_min_symbol_width;
 460
 461	if (available_hblank_bw < 12)
 462		available_hblank_bw = 0;
 463	else
 464		available_hblank_bw -= 12; /* Main link overhead */
 465
 466	return available_hblank_bw;
 467}
 468
 469static void check_audio_bandwidth_dp(
 470	const struct audio_crtc_info *crtc_info,
 471	const struct audio_dp_link_info *dp_link_info,
 472	uint32_t channel_count,
 473	union audio_sample_rates *sample_rates)
 474{
 475	struct dp_audio_layout_config layout_config = {0};
 476	uint32_t available_hblank_bw;
 477	uint32_t av_stream_map_lane_count;
 478	uint32_t audio_sdp_overhead;
 479
 480	/* TODO: Add validation for SST 8b/10 case  */
 481	if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING)
 482		return;
 483
 484	available_hblank_bw = calculate_available_hblank_bw_in_symbols(
 485			crtc_info, dp_link_info);
 486	av_stream_map_lane_count = get_av_stream_map_lane_count(
 487			dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst);
 488	audio_sdp_overhead = get_audio_sdp_overhead(
 489			dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst);
 490	get_audio_layout_config(
 491			channel_count, dp_link_info->encoding, &layout_config);
 492
 493	if (layout_config.max_layouts_per_audio_sdp == 0 ||
 494		layout_config.symbols_per_layout == 0 ||
 495		layout_config.layouts_per_sample_denom == 0) {
 496		return;
 497	}
 498	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 499			crtc_info, &layout_config, channel_count, 192000,
 500			av_stream_map_lane_count, audio_sdp_overhead))
 501		sample_rates->rate.RATE_192 = 0;
 502	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 503			crtc_info, &layout_config, channel_count, 176400,
 504			av_stream_map_lane_count, audio_sdp_overhead))
 505		sample_rates->rate.RATE_176_4 = 0;
 506	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 507			crtc_info, &layout_config, channel_count, 96000,
 508			av_stream_map_lane_count, audio_sdp_overhead))
 509		sample_rates->rate.RATE_96 = 0;
 510	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 511			crtc_info, &layout_config, channel_count, 88200,
 512			av_stream_map_lane_count, audio_sdp_overhead))
 513		sample_rates->rate.RATE_88_2 = 0;
 514	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 515			crtc_info, &layout_config, channel_count, 48000,
 516			av_stream_map_lane_count, audio_sdp_overhead))
 517		sample_rates->rate.RATE_48 = 0;
 518	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 519			crtc_info, &layout_config, channel_count, 44100,
 520			av_stream_map_lane_count, audio_sdp_overhead))
 521		sample_rates->rate.RATE_44_1 = 0;
 522	if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
 523			crtc_info, &layout_config, channel_count, 32000,
 524			av_stream_map_lane_count, audio_sdp_overhead))
 525		sample_rates->rate.RATE_32 = 0;
 526}
 527
 528static void check_audio_bandwidth(
 529	const struct audio_crtc_info *crtc_info,
 530	const struct audio_dp_link_info *dp_link_info,
 531	uint32_t channel_count,
 532	enum signal_type signal,
 533	union audio_sample_rates *sample_rates)
 534{
 535	switch (signal) {
 536	case SIGNAL_TYPE_HDMI_TYPE_A:
 537		check_audio_bandwidth_hdmi(
 538			crtc_info, channel_count, sample_rates);
 539		break;
 540	case SIGNAL_TYPE_EDP:
 541	case SIGNAL_TYPE_DISPLAY_PORT:
 542	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 543		check_audio_bandwidth_dp(
 544			crtc_info, dp_link_info, channel_count, sample_rates);
 545		break;
 546	default:
 547		break;
 548	}
 549}
 550
 551/* expose/not expose HBR capability to Audio driver */
 552static void set_high_bit_rate_capable(
 553	struct audio *audio,
 554	bool capable)
 555{
 556	uint32_t value = 0;
 557
 558	/* set high bit rate audio capable*/
 559	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
 560
 561	set_reg_field_value(value, capable,
 562		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
 563		HBR_CAPABLE);
 564
 565	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
 566}
 567
 568/* set video latency in ms/2+1 */
 569static void set_video_latency(
 570	struct audio *audio,
 571	int latency_in_ms)
 572{
 573	uint32_t value = 0;
 574
 575	if ((latency_in_ms < 0) || (latency_in_ms > 255))
 576		return;
 577
 578	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 579
 580	set_reg_field_value(value, latency_in_ms,
 581		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 582		VIDEO_LIPSYNC);
 583
 584	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 585		value);
 586}
 587
 588/* set audio latency in ms/2+1 */
 589static void set_audio_latency(
 590	struct audio *audio,
 591	int latency_in_ms)
 592{
 593	uint32_t value = 0;
 594
 595	if (latency_in_ms < 0)
 596		latency_in_ms = 0;
 597
 598	if (latency_in_ms > 255)
 599		latency_in_ms = 255;
 600
 601	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 602
 603	set_reg_field_value(value, latency_in_ms,
 604		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 605		AUDIO_LIPSYNC);
 606
 607	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 608		value);
 609}
 610
 611void dce_aud_az_enable(struct audio *audio)
 612{
 613	uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 614	DC_LOGGER_INIT();
 615
 616	set_reg_field_value(value, 1,
 617			    AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 618			    CLOCK_GATING_DISABLE);
 619	set_reg_field_value(value, 1,
 620			    AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 621			    AUDIO_ENABLED);
 622
 623	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 624	set_reg_field_value(value, 0,
 625			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 626			CLOCK_GATING_DISABLE);
 627	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 628
 629	DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
 630			audio->inst, value);
 631}
 632
 633void dce_aud_az_disable_hbr_audio(struct audio *audio)
 634{
 635	set_high_bit_rate_capable(audio, false);
 636}
 637
 638void dce_aud_az_disable(struct audio *audio)
 639{
 640	uint32_t value;
 641	DC_LOGGER_INIT();
 642
 643	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 644	set_reg_field_value(value, 1,
 645			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 646			CLOCK_GATING_DISABLE);
 647	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 648
 649	set_reg_field_value(value, 0,
 650		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 651		AUDIO_ENABLED);
 652	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 653
 654	set_reg_field_value(value, 0,
 655			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 656			CLOCK_GATING_DISABLE);
 657	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 658	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 659	DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u  data: 0x%x\n",
 660			audio->inst, value);
 661}
 662
 663void dce_aud_az_configure(
 664	struct audio *audio,
 665	enum signal_type signal,
 666	const struct audio_crtc_info *crtc_info,
 667	const struct audio_info *audio_info,
 668	const struct audio_dp_link_info *dp_link_info)
 669{
 670	struct dce_audio *aud = DCE_AUD(audio);
 671
 672	uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
 673	uint32_t value;
 674	uint32_t field = 0;
 675	enum audio_format_code audio_format_code;
 676	uint32_t format_index;
 677	uint32_t index;
 678	bool is_ac3_supported = false;
 679	union audio_sample_rates sample_rate;
 680	uint32_t strlen = 0;
 681
 682	if (signal == SIGNAL_TYPE_VIRTUAL)
 683		return;
 684
 685	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 686	set_reg_field_value(value, 1,
 687			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 688			CLOCK_GATING_DISABLE);
 689	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 690
 691	/* Speaker Allocation */
 692	/*
 693	uint32_t value;
 694	uint32_t field = 0;*/
 695	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 696
 697	set_reg_field_value(value,
 698		speakers,
 699		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 700		SPEAKER_ALLOCATION);
 701
 702	/* LFE_PLAYBACK_LEVEL = LFEPBL
 703	 * LFEPBL = 0 : Unknown or refer to other information
 704	 * LFEPBL = 1 : 0dB playback
 705	 * LFEPBL = 2 : +10dB playback
 706	 * LFE_BL = 3 : Reserved
 707	 */
 708	set_reg_field_value(value,
 709		0,
 710		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 711		LFE_PLAYBACK_LEVEL);
 712	/* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
 713	 *  why are we writing to it?  DCE8 does not write this */
 714
 715
 716	set_reg_field_value(value,
 717		0,
 718		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 719		HDMI_CONNECTION);
 720
 721	set_reg_field_value(value,
 722		0,
 723		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 724		DP_CONNECTION);
 725
 726	field = get_reg_field_value(value,
 727			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 728			EXTRA_CONNECTION_INFO);
 729
 730	field &= ~0x1;
 731
 732	set_reg_field_value(value,
 733		field,
 734		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 735		EXTRA_CONNECTION_INFO);
 736
 737	/* set audio for output signal */
 738	switch (signal) {
 739	case SIGNAL_TYPE_HDMI_TYPE_A:
 740		set_reg_field_value(value,
 741			1,
 742			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 743			HDMI_CONNECTION);
 744
 745		break;
 746
 747	case SIGNAL_TYPE_EDP:
 748	case SIGNAL_TYPE_DISPLAY_PORT:
 749	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 750		set_reg_field_value(value,
 751			1,
 752			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 753			DP_CONNECTION);
 754		break;
 755	default:
 756		BREAK_TO_DEBUGGER();
 757		break;
 758	}
 759
 760	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
 761
 762	/*  ACP Data - Supports AI  */
 763	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA);
 764
 765	set_reg_field_value(
 766		value,
 767		audio_info->flags.info.SUPPORT_AI,
 768		AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA,
 769		SUPPORTS_AI);
 770
 771	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value);
 772
 773	/*  Audio Descriptors   */
 774	/* pass through all formats */
 775	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
 776			format_index++) {
 777		audio_format_code =
 778			(AUDIO_FORMAT_CODE_FIRST + format_index);
 779
 780		/* those are unsupported, skip programming */
 781		if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
 782			audio_format_code == AUDIO_FORMAT_CODE_DST)
 783			continue;
 784
 785		value = 0;
 786
 787		/* check if supported */
 788		if (is_audio_format_supported(
 789				audio_info, audio_format_code, &index)) {
 790			const struct audio_mode *audio_mode =
 791					&audio_info->modes[index];
 792			union audio_sample_rates sample_rates =
 793					audio_mode->sample_rates;
 794			uint8_t byte2 = audio_mode->max_bit_rate;
 795			uint8_t channel_count = audio_mode->channel_count;
 796
 797			/* adjust specific properties */
 798			switch (audio_format_code) {
 799			case AUDIO_FORMAT_CODE_LINEARPCM: {
 800
 801				check_audio_bandwidth(
 802					crtc_info,
 803					dp_link_info,
 804					channel_count,
 805					signal,
 806					&sample_rates);
 807
 808				byte2 = audio_mode->sample_size;
 809
 810				set_reg_field_value(value,
 811						sample_rates.all,
 812						AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 813						SUPPORTED_FREQUENCIES_STEREO);
 814				}
 815				break;
 816			case AUDIO_FORMAT_CODE_AC3:
 817				is_ac3_supported = true;
 818				break;
 819			case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
 820			case AUDIO_FORMAT_CODE_DTS_HD:
 821			case AUDIO_FORMAT_CODE_MAT_MLP:
 822			case AUDIO_FORMAT_CODE_DST:
 823			case AUDIO_FORMAT_CODE_WMAPRO:
 824				byte2 = audio_mode->vendor_specific;
 825				break;
 826			default:
 827				break;
 828			}
 829
 830			/* fill audio format data */
 831			set_reg_field_value(value,
 832					channel_count - 1,
 833					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 834					MAX_CHANNELS);
 835
 836			set_reg_field_value(value,
 837					sample_rates.all,
 838					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 839					SUPPORTED_FREQUENCIES);
 840
 841			set_reg_field_value(value,
 842					byte2,
 843					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 844					DESCRIPTOR_BYTE_2);
 845		} /* if */
 846
 847		AZ_REG_WRITE(
 848				AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
 849				value);
 850	} /* for */
 851
 852	if (is_ac3_supported)
 853		/* todo: this reg global.  why program global register? */
 854		REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
 855				0x05);
 856
 857	/* check for 192khz/8-Ch support for HBR requirements */
 858	sample_rate.all = 0;
 859	sample_rate.rate.RATE_192 = 1;
 860
 861	check_audio_bandwidth(
 862		crtc_info,
 863		dp_link_info,
 864		8,
 865		signal,
 866		&sample_rate);
 867
 868	set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
 869
 870	/* Audio and Video Lipsync */
 871	set_video_latency(audio, audio_info->video_latency);
 872	set_audio_latency(audio, audio_info->audio_latency);
 873
 874	value = 0;
 875	set_reg_field_value(value, audio_info->manufacture_id,
 876		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 877		MANUFACTURER_ID);
 878
 879	set_reg_field_value(value, audio_info->product_id,
 880		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 881		PRODUCT_ID);
 882
 883	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 884		value);
 885
 886	value = 0;
 887
 888	/*get display name string length */
 889	while (audio_info->display_name[strlen++] != '\0') {
 890		if (strlen >=
 891		MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
 892			break;
 893		}
 894	set_reg_field_value(value, strlen,
 895		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 896		SINK_DESCRIPTION_LEN);
 897
 898	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 899		value);
 900	DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
 901		audio->inst, value, audio_info->display_name);
 902
 903	/*
 904	*write the port ID:
 905	*PORT_ID0 = display index
 906	*PORT_ID1 = 16bit BDF
 907	*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
 908	*/
 909
 910	value = 0;
 911
 912	set_reg_field_value(value, audio_info->port_id[0],
 913		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
 914		PORT_ID0);
 915
 916	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
 917
 918	value = 0;
 919	set_reg_field_value(value, audio_info->port_id[1],
 920		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
 921		PORT_ID1);
 922
 923	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
 924
 925	/*write the 18 char monitor string */
 926
 927	value = 0;
 928	set_reg_field_value(value, audio_info->display_name[0],
 929		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 930		DESCRIPTION0);
 931
 932	set_reg_field_value(value, audio_info->display_name[1],
 933		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 934		DESCRIPTION1);
 935
 936	set_reg_field_value(value, audio_info->display_name[2],
 937		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 938		DESCRIPTION2);
 939
 940	set_reg_field_value(value, audio_info->display_name[3],
 941		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 942		DESCRIPTION3);
 943
 944	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
 945
 946	value = 0;
 947	set_reg_field_value(value, audio_info->display_name[4],
 948		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 949		DESCRIPTION4);
 950
 951	set_reg_field_value(value, audio_info->display_name[5],
 952		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 953		DESCRIPTION5);
 954
 955	set_reg_field_value(value, audio_info->display_name[6],
 956		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 957		DESCRIPTION6);
 958
 959	set_reg_field_value(value, audio_info->display_name[7],
 960		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 961		DESCRIPTION7);
 962
 963	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
 964
 965	value = 0;
 966	set_reg_field_value(value, audio_info->display_name[8],
 967		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 968		DESCRIPTION8);
 969
 970	set_reg_field_value(value, audio_info->display_name[9],
 971		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 972		DESCRIPTION9);
 973
 974	set_reg_field_value(value, audio_info->display_name[10],
 975		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 976		DESCRIPTION10);
 977
 978	set_reg_field_value(value, audio_info->display_name[11],
 979		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 980		DESCRIPTION11);
 981
 982	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
 983
 984	value = 0;
 985	set_reg_field_value(value, audio_info->display_name[12],
 986		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 987		DESCRIPTION12);
 988
 989	set_reg_field_value(value, audio_info->display_name[13],
 990		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 991		DESCRIPTION13);
 992
 993	set_reg_field_value(value, audio_info->display_name[14],
 994		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 995		DESCRIPTION14);
 996
 997	set_reg_field_value(value, audio_info->display_name[15],
 998		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 999		DESCRIPTION15);
1000
1001	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
1002
1003	value = 0;
1004	set_reg_field_value(value, audio_info->display_name[16],
1005		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
1006		DESCRIPTION16);
1007
1008	set_reg_field_value(value, audio_info->display_name[17],
1009		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
1010		DESCRIPTION17);
1011
1012	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
1013	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
1014	set_reg_field_value(value, 0,
1015			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1016			CLOCK_GATING_DISABLE);
1017	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1018}
1019
1020/*
1021* todo: wall clk related functionality probably belong to clock_src.
1022*/
1023
1024/* search pixel clock value for Azalia HDMI Audio */
1025static void get_azalia_clock_info_hdmi(
1026	uint32_t crtc_pixel_clock_100hz,
1027	uint32_t actual_pixel_clock_100Hz,
1028	struct azalia_clock_info *azalia_clock_info)
1029{
1030	/* audio_dto_phase= 24 * 10,000;
1031	 *   24MHz in [100Hz] units */
1032	azalia_clock_info->audio_dto_phase =
1033			24 * 10000;
1034
1035	/* audio_dto_module = PCLKFrequency * 10,000;
1036	 *  [khz] -> [100Hz] */
1037	azalia_clock_info->audio_dto_module =
1038			actual_pixel_clock_100Hz;
1039}
1040
1041static void get_azalia_clock_info_dp(
1042	uint32_t requested_pixel_clock_100Hz,
1043	const struct audio_pll_info *pll_info,
1044	struct azalia_clock_info *azalia_clock_info)
1045{
1046	/* Reported dpDtoSourceClockInkhz value for
1047	 * DCE8 already adjusted for SS, do not need any
1048	 * adjustment here anymore
1049	 */
1050
1051	/*audio_dto_phase = 24 * 10,000;
1052	 * 24MHz in [100Hz] units */
1053	azalia_clock_info->audio_dto_phase = 24 * 10000;
1054
1055	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
1056	 *  [khz] ->[100Hz] */
1057	azalia_clock_info->audio_dto_module =
1058		pll_info->audio_dto_source_clock_in_khz * 10;
1059}
1060
1061void dce_aud_wall_dto_setup(
1062	struct audio *audio,
1063	enum signal_type signal,
1064	const struct audio_crtc_info *crtc_info,
1065	const struct audio_pll_info *pll_info)
1066{
1067	struct dce_audio *aud = DCE_AUD(audio);
1068
1069	struct azalia_clock_info clock_info = { 0 };
1070
1071	if (dc_is_hdmi_tmds_signal(signal)) {
1072		uint32_t src_sel;
1073
1074		/*DTO0 Programming goal:
1075		-generate 24MHz, 128*Fs from 24MHz
1076		-use DTO0 when an active HDMI port is connected
1077		(optionally a DP is connected) */
1078
1079		/* calculate DTO settings */
1080		get_azalia_clock_info_hdmi(
1081			crtc_info->requested_pixel_clock_100Hz,
1082			crtc_info->calculated_pixel_clock_100Hz,
1083			&clock_info);
1084
1085		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
1086				"calculated_pixel_clock_100Hz =%d\n"\
1087				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
1088				crtc_info->requested_pixel_clock_100Hz,\
1089				crtc_info->calculated_pixel_clock_100Hz,\
1090				clock_info.audio_dto_module,\
1091				clock_info.audio_dto_phase);
1092
1093		/* On TN/SI, Program DTO source select and DTO select before
1094		programming DTO modulo and DTO phase. These bits must be
1095		programmed first, otherwise there will be no HDMI audio at boot
1096		up. This is a HW sequence change (different from old ASICs).
1097		Caution when changing this programming sequence.
1098
1099		HDMI enabled, using DTO0
1100		program master CRTC for DTO0 */
1101		src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
1102		REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
1103			DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
1104			DCCG_AUDIO_DTO_SEL, 0);
1105
1106		/* module */
1107		REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
1108			DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
1109
1110		/* phase */
1111		REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
1112			DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
1113	} else {
1114		/*DTO1 Programming goal:
1115		-generate 24MHz, 512*Fs, 128*Fs from 24MHz
1116		-default is to used DTO1, and switch to DTO0 when an audio
1117		master HDMI port is connected
1118		-use as default for DP
1119
1120		calculate DTO settings */
1121		get_azalia_clock_info_dp(
1122			crtc_info->requested_pixel_clock_100Hz,
1123			pll_info,
1124			&clock_info);
1125
1126		/* Program DTO select before programming DTO modulo and DTO
1127		phase. default to use DTO1 */
1128
1129		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1130				DCCG_AUDIO_DTO_SEL, 1);
1131
1132			/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
1133			 * Select 512fs for DP TODO: web register definition
1134			 * does not match register header file
1135			 * DCE11 version it's commented out while DCE8 it's set to 1
1136			*/
1137
1138		/* module */
1139		REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
1140				DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
1141
1142		/* phase */
1143		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
1144				DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
1145
1146		if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO)
1147			REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1148				DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
1149
1150	}
1151}
1152
1153#if defined(CONFIG_DRM_AMD_DC_SI)
1154static void dce60_aud_wall_dto_setup(
1155	struct audio *audio,
1156	enum signal_type signal,
1157	const struct audio_crtc_info *crtc_info,
1158	const struct audio_pll_info *pll_info)
1159{
1160	struct dce_audio *aud = DCE_AUD(audio);
1161
1162	struct azalia_clock_info clock_info = { 0 };
1163
1164	if (dc_is_hdmi_signal(signal)) {
1165		uint32_t src_sel;
1166
1167		/*DTO0 Programming goal:
1168		-generate 24MHz, 128*Fs from 24MHz
1169		-use DTO0 when an active HDMI port is connected
1170		(optionally a DP is connected) */
1171
1172		/* calculate DTO settings */
1173		get_azalia_clock_info_hdmi(
1174			crtc_info->requested_pixel_clock_100Hz,
1175			crtc_info->calculated_pixel_clock_100Hz,
1176			&clock_info);
1177
1178		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
1179				"calculated_pixel_clock_100Hz =%d\n"\
1180				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
1181				crtc_info->requested_pixel_clock_100Hz,\
1182				crtc_info->calculated_pixel_clock_100Hz,\
1183				clock_info.audio_dto_module,\
1184				clock_info.audio_dto_phase);
1185
1186		/* On TN/SI, Program DTO source select and DTO select before
1187		programming DTO modulo and DTO phase. These bits must be
1188		programmed first, otherwise there will be no HDMI audio at boot
1189		up. This is a HW sequence change (different from old ASICs).
1190		Caution when changing this programming sequence.
1191
1192		HDMI enabled, using DTO0
1193		program master CRTC for DTO0 */
1194		src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
1195		REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
1196			DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
1197			DCCG_AUDIO_DTO_SEL, 0);
1198
1199		/* module */
1200		REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
1201			DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
1202
1203		/* phase */
1204		REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
1205			DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
1206	} else {
1207		/*DTO1 Programming goal:
1208		-generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
1209		-default is to used DTO1, and switch to DTO0 when an audio
1210		master HDMI port is connected
1211		-use as default for DP
1212
1213		calculate DTO settings */
1214		get_azalia_clock_info_dp(
1215			crtc_info->requested_pixel_clock_100Hz,
1216			pll_info,
1217			&clock_info);
1218
1219		/* Program DTO select before programming DTO modulo and DTO
1220		phase. default to use DTO1 */
1221
1222		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1223				DCCG_AUDIO_DTO_SEL, 1);
1224
1225			/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
1226			 * Cannot select 512fs for DP
1227			 *
1228			 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
1229			*/
1230
1231		/* module */
1232		REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
1233				DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
1234
1235		/* phase */
1236		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
1237				DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
1238
1239		/* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
1240
1241	}
1242}
1243#endif
1244
1245static bool dce_aud_endpoint_valid(struct audio *audio)
1246{
1247	uint32_t value;
1248	uint32_t port_connectivity;
1249
1250	value = AZ_REG_READ(
1251			AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1252
1253	port_connectivity = get_reg_field_value(value,
1254			AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1255			PORT_CONNECTIVITY);
1256
1257	return !(port_connectivity == 1);
1258}
1259
1260/* initialize HW state */
1261void dce_aud_hw_init(
1262		struct audio *audio)
1263{
1264	uint32_t value;
1265	struct dce_audio *aud = DCE_AUD(audio);
1266
1267	/* we only need to program the following registers once, so we only do
1268	it for the inst 0*/
1269	if (audio->inst != 0)
1270		return;
1271
1272	/* Suport R5 - 32khz
1273	 * Suport R6 - 44.1khz
1274	 * Suport R7 - 48khz
1275	 */
1276	/*disable clock gating before write to endpoint register*/
1277	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
1278	set_reg_field_value(value, 1,
1279			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1280			CLOCK_GATING_DISABLE);
1281	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1282	REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
1283			AUDIO_RATE_CAPABILITIES, 0x70);
1284
1285	/*Keep alive bit to verify HW block in BU. */
1286	REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
1287			CLKSTOP, 1,
1288			EPSS, 1);
1289	set_reg_field_value(value, 0,
1290			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1291			CLOCK_GATING_DISABLE);
1292	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1293}
1294
1295static const struct audio_funcs funcs = {
1296	.endpoint_valid = dce_aud_endpoint_valid,
1297	.hw_init = dce_aud_hw_init,
1298	.wall_dto_setup = dce_aud_wall_dto_setup,
1299	.az_enable = dce_aud_az_enable,
1300	.az_disable = dce_aud_az_disable,
1301	.az_configure = dce_aud_az_configure,
1302	.az_disable_hbr_audio = dce_aud_az_disable_hbr_audio,
1303	.destroy = dce_aud_destroy,
1304};
1305
1306#if defined(CONFIG_DRM_AMD_DC_SI)
1307static const struct audio_funcs dce60_funcs = {
1308	.endpoint_valid = dce_aud_endpoint_valid,
1309	.hw_init = dce_aud_hw_init,
1310	.wall_dto_setup = dce60_aud_wall_dto_setup,
1311	.az_enable = dce_aud_az_enable,
1312	.az_disable = dce_aud_az_disable,
1313	.az_configure = dce_aud_az_configure,
1314	.destroy = dce_aud_destroy,
1315};
1316#endif
1317
1318void dce_aud_destroy(struct audio **audio)
1319{
1320	struct dce_audio *aud = DCE_AUD(*audio);
1321
1322	kfree(aud);
1323	*audio = NULL;
1324}
1325
1326struct audio *dce_audio_create(
1327		struct dc_context *ctx,
1328		unsigned int inst,
1329		const struct dce_audio_registers *reg,
1330		const struct dce_audio_shift *shifts,
1331		const struct dce_audio_mask *masks
1332		)
1333{
1334	struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1335
1336	if (audio == NULL) {
1337		ASSERT_CRITICAL(audio);
1338		return NULL;
1339	}
1340
1341	audio->base.ctx = ctx;
1342	audio->base.inst = inst;
1343	audio->base.funcs = &funcs;
1344
1345	audio->regs = reg;
1346	audio->shifts = shifts;
1347	audio->masks = masks;
1348	return &audio->base;
1349}
1350
1351#if defined(CONFIG_DRM_AMD_DC_SI)
1352struct audio *dce60_audio_create(
1353		struct dc_context *ctx,
1354		unsigned int inst,
1355		const struct dce_audio_registers *reg,
1356		const struct dce_audio_shift *shifts,
1357		const struct dce_audio_mask *masks
1358		)
1359{
1360	struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1361
1362	if (audio == NULL) {
1363		ASSERT_CRITICAL(audio);
1364		return NULL;
1365	}
1366
1367	audio->base.ctx = ctx;
1368	audio->base.inst = inst;
1369	audio->base.funcs = &dce60_funcs;
1370
1371	audio->regs = reg;
1372	audio->shifts = shifts;
1373	audio->masks = masks;
1374	return &audio->base;
1375}
1376#endif