dcn30_dccg.h

 1/*
 2 * Copyright 2020 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DCN30_DCCG_H__
27#define __DCN30_DCCG_H__
28
29#include "dcn20/dcn20_dccg.h"
30
31
32#define DCCG_REG_LIST_DCN30() \
33	DCCG_REG_LIST_DCN2(),\
34	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
35	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
36	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
37	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
38	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
39	SR(PHYASYMCLK_CLOCK_CNTL),\
40	SR(PHYBSYMCLK_CLOCK_CNTL),\
41	SR(PHYCSYMCLK_CLOCK_CNTL)
42
43#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
44	DCCG_MASK_SH_LIST_DCN2(mask_sh),\
45	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
46	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
47	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
48	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
49	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
50	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
51	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
52	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
53
54struct dccg *dccg3_create(
55	struct dc_context *ctx,
56	const struct dccg_registers *regs,
57	const struct dccg_shift *dccg_shift,
58	const struct dccg_mask *dccg_mask);
59
60struct dccg *dccg30_create(
61	struct dc_context *ctx,
62	const struct dccg_registers *regs,
63	const struct dccg_shift *dccg_shift,
64	const struct dccg_mask *dccg_mask);
65
66#endif //__DCN30_DCCG_H__