dc_dmub_srv.h

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef _DMUB_DC_SRV_H_
 27#define _DMUB_DC_SRV_H_
 28
 29#include "dm_services_types.h"
 30#include "dmub/dmub_srv.h"
 31
 32struct dmub_srv;
 33struct dc;
 34struct pipe_ctx;
 35struct dc_crtc_timing_adjust;
 36struct dc_crtc_timing;
 37struct dc_state;
 38struct dc_surface_update;
 39
 40struct dc_reg_helper_state {
 41	bool gather_in_progress;
 42	uint32_t same_addr_count;
 43	bool should_burst_write;
 44	union dmub_rb_cmd cmd_data;
 45	unsigned int reg_seq_count;
 46};
 47
 48struct dc_dmub_srv {
 49	struct dmub_srv *dmub;
 50	struct dc_reg_helper_state reg_helper_offload;
 51
 52	struct dc_context *ctx;
 53	void *dm;
 54
 55	int32_t idle_exit_counter;
 56	union dmub_shared_state_ips_driver_signals driver_signals;
 57	bool idle_allowed;
 58	bool needs_idle_wake;
 59	bool cursor_offload_enabled;
 60};
 61
 62bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv);
 63
 64bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
 65
 66bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
 67		unsigned int count,
 68		union dmub_rb_cmd *cmd_list);
 69
 70bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
 71		enum dm_dmub_wait_type wait_type,
 72		union dmub_rb_cmd *cmd_list);
 73
 74bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);
 75
 76bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);
 77
 78bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 79				   unsigned int stream_mask);
 80
 81bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);
 82
 83bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);
 84
 85void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 86
 87void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);
 88
 89void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
 90bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);
 91
 92void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv);
 93void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);
 94void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 95void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 96void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
 97
 98bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);
 99
100void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);
101void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);
102
103void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);
104bool dc_dmub_check_min_version(struct dmub_srv *srv);
105
106void dc_dmub_srv_enable_dpia_trace(const struct dc *dc);
107void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index);
108
109bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);
110
111void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);
112
113/**
114 * dc_dmub_srv_set_power_state() - Sets the power state for DMUB service.
115 *
116 * Controls whether messaging the DMCUB or interfacing with it via HW register
117 * interaction is permittable.
118 *
119 * @dc_dmub_srv - The DC DMUB service pointer
120 * @power_state - the DC power state
121 */
122void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state);
123
124/**
125 * dc_dmub_srv_notify_fw_dc_power_state() - Notifies firmware of the DC power state.
126 *
127 * Differs from dc_dmub_srv_set_power_state in that it needs to access HW in order
128 * to message DMCUB of the state transition. Should come after the D0 exit and
129 * before D3 set power state.
130 *
131 * @dc_dmub_srv - The DC DMUB service pointer
132 * @power_state - the DC power state
133 */
134void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv,
135					  enum dc_acpi_cm_power_state power_state);
136
137/**
138 * @dc_dmub_srv_should_detect() - Checks if link detection is required.
139 *
140 * While in idle power states we may need driver to manually redetect in
141 * the case of a missing hotplug. Should be called from a polling timer.
142 *
143 * Return: true if redetection is required.
144 */
145bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv);
146
147/**
148 * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution.
149 *
150 * Refer to dc_wake_and_execute_dmub_cmd_list() for usage and limitations,
151 * This function is a convenience wrapper for a single command execution.
152 *
153 * @ctx: DC context
154 * @cmd: The command to send/receive
155 * @wait_type: The wait behavior for the execution
156 *
157 * Return: true on command submission success, false otherwise
158 */
159bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
160				  enum dm_dmub_wait_type wait_type);
161
162/**
163 * dc_wake_and_execute_dmub_cmd_list() - Wrapper for DMUB command list execution.
164 *
165 * If the DMCUB hardware was asleep then it wakes the DMUB before
166 * executing the command and attempts to re-enter if the command
167 * submission was successful.
168 *
169 * This should be the preferred command submission interface provided
170 * the DC lock is acquired.
171 *
172 * Entry/exit out of idle power optimizations would need to be
173 * manually performed otherwise through dc_allow_idle_optimizations().
174 *
175 * @ctx: DC context
176 * @count: Number of commands to send/receive
177 * @cmd: Array of commands to send
178 * @wait_type: The wait behavior for the execution
179 *
180 * Return: true on command submission success, false otherwise
181 */
182bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
183				       union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);
184
185/**
186 * dc_wake_and_execute_gpint()
187 *
188 * @ctx: DC context
189 * @command_code: The command ID to send to DMCUB
190 * @param: The parameter to message DMCUB
191 * @response: Optional response out value - may be NULL.
192 * @wait_type: The wait behavior for the execution
193 */
194bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
195			       uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type);
196
197void dc_dmub_srv_fams2_update_config(struct dc *dc,
198		struct dc_state *context,
199		bool enable);
200void dc_dmub_srv_fams2_drr_update(struct dc *dc,
201		uint32_t tg_inst,
202		uint32_t vtotal_min,
203		uint32_t vtotal_max,
204		uint32_t vtotal_mid,
205		uint32_t vtotal_mid_frame_num,
206		bool program_manual_trigger);
207void dc_dmub_srv_fams2_passthrough_flip(
208		struct dc *dc,
209		struct dc_state *state,
210		struct dc_stream_state *stream,
211		struct dc_surface_update *srf_updates,
212		int surface_count);
213
214bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv);
215bool dmub_lsdma_send_linear_copy_command(
216	struct dc_dmub_srv *dc_dmub_srv,
217	uint64_t src_addr,
218	uint64_t dst_addr,
219	uint32_t count);
220
221struct lsdma_linear_sub_window_copy_params {
222	uint32_t src_lo;
223	uint32_t src_hi;
224
225	uint32_t dst_lo;
226	uint32_t dst_hi;
227
228	uint32_t src_x        : 16;
229	uint32_t src_y        : 16;
230
231	uint32_t dst_x        : 16;
232	uint32_t dst_y        : 16;
233
234	uint32_t rect_x       : 16;
235	uint32_t rect_y       : 16;
236
237	uint32_t src_pitch    : 16;
238	uint32_t dst_pitch    : 16;
239
240	uint32_t src_slice_pitch;
241	uint32_t dst_slice_pitch;
242
243	uint32_t tmz              : 1;
244	uint32_t element_size     : 3;
245	uint32_t src_cache_policy : 3;
246	uint32_t dst_cache_policy : 3;
247	uint32_t padding          : 22;
248};
249
250bool dmub_lsdma_send_linear_sub_window_copy_command(
251	struct dc_dmub_srv *dc_dmub_srv,
252	struct lsdma_linear_sub_window_copy_params copy_data
253);
254bool dmub_lsdma_send_pio_copy_command(
255	struct dc_dmub_srv *dc_dmub_srv,
256	uint64_t src_addr,
257	uint64_t dst_addr,
258	uint32_t byte_count,
259	uint32_t overlap_disable);
260bool dmub_lsdma_send_pio_constfill_command(
261	struct dc_dmub_srv *dc_dmub_srv,
262	uint64_t dst_addr,
263	uint32_t byte_count,
264	uint32_t data);
265
266struct lsdma_send_tiled_to_tiled_copy_command_params {
267	uint64_t src_addr;
268	uint64_t dst_addr;
269
270	uint32_t src_x            : 16;
271	uint32_t src_y            : 16;
272
273	uint32_t dst_x            : 16;
274	uint32_t dst_y            : 16;
275
276	uint32_t src_width        : 16;
277	uint32_t dst_width        : 16;
278
279	uint32_t rect_x           : 16;
280	uint32_t rect_y           : 16;
281
282	uint32_t src_height       : 16;
283	uint32_t dst_height       : 16;
284
285	uint32_t data_format      : 6;
286	uint32_t swizzle_mode     : 5;
287	uint32_t element_size     : 3;
288	uint32_t dcc              : 1;
289	uint32_t tmz              : 1;
290	uint32_t read_compress    : 2;
291	uint32_t write_compress   : 2;
292	uint32_t max_com          : 2;
293	uint32_t max_uncom        : 1;
294	uint32_t padding          : 9;
295};
296
297bool dmub_lsdma_send_tiled_to_tiled_copy_command(
298	struct dc_dmub_srv *dc_dmub_srv,
299	struct lsdma_send_tiled_to_tiled_copy_command_params params);
300bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data);
301
302/**
303 * struct ips_residency_info - struct containing info from dmub_ips_residency_stats
304 *
305 * @ips_mode: The mode of IPS that the follow stats appertain to
306 * @residency_percent: The percentage of time spent in given IPS mode in millipercent
307 * @entry_counter: The number of entries made in to this IPS state
308 * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode
309 *                        in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.
310 * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode
311 *                          in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.
312 * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c
313 */
314struct ips_residency_info {
315	enum ips_residency_mode ips_mode;
316	unsigned int residency_percent;
317	unsigned int entry_counter;
318	unsigned int total_active_time_us[2];
319	unsigned int total_inactive_time_us[2];
320	unsigned int histogram[16];
321};
322
323bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement);
324
325bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst,
326					  struct dmub_ips_residency_info *driver_info,
327					  enum ips_residency_mode ips_mode);
328
329/**
330 * dc_dmub_srv_cursor_offload_init() - Enables or disables cursor offloading for a stream.
331 *
332 * @dc: pointer to DC object
333 */
334void dc_dmub_srv_cursor_offload_init(struct dc *dc);
335
336/**
337 * dc_dmub_srv_control_cursor_offload() - Enables or disables cursor offloading for a stream.
338 *
339 * @dc: pointer to DC object
340 * @context: the DC context to reference for pipe allocations
341 * @stream: the stream to control
342 * @enable: true to enable cursor offload, false to disable
343 */
344void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,
345					const struct dc_stream_state *stream, bool enable);
346
347/**
348 * dc_dmub_srv_program_cursor_now() - Requests immediate cursor programming for a given pipe.
349 *
350 * @dc: pointer to DC object
351 * @pipe: top-most pipe for a stream.
352 */
353void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe);
354
355/**
356 * dc_dmub_srv_is_cursor_offload_enabled() - Checks if cursor offload is supported.
357 *
358 * @dc: pointer to DC object
359 *
360 * Return: true if cursor offload is supported, false otherwise
361 */
362bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc);
363
364/**
365 * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required.
366 *
367 * @dc - pointer to DC object
368 */
369void dc_dmub_srv_release_hw(const struct dc *dc);
370
371/**
372 * dc_dmub_srv_log_preos_dmcub_info() - Logs preos dmcub fw info.
373 *
374 * @dc - pointer to DC object
375 */
376void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv);
377#endif /* _DMUB_DC_SRV_H_ */