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dc_dmub_srv.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dm_services.h" 27#include "dc.h" 28#include "dc_dmub_srv.h" 29#include "../dmub/dmub_srv.h" 30#include "dm_helpers.h" 31#include "dc_hw_types.h" 32#include "core_types.h" 33#include "../basics/conversion.h" 34#include "cursor_reg_cache.h" 35#include "resource.h" 36#include "clk_mgr.h" 37#include "dc_state_priv.h" 38#include "dc_plane_priv.h" 39 40#define CTX dc_dmub_srv->ctx 41#define DC_LOGGER CTX->logger 42#define GPINT_RETRY_NUM 20 43 44static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 45 struct dmub_srv *dmub) 46{ 47 dc_srv->dmub = dmub; 48 dc_srv->ctx = dc->ctx; 49} 50 51struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 52{ 53 struct dc_dmub_srv *dc_srv = 54 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 55 56 if (dc_srv == NULL) { 57 BREAK_TO_DEBUGGER(); 58 return NULL; 59 } 60 61 dc_dmub_srv_construct(dc_srv, dc, dmub); 62 63 return dc_srv; 64} 65 66void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 67{ 68 if (*dmub_srv) { 69 kfree(*dmub_srv); 70 *dmub_srv = NULL; 71 } 72} 73 74bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv) 75{ 76 struct dmub_srv *dmub; 77 struct dc_context *dc_ctx; 78 enum dmub_status status; 79 80 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 81 return false; 82 83 dc_ctx = dc_dmub_srv->ctx; 84 dmub = dc_dmub_srv->dmub; 85 86 do { 87 status = dmub_srv_wait_for_pending(dmub, 100000); 88 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 89 90 if (status != DMUB_STATUS_OK) { 91 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 92 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 93 } 94 95 return status == DMUB_STATUS_OK; 96} 97 98void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) 99{ 100 struct dmub_srv *dmub = dc_dmub_srv->dmub; 101 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 102 enum dmub_status status = DMUB_STATUS_OK; 103 104 status = dmub_srv_clear_inbox0_ack(dmub); 105 if (status != DMUB_STATUS_OK) { 106 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 107 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 108 } 109} 110 111void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) 112{ 113 struct dmub_srv *dmub = dc_dmub_srv->dmub; 114 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 115 enum dmub_status status = DMUB_STATUS_OK; 116 117 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 118 if (status != DMUB_STATUS_OK) { 119 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 120 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 121 } 122} 123 124void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv, 125 union dmub_inbox0_data_register data) 126{ 127 struct dmub_srv *dmub = dc_dmub_srv->dmub; 128 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 129 enum dmub_status status = DMUB_STATUS_OK; 130 131 status = dmub_srv_send_inbox0_cmd(dmub, data); 132 if (status != DMUB_STATUS_OK) { 133 DC_ERROR("Error sending INBOX0 cmd\n"); 134 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 135 } 136} 137 138static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 139 unsigned int count, 140 union dmub_rb_cmd *cmd_list) 141{ 142 struct dc_context *dc_ctx; 143 struct dmub_srv *dmub; 144 enum dmub_status status = DMUB_STATUS_OK; 145 int i; 146 147 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 148 return false; 149 150 dc_ctx = dc_dmub_srv->ctx; 151 dmub = dc_dmub_srv->dmub; 152 153 for (i = 0 ; i < count; i++) { 154 /* confirm no messages pending */ 155 do { 156 status = dmub_srv_wait_for_idle(dmub, 100000); 157 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 158 159 /* queue command */ 160 if (status == DMUB_STATUS_OK) 161 status = dmub_srv_reg_cmd_execute(dmub, &cmd_list[i]); 162 163 /* check for errors */ 164 if (status != DMUB_STATUS_OK) { 165 break; 166 } 167 } 168 169 if (status != DMUB_STATUS_OK) { 170 if (status != DMUB_STATUS_POWER_STATE_D3) { 171 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 172 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 173 } 174 return false; 175 } 176 177 return true; 178} 179 180static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 181 unsigned int count, 182 union dmub_rb_cmd *cmd_list) 183{ 184 struct dc_context *dc_ctx; 185 struct dmub_srv *dmub; 186 enum dmub_status status; 187 int i; 188 189 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 190 return false; 191 192 dc_ctx = dc_dmub_srv->ctx; 193 dmub = dc_dmub_srv->dmub; 194 195 for (i = 0 ; i < count; i++) { 196 // Queue command 197 if (!cmd_list[i].cmd_common.header.multi_cmd_pending || 198 dmub_rb_num_free(&dmub->inbox1.rb) >= count - i) { 199 status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 200 } else { 201 status = DMUB_STATUS_QUEUE_FULL; 202 } 203 204 if (status == DMUB_STATUS_QUEUE_FULL) { 205 /* Execute and wait for queue to become empty again. */ 206 status = dmub_srv_fb_cmd_execute(dmub); 207 if (status == DMUB_STATUS_POWER_STATE_D3) 208 return false; 209 210 do { 211 status = dmub_srv_wait_for_inbox_free(dmub, 100000, count - i); 212 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 213 214 /* Requeue the command. */ 215 status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 216 } 217 218 if (status != DMUB_STATUS_OK) { 219 if (status != DMUB_STATUS_POWER_STATE_D3) { 220 DC_ERROR("Error queueing DMUB command: status=%d\n", status); 221 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 222 } 223 return false; 224 } 225 } 226 227 status = dmub_srv_fb_cmd_execute(dmub); 228 if (status != DMUB_STATUS_OK) { 229 if (status != DMUB_STATUS_POWER_STATE_D3) { 230 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 231 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 232 } 233 return false; 234 } 235 236 return true; 237} 238 239bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 240 unsigned int count, 241 union dmub_rb_cmd *cmd_list) 242{ 243 bool res = false; 244 245 if (dc_dmub_srv && dc_dmub_srv->dmub) { 246 if (dc_dmub_srv->dmub->inbox_type == DMUB_CMD_INTERFACE_REG) { 247 res = dc_dmub_srv_reg_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 248 } else { 249 res = dc_dmub_srv_fb_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 250 } 251 252 if (res) 253 res = dmub_srv_update_inbox_status(dc_dmub_srv->dmub) == DMUB_STATUS_OK; 254 } 255 256 return res; 257} 258 259bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 260 enum dm_dmub_wait_type wait_type, 261 union dmub_rb_cmd *cmd_list) 262{ 263 struct dmub_srv *dmub; 264 enum dmub_status status; 265 266 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 267 return false; 268 269 dmub = dc_dmub_srv->dmub; 270 271 // Wait for DMUB to process command 272 if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 273 do { 274 status = dmub_srv_wait_for_idle(dmub, 100000); 275 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 276 277 if (status != DMUB_STATUS_OK) { 278 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 279 if (!dmub->debug.timeout_info.timeout_occured) { 280 dmub->debug.timeout_info.timeout_occured = true; 281 if (cmd_list) 282 dmub->debug.timeout_info.timeout_cmd = *cmd_list; 283 dmub->debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv->ctx); 284 } 285 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 286 return false; 287 } 288 289 // Copy data back from ring buffer into command 290 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY && cmd_list) { 291 dmub_srv_cmd_get_response(dc_dmub_srv->dmub, cmd_list); 292 } 293 } 294 295 return true; 296} 297 298bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 299{ 300 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type); 301} 302 303bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 304{ 305 if (!dc_dmub_srv_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list)) 306 return false; 307 308 return dc_dmub_srv_wait_for_idle(dc_dmub_srv, wait_type, cmd_list); 309} 310 311bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) 312{ 313 struct dmub_srv *dmub; 314 struct dc_context *dc_ctx; 315 union dmub_fw_boot_status boot_status; 316 enum dmub_status status; 317 318 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 319 return false; 320 321 dmub = dc_dmub_srv->dmub; 322 dc_ctx = dc_dmub_srv->ctx; 323 324 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 325 if (status != DMUB_STATUS_OK) { 326 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 327 return false; 328 } 329 330 return boot_status.bits.optimized_init_done; 331} 332 333bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 334 unsigned int stream_mask) 335{ 336 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 337 return false; 338 339 return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 340 stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); 341} 342 343bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 344{ 345 struct dmub_srv *dmub; 346 struct dc_context *dc_ctx; 347 union dmub_fw_boot_status boot_status; 348 enum dmub_status status; 349 350 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 351 return false; 352 353 dmub = dc_dmub_srv->dmub; 354 dc_ctx = dc_dmub_srv->ctx; 355 356 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 357 if (status != DMUB_STATUS_OK) { 358 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 359 return false; 360 } 361 362 return boot_status.bits.restore_required; 363} 364 365bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 366{ 367 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 368 return dmub_srv_get_outbox0_msg(dmub, entry); 369} 370 371void dc_dmub_trace_event_control(struct dc *dc, bool enable) 372{ 373 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 374} 375 376void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 377{ 378 union dmub_rb_cmd cmd = { 0 }; 379 380 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 381 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 382 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 383 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 384 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 385 386 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 387 388 // Send the command to the DMCUB. 389 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 390} 391 392void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 393{ 394 union dmub_rb_cmd cmd = { 0 }; 395 396 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 397 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 398 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 399 400 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 401 402 // Send the command to the DMCUB. 403 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 404} 405 406static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 407{ 408 uint8_t pipes = 0; 409 int i = 0; 410 411 for (i = 0; i < MAX_PIPES; i++) { 412 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 413 414 if (pipe->stream == stream && pipe->stream_res.tg) 415 pipes = i; 416 } 417 return pipes; 418} 419 420static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 421 struct pipe_ctx *head_pipe, 422 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 423{ 424 int j; 425 int pipe_idx = 0; 426 427 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 428 for (j = 0; j < dc->res_pool->pipe_count; j++) { 429 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 430 431 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 432 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 433 } 434 } 435 fams_pipe_data->pipe_count = pipe_idx; 436} 437 438bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 439{ 440 union dmub_rb_cmd cmd = { 0 }; 441 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 442 int i = 0, k = 0; 443 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 444 uint8_t visual_confirm_enabled; 445 struct dc_stream_status *stream_status = NULL; 446 447 if (dc == NULL) 448 return false; 449 450 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 451 452 // Format command. 453 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 454 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 455 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 456 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 457 458 if (should_manage_pstate) { 459 for (i = 0; i < dc->res_pool->pipe_count; i++) { 460 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 461 462 if (!pipe->stream) 463 continue; 464 465 /* If FAMS is being used to support P-State and there is a stream 466 * that does not use FAMS, we are in an FPO + VActive scenario. 467 * Assign vactive stretch margin in this case. 468 */ 469 stream_status = dc_state_get_stream_status(context, pipe->stream); 470 if (stream_status && !stream_status->fpo_in_use) { 471 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; 472 break; 473 } 474 } 475 } 476 477 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 478 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 479 480 if (!resource_is_pipe_type(pipe, OTG_MASTER)) 481 continue; 482 483 stream_status = dc_state_get_stream_status(context, pipe->stream); 484 if (stream_status && stream_status->fpo_in_use) { 485 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 486 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 487 488 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 489 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 490 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 491 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 492 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 493 k++; 494 } 495 } 496 cmd.fw_assisted_mclk_switch.header.payload_bytes = 497 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 498 499 // Send the command to the DMCUB. 500 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 501 502 return true; 503} 504 505void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv) 506{ 507 union dmub_rb_cmd cmd = { 0 }; 508 509 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 510 return; 511 512 memset(&cmd, 0, sizeof(cmd)); 513 514 /* Prepare fw command */ 515 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 516 cmd.query_feature_caps.header.sub_type = 0; 517 cmd.query_feature_caps.header.ret_status = 1; 518 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 519 520 /* If command was processed, copy feature caps to dmub srv */ 521 if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 522 cmd.query_feature_caps.header.ret_status == 0) { 523 memcpy(&dc_dmub_srv->dmub->feature_caps, 524 &cmd.query_feature_caps.query_feature_caps_data, 525 sizeof(struct dmub_feature_caps)); 526 } 527} 528 529void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 530{ 531 union dmub_rb_cmd cmd = { 0 }; 532 unsigned int panel_inst = 0; 533 534 if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) && 535 dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE) 536 return; 537 538 memset(&cmd, 0, sizeof(cmd)); 539 540 // Prepare fw command 541 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 542 cmd.visual_confirm_color.header.sub_type = 0; 543 cmd.visual_confirm_color.header.ret_status = 1; 544 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 545 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 546 547 // If command was processed, copy feature caps to dmub srv 548 if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 549 cmd.visual_confirm_color.header.ret_status == 0) { 550 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 551 &cmd.visual_confirm_color.visual_confirm_color_data, 552 sizeof(struct dmub_visual_confirm_color)); 553 } 554} 555 556/** 557 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 558 * 559 * @dc: [in] pointer to dc object 560 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 561 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 562 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 563 * @context: [in] DC state for access to phantom stream 564 * 565 * Populate the DMCUB SubVP command with DRR pipe info. All the information 566 * required for calculating the SubVP + DRR microschedule is populated here. 567 * 568 * High level algorithm: 569 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 570 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 571 * 3. Populate the drr_info with the min and max supported vtotal values 572 */ 573static void populate_subvp_cmd_drr_info(struct dc *dc, 574 struct dc_state *context, 575 struct pipe_ctx *subvp_pipe, 576 struct pipe_ctx *vblank_pipe, 577 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 578{ 579 struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream); 580 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 581 struct dc_crtc_timing *phantom_timing; 582 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 583 uint16_t drr_frame_us = 0; 584 uint16_t min_drr_supported_us = 0; 585 uint16_t max_drr_supported_us = 0; 586 uint16_t max_drr_vblank_us = 0; 587 uint16_t max_drr_mallregion_us = 0; 588 uint16_t mall_region_us = 0; 589 uint16_t prefetch_us = 0; 590 uint16_t subvp_active_us = 0; 591 uint16_t drr_active_us = 0; 592 uint16_t min_vtotal_supported = 0; 593 uint16_t max_vtotal_supported = 0; 594 595 if (!phantom_stream) 596 return; 597 598 phantom_timing = &phantom_stream->timing; 599 600 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 601 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 602 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 603 604 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 605 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 606 // P-State allow width and FW delays already included phantom_timing->v_addressable 607 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 608 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 609 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 610 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 611 (((uint64_t)drr_timing->h_total * 1000000))); 612 613 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 614 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 615 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 616 (((uint64_t)main_timing->pix_clk_100hz * 100))); 617 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 618 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 619 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 620 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 621 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 622 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 623 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 624 (((uint64_t)drr_timing->h_total * 1000000))); 625 626 /* When calculating the max vtotal supported for SubVP + DRR cases, add 627 * margin due to possible rounding errors (being off by 1 line in the 628 * FW calculation can incorrectly push the P-State switch to wait 1 frame 629 * longer). 630 */ 631 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 632 633 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 634 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 635 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 636} 637 638/** 639 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 640 * 641 * @dc: [in] current dc state 642 * @context: [in] new dc state 643 * @cmd: [in] DMUB cmd to be populated with SubVP info 644 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 645 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 646 * 647 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 648 * required to calculate the microschedule for SubVP + VBLANK case is stored in 649 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 650 * is a DRR display -- if it is make a call to populate drr_info. 651 */ 652static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 653 struct dc_state *context, 654 union dmub_rb_cmd *cmd, 655 struct pipe_ctx *vblank_pipe, 656 uint8_t cmd_pipe_index) 657{ 658 uint32_t i; 659 struct pipe_ctx *pipe = NULL; 660 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 661 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 662 663 // Find the SubVP pipe 664 for (i = 0; i < dc->res_pool->pipe_count; i++) { 665 pipe = &context->res_ctx.pipe_ctx[i]; 666 667 // We check for master pipe, but it shouldn't matter since we only need 668 // the pipe for timing info (stream should be same for any pipe splits) 669 if (!resource_is_pipe_type(pipe, OTG_MASTER) || 670 !resource_is_pipe_type(pipe, DPP_PIPE)) 671 continue; 672 673 // Find the SubVP pipe 674 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) 675 break; 676 } 677 678 pipe_data->mode = VBLANK; 679 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 680 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 681 vblank_pipe->stream->timing.v_front_porch; 682 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 683 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 684 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 685 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 686 pipe_data->pipe_config.vblank_data.vblank_end = 687 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 688 689 if (vblank_pipe->stream->ignore_msa_timing_param && 690 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed)) 691 populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data); 692} 693 694/** 695 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 696 * 697 * @dc: [in] current dc state 698 * @context: [in] new dc state 699 * @cmd: [in] DMUB cmd to be populated with SubVP info 700 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 701 * 702 * For SubVP + SubVP, we use a single vertical interrupt to start the 703 * microschedule for both SubVP pipes. In order for this to work correctly, the 704 * MALL REGION of both SubVP pipes must start at the same time. This function 705 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 706 * the shorter prefetch so that both MALL REGION's will start at the same time. 707 */ 708static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 709 struct dc_state *context, 710 union dmub_rb_cmd *cmd, 711 struct pipe_ctx *subvp_pipes[]) 712{ 713 uint32_t subvp0_prefetch_us = 0; 714 uint32_t subvp1_prefetch_us = 0; 715 uint32_t prefetch_delta_us = 0; 716 struct dc_stream_state *phantom_stream0 = NULL; 717 struct dc_stream_state *phantom_stream1 = NULL; 718 struct dc_crtc_timing *phantom_timing0 = NULL; 719 struct dc_crtc_timing *phantom_timing1 = NULL; 720 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 721 722 phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]->stream); 723 if (!phantom_stream0) 724 return; 725 726 phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]->stream); 727 if (!phantom_stream1) 728 return; 729 730 phantom_timing0 = &phantom_stream0->timing; 731 phantom_timing1 = &phantom_stream1->timing; 732 733 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 734 (uint64_t)phantom_timing0->h_total * 1000000), 735 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 736 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 737 (uint64_t)phantom_timing1->h_total * 1000000), 738 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 739 740 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 741 // should increase it's prefetch time to match the other 742 if (subvp0_prefetch_us > subvp1_prefetch_us) { 743 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 744 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 745 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 746 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 747 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 748 ((uint64_t)phantom_timing1->h_total * 1000000)); 749 750 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 751 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 752 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 753 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 754 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 755 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 756 ((uint64_t)phantom_timing0->h_total * 1000000)); 757 } 758} 759 760/** 761 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 762 * 763 * @dc: [in] current dc state 764 * @context: [in] new dc state 765 * @cmd: [in] DMUB cmd to be populated with SubVP info 766 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 767 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 768 * 769 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 770 * required to calculate the microschedule for the SubVP pipe is stored in the 771 * pipe_data of the DMCUB SubVP command. 772 */ 773static void populate_subvp_cmd_pipe_info(struct dc *dc, 774 struct dc_state *context, 775 union dmub_rb_cmd *cmd, 776 struct pipe_ctx *subvp_pipe, 777 uint8_t cmd_pipe_index) 778{ 779 uint32_t j; 780 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 781 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 782 struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream); 783 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 784 struct dc_crtc_timing *phantom_timing; 785 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 786 787 if (!phantom_stream) 788 return; 789 790 phantom_timing = &phantom_stream->timing; 791 792 pipe_data->mode = SUBVP; 793 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 794 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 795 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 796 pipe_data->pipe_config.subvp_data.main_vblank_start = 797 main_timing->v_total - main_timing->v_front_porch; 798 pipe_data->pipe_config.subvp_data.main_vblank_end = 799 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 800 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 801 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 802 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param && 803 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed); 804 805 /* Calculate the scaling factor from the src and dst height. 806 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 807 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 808 * 809 * Make sure to combine stream and plane scaling together. 810 */ 811 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 812 &out_num_stream, &out_den_stream); 813 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 814 &out_num_plane, &out_den_plane); 815 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 816 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 817 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 818 819 // Prefetch lines is equal to VACTIVE + BP + VSYNC 820 pipe_data->pipe_config.subvp_data.prefetch_lines = 821 phantom_timing->v_total - phantom_timing->v_front_porch; 822 823 // Round up 824 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 825 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 826 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 827 pipe_data->pipe_config.subvp_data.processing_delay_lines = 828 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 829 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 830 831 if (subvp_pipe->bottom_pipe) { 832 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 833 } else if (subvp_pipe->next_odm_pipe) { 834 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 835 } else { 836 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF; 837 } 838 839 // Find phantom pipe index based on phantom stream 840 for (j = 0; j < dc->res_pool->pipe_count; j++) { 841 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 842 843 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && 844 phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { 845 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 846 if (phantom_pipe->bottom_pipe) { 847 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 848 } else if (phantom_pipe->next_odm_pipe) { 849 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 850 } else { 851 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF; 852 } 853 break; 854 } 855 } 856} 857 858/** 859 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 860 * 861 * @dc: [in] current dc state 862 * @context: [in] new dc state 863 * @enable: [in] if true enables the pipes population 864 * 865 * This function loops through each pipe and populates the DMUB SubVP CMD info 866 * based on the pipe (e.g. SubVP, VBLANK). 867 */ 868void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 869 struct dc_state *context, 870 bool enable) 871{ 872 uint8_t cmd_pipe_index = 0; 873 uint32_t i; 874 uint8_t subvp_count = 0; 875 union dmub_rb_cmd cmd; 876 struct pipe_ctx *subvp_pipes[2]; 877 uint32_t wm_val_refclk = 0; 878 enum mall_stream_type pipe_mall_type; 879 880 memset(&cmd, 0, sizeof(cmd)); 881 // FW command for SUBVP 882 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 883 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 884 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 885 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 886 887 for (i = 0; i < dc->res_pool->pipe_count; i++) { 888 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 889 890 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 891 */ 892 if (resource_is_pipe_type(pipe, OTG_MASTER) && 893 resource_is_pipe_type(pipe, DPP_PIPE) && 894 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) 895 subvp_pipes[subvp_count++] = pipe; 896 } 897 898 if (enable) { 899 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 900 for (i = 0; i < dc->res_pool->pipe_count; i++) { 901 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 902 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe); 903 904 if (!pipe->stream) 905 continue; 906 907 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 908 * Any ODM or MPC splits being used in SubVP will be handled internally in 909 * populate_subvp_cmd_pipe_info 910 */ 911 if (resource_is_pipe_type(pipe, OTG_MASTER) && 912 resource_is_pipe_type(pipe, DPP_PIPE) && 913 pipe_mall_type == SUBVP_MAIN) { 914 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 915 } else if (resource_is_pipe_type(pipe, OTG_MASTER) && 916 resource_is_pipe_type(pipe, DPP_PIPE) && 917 pipe_mall_type == SUBVP_NONE) { 918 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 919 // we run through DML without calculating "natural" P-state support 920 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 921 922 } 923 } 924 if (subvp_count == 2) { 925 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 926 } 927 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 928 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 929 930 // Store the original watermark value for this SubVP config so we can lower it when the 931 // MCLK switch starts 932 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 933 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 934 935 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 936 } 937 938 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 939} 940 941bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 942{ 943 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 944 return false; 945 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub); 946} 947 948void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 949{ 950 uint32_t i; 951 952 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 953 DC_LOG_ERROR("%s: invalid parameters.", __func__); 954 return; 955 } 956 957 DC_LOG_ERROR("%s: DMCUB error - collecting diagnostic data\n", __func__); 958 959 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv)) { 960 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 961 return; 962 } 963 964 DC_LOG_DEBUG("DMCUB STATE:"); 965 DC_LOG_DEBUG(" dmcub_version : %08x", dc_dmub_srv->dmub->debug.dmcub_version); 966 DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]); 967 DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]); 968 DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]); 969 DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]); 970 DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]); 971 DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]); 972 DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]); 973 DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]); 974 DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]); 975 DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]); 976 DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]); 977 DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]); 978 DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]); 979 DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]); 980 DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]); 981 DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]); 982 for (i = 0; i < DMUB_PC_SNAPSHOT_COUNT; i++) 983 DC_LOG_DEBUG(" pc[%d] : %08x", i, dc_dmub_srv->dmub->debug.pc[i]); 984 DC_LOG_DEBUG(" unk_fault_addr : %08x", dc_dmub_srv->dmub->debug.undefined_address_fault_addr); 985 DC_LOG_DEBUG(" inst_fault_addr : %08x", dc_dmub_srv->dmub->debug.inst_fetch_fault_addr); 986 DC_LOG_DEBUG(" data_fault_addr : %08x", dc_dmub_srv->dmub->debug.data_write_fault_addr); 987 DC_LOG_DEBUG(" inbox1_rptr : %08x", dc_dmub_srv->dmub->debug.inbox1_rptr); 988 DC_LOG_DEBUG(" inbox1_wptr : %08x", dc_dmub_srv->dmub->debug.inbox1_wptr); 989 DC_LOG_DEBUG(" inbox1_size : %08x", dc_dmub_srv->dmub->debug.inbox1_size); 990 DC_LOG_DEBUG(" inbox0_rptr : %08x", dc_dmub_srv->dmub->debug.inbox0_rptr); 991 DC_LOG_DEBUG(" inbox0_wptr : %08x", dc_dmub_srv->dmub->debug.inbox0_wptr); 992 DC_LOG_DEBUG(" inbox0_size : %08x", dc_dmub_srv->dmub->debug.inbox0_size); 993 DC_LOG_DEBUG(" outbox1_rptr : %08x", dc_dmub_srv->dmub->debug.outbox1_rptr); 994 DC_LOG_DEBUG(" outbox1_wptr : %08x", dc_dmub_srv->dmub->debug.outbox1_wptr); 995 DC_LOG_DEBUG(" outbox1_size : %08x", dc_dmub_srv->dmub->debug.outbox1_size); 996 DC_LOG_DEBUG(" is_enabled : %d", dc_dmub_srv->dmub->debug.is_dmcub_enabled); 997 DC_LOG_DEBUG(" is_soft_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_soft_reset); 998 DC_LOG_DEBUG(" is_secure_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_secure_reset); 999 DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en); 1000 DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled); 1001 DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled); 1002} 1003 1004static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 1005{ 1006 if (pipe_ctx->plane_state != NULL) { 1007 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 1008 resource_can_pipe_disable_cursor(pipe_ctx)) 1009 return false; 1010 } 1011 1012 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 1013 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 1014 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 1015 return true; 1016 1017 if (pipe_ctx->stream->link->replay_settings.config.replay_supported) 1018 return true; 1019 1020 return false; 1021} 1022 1023static void dc_build_cursor_update_payload0( 1024 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 1025 struct dmub_cmd_update_cursor_payload0 *payload) 1026{ 1027 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1028 unsigned int panel_inst = 0; 1029 1030 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 1031 pipe_ctx->stream->link, &panel_inst)) 1032 return; 1033 1034 /* Payload: Cursor Rect is built from position & attribute 1035 * x & y are obtained from postion 1036 */ 1037 payload->cursor_rect.x = hubp->cur_rect.x; 1038 payload->cursor_rect.y = hubp->cur_rect.y; 1039 /* w & h are obtained from attribute */ 1040 payload->cursor_rect.width = hubp->cur_rect.w; 1041 payload->cursor_rect.height = hubp->cur_rect.h; 1042 1043 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 1044 payload->pipe_idx = p_idx; 1045 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 1046 payload->panel_inst = panel_inst; 1047} 1048 1049static void dc_build_cursor_position_update_payload0( 1050 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 1051 const struct hubp *hubp, const struct dpp *dpp) 1052{ 1053 /* Hubp */ 1054 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 1055 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 1056 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 1057 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 1058 1059 /* dpp */ 1060 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 1061 pl->position_cfg.pipe_idx = p_idx; 1062} 1063 1064static void dc_build_cursor_attribute_update_payload1( 1065 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 1066 const struct hubp *hubp, const struct dpp *dpp) 1067{ 1068 /* Hubp */ 1069 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 1070 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 1071 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 1072 pl_A->aHubp.size.raw = hubp->att.size.raw; 1073 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 1074 1075 /* dpp */ 1076 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 1077} 1078 1079/** 1080 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 1081 * 1082 * @pCtx: [in] pipe context 1083 * @pipe_idx: [in] pipe index 1084 * 1085 * This function would store the cursor related information and pass it into 1086 * dmub 1087 */ 1088void dc_send_update_cursor_info_to_dmu( 1089 struct pipe_ctx *pCtx, uint8_t pipe_idx) 1090{ 1091 union dmub_rb_cmd cmd[2]; 1092 union dmub_cmd_update_cursor_info_data *update_cursor_info_0 = 1093 &cmd[0].update_cursor_info.update_cursor_info_data; 1094 1095 memset(cmd, 0, sizeof(cmd)); 1096 1097 if (!dc_dmub_should_update_cursor_data(pCtx)) 1098 return; 1099 /* 1100 * Since we use multi_cmd_pending for dmub command, the 2nd command is 1101 * only assigned to store cursor attributes info. 1102 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 1103 * is to store cursor position info. 1104 * 1105 * Command heaer type must be the same type if using multi_cmd_pending. 1106 * Besides, while process 2nd command in DMU, the sub type is useless. 1107 * So it's meanless to pass the sub type header with different type. 1108 */ 1109 1110 { 1111 /* Build Payload#0 Header */ 1112 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1113 cmd[0].update_cursor_info.header.payload_bytes = 1114 sizeof(cmd[0].update_cursor_info.update_cursor_info_data); 1115 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd 1116 1117 /* Prepare Payload */ 1118 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0); 1119 1120 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx, 1121 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1122 } 1123 { 1124 /* Build Payload#1 Header */ 1125 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1126 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1127 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command. 1128 1129 dc_build_cursor_attribute_update_payload1( 1130 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1131 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1132 1133 /* Combine 2nd cmds update_curosr_info to DMU */ 1134 dc_wake_and_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1135 } 1136} 1137 1138bool dc_dmub_check_min_version(struct dmub_srv *srv) 1139{ 1140 if (!srv->hw_funcs.is_psrsu_supported) 1141 return true; 1142 return srv->hw_funcs.is_psrsu_supported(srv); 1143} 1144 1145void dc_dmub_srv_enable_dpia_trace(const struct dc *dc) 1146{ 1147 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1148 1149 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 1150 DC_LOG_ERROR("%s: invalid parameters.", __func__); 1151 return; 1152 } 1153 1154 if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 1155 0x0010, NULL, DM_DMUB_WAIT_TYPE_WAIT)) { 1156 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1157 return; 1158 } 1159 1160 if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 1161 0x0000, NULL, DM_DMUB_WAIT_TYPE_WAIT)) { 1162 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1163 return; 1164 } 1165 1166 DC_LOG_DEBUG("Enabled DPIA trace\n"); 1167} 1168 1169void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index) 1170{ 1171 dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index); 1172} 1173 1174void dc_dmub_srv_cursor_offload_init(struct dc *dc) 1175{ 1176 struct dmub_rb_cmd_cursor_offload_init *init; 1177 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1178 union dmub_rb_cmd cmd; 1179 1180 if (!dc->config.enable_cursor_offload) 1181 return; 1182 1183 if (!dc_dmub_srv->dmub->meta_info.feature_bits.bits.cursor_offload_v1_support) 1184 return; 1185 1186 if (!dc_dmub_srv->dmub->cursor_offload_fb.gpu_addr || !dc_dmub_srv->dmub->cursor_offload_fb.cpu_addr) 1187 return; 1188 1189 if (!dc_dmub_srv->dmub->cursor_offload_v1) 1190 return; 1191 1192 if (!dc_dmub_srv->dmub->shared_state) 1193 return; 1194 1195 memset(&cmd, 0, sizeof(cmd)); 1196 1197 init = &cmd.cursor_offload_init; 1198 init->header.type = DMUB_CMD__CURSOR_OFFLOAD; 1199 init->header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_INIT; 1200 init->header.payload_bytes = sizeof(init->init_data); 1201 init->init_data.state_addr.quad_part = dc_dmub_srv->dmub->cursor_offload_fb.gpu_addr; 1202 init->init_data.state_size = dc_dmub_srv->dmub->cursor_offload_fb.size; 1203 1204 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1205 1206 dc_dmub_srv->cursor_offload_enabled = true; 1207} 1208 1209void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context, 1210 const struct dc_stream_state *stream, bool enable) 1211{ 1212 struct pipe_ctx const *pipe_ctx; 1213 struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl; 1214 union dmub_rb_cmd cmd; 1215 1216 if (!dc_dmub_srv_is_cursor_offload_enabled(dc)) 1217 return; 1218 1219 if (!stream) 1220 return; 1221 1222 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1223 if (!pipe_ctx || !pipe_ctx->stream_res.tg || pipe_ctx->stream != stream) 1224 return; 1225 1226 memset(&cmd, 0, sizeof(cmd)); 1227 1228 cntl = &cmd.cursor_offload_stream_ctnl; 1229 cntl->header.type = DMUB_CMD__CURSOR_OFFLOAD; 1230 cntl->header.sub_type = 1231 enable ? DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE : DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE; 1232 cntl->header.payload_bytes = sizeof(cntl->data); 1233 1234 cntl->data.otg_inst = pipe_ctx->stream_res.tg->inst; 1235 cntl->data.line_time_in_ns = 1u + (uint32_t)(div64_u64(stream->timing.h_total * 1000000ull, 1236 stream->timing.pix_clk_100hz / 10)); 1237 1238 cntl->data.v_total_max = stream->adjust.v_total_max > stream->timing.v_total ? 1239 stream->adjust.v_total_max : 1240 stream->timing.v_total; 1241 1242 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, 1243 enable ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT); 1244} 1245 1246void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe) 1247{ 1248 struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl; 1249 union dmub_rb_cmd cmd; 1250 1251 if (!dc_dmub_srv_is_cursor_offload_enabled(dc)) 1252 return; 1253 1254 if (!pipe || !pipe->stream || !pipe->stream_res.tg) 1255 return; 1256 1257 memset(&cmd, 0, sizeof(cmd)); 1258 1259 cntl = &cmd.cursor_offload_stream_ctnl; 1260 cntl->header.type = DMUB_CMD__CURSOR_OFFLOAD; 1261 cntl->header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM; 1262 cntl->header.payload_bytes = sizeof(cntl->data); 1263 cntl->data.otg_inst = pipe->stream_res.tg->inst; 1264 1265 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 1266} 1267 1268bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait) 1269{ 1270 struct dc_context *dc_ctx; 1271 enum dmub_status status; 1272 1273 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1274 return true; 1275 1276 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 1277 return true; 1278 1279 dc_ctx = dc_dmub_srv->ctx; 1280 1281 if (wait) { 1282 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) { 1283 do { 1284 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000); 1285 } while (status != DMUB_STATUS_OK); 1286 } else { 1287 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000); 1288 if (status != DMUB_STATUS_OK) { 1289 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status); 1290 return false; 1291 } 1292 } 1293 } else 1294 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub); 1295 1296 return true; 1297} 1298 1299static int count_active_streams(const struct dc *dc) 1300{ 1301 int i, count = 0; 1302 1303 for (i = 0; i < dc->current_state->stream_count; ++i) { 1304 struct dc_stream_state *stream = dc->current_state->streams[i]; 1305 1306 if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off)) 1307 count += 1; 1308 } 1309 1310 return count; 1311} 1312 1313static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) 1314{ 1315 volatile const struct dmub_shared_state_ips_fw *ips_fw; 1316 struct dc_dmub_srv *dc_dmub_srv; 1317 union dmub_rb_cmd cmd = {0}; 1318 1319 if (dc->debug.dmcub_emulation) 1320 return; 1321 1322 if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub) 1323 return; 1324 1325 dc_dmub_srv = dc->ctx->dmub_srv; 1326 ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1327 1328 memset(&cmd, 0, sizeof(cmd)); 1329 cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT; 1330 cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE; 1331 cmd.idle_opt_notify_idle.header.payload_bytes = 1332 sizeof(cmd.idle_opt_notify_idle) - 1333 sizeof(cmd.idle_opt_notify_idle.header); 1334 1335 cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle; 1336 1337 if (dc->work_arounds.skip_psr_ips_crtc_disable) 1338 cmd.idle_opt_notify_idle.cntl_data.skip_otg_disable = true; 1339 1340 if (allow_idle) { 1341 volatile struct dmub_shared_state_ips_driver *ips_driver = 1342 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver; 1343 union dmub_shared_state_ips_driver_signals new_signals; 1344 1345 DC_LOG_IPS( 1346 "%s wait idle (ips1_commit=%u ips2_commit=%u)", 1347 __func__, 1348 ips_fw->signals.bits.ips1_commit, 1349 ips_fw->signals.bits.ips2_commit); 1350 1351 dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL); 1352 1353 memset(&new_signals, 0, sizeof(new_signals)); 1354 1355 new_signals.bits.allow_idle = 1; /* always set */ 1356 1357 if (dc->config.disable_ips == DMUB_IPS_ENABLE || 1358 dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) { 1359 new_signals.bits.allow_pg = 1; 1360 new_signals.bits.allow_ips1 = 1; 1361 new_signals.bits.allow_ips2 = 1; 1362 new_signals.bits.allow_z10 = 1; 1363 // New in IPSv2.0 1364 new_signals.bits.allow_ips1z8 = 1; 1365 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) { 1366 new_signals.bits.allow_ips1 = 1; 1367 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) { 1368 // IPSv1.0 only 1369 new_signals.bits.allow_pg = 1; 1370 new_signals.bits.allow_ips1 = 1; 1371 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) { 1372 // IPSv1.0 only 1373 new_signals.bits.allow_pg = 1; 1374 new_signals.bits.allow_ips1 = 1; 1375 new_signals.bits.allow_ips2 = 1; 1376 } else if (dc->config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) { 1377 /* TODO: Move this logic out to hwseq */ 1378 if (count_active_streams(dc) == 0) { 1379 /* IPS2 - Display off */ 1380 new_signals.bits.allow_pg = 1; 1381 new_signals.bits.allow_ips1 = 1; 1382 new_signals.bits.allow_ips2 = 1; 1383 new_signals.bits.allow_z10 = 1; 1384 // New in IPSv2.0 1385 new_signals.bits.allow_ips1z8 = 1; 1386 } else { 1387 /* RCG only */ 1388 new_signals.bits.allow_pg = 0; 1389 new_signals.bits.allow_ips1 = 1; 1390 new_signals.bits.allow_ips2 = 0; 1391 new_signals.bits.allow_z10 = 0; 1392 } 1393 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_Z8_RETENTION) { 1394 new_signals.bits.allow_pg = 1; 1395 new_signals.bits.allow_ips1 = 1; 1396 new_signals.bits.allow_ips2 = 1; 1397 new_signals.bits.allow_z10 = 1; 1398 } 1399 // Setting RCG allow bits (IPSv2.0) 1400 if (dc->config.disable_ips_rcg == DMUB_IPS_RCG_ENABLE) { 1401 new_signals.bits.allow_ips0_rcg = 1; 1402 new_signals.bits.allow_ips1_rcg = 1; 1403 } else if (dc->config.disable_ips_rcg == DMUB_IPS0_RCG_DISABLE) { 1404 new_signals.bits.allow_ips1_rcg = 1; 1405 } else if (dc->config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) { 1406 new_signals.bits.allow_ips0_rcg = 1; 1407 } 1408 // IPS dynamic allow bits (IPSv2 change, vpb use case) 1409 if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) { 1410 new_signals.bits.allow_dynamic_ips1 = 1; 1411 } else if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) { 1412 new_signals.bits.allow_dynamic_ips1 = 1; 1413 new_signals.bits.allow_dynamic_ips1_z8 = 1; 1414 } 1415 ips_driver->signals = new_signals; 1416 dc_dmub_srv->driver_signals = ips_driver->signals; 1417 } 1418 1419 DC_LOG_IPS( 1420 "%s send allow_idle=%d (ips1_commit=%u ips2_commit=%u)", 1421 __func__, 1422 allow_idle, 1423 ips_fw->signals.bits.ips1_commit, 1424 ips_fw->signals.bits.ips2_commit); 1425 1426 /* NOTE: This does not use the "wake" interface since this is part of the wake path. */ 1427 /* We also do not perform a wait since DMCUB could enter idle after the notification. */ 1428 dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT); 1429 1430 /* Register access should stop at this point. */ 1431 if (allow_idle) 1432 dc_dmub_srv->needs_idle_wake = true; 1433} 1434 1435static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) 1436{ 1437 struct dc_dmub_srv *dc_dmub_srv; 1438 uint32_t rcg_exit_count = 0, ips1_exit_count = 0, ips2_exit_count = 0, ips1z8_exit_count = 0; 1439 1440 if (dc->debug.dmcub_emulation) 1441 return; 1442 1443 if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub) 1444 return; 1445 1446 dc_dmub_srv = dc->ctx->dmub_srv; 1447 1448 if (dc->clk_mgr->funcs->exit_low_power_state) { 1449 volatile const struct dmub_shared_state_ips_fw *ips_fw = 1450 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1451 volatile struct dmub_shared_state_ips_driver *ips_driver = 1452 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver; 1453 union dmub_shared_state_ips_driver_signals prev_driver_signals = ips_driver->signals; 1454 1455 rcg_exit_count = ips_fw->rcg_exit_count; 1456 ips1_exit_count = ips_fw->ips1_exit_count; 1457 ips2_exit_count = ips_fw->ips2_exit_count; 1458 ips1z8_exit_count = ips_fw->ips1_z8ret_exit_count; 1459 1460 ips_driver->signals.all = 0; 1461 dc_dmub_srv->driver_signals = ips_driver->signals; 1462 1463 DC_LOG_IPS( 1464 "%s (allow ips1=%u ips2=%u) (commit ips1=%u ips2=%u ips1z8=%u) (count rcg=%u ips1=%u ips2=%u ips1_z8=%u)", 1465 __func__, 1466 ips_driver->signals.bits.allow_ips1, 1467 ips_driver->signals.bits.allow_ips2, 1468 ips_fw->signals.bits.ips1_commit, 1469 ips_fw->signals.bits.ips2_commit, 1470 ips_fw->signals.bits.ips1z8_commit, 1471 ips_fw->rcg_entry_count, 1472 ips_fw->ips1_entry_count, 1473 ips_fw->ips2_entry_count, 1474 ips_fw->ips1_z8ret_entry_count); 1475 1476 /* Note: register access has technically not resumed for DCN here, but we 1477 * need to be message PMFW through our standard register interface. 1478 */ 1479 dc_dmub_srv->needs_idle_wake = false; 1480 1481 if (!dc->caps.ips_v2_support && ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) && 1482 (!dc->debug.optimize_ips_handshake || 1483 ips_fw->signals.bits.ips2_commit || !ips_fw->signals.bits.in_idle))) { 1484 DC_LOG_IPS( 1485 "wait IPS2 eval (ips1_commit=%u ips2_commit=%u )", 1486 ips_fw->signals.bits.ips1_commit, 1487 ips_fw->signals.bits.ips2_commit); 1488 1489 if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit) 1490 udelay(dc->debug.ips2_eval_delay_us); 1491 1492 DC_LOG_IPS( 1493 "exit IPS2 #1 (ips1_commit=%u ips2_commit=%u)", 1494 ips_fw->signals.bits.ips1_commit, 1495 ips_fw->signals.bits.ips2_commit); 1496 1497 // Tell PMFW to exit low power state 1498 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr); 1499 1500 if (ips_fw->signals.bits.ips2_commit) { 1501 1502 DC_LOG_IPS( 1503 "wait IPS2 entry delay (ips1_commit=%u ips2_commit=%u)", 1504 ips_fw->signals.bits.ips1_commit, 1505 ips_fw->signals.bits.ips2_commit); 1506 1507 // Wait for IPS2 entry upper bound 1508 udelay(dc->debug.ips2_entry_delay_us); 1509 1510 DC_LOG_IPS( 1511 "exit IPS2 #2 (ips1_commit=%u ips2_commit=%u)", 1512 ips_fw->signals.bits.ips1_commit, 1513 ips_fw->signals.bits.ips2_commit); 1514 1515 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr); 1516 1517 DC_LOG_IPS( 1518 "wait IPS2 commit clear (ips1_commit=%u ips2_commit=%u)", 1519 ips_fw->signals.bits.ips1_commit, 1520 ips_fw->signals.bits.ips2_commit); 1521 1522 while (ips_fw->signals.bits.ips2_commit) 1523 udelay(1); 1524 1525 DC_LOG_IPS( 1526 "wait hw_pwr_up (ips1_commit=%u ips2_commit=%u)", 1527 ips_fw->signals.bits.ips1_commit, 1528 ips_fw->signals.bits.ips2_commit); 1529 1530 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true)) 1531 ASSERT(0); 1532 1533 DC_LOG_IPS( 1534 "resync inbox1 (ips1_commit=%u ips2_commit=%u)", 1535 ips_fw->signals.bits.ips1_commit, 1536 ips_fw->signals.bits.ips2_commit); 1537 1538 dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub); 1539 } 1540 } 1541 1542 dc_dmub_srv_notify_idle(dc, false); 1543 if (prev_driver_signals.bits.allow_ips1 || prev_driver_signals.all == 0) { 1544 DC_LOG_IPS( 1545 "wait for IPS1 commit clear (ips1_commit=%u ips2_commit=%u ips1z8=%u)", 1546 ips_fw->signals.bits.ips1_commit, 1547 ips_fw->signals.bits.ips2_commit, 1548 ips_fw->signals.bits.ips1z8_commit); 1549 1550 while (ips_fw->signals.bits.ips1_commit) 1551 udelay(1); 1552 1553 DC_LOG_IPS( 1554 "wait for IPS1 commit clear done (ips1_commit=%u ips2_commit=%u ips1z8=%u)", 1555 ips_fw->signals.bits.ips1_commit, 1556 ips_fw->signals.bits.ips2_commit, 1557 ips_fw->signals.bits.ips1z8_commit); 1558 } 1559 } 1560 1561 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true)) 1562 ASSERT(0); 1563 1564 DC_LOG_IPS("%s exit (count rcg=%u ips1=%u ips2=%u ips1z8=%u)", 1565 __func__, 1566 rcg_exit_count, 1567 ips1_exit_count, 1568 ips2_exit_count, 1569 ips1z8_exit_count); 1570} 1571 1572void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state) 1573{ 1574 struct dmub_srv *dmub; 1575 1576 if (!dc_dmub_srv) 1577 return; 1578 1579 dmub = dc_dmub_srv->dmub; 1580 1581 if (power_state == DC_ACPI_CM_POWER_STATE_D0) 1582 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0); 1583 else 1584 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3); 1585} 1586 1587void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, 1588 enum dc_acpi_cm_power_state power_state) 1589{ 1590 union dmub_rb_cmd cmd; 1591 1592 if (!dc_dmub_srv) 1593 return; 1594 1595 memset(&cmd, 0, sizeof(cmd)); 1596 1597 cmd.idle_opt_set_dc_power_state.header.type = DMUB_CMD__IDLE_OPT; 1598 cmd.idle_opt_set_dc_power_state.header.sub_type = DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE; 1599 cmd.idle_opt_set_dc_power_state.header.payload_bytes = 1600 sizeof(cmd.idle_opt_set_dc_power_state) - sizeof(cmd.idle_opt_set_dc_power_state.header); 1601 1602 if (power_state == DC_ACPI_CM_POWER_STATE_D0) { 1603 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D0; 1604 } else if (power_state == DC_ACPI_CM_POWER_STATE_D3) { 1605 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D3; 1606 } else { 1607 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN; 1608 } 1609 1610 dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1611} 1612 1613bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) 1614{ 1615 volatile const struct dmub_shared_state_ips_fw *ips_fw; 1616 bool reallow_idle = false, should_detect = false; 1617 1618 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1619 return false; 1620 1621 if (dc_dmub_srv->dmub->shared_state && 1622 dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) { 1623 ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1624 return ips_fw->signals.bits.detection_required; 1625 } 1626 1627 /* Detection may require reading scratch 0 - exit out of idle prior to the read. */ 1628 if (dc_dmub_srv->idle_allowed) { 1629 dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false); 1630 reallow_idle = true; 1631 } 1632 1633 should_detect = dmub_srv_should_detect(dc_dmub_srv->dmub); 1634 1635 /* Re-enter idle if we're not about to immediately redetect links. */ 1636 if (!should_detect && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1637 !dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle) 1638 dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true); 1639 1640 return should_detect; 1641} 1642 1643void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle) 1644{ 1645 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1646 1647 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1648 return; 1649 1650 allow_idle &= (!dc->debug.ips_disallow_entry); 1651 1652 if (dc_dmub_srv->idle_allowed == allow_idle) 1653 return; 1654 1655 DC_LOG_IPS("%s state change: old=%d new=%d", __func__, dc_dmub_srv->idle_allowed, allow_idle); 1656 1657 /* 1658 * Entering a low power state requires a driver notification. 1659 * Powering up the hardware requires notifying PMFW and DMCUB. 1660 * Clearing the driver idle allow requires a DMCUB command. 1661 * DMCUB commands requires the DMCUB to be powered up and restored. 1662 */ 1663 1664 if (!allow_idle) { 1665 dc_dmub_srv->idle_exit_counter += 1; 1666 1667 dc_dmub_srv_exit_low_power_state(dc); 1668 /* 1669 * Idle is considered fully exited only after the sequence above 1670 * fully completes. If we have a race of two threads exiting 1671 * at the same time then it's safe to perform the sequence 1672 * twice as long as we're not re-entering. 1673 * 1674 * Infinite command submission is avoided by using the 1675 * dm_execute_dmub_cmd submission instead of the "wake" helpers. 1676 */ 1677 dc_dmub_srv->idle_allowed = false; 1678 1679 dc_dmub_srv->idle_exit_counter -= 1; 1680 if (dc_dmub_srv->idle_exit_counter < 0) { 1681 ASSERT(0); 1682 dc_dmub_srv->idle_exit_counter = 0; 1683 } 1684 } else { 1685 /* Consider idle as notified prior to the actual submission to 1686 * prevent multiple entries. */ 1687 dc_dmub_srv->idle_allowed = true; 1688 1689 dc_dmub_srv_notify_idle(dc, allow_idle); 1690 } 1691} 1692 1693bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, 1694 enum dm_dmub_wait_type wait_type) 1695{ 1696 return dc_wake_and_execute_dmub_cmd_list(ctx, 1, cmd, wait_type); 1697} 1698 1699bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, 1700 union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 1701{ 1702 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1703 bool result = false, reallow_idle = false; 1704 1705 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1706 return false; 1707 1708 if (count == 0) 1709 return true; 1710 1711 if (dc_dmub_srv->idle_allowed) { 1712 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false); 1713 reallow_idle = true; 1714 } 1715 1716 /* 1717 * These may have different implementations in DM, so ensure 1718 * that we guide it to the expected helper. 1719 */ 1720 if (count > 1) 1721 result = dm_execute_dmub_cmd_list(ctx, count, cmd, wait_type); 1722 else 1723 result = dm_execute_dmub_cmd(ctx, cmd, wait_type); 1724 1725 if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1726 !ctx->dc->debug.disable_dmub_reallow_idle) 1727 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); 1728 1729 return result; 1730} 1731 1732static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 1733 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type) 1734{ 1735 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1736 const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30; 1737 enum dmub_status status; 1738 1739 if (response) 1740 *response = 0; 1741 1742 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1743 return false; 1744 1745 status = dmub_srv_send_gpint_command(dc_dmub_srv->dmub, command_code, param, wait_us); 1746 if (status != DMUB_STATUS_OK) { 1747 if (status == DMUB_STATUS_TIMEOUT && wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT) 1748 return true; 1749 1750 return false; 1751 } 1752 1753 if (response && wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 1754 dmub_srv_get_gpint_response(dc_dmub_srv->dmub, response); 1755 1756 return true; 1757} 1758 1759bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 1760 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type) 1761{ 1762 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1763 bool result = false, reallow_idle = false; 1764 1765 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1766 return false; 1767 1768 if (dc_dmub_srv->idle_allowed) { 1769 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false); 1770 reallow_idle = true; 1771 } 1772 1773 result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type); 1774 1775 if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1776 !ctx->dc->debug.disable_dmub_reallow_idle) 1777 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); 1778 1779 return result; 1780} 1781 1782static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc, 1783 struct dc_state *context, 1784 bool enable) 1785{ 1786 uint8_t num_cmds = 1; 1787 uint32_t i; 1788 union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1]; 1789 struct dmub_rb_cmd_fams2 *global_cmd = &cmd[0].fams2_config; 1790 1791 memset(cmd, 0, sizeof(union dmub_rb_cmd) * (2 * MAX_STREAMS + 1)); 1792 /* fill in generic command header */ 1793 global_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1794 global_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1795 global_cmd->header.payload_bytes = 1796 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1797 1798 if (enable) { 1799 /* send global configuration parameters */ 1800 memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub_cmd_fams2_global_config)); 1801 1802 /* copy static feature configuration overrides */ 1803 global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery; 1804 global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug; 1805 global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip; 1806 1807 /* construct per-stream configs */ 1808 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { 1809 struct dmub_rb_cmd_fams2 *stream_base_cmd = &cmd[i+1].fams2_config; 1810 struct dmub_rb_cmd_fams2 *stream_sub_state_cmd = &cmd[i+1+context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config; 1811 1812 /* configure command header */ 1813 stream_base_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1814 stream_base_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1815 stream_base_cmd->header.payload_bytes = 1816 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1817 stream_base_cmd->header.multi_cmd_pending = 1; 1818 stream_sub_state_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1819 stream_sub_state_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1820 stream_sub_state_cmd->header.payload_bytes = 1821 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1822 stream_sub_state_cmd->header.multi_cmd_pending = 1; 1823 /* copy stream static base state */ 1824 memcpy(&stream_base_cmd->config, 1825 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], 1826 sizeof(union dmub_cmd_fams2_config)); 1827 /* copy stream static sub state */ 1828 memcpy(&stream_sub_state_cmd->config, 1829 &context->bw_ctx.bw.dcn.fams2_stream_sub_params[i], 1830 sizeof(union dmub_cmd_fams2_config)); 1831 } 1832 } 1833 1834 /* apply feature configuration based on current driver state */ 1835 global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2; 1836 global_cmd->config.global.features.bits.enable = enable; 1837 1838 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { 1839 /* set multi pending for global, and unset for last stream cmd */ 1840 global_cmd->header.multi_cmd_pending = 1; 1841 cmd[2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending = 0; 1842 num_cmds += 2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams; 1843 } 1844 1845 dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1846} 1847 1848static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc, 1849 struct dc_state *context, 1850 bool enable) 1851{ 1852 struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr; 1853 union dmub_rb_cmd cmd; 1854 uint32_t i; 1855 1856 memset(config, 0, sizeof(*config)); 1857 memset(&cmd, 0, sizeof(cmd)); 1858 1859 cmd.ib_fams2_config.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1860 cmd.ib_fams2_config.header.sub_type = DMUB_CMD__FAMS2_IB_CONFIG; 1861 1862 cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr; 1863 cmd.ib_fams2_config.ib_data.size = sizeof(*config); 1864 1865 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { 1866 /* copy static feature configuration overrides */ 1867 config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery; 1868 config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip; 1869 config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug; 1870 1871 /* send global configuration parameters */ 1872 memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config, 1873 sizeof(struct dmub_cmd_fams2_global_config)); 1874 1875 /* construct per-stream configs */ 1876 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { 1877 /* copy stream static base state */ 1878 memcpy(&config->stream_v1[i].base, 1879 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], 1880 sizeof(config->stream_v1[i].base)); 1881 1882 /* copy stream static sub-state */ 1883 memcpy(&config->stream_v1[i].sub_state, 1884 &context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[i], 1885 sizeof(config->stream_v1[i].sub_state)); 1886 } 1887 } 1888 1889 config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2; 1890 config->global.features.bits.enable = enable; 1891 1892 dm_execute_dmub_cmd_list(dc->ctx, 1, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1893} 1894 1895void dc_dmub_srv_fams2_update_config(struct dc *dc, 1896 struct dc_state *context, 1897 bool enable) 1898{ 1899 if (dc->debug.fams_version.major == 2) 1900 dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable); 1901 if (dc->debug.fams_version.major == 3) 1902 dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable); 1903} 1904 1905void dc_dmub_srv_fams2_drr_update(struct dc *dc, 1906 uint32_t tg_inst, 1907 uint32_t vtotal_min, 1908 uint32_t vtotal_max, 1909 uint32_t vtotal_mid, 1910 uint32_t vtotal_mid_frame_num, 1911 bool program_manual_trigger) 1912{ 1913 union dmub_rb_cmd cmd = { 0 }; 1914 1915 cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1916 cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE; 1917 cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst; 1918 cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 1919 cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 1920 cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid; 1921 cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid_frame_num = vtotal_mid_frame_num; 1922 cmd.fams2_drr_update.dmub_optc_state_req.program_manual_trigger = program_manual_trigger; 1923 1924 cmd.fams2_drr_update.header.payload_bytes = 1925 sizeof(cmd.fams2_drr_update) - sizeof(cmd.fams2_drr_update.header); 1926 1927 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1928} 1929 1930void dc_dmub_srv_fams2_passthrough_flip( 1931 struct dc *dc, 1932 struct dc_state *state, 1933 struct dc_stream_state *stream, 1934 struct dc_surface_update *srf_updates, 1935 int surface_count) 1936{ 1937 int plane_index; 1938 union dmub_rb_cmd cmds[MAX_PLANES]; 1939 struct dc_plane_address *address; 1940 struct dc_plane_state *plane_state; 1941 int num_cmds = 0; 1942 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 1943 1944 if (surface_count <= 0 || stream_status == NULL) 1945 return; 1946 1947 memset(cmds, 0, sizeof(union dmub_rb_cmd) * MAX_PLANES); 1948 1949 /* build command for each surface update */ 1950 for (plane_index = 0; plane_index < surface_count; plane_index++) { 1951 plane_state = srf_updates[plane_index].surface; 1952 address = &plane_state->address; 1953 1954 /* skip if there is no address update for plane */ 1955 if (!srf_updates[plane_index].flip_addr) 1956 continue; 1957 1958 /* build command header */ 1959 cmds[num_cmds].fams2_flip.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1960 cmds[num_cmds].fams2_flip.header.sub_type = DMUB_CMD__FAMS2_FLIP; 1961 cmds[num_cmds].fams2_flip.header.payload_bytes = 1962 sizeof(struct dmub_rb_cmd_fams2_flip) - sizeof(struct dmub_cmd_header); 1963 1964 /* for chaining multiple commands, all but last command should set to 1 */ 1965 cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1; 1966 1967 /* set topology info */ 1968 cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state); 1969 if (stream_status) 1970 cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst; 1971 1972 cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate; 1973 1974 /* build address info for command */ 1975 switch (address->type) { 1976 case PLN_ADDR_TYPE_GRAPHICS: 1977 if (address->grph.addr.quad_part == 0) { 1978 BREAK_TO_DEBUGGER(); 1979 break; 1980 } 1981 1982 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo = 1983 address->grph.meta_addr.low_part; 1984 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi = 1985 (uint16_t)address->grph.meta_addr.high_part; 1986 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo = 1987 address->grph.addr.low_part; 1988 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi = 1989 (uint16_t)address->grph.addr.high_part; 1990 break; 1991 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 1992 if (address->video_progressive.luma_addr.quad_part == 0 || 1993 address->video_progressive.chroma_addr.quad_part == 0) { 1994 BREAK_TO_DEBUGGER(); 1995 break; 1996 } 1997 1998 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo = 1999 address->video_progressive.luma_meta_addr.low_part; 2000 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi = 2001 (uint16_t)address->video_progressive.luma_meta_addr.high_part; 2002 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_lo = 2003 address->video_progressive.chroma_meta_addr.low_part; 2004 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_hi = 2005 (uint16_t)address->video_progressive.chroma_meta_addr.high_part; 2006 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo = 2007 address->video_progressive.luma_addr.low_part; 2008 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi = 2009 (uint16_t)address->video_progressive.luma_addr.high_part; 2010 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_lo = 2011 address->video_progressive.chroma_addr.low_part; 2012 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_hi = 2013 (uint16_t)address->video_progressive.chroma_addr.high_part; 2014 break; 2015 default: 2016 // Should never be hit 2017 BREAK_TO_DEBUGGER(); 2018 break; 2019 } 2020 2021 num_cmds++; 2022 } 2023 2024 if (num_cmds > 0) { 2025 cmds[num_cmds - 1].fams2_flip.header.multi_cmd_pending = 0; 2026 dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT); 2027 } 2028} 2029 2030 2031bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement) 2032{ 2033 union dmub_rb_cmd cmd; 2034 2035 memset(&cmd, 0, sizeof(cmd)); 2036 2037 cmd.ips_residency_cntl.header.type = DMUB_CMD__IPS; 2038 cmd.ips_residency_cntl.header.sub_type = DMUB_CMD__IPS_RESIDENCY_CNTL; 2039 cmd.ips_residency_cntl.header.payload_bytes = sizeof(struct dmub_cmd_ips_residency_cntl_data); 2040 2041 // only panel_inst=0 is supported at the moment 2042 cmd.ips_residency_cntl.cntl_data.panel_inst = panel_inst; 2043 cmd.ips_residency_cntl.cntl_data.start_measurement = start_measurement; 2044 2045 if (!dc_wake_and_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 2046 return false; 2047 2048 return true; 2049} 2050 2051bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, struct dmub_ips_residency_info *driver_info, 2052 enum ips_residency_mode ips_mode) 2053{ 2054 union dmub_rb_cmd cmd; 2055 uint32_t bytes = sizeof(struct dmub_ips_residency_info); 2056 2057 dmub_flush_buffer_mem(&ctx->dmub_srv->dmub->scratch_mem_fb); 2058 memset(&cmd, 0, sizeof(cmd)); 2059 2060 cmd.ips_query_residency_info.header.type = DMUB_CMD__IPS; 2061 cmd.ips_query_residency_info.header.sub_type = DMUB_CMD__IPS_QUERY_RESIDENCY_INFO; 2062 cmd.ips_query_residency_info.header.payload_bytes = sizeof(struct dmub_cmd_ips_query_residency_info_data); 2063 2064 cmd.ips_query_residency_info.info_data.dest.quad_part = ctx->dmub_srv->dmub->scratch_mem_fb.gpu_addr; 2065 cmd.ips_query_residency_info.info_data.size = bytes; 2066 cmd.ips_query_residency_info.info_data.panel_inst = panel_inst; 2067 cmd.ips_query_residency_info.info_data.ips_mode = (uint32_t)ips_mode; 2068 2069 if (!dc_wake_and_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) || 2070 cmd.ips_query_residency_info.header.ret_status == 0) 2071 return false; 2072 2073 // copy the result to the output since ret_status != 0 means the command returned data 2074 memcpy(driver_info, ctx->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes); 2075 2076 return true; 2077} 2078 2079bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv) 2080{ 2081 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2082 union dmub_rb_cmd cmd; 2083 enum dm_dmub_wait_type wait_type; 2084 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2085 bool result; 2086 2087 if (!dc_dmub_srv->dmub->feature_caps.lsdma_support_in_dmu) 2088 return false; 2089 2090 memset(&cmd, 0, sizeof(cmd)); 2091 2092 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2093 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_INIT_CONFIG; 2094 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2095 2096 lsdma_data->u.init_data.gpu_addr_base.quad_part = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.gpu_addr; 2097 lsdma_data->u.init_data.ring_size = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.size; 2098 2099 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2100 2101 if (!result) 2102 DC_ERROR("LSDMA Init failed in DMUB"); 2103 2104 return result; 2105} 2106 2107bool dmub_lsdma_send_linear_copy_command( 2108 struct dc_dmub_srv *dc_dmub_srv, 2109 uint64_t src_addr, 2110 uint64_t dst_addr, 2111 uint32_t count 2112) 2113{ 2114 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2115 union dmub_rb_cmd cmd; 2116 enum dm_dmub_wait_type wait_type; 2117 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2118 bool result; 2119 2120 memset(&cmd, 0, sizeof(cmd)); 2121 2122 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2123 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_LINEAR_COPY; 2124 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2125 2126 lsdma_data->u.linear_copy_data.count = count - 1; // LSDMA controller expects bytes to copy -1 2127 lsdma_data->u.linear_copy_data.src_lo = src_addr & 0xFFFFFFFF; 2128 lsdma_data->u.linear_copy_data.src_hi = (src_addr >> 32) & 0xFFFFFFFF; 2129 lsdma_data->u.linear_copy_data.dst_lo = dst_addr & 0xFFFFFFFF; 2130 lsdma_data->u.linear_copy_data.dst_hi = (dst_addr >> 32) & 0xFFFFFFFF; 2131 2132 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2133 2134 if (!result) 2135 DC_ERROR("LSDMA Linear Copy failed in DMUB"); 2136 2137 return result; 2138} 2139 2140bool dmub_lsdma_send_linear_sub_window_copy_command( 2141 struct dc_dmub_srv *dc_dmub_srv, 2142 struct lsdma_linear_sub_window_copy_params copy_data 2143) 2144{ 2145 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2146 union dmub_rb_cmd cmd; 2147 enum dm_dmub_wait_type wait_type; 2148 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2149 bool result; 2150 2151 memset(&cmd, 0, sizeof(cmd)); 2152 2153 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2154 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY; 2155 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2156 2157 lsdma_data->u.linear_sub_window_copy_data.tmz = copy_data.tmz; 2158 lsdma_data->u.linear_sub_window_copy_data.element_size = copy_data.element_size; 2159 lsdma_data->u.linear_sub_window_copy_data.src_lo = copy_data.src_lo; 2160 lsdma_data->u.linear_sub_window_copy_data.src_hi = copy_data.src_hi; 2161 lsdma_data->u.linear_sub_window_copy_data.src_x = copy_data.src_x; 2162 lsdma_data->u.linear_sub_window_copy_data.src_y = copy_data.src_y; 2163 lsdma_data->u.linear_sub_window_copy_data.src_pitch = copy_data.src_pitch; 2164 lsdma_data->u.linear_sub_window_copy_data.src_slice_pitch = copy_data.src_slice_pitch; 2165 lsdma_data->u.linear_sub_window_copy_data.dst_lo = copy_data.dst_lo; 2166 lsdma_data->u.linear_sub_window_copy_data.dst_hi = copy_data.dst_hi; 2167 lsdma_data->u.linear_sub_window_copy_data.dst_x = copy_data.dst_x; 2168 lsdma_data->u.linear_sub_window_copy_data.dst_y = copy_data.dst_y; 2169 lsdma_data->u.linear_sub_window_copy_data.dst_pitch = copy_data.dst_pitch; 2170 lsdma_data->u.linear_sub_window_copy_data.dst_slice_pitch = copy_data.dst_slice_pitch; 2171 lsdma_data->u.linear_sub_window_copy_data.rect_x = copy_data.rect_x; 2172 lsdma_data->u.linear_sub_window_copy_data.rect_y = copy_data.rect_y; 2173 lsdma_data->u.linear_sub_window_copy_data.src_cache_policy = copy_data.src_cache_policy; 2174 lsdma_data->u.linear_sub_window_copy_data.dst_cache_policy = copy_data.dst_cache_policy; 2175 2176 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2177 2178 if (!result) 2179 DC_ERROR("LSDMA Linear Sub Window Copy failed in DMUB"); 2180 2181 return result; 2182} 2183 2184bool dmub_lsdma_send_tiled_to_tiled_copy_command( 2185 struct dc_dmub_srv *dc_dmub_srv, 2186 struct lsdma_send_tiled_to_tiled_copy_command_params params 2187) 2188{ 2189 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2190 union dmub_rb_cmd cmd; 2191 enum dm_dmub_wait_type wait_type; 2192 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2193 bool result; 2194 2195 memset(&cmd, 0, sizeof(cmd)); 2196 2197 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2198 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_TILED_TO_TILED_COPY; 2199 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2200 2201 lsdma_data->u.tiled_copy_data.src_addr_lo = params.src_addr & 0xFFFFFFFF; 2202 lsdma_data->u.tiled_copy_data.src_addr_hi = (params.src_addr >> 32) & 0xFFFFFFFF; 2203 lsdma_data->u.tiled_copy_data.dst_addr_lo = params.dst_addr & 0xFFFFFFFF; 2204 lsdma_data->u.tiled_copy_data.dst_addr_hi = (params.dst_addr >> 32) & 0xFFFFFFFF; 2205 lsdma_data->u.tiled_copy_data.src_x = params.src_x; 2206 lsdma_data->u.tiled_copy_data.src_y = params.src_y; 2207 lsdma_data->u.tiled_copy_data.dst_x = params.dst_x; 2208 lsdma_data->u.tiled_copy_data.dst_y = params.dst_y; 2209 lsdma_data->u.tiled_copy_data.src_width = params.src_width; 2210 lsdma_data->u.tiled_copy_data.dst_width = params.dst_width; 2211 lsdma_data->u.tiled_copy_data.src_swizzle_mode = params.swizzle_mode; 2212 lsdma_data->u.tiled_copy_data.dst_swizzle_mode = params.swizzle_mode; 2213 lsdma_data->u.tiled_copy_data.src_element_size = params.element_size; 2214 lsdma_data->u.tiled_copy_data.dst_element_size = params.element_size; 2215 lsdma_data->u.tiled_copy_data.rect_x = params.rect_x; 2216 lsdma_data->u.tiled_copy_data.rect_y = params.rect_y; 2217 lsdma_data->u.tiled_copy_data.dcc = params.dcc; 2218 lsdma_data->u.tiled_copy_data.tmz = params.tmz; 2219 lsdma_data->u.tiled_copy_data.read_compress = params.read_compress; 2220 lsdma_data->u.tiled_copy_data.write_compress = params.write_compress; 2221 lsdma_data->u.tiled_copy_data.src_height = params.src_height; 2222 lsdma_data->u.tiled_copy_data.dst_height = params.dst_height; 2223 lsdma_data->u.tiled_copy_data.data_format = params.data_format; 2224 lsdma_data->u.tiled_copy_data.max_com = params.max_com; 2225 lsdma_data->u.tiled_copy_data.max_uncom = params.max_uncom; 2226 2227 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2228 2229 if (!result) 2230 DC_ERROR("LSDMA Tiled to Tiled Copy failed in DMUB"); 2231 2232 return result; 2233} 2234 2235bool dmub_lsdma_send_pio_copy_command( 2236 struct dc_dmub_srv *dc_dmub_srv, 2237 uint64_t src_addr, 2238 uint64_t dst_addr, 2239 uint32_t byte_count, 2240 uint32_t overlap_disable 2241) 2242{ 2243 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2244 union dmub_rb_cmd cmd; 2245 enum dm_dmub_wait_type wait_type; 2246 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2247 bool result; 2248 2249 memset(&cmd, 0, sizeof(cmd)); 2250 2251 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2252 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_PIO_COPY; 2253 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2254 2255 lsdma_data->u.pio_copy_data.packet.fields.byte_count = byte_count; 2256 lsdma_data->u.pio_copy_data.packet.fields.overlap_disable = overlap_disable; 2257 lsdma_data->u.pio_copy_data.src_lo = src_addr & 0xFFFFFFFF; 2258 lsdma_data->u.pio_copy_data.src_hi = (src_addr >> 32) & 0xFFFFFFFF; 2259 lsdma_data->u.pio_copy_data.dst_lo = dst_addr & 0xFFFFFFFF; 2260 lsdma_data->u.pio_copy_data.dst_hi = (dst_addr >> 32) & 0xFFFFFFFF; 2261 2262 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2263 2264 if (!result) 2265 DC_ERROR("LSDMA PIO Copy failed in DMUB"); 2266 2267 return result; 2268} 2269 2270bool dmub_lsdma_send_pio_constfill_command( 2271 struct dc_dmub_srv *dc_dmub_srv, 2272 uint64_t dst_addr, 2273 uint32_t byte_count, 2274 uint32_t data 2275) 2276{ 2277 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2278 union dmub_rb_cmd cmd; 2279 enum dm_dmub_wait_type wait_type; 2280 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2281 bool result; 2282 2283 memset(&cmd, 0, sizeof(cmd)); 2284 2285 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2286 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_PIO_CONSTFILL; 2287 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2288 2289 lsdma_data->u.pio_constfill_data.packet.fields.constant_fill = 1; 2290 lsdma_data->u.pio_constfill_data.packet.fields.byte_count = byte_count; 2291 lsdma_data->u.pio_constfill_data.dst_lo = dst_addr & 0xFFFFFFFF; 2292 lsdma_data->u.pio_constfill_data.dst_hi = (dst_addr >> 32) & 0xFFFFFFFF; 2293 lsdma_data->u.pio_constfill_data.data = data; 2294 2295 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2296 2297 if (!result) 2298 DC_ERROR("LSDMA PIO Constfill failed in DMUB"); 2299 2300 return result; 2301} 2302 2303bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data) 2304{ 2305 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 2306 union dmub_rb_cmd cmd; 2307 enum dm_dmub_wait_type wait_type; 2308 struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; 2309 bool result; 2310 2311 memset(&cmd, 0, sizeof(cmd)); 2312 2313 cmd.cmd_common.header.type = DMUB_CMD__LSDMA; 2314 cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_POLL_REG_WRITE; 2315 wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 2316 2317 lsdma_data->u.reg_write_data.reg_addr = reg_addr; 2318 lsdma_data->u.reg_write_data.reg_data = reg_data; 2319 2320 result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); 2321 2322 if (!result) 2323 DC_ERROR("LSDMA Poll Reg failed in DMUB"); 2324 2325 return result; 2326} 2327 2328bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc) 2329{ 2330 return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled; 2331} 2332 2333void dc_dmub_srv_release_hw(const struct dc *dc) 2334{ 2335 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 2336 union dmub_rb_cmd cmd = {0}; 2337 2338 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2339 return; 2340 2341 memset(&cmd, 0, sizeof(cmd)); 2342 cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT; 2343 cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_RELEASE_HW; 2344 cmd.idle_opt_notify_idle.header.payload_bytes = 2345 sizeof(cmd.idle_opt_notify_idle) - 2346 sizeof(cmd.idle_opt_notify_idle.header); 2347 2348 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 2349} 2350 2351void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv) 2352{ 2353 struct dmub_srv *dmub; 2354 2355 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2356 return; 2357 2358 dmub = dc_dmub_srv->dmub; 2359 2360 if (dmub_srv_get_preos_info(dmub)) { 2361 DC_LOG_DEBUG("%s: PreOS DMCUB Info", __func__); 2362 DC_LOG_DEBUG("fw_version : 0x%08x", dmub->preos_info.fw_version); 2363 DC_LOG_DEBUG("boot_options : 0x%08x", dmub->preos_info.boot_options); 2364 DC_LOG_DEBUG("boot_status : 0x%08x", dmub->preos_info.boot_status); 2365 DC_LOG_DEBUG("trace_buffer_phy_addr : 0x%016llx", dmub->preos_info.trace_buffer_phy_addr); 2366 DC_LOG_DEBUG("trace_buffer_size_bytes : 0x%08x", dmub->preos_info.trace_buffer_size); 2367 DC_LOG_DEBUG("fb_base : 0x%016llx", dmub->preos_info.fb_base); 2368 DC_LOG_DEBUG("fb_offset : 0x%016llx", dmub->preos_info.fb_offset); 2369 } 2370}
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