dcn316_clk_mgr.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26
 27
 28#include "dccg.h"
 29#include "clk_mgr_internal.h"
 30
 31// For dce12_get_dp_ref_freq_khz
 32#include "dce100/dce_clk_mgr.h"
 33// For dcn20_update_clocks_update_dpp_dto
 34#include "dcn20/dcn20_clk_mgr.h"
 35#include "dcn31/dcn31_clk_mgr.h"
 36#include "dcn316_clk_mgr.h"
 37#include "reg_helper.h"
 38#include "core_types.h"
 39#include "dcn316_smu.h"
 40#include "dm_helpers.h"
 41#include "dc_dmub_srv.h"
 42#include "link_service.h"
 43
 44// DCN316 this is CLK1 instance
 45#define MAX_INSTANCE                                        7
 46#define MAX_SEGMENT                                         6
 47
 48struct IP_BASE_INSTANCE {
 49    unsigned int segment[MAX_SEGMENT];
 50};
 51
 52struct IP_BASE {
 53    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 54};
 55
 56#define regCLK1_CLK_PLL_REQ						0x0237
 57#define regCLK1_CLK_PLL_REQ_BASE_IDX			0
 58
 59#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT		0x0
 60#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT	0xc
 61#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT	0x10
 62#define CLK1_CLK_PLL_REQ__FbMult_int_MASK		0x000001FFL
 63#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK		0x0000F000L
 64#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK		0xFFFF0000L
 65
 66#define TO_CLK_MGR_DCN316(clk_mgr)\
 67	container_of(clk_mgr, struct clk_mgr_dcn316, base)
 68
 69static int dcn316_get_active_display_cnt_wa(
 70		struct dc *dc,
 71		struct dc_state *context)
 72{
 73	int i, display_count;
 74	bool tmds_present = false;
 75
 76	display_count = 0;
 77	for (i = 0; i < context->stream_count; i++) {
 78		const struct dc_stream_state *stream = context->streams[i];
 79
 80		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
 81				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
 82				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 83			tmds_present = true;
 84	}
 85
 86	for (i = 0; i < dc->link_count; i++) {
 87		const struct dc_link *link = dc->links[i];
 88
 89		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
 90		if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
 91				link->link_enc->funcs->is_dig_enabled(link->link_enc))
 92			display_count++;
 93	}
 94
 95	/* WA for hang on HDMI after display off back back on*/
 96	if (display_count == 0 && tmds_present)
 97		display_count = 1;
 98
 99	return display_count;
100}
101
102static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
103		bool safe_to_lower, bool disable)
104{
105	struct dc *dc = clk_mgr_base->ctx->dc;
106	int i;
107
108	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
109		struct pipe_ctx *pipe = safe_to_lower
110			? &context->res_ctx.pipe_ctx[i]
111			: &dc->current_state->res_ctx.pipe_ctx[i];
112
113		if (pipe->top_pipe || pipe->prev_odm_pipe)
114			continue;
115		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
116				     !pipe->stream->link_enc)) {
117			if (disable) {
118				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
119					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
120
121				reset_sync_context_for_pipe(dc, context, i);
122			} else
123				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
124		}
125	}
126}
127
128static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
129{
130	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
131
132	dcn316_smu_enable_pme_wa(clk_mgr);
133}
134
135static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
136			struct dc_state *context,
137			bool safe_to_lower)
138{
139	union dmub_rb_cmd cmd;
140	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
141	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
142	struct dc *dc = clk_mgr_base->ctx->dc;
143	int display_count = 0;
144	bool update_dppclk = false;
145	bool update_dispclk = false;
146	bool dpp_clock_lowered = false;
147
148	if (dc->work_arounds.skip_clock_update)
149		return;
150
151	/*
152	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
153	 * also if safe to lower is false, we just go in the higher state
154	 */
155	clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
156	if (safe_to_lower) {
157		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
158			dcn316_smu_set_dtbclk(clk_mgr, false);
159			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
160		}
161		/* check that we're not already in lower */
162		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
163			display_count = dcn316_get_active_display_cnt_wa(dc, context);
164			/* if we can go lower, go lower */
165			if (display_count == 0) {
166				union display_idle_optimization_u idle_info = { 0 };
167				idle_info.idle_info.df_request_disabled = 1;
168				idle_info.idle_info.phy_ref_clk_off = 1;
169				idle_info.idle_info.s0i2_rdy = 1;
170				dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
171				/* update power state */
172				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
173			}
174		}
175	} else {
176		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
177			dcn316_smu_set_dtbclk(clk_mgr, true);
178			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
179		}
180
181		/* check that we're not already in D0 */
182		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
183			union display_idle_optimization_u idle_info = { 0 };
184			dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
185			/* update power state */
186			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
187		}
188	}
189
190	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
191		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
192		dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
193	}
194
195	if (should_set_clock(safe_to_lower,
196			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
197		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
198		dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
199	}
200
201	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
202	if (new_clocks->dppclk_khz < 100000)
203		new_clocks->dppclk_khz = 100000;
204
205	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
206		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
207			dpp_clock_lowered = true;
208		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
209		update_dppclk = true;
210	}
211
212	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
213	    (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
214		int requested_dispclk_khz = new_clocks->dispclk_khz;
215
216		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
217
218		/* Clamp the requested clock to PMFW based on their limit. */
219		if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
220			requested_dispclk_khz = dc->debug.min_disp_clk_khz;
221
222		dcn316_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
223		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
224		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
225
226		update_dispclk = true;
227	}
228
229	if (dpp_clock_lowered) {
230		// increase per DPP DTO before lowering global dppclk
231		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
232		dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
233	} else {
234		// increase global DPPCLK before lowering per DPP DTO
235		if (update_dppclk || update_dispclk)
236			dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
237		// always update dtos unless clock is lowered and not safe to lower
238		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
239			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
240	}
241
242	// notify DMCUB of latest clocks
243	memset(&cmd, 0, sizeof(cmd));
244	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
245	cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
246	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
247	cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
248		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
249	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
250	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
251
252	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
253}
254
255static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
256		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
257{
258	return;
259}
260
261static struct clk_bw_params dcn316_bw_params = {
262	.vram_type = Ddr4MemType,
263	.num_channels = 1,
264	.clk_table = {
265		.num_entries = 5,
266	},
267
268};
269
270static struct wm_table ddr4_wm_table = {
271	.entries = {
272		{
273			.wm_inst = WM_A,
274			.wm_type = WM_TYPE_PSTATE_CHG,
275			.pstate_latency_us = 11.72,
276			.sr_exit_time_us = 6.09,
277			.sr_enter_plus_exit_time_us = 7.14,
278			.valid = true,
279		},
280		{
281			.wm_inst = WM_B,
282			.wm_type = WM_TYPE_PSTATE_CHG,
283			.pstate_latency_us = 11.72,
284			.sr_exit_time_us = 10.12,
285			.sr_enter_plus_exit_time_us = 11.48,
286			.valid = true,
287		},
288		{
289			.wm_inst = WM_C,
290			.wm_type = WM_TYPE_PSTATE_CHG,
291			.pstate_latency_us = 11.72,
292			.sr_exit_time_us = 10.12,
293			.sr_enter_plus_exit_time_us = 11.48,
294			.valid = true,
295		},
296		{
297			.wm_inst = WM_D,
298			.wm_type = WM_TYPE_PSTATE_CHG,
299			.pstate_latency_us = 11.72,
300			.sr_exit_time_us = 10.12,
301			.sr_enter_plus_exit_time_us = 11.48,
302			.valid = true,
303		},
304	}
305};
306
307static struct wm_table lpddr5_wm_table = {
308	.entries = {
309		{
310			.wm_inst = WM_A,
311			.wm_type = WM_TYPE_PSTATE_CHG,
312			.pstate_latency_us = 11.65333,
313			.sr_exit_time_us = 11.5,
314			.sr_enter_plus_exit_time_us = 14.5,
315			.valid = true,
316		},
317		{
318			.wm_inst = WM_B,
319			.wm_type = WM_TYPE_PSTATE_CHG,
320			.pstate_latency_us = 11.65333,
321			.sr_exit_time_us = 11.5,
322			.sr_enter_plus_exit_time_us = 14.5,
323			.valid = true,
324		},
325		{
326			.wm_inst = WM_C,
327			.wm_type = WM_TYPE_PSTATE_CHG,
328			.pstate_latency_us = 11.65333,
329			.sr_exit_time_us = 11.5,
330			.sr_enter_plus_exit_time_us = 14.5,
331			.valid = true,
332		},
333		{
334			.wm_inst = WM_D,
335			.wm_type = WM_TYPE_PSTATE_CHG,
336			.pstate_latency_us = 11.65333,
337			.sr_exit_time_us = 11.5,
338			.sr_enter_plus_exit_time_us = 14.5,
339			.valid = true,
340		},
341	}
342};
343
344static DpmClocks_316_t dummy_clocks;
345
346static struct dcn316_watermarks dummy_wms = { 0 };
347
348static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
349{
350	int i, num_valid_sets;
351
352	num_valid_sets = 0;
353
354	for (i = 0; i < WM_SET_COUNT; i++) {
355		/* skip empty entries, the smu array has no holes*/
356		if (!bw_params->wm_table.entries[i].valid)
357			continue;
358
359		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
360		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
361		/* We will not select WM based on fclk, so leave it as unconstrained */
362		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
363		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
364
365		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
366			if (i == 0)
367				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
368			else {
369				/* add 1 to make it non-overlapping with next lvl */
370				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
371						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
372			}
373			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
374					bw_params->clk_table.entries[i].dcfclk_mhz;
375
376		} else {
377			/* unconstrained for memory retraining */
378			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
379			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
380
381			/* Modify previous watermark range to cover up to max */
382			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
383		}
384		num_valid_sets++;
385	}
386
387	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
388
389	/* modify the min and max to make sure we cover the whole range*/
390	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
391	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
392	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
393	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
394
395	/* This is for writeback only, does not matter currently as no writeback support*/
396	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
397	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
398	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
399	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
400	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
401}
402
403static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
404{
405	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
406	struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
407	struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
408
409	if (!clk_mgr->smu_ver)
410		return;
411
412	if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
413		return;
414
415	memset(table, 0, sizeof(*table));
416
417	dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
418
419	dcn316_smu_set_dram_addr_high(clk_mgr,
420			clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
421	dcn316_smu_set_dram_addr_low(clk_mgr,
422			clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
423	dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
424}
425
426static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
427		struct dcn316_smu_dpm_clks *smu_dpm_clks)
428{
429	DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
430
431	if (!clk_mgr->smu_ver)
432		return;
433
434	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
435		return;
436
437	memset(table, 0, sizeof(*table));
438
439	dcn316_smu_set_dram_addr_high(clk_mgr,
440			smu_dpm_clks->mc_address.high_part);
441	dcn316_smu_set_dram_addr_low(clk_mgr,
442			smu_dpm_clks->mc_address.low_part);
443	dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
444}
445
446static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
447{
448	uint32_t max = 0;
449	int i;
450
451	for (i = 0; i < num_clocks; ++i) {
452		if (clocks[i] > max)
453			max = clocks[i];
454	}
455
456	return max;
457}
458
459static unsigned int find_clk_for_voltage(
460		const DpmClocks_316_t *clock_table,
461		const uint32_t clocks[],
462		unsigned int voltage)
463{
464	int i;
465	int max_voltage = 0;
466	int clock = 0;
467
468	for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
469		if (clock_table->SocVoltage[i] == voltage) {
470			return clocks[i];
471		} else if (clock_table->SocVoltage[i] >= max_voltage &&
472				clock_table->SocVoltage[i] < voltage) {
473			max_voltage = clock_table->SocVoltage[i];
474			clock = clocks[i];
475		}
476	}
477
478	ASSERT(clock);
479	return clock;
480}
481
482static void dcn316_clk_mgr_helper_populate_bw_params(
483		struct clk_mgr_internal *clk_mgr,
484		struct integrated_info *bios_info,
485		const DpmClocks_316_t *clock_table)
486{
487	int i, j;
488	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
489	uint32_t max_dispclk = 0, max_dppclk = 0;
490
491	j = -1;
492
493	static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,
494		"number of reported pstate levels exceeds maximum");
495
496	/* Find lowest DPM, FCLK is filled in reverse order*/
497
498	for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
499		if (clock_table->DfPstateTable[i].FClk != 0) {
500			j = i;
501			break;
502		}
503	}
504
505	if (j == -1) {
506		/* clock table is all 0s, just use our own hardcode */
507		ASSERT(0);
508		return;
509	}
510
511	bw_params->clk_table.num_entries = j + 1;
512
513	/* dispclk and dppclk can be max at any voltage, same number of levels for both */
514	if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
515	    clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
516		max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
517		max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
518	} else {
519		ASSERT(0);
520	}
521
522	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
523		int temp;
524
525		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
526		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
527		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
528		switch (clock_table->DfPstateTable[j].WckRatio) {
529		case WCK_RATIO_1_2:
530			bw_params->clk_table.entries[i].wck_ratio = 2;
531			break;
532		case WCK_RATIO_1_4:
533			bw_params->clk_table.entries[i].wck_ratio = 4;
534			break;
535		default:
536			bw_params->clk_table.entries[i].wck_ratio = 1;
537		}
538		temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
539		if (temp)
540			bw_params->clk_table.entries[i].dcfclk_mhz = temp;
541		temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
542		if (temp)
543			bw_params->clk_table.entries[i].socclk_mhz = temp;
544		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
545		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
546	}
547
548	bw_params->vram_type = bios_info->memory_type;
549	bw_params->num_channels = bios_info->ma_channel_number;
550	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
551
552	for (i = 0; i < WM_SET_COUNT; i++) {
553		bw_params->wm_table.entries[i].wm_inst = i;
554
555		if (i >= bw_params->clk_table.num_entries) {
556			bw_params->wm_table.entries[i].valid = false;
557			continue;
558		}
559
560		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
561		bw_params->wm_table.entries[i].valid = true;
562	}
563}
564
565
566
567static struct clk_mgr_funcs dcn316_funcs = {
568	.enable_pme_wa = dcn316_enable_pme_wa,
569	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
570	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
571	.update_clocks = dcn316_update_clocks,
572	.init_clocks = dcn31_init_clocks,
573	.are_clock_states_equal = dcn31_are_clock_states_equal,
574	.notify_wm_ranges = dcn316_notify_wm_ranges
575};
576extern struct clk_mgr_funcs dcn3_fpga_funcs;
577
578void dcn316_clk_mgr_construct(
579		struct dc_context *ctx,
580		struct clk_mgr_dcn316 *clk_mgr,
581		struct pp_smu_funcs *pp_smu,
582		struct dccg *dccg)
583{
584	struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
585	struct clk_log_info log_info = {0};
586
587	clk_mgr->base.base.ctx = ctx;
588	clk_mgr->base.base.funcs = &dcn316_funcs;
589
590	clk_mgr->base.pp_smu = pp_smu;
591
592	clk_mgr->base.dccg = dccg;
593	clk_mgr->base.dfs_bypass_disp_clk = 0;
594
595	clk_mgr->base.dprefclk_ss_percentage = 0;
596	clk_mgr->base.dprefclk_ss_divider = 1000;
597	clk_mgr->base.ss_on_dprefclk = false;
598	clk_mgr->base.dfs_ref_freq_khz = 48000;
599
600	clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
601				clk_mgr->base.base.ctx,
602				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
603				sizeof(struct dcn316_watermarks),
604				&clk_mgr->smu_wm_set.mc_address.quad_part);
605
606	if (!clk_mgr->smu_wm_set.wm_set) {
607		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
608		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
609	}
610	ASSERT(clk_mgr->smu_wm_set.wm_set);
611
612	smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
613				clk_mgr->base.base.ctx,
614				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
615				sizeof(DpmClocks_316_t),
616				&smu_dpm_clks.mc_address.quad_part);
617
618	if (smu_dpm_clks.dpm_clks == NULL) {
619		smu_dpm_clks.dpm_clks = &dummy_clocks;
620		smu_dpm_clks.mc_address.quad_part = 0;
621	}
622
623	ASSERT(smu_dpm_clks.dpm_clks);
624
625	clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
626
627	if (clk_mgr->base.smu_ver > 0)
628		clk_mgr->base.smu_present = true;
629
630	// Skip this for now as it did not work on DCN315, renable during bring up
631	//clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
632	clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
633
634	/* in case we don't get a value from the register, use default */
635	if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
636		clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
637
638
639	if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
640		dcn316_bw_params.wm_table = lpddr5_wm_table;
641	} else {
642		dcn316_bw_params.wm_table = ddr4_wm_table;
643	}
644	/* Saved clocks configured at boot for debug purposes */
645	dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
646				  &clk_mgr->base.base, &log_info);
647
648	clk_mgr->base.base.dprefclk_khz = 600000;
649	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
650	clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
651	dce_clock_read_ss_info(&clk_mgr->base);
652	/*clk_mgr->base.dccg->ref_dtbclk_khz =
653	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
654
655	clk_mgr->base.base.bw_params = &dcn316_bw_params;
656
657	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
658		dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
659
660		if (ctx->dc_bios->integrated_info) {
661			dcn316_clk_mgr_helper_populate_bw_params(
662					&clk_mgr->base,
663					ctx->dc_bios->integrated_info,
664					smu_dpm_clks.dpm_clks);
665		}
666	}
667
668	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
669		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
670				smu_dpm_clks.dpm_clks);
671}
672
673void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
674{
675	struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
676
677	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
678		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
679				clk_mgr->smu_wm_set.wm_set);
680}