dcn315_clk_mgr.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26
 27
 28#include "dccg.h"
 29#include "clk_mgr_internal.h"
 30
 31// For dce12_get_dp_ref_freq_khz
 32#include "dce100/dce_clk_mgr.h"
 33// For dcn20_update_clocks_update_dpp_dto
 34#include "dcn20/dcn20_clk_mgr.h"
 35#include "dcn31/dcn31_clk_mgr.h"
 36#include "dcn315_clk_mgr.h"
 37
 38#include "core_types.h"
 39#include "dcn315_smu.h"
 40#include "dm_helpers.h"
 41
 42#include "dc_dmub_srv.h"
 43
 44#include "logger_types.h"
 45#undef DC_LOGGER
 46#define DC_LOGGER \
 47	clk_mgr->base.base.ctx->logger
 48
 49#include "link_service.h"
 50
 51#define TO_CLK_MGR_DCN315(clk_mgr)\
 52	container_of(clk_mgr, struct clk_mgr_dcn315, base)
 53
 54#define UNSUPPORTED_DCFCLK 10000000
 55#define MIN_DPP_DISP_CLK     100000
 56
 57static int dcn315_get_active_display_cnt_wa(
 58		struct dc *dc,
 59		struct dc_state *context)
 60{
 61	int i, display_count;
 62	bool tmds_present = false;
 63
 64	display_count = 0;
 65	for (i = 0; i < context->stream_count; i++) {
 66		const struct dc_stream_state *stream = context->streams[i];
 67
 68		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
 69				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
 70				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 71			tmds_present = true;
 72	}
 73
 74	for (i = 0; i < dc->link_count; i++) {
 75		const struct dc_link *link = dc->links[i];
 76
 77		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
 78		if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
 79				link->link_enc->funcs->is_dig_enabled(link->link_enc))
 80			display_count++;
 81	}
 82
 83	/* WA for hang on HDMI after display off back back on*/
 84	if (display_count == 0 && tmds_present)
 85		display_count = 1;
 86
 87	return display_count;
 88}
 89
 90static bool should_disable_otg(struct pipe_ctx *pipe)
 91{
 92	bool ret = true;
 93
 94	if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&
 95			pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))
 96		ret = false;
 97	return ret;
 98}
 99
100static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
101{
102	struct dc *dc = clk_mgr_base->ctx->dc;
103	int i;
104
105	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
106		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
107
108		if (pipe->top_pipe || pipe->prev_odm_pipe)
109			continue;
110		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
111					dc_is_virtual_signal(pipe->stream->signal))) {
112
113			/* This w/a should not trigger when we have a dig active */
114			if (should_disable_otg(pipe)) {
115				if (disable) {
116					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
117					reset_sync_context_for_pipe(dc, context, i);
118				} else
119					pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
120			}
121		}
122	}
123}
124
125static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
126			struct dc_state *context,
127			bool safe_to_lower)
128{
129	union dmub_rb_cmd cmd;
130	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
131	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
132	struct dc *dc = clk_mgr_base->ctx->dc;
133	int display_count = 0;
134	bool update_dppclk = false;
135	bool update_dispclk = false;
136	bool dpp_clock_lowered = false;
137
138	if (dc->work_arounds.skip_clock_update)
139		return;
140
141	display_count = dcn315_get_active_display_cnt_wa(dc, context);
142	/*
143	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
144	 * also if safe to lower is false, we just go in the higher state
145	 */
146	clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
147	if (safe_to_lower) {
148		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
149			dcn315_smu_set_dtbclk(clk_mgr, false);
150			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
151		}
152		/* check that we're not already in lower */
153		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
154			/* if we can go lower, go lower */
155			if (display_count == 0) {
156				union display_idle_optimization_u idle_info = { 0 };
157				idle_info.idle_info.df_request_disabled = 1;
158				idle_info.idle_info.phy_ref_clk_off = 1;
159				idle_info.idle_info.s0i2_rdy = 1;
160				dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
161				/* update power state */
162				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
163			}
164		}
165	} else {
166		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
167			dcn315_smu_set_dtbclk(clk_mgr, true);
168			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
169		}
170		/* check that we're not already in D0 */
171		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
172			union display_idle_optimization_u idle_info = { 0 };
173			dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
174			/* update power state */
175			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
176		}
177	}
178
179	/* Lock pstate by requesting unsupported dcfclk if change is unsupported */
180	if (!new_clocks->p_state_change_support)
181		new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
182	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
183		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
184		dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
185	}
186
187	if (should_set_clock(safe_to_lower,
188			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
189		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
190		dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
191	}
192
193	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
194	if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
195		new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
196
197	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
198		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
199			dpp_clock_lowered = true;
200		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
201		update_dppclk = true;
202	}
203
204	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
205	    (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
206		int requested_dispclk_khz = new_clocks->dispclk_khz;
207
208		dcn315_disable_otg_wa(clk_mgr_base, context, true);
209
210		/* Clamp the requested clock to PMFW based on their limit. */
211		if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
212			requested_dispclk_khz = dc->debug.min_disp_clk_khz;
213
214		dcn315_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
215		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
216		dcn315_disable_otg_wa(clk_mgr_base, context, false);
217
218		update_dispclk = true;
219	}
220
221	if (dpp_clock_lowered) {
222		// increase per DPP DTO before lowering global dppclk
223		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
224		dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
225	} else {
226		// increase global DPPCLK before lowering per DPP DTO
227		if (update_dppclk || update_dispclk)
228			dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
229		// always update dtos unless clock is lowered and not safe to lower
230		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
231			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
232	}
233
234	// notify DMCUB of latest clocks
235	memset(&cmd, 0, sizeof(cmd));
236	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
237	cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
238	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
239	cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
240		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
241	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
242	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
243
244	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
245}
246
247static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
248		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
249{
250	return;
251}
252
253static struct clk_bw_params dcn315_bw_params = {
254	.vram_type = Ddr4MemType,
255	.num_channels = 2,
256	.clk_table = {
257		.entries = {
258			{
259				.voltage = 0,
260				.dispclk_mhz = 640,
261				.dppclk_mhz = 640,
262				.phyclk_mhz = 810,
263				.phyclk_d18_mhz = 667,
264				.dtbclk_mhz = 600,
265			},
266			{
267				.voltage = 1,
268				.dispclk_mhz = 739,
269				.dppclk_mhz = 739,
270				.phyclk_mhz = 810,
271				.phyclk_d18_mhz = 667,
272				.dtbclk_mhz = 600,
273			},
274			{
275				.voltage = 2,
276				.dispclk_mhz = 960,
277				.dppclk_mhz = 960,
278				.phyclk_mhz = 810,
279				.phyclk_d18_mhz = 667,
280				.dtbclk_mhz = 600,
281			},
282			{
283				.voltage = 3,
284				.dispclk_mhz = 1200,
285				.dppclk_mhz = 1200,
286				.phyclk_mhz = 810,
287				.phyclk_d18_mhz = 667,
288				.dtbclk_mhz = 600,
289			},
290			{
291				.voltage = 4,
292				.dispclk_mhz = 1372,
293				.dppclk_mhz = 1372,
294				.phyclk_mhz = 810,
295				.phyclk_d18_mhz = 667,
296				.dtbclk_mhz = 600,
297			},
298		},
299		.num_entries = 5,
300	},
301
302};
303
304static struct wm_table ddr5_wm_table = {
305	.entries = {
306		{
307			.wm_inst = WM_A,
308			.wm_type = WM_TYPE_PSTATE_CHG,
309			.pstate_latency_us = 129.0,
310			.sr_exit_time_us = 11.5,
311			.sr_enter_plus_exit_time_us = 14.5,
312			.valid = true,
313		},
314		{
315			.wm_inst = WM_B,
316			.wm_type = WM_TYPE_PSTATE_CHG,
317			.pstate_latency_us = 129.0,
318			.sr_exit_time_us = 11.5,
319			.sr_enter_plus_exit_time_us = 14.5,
320			.valid = true,
321		},
322		{
323			.wm_inst = WM_C,
324			.wm_type = WM_TYPE_PSTATE_CHG,
325			.pstate_latency_us = 129.0,
326			.sr_exit_time_us = 11.5,
327			.sr_enter_plus_exit_time_us = 14.5,
328			.valid = true,
329		},
330		{
331			.wm_inst = WM_D,
332			.wm_type = WM_TYPE_PSTATE_CHG,
333			.pstate_latency_us = 129.0,
334			.sr_exit_time_us = 11.5,
335			.sr_enter_plus_exit_time_us = 14.5,
336			.valid = true,
337		},
338	}
339};
340
341static struct wm_table lpddr5_wm_table = {
342	.entries = {
343		{
344			.wm_inst = WM_A,
345			.wm_type = WM_TYPE_PSTATE_CHG,
346			.pstate_latency_us = 129.0,
347			.sr_exit_time_us = 11.5,
348			.sr_enter_plus_exit_time_us = 14.5,
349			.valid = true,
350		},
351		{
352			.wm_inst = WM_B,
353			.wm_type = WM_TYPE_PSTATE_CHG,
354			.pstate_latency_us = 129.0,
355			.sr_exit_time_us = 11.5,
356			.sr_enter_plus_exit_time_us = 14.5,
357			.valid = true,
358		},
359		{
360			.wm_inst = WM_C,
361			.wm_type = WM_TYPE_PSTATE_CHG,
362			.pstate_latency_us = 129.0,
363			.sr_exit_time_us = 11.5,
364			.sr_enter_plus_exit_time_us = 14.5,
365			.valid = true,
366		},
367		{
368			.wm_inst = WM_D,
369			.wm_type = WM_TYPE_PSTATE_CHG,
370			.pstate_latency_us = 129.0,
371			.sr_exit_time_us = 11.5,
372			.sr_enter_plus_exit_time_us = 14.5,
373			.valid = true,
374		},
375	}
376};
377
378/* Temporary Place holder until we can get them from fuse */
379static DpmClocks_315_t dummy_clocks = { 0 };
380static struct dcn315_watermarks dummy_wms = { 0 };
381
382static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
383{
384	int i, num_valid_sets;
385
386	num_valid_sets = 0;
387
388	for (i = 0; i < WM_SET_COUNT; i++) {
389		/* skip empty entries, the smu array has no holes*/
390		if (!bw_params->wm_table.entries[i].valid)
391			continue;
392
393		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
394		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
395		/* We will not select WM based on fclk, so leave it as unconstrained */
396		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
397		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
398
399		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
400			if (i == 0)
401				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
402			else {
403				/* add 1 to make it non-overlapping with next lvl */
404				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
405						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
406			}
407			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
408					bw_params->clk_table.entries[i].dcfclk_mhz;
409
410		} else {
411			/* unconstrained for memory retraining */
412			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
413			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
414
415			/* Modify previous watermark range to cover up to max */
416			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
417		}
418		num_valid_sets++;
419	}
420
421	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
422
423	/* modify the min and max to make sure we cover the whole range*/
424	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
425	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
426	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
427	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
428
429	/* This is for writeback only, does not matter currently as no writeback support*/
430	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
431	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
432	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
433	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
434	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
435}
436
437static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
438{
439	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
440	struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
441	struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
442
443	if (!clk_mgr->smu_ver)
444		return;
445
446	if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
447		return;
448
449	memset(table, 0, sizeof(*table));
450
451	dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
452
453	dcn315_smu_set_dram_addr_high(clk_mgr,
454			clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
455	dcn315_smu_set_dram_addr_low(clk_mgr,
456			clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
457	dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
458}
459
460static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
461		struct dcn315_smu_dpm_clks *smu_dpm_clks)
462{
463	DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
464
465	if (!clk_mgr->smu_ver)
466		return;
467
468	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
469		return;
470
471	memset(table, 0, sizeof(*table));
472
473	dcn315_smu_set_dram_addr_high(clk_mgr,
474			smu_dpm_clks->mc_address.high_part);
475	dcn315_smu_set_dram_addr_low(clk_mgr,
476			smu_dpm_clks->mc_address.low_part);
477	dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
478}
479
480static void dcn315_clk_mgr_helper_populate_bw_params(
481		struct clk_mgr_internal *clk_mgr,
482		struct integrated_info *bios_info,
483		const DpmClocks_315_t *clock_table)
484{
485	int i;
486	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
487	uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
488	struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
489
490	/* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
491	for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
492		int j;
493
494		/* DF table is sorted with clocks decreasing */
495		for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
496			if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
497				max_pstate = j;
498		}
499		/* Max DCFCLK should match up with max pstate */
500		if (i == clock_table->NumDcfClkLevelsEnabled - 1)
501			max_pstate = 0;
502
503		/* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
504		for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
505			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
506				break;
507		bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
508		bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
509		bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
510
511		/* Now update clocks we do read */
512		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
513		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
514		bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
515		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
516		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
517		bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
518		bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
519		bw_params->clk_table.entries[i].wck_ratio = 1;
520	}
521
522	/* Make sure to include at least one entry */
523	if (i == 0) {
524		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
525		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
526		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
527		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
528		bw_params->clk_table.entries[i].wck_ratio = 1;
529		i++;
530	} else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) {
531		bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
532		bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
533		bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
534		bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
535	}
536	bw_params->clk_table.num_entries = i;
537
538	/* Set any 0 clocks to max default setting. Not an issue for
539	 * power since we aren't doing switching in such case anyway
540	 */
541	for (i = 0; i < bw_params->clk_table.num_entries; i++) {
542		if (!bw_params->clk_table.entries[i].fclk_mhz) {
543			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
544			bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
545			bw_params->clk_table.entries[i].voltage = def_max.voltage;
546		}
547		if (!bw_params->clk_table.entries[i].dcfclk_mhz)
548			bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
549		if (!bw_params->clk_table.entries[i].socclk_mhz)
550			bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
551		if (!bw_params->clk_table.entries[i].dispclk_mhz)
552			bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
553		if (!bw_params->clk_table.entries[i].dppclk_mhz)
554			bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
555		if (!bw_params->clk_table.entries[i].phyclk_mhz)
556			bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
557		if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
558			bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
559		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
560			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
561	}
562
563	/* Make sure all highest default clocks are included*/
564	ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
565	ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
566	ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
567	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
568	bw_params->vram_type = bios_info->memory_type;
569	bw_params->num_channels = bios_info->ma_channel_number;
570	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
571
572	for (i = 0; i < WM_SET_COUNT; i++) {
573		bw_params->wm_table.entries[i].wm_inst = i;
574
575		if (i >= bw_params->clk_table.num_entries) {
576			bw_params->wm_table.entries[i].valid = false;
577			continue;
578		}
579
580		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
581		bw_params->wm_table.entries[i].valid = true;
582	}
583}
584
585static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
586{
587	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
588
589	dcn315_smu_enable_pme_wa(clk_mgr);
590}
591
592static struct clk_mgr_funcs dcn315_funcs = {
593	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
594	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
595	.update_clocks = dcn315_update_clocks,
596	.init_clocks = dcn31_init_clocks,
597	.enable_pme_wa = dcn315_enable_pme_wa,
598	.are_clock_states_equal = dcn31_are_clock_states_equal,
599	.notify_wm_ranges = dcn315_notify_wm_ranges
600};
601extern struct clk_mgr_funcs dcn3_fpga_funcs;
602
603void dcn315_clk_mgr_construct(
604		struct dc_context *ctx,
605		struct clk_mgr_dcn315 *clk_mgr,
606		struct pp_smu_funcs *pp_smu,
607		struct dccg *dccg)
608{
609	struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
610	struct clk_log_info log_info = {0};
611
612	clk_mgr->base.base.ctx = ctx;
613	clk_mgr->base.base.funcs = &dcn315_funcs;
614
615	clk_mgr->base.pp_smu = pp_smu;
616
617	clk_mgr->base.dccg = dccg;
618	clk_mgr->base.dfs_bypass_disp_clk = 0;
619
620	clk_mgr->base.dprefclk_ss_percentage = 0;
621	clk_mgr->base.dprefclk_ss_divider = 1000;
622	clk_mgr->base.ss_on_dprefclk = false;
623	clk_mgr->base.dfs_ref_freq_khz = 48000;
624
625	clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
626				clk_mgr->base.base.ctx,
627				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
628				sizeof(struct dcn315_watermarks),
629				&clk_mgr->smu_wm_set.mc_address.quad_part);
630
631	if (!clk_mgr->smu_wm_set.wm_set) {
632		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
633		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
634	}
635	ASSERT(clk_mgr->smu_wm_set.wm_set);
636
637	smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
638				clk_mgr->base.base.ctx,
639				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
640				sizeof(DpmClocks_315_t),
641				&smu_dpm_clks.mc_address.quad_part);
642
643	if (smu_dpm_clks.dpm_clks == NULL) {
644		smu_dpm_clks.dpm_clks = &dummy_clocks;
645		smu_dpm_clks.mc_address.quad_part = 0;
646	}
647
648	ASSERT(smu_dpm_clks.dpm_clks);
649
650	clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
651
652	if (clk_mgr->base.smu_ver > 0)
653		clk_mgr->base.smu_present = true;
654
655	if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
656		dcn315_bw_params.wm_table = lpddr5_wm_table;
657	} else {
658		dcn315_bw_params.wm_table = ddr5_wm_table;
659	}
660	/* Saved clocks configured at boot for debug purposes */
661	dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
662				  &clk_mgr->base.base, &log_info);
663
664	clk_mgr->base.base.dprefclk_khz = 600000;
665	clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
666	clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
667	dce_clock_read_ss_info(&clk_mgr->base);
668	clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
669
670	clk_mgr->base.base.bw_params = &dcn315_bw_params;
671
672	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
673		int i;
674
675		dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
676		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
677				   "NumDispClkLevelsEnabled: %d\n"
678				   "NumSocClkLevelsEnabled: %d\n"
679				   "VcnClkLevelsEnabled: %d\n"
680				   "NumDfPst atesEnabled: %d\n"
681				   "MinGfxClk: %d\n"
682				   "MaxGfxClk: %d\n",
683				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
684				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
685				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
686				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
687				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
688				   smu_dpm_clks.dpm_clks->MinGfxClk,
689				   smu_dpm_clks.dpm_clks->MaxGfxClk);
690		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
691			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
692					   i,
693					   smu_dpm_clks.dpm_clks->DcfClocks[i]);
694		}
695		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
696			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
697					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);
698		}
699		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
700			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
701					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);
702		}
703		for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
704			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
705					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
706
707		for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
708			DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
709					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
710					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
711					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
712					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
713					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
714		}
715
716		if (ctx->dc_bios->integrated_info) {
717			dcn315_clk_mgr_helper_populate_bw_params(
718					&clk_mgr->base,
719					ctx->dc_bios->integrated_info,
720					smu_dpm_clks.dpm_clks);
721		}
722	}
723
724	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
725		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
726				smu_dpm_clks.dpm_clks);
727}
728
729void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
730{
731	struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
732
733	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
734		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
735				clk_mgr->smu_wm_set.wm_set);
736}