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dcn31_clk_mgr.h

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h C
 1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DCN31_CLK_MGR_H__
27#define __DCN31_CLK_MGR_H__
28#include "clk_mgr_internal.h"
29
30struct dcn31_watermarks;
31
32struct dcn31_smu_watermark_set {
33	struct dcn31_watermarks *wm_set;
34	union large_integer mc_address;
35};
36
37struct clk_mgr_dcn31 {
38	struct clk_mgr_internal base;
39	struct dcn31_smu_watermark_set smu_wm_set;
40};
41
42bool dcn31_are_clock_states_equal(struct dc_clocks *a,
43		struct dc_clocks *b);
44void dcn31_init_clocks(struct clk_mgr *clk_mgr);
45void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
46			struct dc_state *context,
47			bool safe_to_lower);
48
49void dcn31_clk_mgr_construct(struct dc_context *ctx,
50		struct clk_mgr_dcn31 *clk_mgr,
51		struct pp_smu_funcs *pp_smu,
52		struct dccg *dccg);
53
54int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
55
56void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
57
58#endif //__DCN31_CLK_MGR_H__
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