dcn30_clk_mgr.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dccg.h"
 27#include "clk_mgr_internal.h"
 28#include "dcn30_clk_mgr_smu_msg.h"
 29#include "dcn20/dcn20_clk_mgr.h"
 30#include "dce100/dce_clk_mgr.h"
 31#include "dcn30/dcn30_clk_mgr.h"
 32#include "dml/dcn30/dcn30_fpu.h"
 33#include "dcn30/dcn30m_clk_mgr.h"
 34#include "reg_helper.h"
 35#include "core_types.h"
 36#include "dm_helpers.h"
 37#include "atomfirmware.h"
 38#include "sienna_cichlid_ip_offset.h"
 39#include "dcn/dcn_3_0_0_offset.h"
 40#include "dcn/dcn_3_0_0_sh_mask.h"
 41#include "nbio/nbio_7_4_offset.h"
 42#include "dpcs/dpcs_3_0_0_offset.h"
 43#include "dpcs/dpcs_3_0_0_sh_mask.h"
 44#include "mmhub/mmhub_2_0_0_offset.h"
 45#include "mmhub/mmhub_2_0_0_sh_mask.h"
 46#include "dcn30_smu11_driver_if.h"
 47
 48#undef FN
 49#define FN(reg_name, field_name) \
 50	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
 51
 52#define REG(reg) \
 53	(clk_mgr->regs->reg)
 54
 55#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 56
 57#define BASE(seg) BASE_INNER(seg)
 58
 59#define SR(reg_name)\
 60		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 61					mm ## reg_name
 62
 63#undef CLK_SRI
 64#define CLK_SRI(reg_name, block, inst)\
 65	.reg_name = mm ## block ## _ ## reg_name
 66
 67static const struct clk_mgr_registers clk_mgr_regs = {
 68	CLK_REG_LIST_DCN3()
 69};
 70
 71static const struct clk_mgr_shift clk_mgr_shift = {
 72	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
 73};
 74
 75static const struct clk_mgr_mask clk_mgr_mask = {
 76	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
 77};
 78
 79
 80/* Query SMU for all clock states for a particular clock */
 81static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
 82{
 83	unsigned int i;
 84	char *entry_i = (char *)entry_0;
 85	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
 86
 87	if (ret & (1 << 31))
 88		/* fine-grained, only min and max */
 89		*num_levels = 2;
 90	else
 91		/* discrete, a number of fixed states */
 92		/* will set num_levels to 0 on failure */
 93		*num_levels = ret & 0xFF;
 94
 95	/* if the initial message failed, num_levels will be 0 */
 96	for (i = 0; i < *num_levels; i++) {
 97		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
 98		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
 99	}
100}
101
102static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
103{
104	DC_FP_START();
105	dcn3_fpu_build_wm_range_table(&clk_mgr->base);
106	DC_FP_END();
107}
108
109void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
110{
111	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
112	unsigned int num_levels;
113
114	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
115	clk_mgr_base->clks.p_state_change_support = true;
116	clk_mgr_base->clks.prev_p_state_change_support = true;
117	clk_mgr->smu_present = false;
118
119	if (!clk_mgr_base->bw_params)
120		return;
121
122	if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
123		clk_mgr->smu_present = true;
124
125	if (!clk_mgr->smu_present)
126		return;
127
128	// do we fail if these fail? if so, how? do we not care to check?
129	dcn30_smu_check_driver_if_version(clk_mgr);
130	dcn30_smu_check_msg_header_version(clk_mgr);
131
132	/* DCFCLK */
133	dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
134			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
135			&num_levels);
136	dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, 0);
137
138	/* DTBCLK */
139	dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
140			&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
141			&num_levels);
142
143	/* SOCCLK */
144	dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
145					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
146					&num_levels);
147	// DPREFCLK ???
148
149	/* DISPCLK */
150	dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
151			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
152			&num_levels);
153
154	/* DPPCLK */
155	dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
156			&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
157			&num_levels);
158
159	/* PHYCLK */
160	dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
161			&clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
162			&num_levels);
163
164	/* Get UCLK, update bounding box */
165	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
166
167	/* WM range table */
168	DC_FP_START();
169	dcn3_build_wm_range_table(clk_mgr);
170	DC_FP_END();
171}
172
173static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
174{
175	/* get FbMult value */
176	struct fixed31_32 pll_req;
177	/* get FbMult value */
178	uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
179
180	/* set up a fixed-point number
181	 * this works because the int part is on the right edge of the register
182	 * and the frac part is on the left edge
183	 */
184	pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
185	pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
186
187	/* multiply by REFCLK period */
188	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
189
190	return dc_fixpt_floor(pll_req);
191}
192
193static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
194			struct dc_state *context,
195			bool safe_to_lower)
196{
197	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
198	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
199	struct dc *dc = clk_mgr_base->ctx->dc;
200	int display_count;
201	bool update_dppclk = false;
202	bool update_dispclk = false;
203	bool enter_display_off = false;
204	bool dpp_clock_lowered = false;
205	bool update_pstate_unsupported_clk = false;
206	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
207	bool force_reset = false;
208	bool update_uclk = false;
209	bool p_state_change_support;
210
211	if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
212		return;
213
214	if (clk_mgr_base->clks.dispclk_khz == 0 ||
215			(dc->debug.force_clock_mode & 0x1)) {
216		/* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
217		force_reset = true;
218
219		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
220
221		/* force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level. */
222	}
223	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
224
225	if (display_count == 0)
226		enter_display_off = true;
227
228	if (enter_display_off == safe_to_lower)
229		dcn30_smu_set_num_of_displays(clk_mgr, display_count);
230
231	if (dc->debug.force_min_dcfclk_mhz > 0)
232		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
233				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
234
235	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
236		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
237		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
238	}
239
240	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
241		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
242		dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
243	}
244
245	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
246		/* We don't actually care about socclk, don't notify SMU of hard min */
247		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
248
249	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
250	p_state_change_support = new_clocks->p_state_change_support;
251
252	// invalidate the current P-State forced min in certain dc_mode_softmax situations
253	if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {
254		if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) !=
255				(clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))
256			update_pstate_unsupported_clk = true;
257	}
258
259	if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) ||
260			update_pstate_unsupported_clk) {
261		clk_mgr_base->clks.p_state_change_support = p_state_change_support;
262
263		/* to disable P-State switching, set UCLK min = max */
264		if (!clk_mgr_base->clks.p_state_change_support) {
265			if (dc->clk_mgr->dc_mode_softmax_enabled &&
266				new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
267				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
268					dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
269			else
270				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
271					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
272		}
273	}
274
275	/* Always update saved value, even if new value not set due to P-State switching unsupported */
276	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
277		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
278		update_uclk = true;
279	}
280
281	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
282	if (clk_mgr_base->clks.p_state_change_support &&
283			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
284		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
285
286	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
287		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
288			dpp_clock_lowered = true;
289
290		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
291		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
292		update_dppclk = true;
293	}
294
295	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
296		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
297		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
298		update_dispclk = true;
299	}
300
301	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
302		if (dpp_clock_lowered) {
303			/* if clock is being lowered, increase DTO before lowering refclk */
304			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
305			dcn20_update_clocks_update_dentist(clk_mgr, context);
306		} else {
307			/* if clock is being raised, increase refclk before lowering DTO */
308			if (update_dppclk || update_dispclk)
309				dcn20_update_clocks_update_dentist(clk_mgr, context);
310			/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
311			 * that we do not lower dto when it is not safe to lower. We do not need to
312			 * compare the current and new dppclk before calling this function.*/
313			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
314		}
315	}
316
317	if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
318		/*update dmcu for wait_loop count*/
319		dmcu->funcs->set_psr_wait_loop(dmcu,
320				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
321}
322
323
324static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
325{
326	unsigned int i;
327	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
328	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
329
330	if (!clk_mgr->smu_present)
331		return;
332
333	if (!table)
334		// should log failure
335		return;
336
337	memset(table, 0, sizeof(*table));
338
339	/* collect valid ranges, place in pmfw table */
340	for (i = 0; i < WM_SET_COUNT; i++)
341		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
342			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
343			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
344			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
345			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
346			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
347			table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
348		}
349
350	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
351	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
352	dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
353}
354
355/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
356static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
357{
358	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
359
360	if (!clk_mgr->smu_present)
361		return;
362
363	if (current_mode) {
364		if (clk_mgr_base->clks.p_state_change_support)
365			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
366					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
367		else
368			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
369					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
370	} else {
371		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
372				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
373	}
374}
375
376/* Set max memclk to highest DPM value */
377static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
378{
379	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
380
381	if (!clk_mgr->smu_present)
382		return;
383
384	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
385			clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
386}
387
388static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
389{
390	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
391
392	if (!clk_mgr->smu_present)
393		return;
394
395	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
396}
397static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
398{
399	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
400
401	if (!clk_mgr->smu_present)
402		return;
403	dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
404}
405
406/* Get current memclk states, update bounding box */
407static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
408{
409	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
410	unsigned int num_levels;
411
412	if (!clk_mgr->smu_present)
413		return;
414
415	/* Refresh memclk states */
416	dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
417			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
418			&num_levels);
419	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
420
421	clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
422
423	/* Refresh bounding box */
424	DC_FP_START();
425	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
426			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
427	DC_FP_END();
428}
429
430static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
431{
432	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
433	return clk_mgr->smu_present;
434}
435
436static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
437					struct dc_clocks *b)
438{
439	if (a->dispclk_khz != b->dispclk_khz)
440		return false;
441	else if (a->dppclk_khz != b->dppclk_khz)
442		return false;
443	else if (a->dcfclk_khz != b->dcfclk_khz)
444		return false;
445	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
446		return false;
447	else if (a->dramclk_khz != b->dramclk_khz)
448		return false;
449	else if (a->p_state_change_support != b->p_state_change_support)
450		return false;
451
452	return true;
453}
454
455static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
456{
457	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
458
459	if (!clk_mgr->smu_present)
460		return;
461
462	dcn30_smu_set_pme_workaround(clk_mgr);
463}
464
465/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
466static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
467{
468	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
469	unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
470
471	if (!clk_mgr->smu_present)
472		return;
473
474	/* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */
475
476	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
477
478	for (i = 0; i < MAX_LINKS; i++) {
479		if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
480			max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
481	}
482
483	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
484		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
485		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
486	}
487}
488
489static struct clk_mgr_funcs dcn3_funcs = {
490		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
491		.update_clocks = dcn3_update_clocks,
492		.init_clocks = dcn3_init_clocks,
493		.notify_wm_ranges = dcn3_notify_wm_ranges,
494		.set_hard_min_memclk = dcn3_set_hard_min_memclk,
495		.set_hard_max_memclk = dcn3_set_hard_max_memclk,
496		.set_max_memclk = dcn3_set_max_memclk,
497		.set_min_memclk = dcn3_set_min_memclk,
498		.get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
499		.are_clock_states_equal = dcn3_are_clock_states_equal,
500		.enable_pme_wa = dcn3_enable_pme_wa,
501		.notify_link_rate_change = dcn30_notify_link_rate_change,
502		.is_smu_present = dcn3_is_smu_present,
503		.set_smartmux_switch = dcn30m_set_smartmux_switch
504};
505
506static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
507{
508	dcn2_init_clocks(clk_mgr);
509
510/* TODO: Implement the functions and remove the ifndef guard */
511}
512
513struct clk_mgr_funcs dcn3_fpga_funcs = {
514	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
515	.update_clocks = dcn2_update_clocks_fpga,
516	.init_clocks = dcn3_init_clocks_fpga,
517};
518
519/*todo for dcn30 for clk register offset*/
520void dcn3_clk_mgr_construct(
521		struct dc_context *ctx,
522		struct clk_mgr_internal *clk_mgr,
523		struct pp_smu_funcs *pp_smu,
524		struct dccg *dccg)
525{
526	struct clk_state_registers_and_bypass s = { 0 };
527
528	clk_mgr->base.ctx = ctx;
529	clk_mgr->base.funcs = &dcn3_funcs;
530	clk_mgr->regs = &clk_mgr_regs;
531	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
532	clk_mgr->clk_mgr_mask = &clk_mgr_mask;
533
534	clk_mgr->dccg = dccg;
535	clk_mgr->dfs_bypass_disp_clk = 0;
536
537	clk_mgr->dprefclk_ss_percentage = 0;
538	clk_mgr->dprefclk_ss_divider = 1000;
539	clk_mgr->ss_on_dprefclk = false;
540	clk_mgr->dfs_ref_freq_khz = 100000;
541
542	clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
543
544	/* integer part is now VCO frequency in kHz */
545	clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
546
547	/* in case we don't get a value from the register, use default */
548	if (clk_mgr->base.dentist_vco_freq_khz == 0)
549		clk_mgr->base.dentist_vco_freq_khz = 3650000;
550	/* Convert dprefclk units from MHz to KHz */
551	/* Value already divided by 10, some resolution lost */
552
553	/*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
554	//ASSERT(s.dprefclk != 0);
555	if (s.dprefclk != 0)
556		clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
557
558	clk_mgr->dfs_bypass_enabled = false;
559
560	clk_mgr->smu_present = false;
561
562	dce_clock_read_ss_info(clk_mgr);
563
564	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
565	if (!clk_mgr->base.bw_params) {
566		BREAK_TO_DEBUGGER();
567		return;
568	}
569
570	/* need physical address of table to give to PMFW */
571	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
572			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
573			&clk_mgr->wm_range_table_addr);
574	if (!clk_mgr->wm_range_table) {
575		BREAK_TO_DEBUGGER();
576		return;
577	}
578}
579
580void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
581{
582	kfree(clk_mgr->base.bw_params);
583
584	if (clk_mgr->wm_range_table)
585		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
586				clk_mgr->wm_range_table);
587}