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command_table_helper2_dce112.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
1/* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dm_services.h" 27 28#include "atom.h" 29 30#include "include/bios_parser_types.h" 31 32#include "../command_table_helper.h" 33 34#include "../command_table_helper2.h" 35 36static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 37{ 38 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP; 39 40 switch (s) { 41 case SIGNAL_TYPE_DISPLAY_PORT: 42 case SIGNAL_TYPE_EDP: 43 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP; 44 break; 45 case SIGNAL_TYPE_DVI_SINGLE_LINK: 46 case SIGNAL_TYPE_DVI_DUAL_LINK: 47 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI; 48 break; 49 case SIGNAL_TYPE_HDMI_TYPE_A: 50 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI; 51 break; 52 case SIGNAL_TYPE_DISPLAY_PORT_MST: 53 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST; 54 break; 55 default: 56 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI; 57 break; 58 } 59 60 return atom_dig_mode; 61} 62 63static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 64{ 65 uint8_t atom_hpd_sel = 0; 66 67 switch (id) { 68 case HPD_SOURCEID1: 69 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL; 70 break; 71 case HPD_SOURCEID2: 72 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL; 73 break; 74 case HPD_SOURCEID3: 75 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL; 76 break; 77 case HPD_SOURCEID4: 78 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL; 79 break; 80 case HPD_SOURCEID5: 81 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL; 82 break; 83 case HPD_SOURCEID6: 84 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL; 85 break; 86 case HPD_SOURCEID_UNKNOWN: 87 default: 88 atom_hpd_sel = 0; 89 break; 90 } 91 return atom_hpd_sel; 92} 93 94static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 95{ 96 /* On any ASIC after DCE80, we manually program the DIG_FE 97 * selection (see connect_dig_be_to_fe function of the link 98 * encoder), so translation should always return 0 (no FE). 99 */ 100 101 return 0; 102} 103 104static bool clock_source_id_to_atom( 105 enum clock_source_id id, 106 uint32_t *atom_pll_id) 107{ 108 bool result = true; 109 110 if (atom_pll_id != NULL) 111 switch (id) { 112 case CLOCK_SOURCE_COMBO_PHY_PLL0: 113 *atom_pll_id = ATOM_COMBOPHY_PLL0; 114 break; 115 case CLOCK_SOURCE_COMBO_PHY_PLL1: 116 *atom_pll_id = ATOM_COMBOPHY_PLL1; 117 break; 118 case CLOCK_SOURCE_COMBO_PHY_PLL2: 119 *atom_pll_id = ATOM_COMBOPHY_PLL2; 120 break; 121 case CLOCK_SOURCE_COMBO_PHY_PLL3: 122 *atom_pll_id = ATOM_COMBOPHY_PLL3; 123 break; 124 case CLOCK_SOURCE_COMBO_PHY_PLL4: 125 *atom_pll_id = ATOM_COMBOPHY_PLL4; 126 break; 127 case CLOCK_SOURCE_COMBO_PHY_PLL5: 128 *atom_pll_id = ATOM_COMBOPHY_PLL5; 129 break; 130 case CLOCK_SOURCE_COMBO_DISPLAY_PLL0: 131 *atom_pll_id = ATOM_PPLL0; 132 break; 133 case CLOCK_SOURCE_ID_DFS: 134 *atom_pll_id = ATOM_GCK_DFS; 135 break; 136 case CLOCK_SOURCE_ID_VCE: 137 *atom_pll_id = ATOM_DP_DTO; 138 break; 139 case CLOCK_SOURCE_ID_DP_DTO: 140 *atom_pll_id = ATOM_DP_DTO; 141 break; 142 case CLOCK_SOURCE_ID_UNDEFINED: 143 /* Should not happen */ 144 *atom_pll_id = ATOM_PPLL_INVALID; 145 result = false; 146 break; 147 default: 148 result = false; 149 break; 150 } 151 152 return result; 153} 154 155static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action) 156{ 157 uint8_t atom_action = 0; 158 159 switch (action) { 160 case ENCODER_CONTROL_ENABLE: 161 atom_action = ATOM_ENABLE; 162 break; 163 case ENCODER_CONTROL_DISABLE: 164 atom_action = ATOM_DISABLE; 165 break; 166 case ENCODER_CONTROL_SETUP: 167 atom_action = ATOM_ENCODER_CMD_STREAM_SETUP; 168 break; 169 case ENCODER_CONTROL_INIT: 170 atom_action = ATOM_ENCODER_INIT; 171 break; 172 default: 173 BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */ 174 break; 175 } 176 177 return atom_action; 178} 179 180static uint8_t disp_power_gating_action_to_atom( 181 enum bp_pipe_control_action action) 182{ 183 uint8_t atom_pipe_action = 0; 184 185 switch (action) { 186 case ASIC_PIPE_DISABLE: 187 atom_pipe_action = ATOM_DISABLE; 188 break; 189 case ASIC_PIPE_ENABLE: 190 atom_pipe_action = ATOM_ENABLE; 191 break; 192 case ASIC_PIPE_INIT: 193 atom_pipe_action = ATOM_INIT; 194 break; 195 default: 196 ASSERT_CRITICAL(false); /* Unhandle action in driver! */ 197 break; 198 } 199 200 return atom_pipe_action; 201} 202 203static bool dc_clock_type_to_atom( 204 enum bp_dce_clock_type id, 205 uint32_t *atom_clock_type) 206{ 207 bool retCode = true; 208 209 if (atom_clock_type != NULL) { 210 switch (id) { 211 case DCECLOCK_TYPE_DISPLAY_CLOCK: 212 *atom_clock_type = DCE_CLOCK_TYPE_DISPCLK; 213 break; 214 215 case DCECLOCK_TYPE_DPREFCLK: 216 *atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK; 217 break; 218 219 default: 220 ASSERT_CRITICAL(false); /* Unhandle action in driver! */ 221 break; 222 } 223 } 224 225 return retCode; 226} 227 228static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id) 229{ 230 uint8_t atomColorDepth = 0; 231 232 switch (id) { 233 case TRANSMITTER_COLOR_DEPTH_24: 234 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS; 235 break; 236 case TRANSMITTER_COLOR_DEPTH_30: 237 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4; 238 break; 239 case TRANSMITTER_COLOR_DEPTH_36: 240 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2; 241 break; 242 case TRANSMITTER_COLOR_DEPTH_48: 243 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1; 244 break; 245 default: 246 ASSERT_CRITICAL(false); /* Unhandle action in driver! */ 247 break; 248 } 249 250 return atomColorDepth; 251} 252 253/* function table */ 254static const struct command_table_helper command_table_helper_funcs = { 255 .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2, 256 .encoder_action_to_atom = encoder_action_to_atom, 257 .engine_bp_to_atom = engine_bp_to_atom, 258 .clock_source_id_to_atom = clock_source_id_to_atom, 259 .clock_source_id_to_atom_phy_clk_src_id = 260 clock_source_id_to_atom_phy_clk_src_id, 261 .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode, 262 .hpd_sel_to_atom = hpd_sel_to_atom, 263 .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom, 264 .phy_id_to_atom = phy_id_to_atom, 265 .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom, 266 .clock_source_id_to_ref_clk_src = NULL, 267 .transmitter_bp_to_atom = NULL, 268 .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2, 269 .encoder_mode_bp_to_atom = 270 dal_cmd_table_helper_encoder_mode_bp_to_atom2, 271 .dc_clock_type_to_atom = dc_clock_type_to_atom, 272 .transmitter_color_depth_to_atom = transmitter_color_depth_to_atom, 273}; 274 275/* 276 * dal_cmd_tbl_helper_dce110_get_table 277 * 278 * @brief 279 * Initialize command table helper functions 280 * 281 * @param 282 * const struct command_table_helper **h - [out] struct of functions 283 * 284 */ 285const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void) 286{ 287 return &command_table_helper_funcs; 288}
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