amdgpu_dm_irq.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2015 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24
 25#ifndef __AMDGPU_DM_IRQ_H__
 26#define __AMDGPU_DM_IRQ_H__
 27
 28#include "irq_types.h" /* DAL irq definitions */
 29
 30/*
 31 * Display Manager IRQ-related interfaces (for use by DAL).
 32 */
 33
 34/**
 35 * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
 36 *
 37 * This function should be called exactly once - during DM initialization.
 38 *
 39 * Returns:
 40 *	0 - success
 41 *	non-zero - error
 42 */
 43int amdgpu_dm_irq_init(struct amdgpu_device *adev);
 44
 45/**
 46 * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
 47 *
 48 * This function should be called exactly once - during DM destruction.
 49 *
 50 */
 51void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
 52
 53/**
 54 * amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
 55 *
 56 * @adev: AMD DRM device
 57 * @int_params: parameters for the irq
 58 * @ih: pointer to the irq hander function
 59 * @handler_args: arguments which will be passed to ih
 60 *
 61 * Returns:
 62 * 	IRQ Handler Index on success.
 63 * 	NULL on failure.
 64 *
 65 * Cannot be called from an interrupt handler.
 66 */
 67void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
 68				       struct dc_interrupt_params *int_params,
 69				       void (*ih)(void *),
 70				       void *handler_args);
 71
 72/**
 73 * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
 74 *	by amdgpu_dm_irq_register_interrupt().
 75 *
 76 * @adev: AMD DRM device.
 77 * @ih_index: irq handler index which was returned by
 78 *	amdgpu_dm_irq_register_interrupt
 79 */
 80void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
 81					enum dc_irq_source irq_source,
 82					void *ih_index);
 83
 84void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
 85
 86void amdgpu_dm_outbox_init(struct amdgpu_device *adev);
 87void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
 88void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
 89
 90/**
 91 * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
 92 *
 93 */
 94void amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
 95
 96/**
 97 * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
 98 * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
 99 *
100 */
101void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
102void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
103
104#endif /* __AMDGPU_DM_IRQ_H__ */