amdgpu_dm_helpers.c

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright 2015 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include <acpi/video.h>
  28
  29#include <linux/string.h>
  30#include <linux/acpi.h>
  31#include <linux/i2c.h>
  32
  33#include <drm/drm_atomic.h>
  34#include <drm/drm_probe_helper.h>
  35#include <drm/amdgpu_drm.h>
  36#include <drm/drm_edid.h>
  37#include <drm/drm_fixed.h>
  38
  39#include "dm_services.h"
  40#include "amdgpu.h"
  41#include "dc.h"
  42#include "amdgpu_dm.h"
  43#include "amdgpu_dm_irq.h"
  44#include "amdgpu_dm_mst_types.h"
  45#include "dpcd_defs.h"
  46#include "dc/inc/core_types.h"
  47
  48#include "dm_helpers.h"
  49#include "ddc_service_types.h"
  50#include "clk_mgr.h"
  51
  52static u32 edid_extract_panel_id(struct edid *edid)
  53{
  54	return (u32)edid->mfg_id[0] << 24   |
  55	       (u32)edid->mfg_id[1] << 16   |
  56	       (u32)EDID_PRODUCT_ID(edid);
  57}
  58
  59static void apply_edid_quirks(struct drm_device *dev, struct edid *edid, struct dc_edid_caps *edid_caps)
  60{
  61	uint32_t panel_id = edid_extract_panel_id(edid);
  62
  63	switch (panel_id) {
  64	/* Workaround for monitors that need a delay after detecting the link */
  65	case drm_edid_encode_panel_id('G', 'B', 'T', 0x3215):
  66		drm_dbg_driver(dev, "Add 10s delay for link detection for panel id %X\n", panel_id);
  67		edid_caps->panel_patch.wait_after_dpcd_poweroff_ms = 10000;
  68		break;
  69	/* Workaround for some monitors which does not work well with FAMS */
  70	case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  71	case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  72	case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  73		drm_dbg_driver(dev, "Disabling FAMS on monitor with panel id %X\n", panel_id);
  74		edid_caps->panel_patch.disable_fams = true;
  75		break;
  76	/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
  77	case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
  78	case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
  79	case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
  80	case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
  81	case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):
  82		drm_dbg_driver(dev, "Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
  83		edid_caps->panel_patch.remove_sink_ext_caps = true;
  84		break;
  85	case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154):
  86	case drm_edid_encode_panel_id('S', 'D', 'C', 0x4171):
  87		drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id);
  88		edid_caps->panel_patch.disable_colorimetry = true;
  89		break;
  90	default:
  91		return;
  92	}
  93}
  94
  95/**
  96 * dm_helpers_parse_edid_caps() - Parse edid caps
  97 *
  98 * @link: current detected link
  99 * @edid:	[in] pointer to edid
 100 * @edid_caps:	[in] pointer to edid caps
 101 *
 102 * Return: void
 103 */
 104enum dc_edid_status dm_helpers_parse_edid_caps(
 105		struct dc_link *link,
 106		const struct dc_edid *edid,
 107		struct dc_edid_caps *edid_caps)
 108{
 109	struct amdgpu_dm_connector *aconnector = link->priv;
 110	struct drm_connector *connector = &aconnector->base;
 111	struct drm_device *dev = connector->dev;
 112	struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
 113	struct cea_sad *sads;
 114	int sad_count = -1;
 115	int sadb_count = -1;
 116	int i = 0;
 117	uint8_t *sadb = NULL;
 118
 119	enum dc_edid_status result = EDID_OK;
 120
 121	if (!edid_caps || !edid)
 122		return EDID_BAD_INPUT;
 123
 124	if (!drm_edid_is_valid(edid_buf))
 125		result = EDID_BAD_CHECKSUM;
 126
 127	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 128					((uint16_t) edid_buf->mfg_id[1])<<8;
 129	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 130					((uint16_t) edid_buf->prod_code[1])<<8;
 131	edid_caps->serial_number = edid_buf->serial;
 132	edid_caps->manufacture_week = edid_buf->mfg_week;
 133	edid_caps->manufacture_year = edid_buf->mfg_year;
 134	edid_caps->analog = !(edid_buf->input & DRM_EDID_INPUT_DIGITAL);
 135
 136	drm_edid_get_monitor_name(edid_buf,
 137				  edid_caps->display_name,
 138				  AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 139
 140	edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 141
 142	if (edid_caps->edid_hdmi)
 143		populate_hdmi_info_from_connector(&connector->display_info.hdmi, edid_caps);
 144
 145	apply_edid_quirks(dev, edid_buf, edid_caps);
 146
 147	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 148	if (sad_count <= 0)
 149		return result;
 150
 151	edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 152	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 153		struct cea_sad *sad = &sads[i];
 154
 155		edid_caps->audio_modes[i].format_code = sad->format;
 156		edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 157		edid_caps->audio_modes[i].sample_rate = sad->freq;
 158		edid_caps->audio_modes[i].sample_size = sad->byte2;
 159	}
 160
 161	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 162
 163	if (sadb_count < 0) {
 164		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 165		sadb_count = 0;
 166	}
 167
 168	if (sadb_count)
 169		edid_caps->speaker_flags = sadb[0];
 170	else
 171		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 172
 173	kfree(sads);
 174	kfree(sadb);
 175
 176	return result;
 177}
 178
 179static void
 180fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 181				   bool enable,
 182				   struct drm_dp_mst_atomic_payload *target_payload,
 183				   struct dc_dp_mst_stream_allocation_table *table)
 184{
 185	struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 186	struct dc_dp_mst_stream_allocation *sa;
 187	struct link_mst_stream_allocation_table copy_of_link_table =
 188										link->mst_stream_alloc_table;
 189
 190	int i;
 191	int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 192	struct link_mst_stream_allocation *dc_alloc;
 193
 194	/* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 195	if (enable) {
 196		dc_alloc =
 197		&copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 198		dc_alloc->vcp_id = target_payload->vcpi;
 199		dc_alloc->slot_count = target_payload->time_slots;
 200	} else {
 201		for (i = 0; i < copy_of_link_table.stream_count; i++) {
 202			dc_alloc =
 203			&copy_of_link_table.stream_allocations[i];
 204
 205			if (dc_alloc->vcp_id == target_payload->vcpi) {
 206				dc_alloc->vcp_id = 0;
 207				dc_alloc->slot_count = 0;
 208				break;
 209			}
 210		}
 211		ASSERT(i != copy_of_link_table.stream_count);
 212	}
 213
 214	/* Fill payload info*/
 215	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 216		dc_alloc =
 217			&copy_of_link_table.stream_allocations[i];
 218		if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 219			sa = &new_table.stream_allocations[new_table.stream_count];
 220			sa->slot_count = dc_alloc->slot_count;
 221			sa->vcp_id = dc_alloc->vcp_id;
 222			new_table.stream_count++;
 223		}
 224	}
 225
 226	/* Overwrite the old table */
 227	*table = new_table;
 228}
 229
 230void dm_helpers_dp_update_branch_info(
 231	struct dc_context *ctx,
 232	const struct dc_link *link)
 233{}
 234
 235static void dm_helpers_construct_old_payload(
 236			struct drm_dp_mst_topology_mgr *mgr,
 237			struct drm_dp_mst_topology_state *mst_state,
 238			struct drm_dp_mst_atomic_payload *new_payload,
 239			struct drm_dp_mst_atomic_payload *old_payload)
 240{
 241	struct drm_dp_mst_atomic_payload *pos;
 242	int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
 243	u8 next_payload_vc_start = mgr->next_start_slot;
 244	u8 payload_vc_start = new_payload->vc_start_slot;
 245	u8 allocated_time_slots;
 246
 247	*old_payload = *new_payload;
 248
 249	/* Set correct time_slots/PBN of old payload.
 250	 * other fields (delete & dsc_enabled) in
 251	 * struct drm_dp_mst_atomic_payload are don't care fields
 252	 * while calling drm_dp_remove_payload_part2()
 253	 */
 254	list_for_each_entry(pos, &mst_state->payloads, next) {
 255		if (pos != new_payload &&
 256		    pos->vc_start_slot > payload_vc_start &&
 257		    pos->vc_start_slot < next_payload_vc_start)
 258			next_payload_vc_start = pos->vc_start_slot;
 259	}
 260
 261	allocated_time_slots = next_payload_vc_start - payload_vc_start;
 262
 263	old_payload->time_slots = allocated_time_slots;
 264	old_payload->pbn = allocated_time_slots * pbn_per_slot;
 265}
 266
 267/*
 268 * Writes payload allocation table in immediate downstream device.
 269 */
 270bool dm_helpers_dp_mst_write_payload_allocation_table(
 271		struct dc_context *ctx,
 272		const struct dc_stream_state *stream,
 273		struct dc_dp_mst_stream_allocation_table *proposed_table,
 274		bool enable)
 275{
 276	struct amdgpu_dm_connector *aconnector;
 277	struct drm_dp_mst_topology_state *mst_state;
 278	struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 279	struct drm_dp_mst_topology_mgr *mst_mgr;
 280
 281	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 282	/* Accessing the connector state is required for vcpi_slots allocation
 283	 * and directly relies on behaviour in commit check
 284	 * that blocks before commit guaranteeing that the state
 285	 * is not gonna be swapped while still in use in commit tail
 286	 */
 287
 288	if (!aconnector || !aconnector->mst_root)
 289		return false;
 290
 291	mst_mgr = &aconnector->mst_root->mst_mgr;
 292	mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 293	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 294
 295	if (enable) {
 296		target_payload = new_payload;
 297
 298		/* It's OK for this to fail */
 299		drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 300	} else {
 301		/* construct old payload by VCPI*/
 302		dm_helpers_construct_old_payload(mst_mgr, mst_state,
 303						 new_payload, &old_payload);
 304		target_payload = &old_payload;
 305
 306		drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
 307	}
 308
 309	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 310	 * AUX message. The sequence is slot 1-63 allocated sequence for each
 311	 * stream. AMD ASIC stream slot allocation should follow the same
 312	 * sequence. copy DRM MST allocation to dc
 313	 */
 314	fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 315
 316	return true;
 317}
 318
 319/*
 320 * poll pending down reply
 321 */
 322void dm_helpers_dp_mst_poll_pending_down_reply(
 323	struct dc_context *ctx,
 324	const struct dc_link *link)
 325{}
 326
 327/*
 328 * Clear payload allocation table before enable MST DP link.
 329 */
 330void dm_helpers_dp_mst_clear_payload_allocation_table(
 331	struct dc_context *ctx,
 332	const struct dc_link *link)
 333{}
 334
 335/*
 336 * Polls for ACT (allocation change trigger) handled and sends
 337 * ALLOCATE_PAYLOAD message.
 338 */
 339enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 340		struct dc_context *ctx,
 341		const struct dc_stream_state *stream)
 342{
 343	struct amdgpu_dm_connector *aconnector;
 344	struct drm_dp_mst_topology_mgr *mst_mgr;
 345	int ret;
 346
 347	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 348
 349	if (!aconnector || !aconnector->mst_root)
 350		return ACT_FAILED;
 351
 352	mst_mgr = &aconnector->mst_root->mst_mgr;
 353
 354	if (!mst_mgr->mst_state)
 355		return ACT_FAILED;
 356
 357	ret = drm_dp_check_act_status(mst_mgr);
 358
 359	if (ret)
 360		return ACT_FAILED;
 361
 362	return ACT_SUCCESS;
 363}
 364
 365void dm_helpers_dp_mst_send_payload_allocation(
 366		struct dc_context *ctx,
 367		const struct dc_stream_state *stream)
 368{
 369	struct amdgpu_dm_connector *aconnector;
 370	struct drm_dp_mst_topology_state *mst_state;
 371	struct drm_dp_mst_topology_mgr *mst_mgr;
 372	struct drm_dp_mst_atomic_payload *new_payload;
 373	enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 374	enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 375	int ret = 0;
 376
 377	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 378
 379	if (!aconnector || !aconnector->mst_root)
 380		return;
 381
 382	mst_mgr = &aconnector->mst_root->mst_mgr;
 383	mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 384	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 385
 386	ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
 387
 388	if (ret) {
 389		amdgpu_dm_set_mst_status(&aconnector->mst_status,
 390			set_flag, false);
 391	} else {
 392		amdgpu_dm_set_mst_status(&aconnector->mst_status,
 393			set_flag, true);
 394		amdgpu_dm_set_mst_status(&aconnector->mst_status,
 395			clr_flag, false);
 396	}
 397}
 398
 399void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(
 400		struct dc_context *ctx,
 401		const struct dc_stream_state *stream)
 402{
 403	struct amdgpu_dm_connector *aconnector;
 404	struct drm_dp_mst_topology_state *mst_state;
 405	struct drm_dp_mst_topology_mgr *mst_mgr;
 406	struct drm_dp_mst_atomic_payload *new_payload, old_payload;
 407	enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 408	enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 409
 410	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 411
 412	if (!aconnector || !aconnector->mst_root)
 413		return;
 414
 415	mst_mgr = &aconnector->mst_root->mst_mgr;
 416	mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 417	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 418	dm_helpers_construct_old_payload(mst_mgr, mst_state,
 419					 new_payload, &old_payload);
 420
 421	drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
 422
 423	amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);
 424	amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);
 425 }
 426
 427void dm_dtn_log_begin(struct dc_context *ctx,
 428	struct dc_log_buffer_ctx *log_ctx)
 429{
 430	static const char msg[] = "[dtn begin]\n";
 431
 432	if (!log_ctx) {
 433		pr_info("%s", msg);
 434		return;
 435	}
 436
 437	dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 438}
 439
 440__printf(3, 4)
 441void dm_dtn_log_append_v(struct dc_context *ctx,
 442	struct dc_log_buffer_ctx *log_ctx,
 443	const char *msg, ...)
 444{
 445	va_list args;
 446	size_t total;
 447	int n;
 448
 449	if (!log_ctx) {
 450		/* No context, redirect to dmesg. */
 451		struct va_format vaf;
 452
 453		vaf.fmt = msg;
 454		vaf.va = &args;
 455
 456		va_start(args, msg);
 457		pr_info("%pV", &vaf);
 458		va_end(args);
 459
 460		return;
 461	}
 462
 463	/* Measure the output. */
 464	va_start(args, msg);
 465	n = vsnprintf(NULL, 0, msg, args);
 466	va_end(args);
 467
 468	if (n <= 0)
 469		return;
 470
 471	/* Reallocate the string buffer as needed. */
 472	total = log_ctx->pos + n + 1;
 473
 474	if (total > log_ctx->size) {
 475		char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 476
 477		if (buf) {
 478			memcpy(buf, log_ctx->buf, log_ctx->pos);
 479			kfree(log_ctx->buf);
 480
 481			log_ctx->buf = buf;
 482			log_ctx->size = total;
 483		}
 484	}
 485
 486	if (!log_ctx->buf)
 487		return;
 488
 489	/* Write the formatted string to the log buffer. */
 490	va_start(args, msg);
 491	n = vscnprintf(
 492		log_ctx->buf + log_ctx->pos,
 493		log_ctx->size - log_ctx->pos,
 494		msg,
 495		args);
 496	va_end(args);
 497
 498	if (n > 0)
 499		log_ctx->pos += n;
 500}
 501
 502void dm_dtn_log_end(struct dc_context *ctx,
 503	struct dc_log_buffer_ctx *log_ctx)
 504{
 505	static const char msg[] = "[dtn end]\n";
 506
 507	if (!log_ctx) {
 508		pr_info("%s", msg);
 509		return;
 510	}
 511
 512	dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 513}
 514
 515bool dm_helpers_dp_mst_start_top_mgr(
 516		struct dc_context *ctx,
 517		const struct dc_link *link,
 518		bool boot)
 519{
 520	struct amdgpu_dm_connector *aconnector = link->priv;
 521	int ret;
 522
 523	if (!aconnector) {
 524		DRM_ERROR("Failed to find connector for link!");
 525		return false;
 526	}
 527
 528	if (boot) {
 529		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 530					aconnector, aconnector->base.base.id);
 531		return true;
 532	}
 533
 534	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 535			aconnector, aconnector->base.base.id);
 536
 537	ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 538	if (ret < 0) {
 539		DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 540		return false;
 541	}
 542
 543	DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 544		aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 545
 546	return true;
 547}
 548
 549bool dm_helpers_dp_mst_stop_top_mgr(
 550		struct dc_context *ctx,
 551		struct dc_link *link)
 552{
 553	struct amdgpu_dm_connector *aconnector = link->priv;
 554
 555	if (!aconnector) {
 556		DRM_ERROR("Failed to find connector for link!");
 557		return false;
 558	}
 559
 560	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 561			aconnector, aconnector->base.base.id);
 562
 563	if (aconnector->mst_mgr.mst_state == true) {
 564		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 565		link->cur_link_settings.lane_count = 0;
 566	}
 567
 568	return false;
 569}
 570
 571bool dm_helpers_dp_read_dpcd(
 572		struct dc_context *ctx,
 573		const struct dc_link *link,
 574		uint32_t address,
 575		uint8_t *data,
 576		uint32_t size)
 577{
 578
 579	struct amdgpu_dm_connector *aconnector = link->priv;
 580
 581	if (!aconnector)
 582		return false;
 583
 584	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 585				size) == size;
 586}
 587
 588bool dm_helpers_dp_write_dpcd(
 589		struct dc_context *ctx,
 590		const struct dc_link *link,
 591		uint32_t address,
 592		const uint8_t *data,
 593		uint32_t size)
 594{
 595	struct amdgpu_dm_connector *aconnector = link->priv;
 596
 597	if (!aconnector)
 598		return false;
 599
 600	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 601			address, (uint8_t *)data, size) > 0;
 602}
 603
 604bool dm_helpers_submit_i2c(
 605		struct dc_context *ctx,
 606		const struct dc_link *link,
 607		struct i2c_command *cmd)
 608{
 609	struct amdgpu_dm_connector *aconnector = link->priv;
 610	struct i2c_msg *msgs;
 611	int i = 0;
 612	int num = cmd->number_of_payloads;
 613	bool result;
 614
 615	if (!aconnector) {
 616		DRM_ERROR("Failed to find connector for link!");
 617		return false;
 618	}
 619
 620	msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 621
 622	if (!msgs)
 623		return false;
 624
 625	for (i = 0; i < num; i++) {
 626		msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 627		msgs[i].addr = cmd->payloads[i].address;
 628		msgs[i].len = cmd->payloads[i].length;
 629		msgs[i].buf = cmd->payloads[i].data;
 630	}
 631
 632	result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 633
 634	kfree(msgs);
 635
 636	return result;
 637}
 638
 639bool dm_helpers_execute_fused_io(
 640		struct dc_context *ctx,
 641		struct dc_link *link,
 642		union dmub_rb_cmd *commands,
 643		uint8_t count,
 644		uint32_t timeout_us
 645)
 646{
 647	struct amdgpu_device *dev = ctx->driver_context;
 648
 649	return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us);
 650}
 651
 652static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 653		bool is_write_cmd,
 654		unsigned char cmd,
 655		unsigned int length,
 656		unsigned int offset,
 657		unsigned char *data)
 658{
 659	bool success = false;
 660	unsigned char rc_data[16] = {0};
 661	unsigned char rc_offset[4] = {0};
 662	unsigned char rc_length[2] = {0};
 663	unsigned char rc_cmd = 0;
 664	unsigned char rc_result = 0xFF;
 665	unsigned char i = 0;
 666	int ret;
 667
 668	if (is_write_cmd) {
 669		// write rc data
 670		memmove(rc_data, data, length);
 671		ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 672		if (ret < 0)
 673			goto err;
 674	}
 675
 676	// write rc offset
 677	rc_offset[0] = (unsigned char) offset & 0xFF;
 678	rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 679	rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 680	rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 681	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 682	if (ret < 0)
 683		goto err;
 684
 685	// write rc length
 686	rc_length[0] = (unsigned char) length & 0xFF;
 687	rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 688	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 689	if (ret < 0)
 690		goto err;
 691
 692	// write rc cmd
 693	rc_cmd = cmd | 0x80;
 694	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 695	if (ret < 0)
 696		goto err;
 697
 698	// poll until active is 0
 699	for (i = 0; i < 10; i++) {
 700		drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 701		if (rc_cmd == cmd)
 702			// active is 0
 703			break;
 704		msleep(10);
 705	}
 706
 707	// read rc result
 708	drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 709	success = (rc_result == 0);
 710
 711	if (success && !is_write_cmd) {
 712		// read rc data
 713		drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 714	}
 715
 716	drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
 717
 718	return success;
 719
 720err:
 721	DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 722	return false;
 723}
 724
 725static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 726{
 727	unsigned char data[16] = {0};
 728
 729	drm_dbg_dp(aux->drm_dev, "Start\n");
 730
 731	// Step 2
 732	data[0] = 'P';
 733	data[1] = 'R';
 734	data[2] = 'I';
 735	data[3] = 'U';
 736	data[4] = 'S';
 737
 738	if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 739		return;
 740
 741	// Step 3 and 4
 742	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 743		return;
 744
 745	data[0] &= (~(1 << 1)); // set bit 1 to 0
 746	if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 747		return;
 748
 749	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 750		return;
 751
 752	data[0] &= (~(1 << 1)); // set bit 1 to 0
 753	if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 754		return;
 755
 756	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 757		return;
 758
 759	data[0] &= (~(1 << 1)); // set bit 1 to 0
 760	if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 761		return;
 762
 763	// Step 3 and 5
 764	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 765		return;
 766
 767	data[0] |= (1 << 1); // set bit 1 to 1
 768	if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 769		return;
 770
 771	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 772		return;
 773
 774	data[0] |= (1 << 1); // set bit 1 to 1
 775
 776	if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 777		return;
 778
 779	data[0] |= (1 << 1); // set bit 1 to 1
 780	if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 781		return;
 782
 783	// Step 6
 784	if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 785		return;
 786
 787	drm_dbg_dp(aux->drm_dev, "Done\n");
 788}
 789
 790/* MST Dock */
 791static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 792
 793static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 794		struct drm_dp_aux *aux,
 795		const struct dc_stream_state *stream,
 796		bool enable)
 797{
 798	uint8_t ret = 0;
 799
 800	drm_dbg_dp(aux->drm_dev,
 801		   "MST_DSC Configure DSC to non-virtual dpcd synaptics\n");
 802
 803	if (enable) {
 804		/* When DSC is enabled on previous boot and reboot with the hub,
 805		 * there is a chance that Synaptics hub gets stuck during reboot sequence.
 806		 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 807		 */
 808		if (!stream->link->link_status.link_active &&
 809			memcmp(stream->link->dpcd_caps.branch_dev_name,
 810				(int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 811			apply_synaptics_fifo_reset_wa(aux);
 812
 813		ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 814		DRM_INFO("MST_DSC Send DSC enable to synaptics\n");
 815
 816	} else {
 817		/* Synaptics hub not support virtual dpcd,
 818		 * external monitor occur garbage while disable DSC,
 819		 * Disable DSC only when entire link status turn to false,
 820		 */
 821		if (!stream->link->link_status.link_active) {
 822			ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 823			DRM_INFO("MST_DSC Send DSC disable to synaptics\n");
 824		}
 825	}
 826
 827	return ret;
 828}
 829
 830bool dm_helpers_dp_write_dsc_enable(
 831		struct dc_context *ctx,
 832		const struct dc_stream_state *stream,
 833		bool enable)
 834{
 835	static const uint8_t DSC_DISABLE;
 836	static const uint8_t DSC_DECODING = 0x01;
 837	static const uint8_t DSC_PASSTHROUGH = 0x02;
 838
 839	struct amdgpu_dm_connector *aconnector =
 840		(struct amdgpu_dm_connector *)stream->dm_stream_context;
 841	struct drm_device *dev = aconnector->base.dev;
 842	struct drm_dp_mst_port *port;
 843	uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 844	uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 845	uint8_t ret = 0;
 846
 847	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 848		if (!aconnector->dsc_aux)
 849			return false;
 850
 851		// apply w/a to synaptics
 852		if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 853		    (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 854			return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 855				aconnector->dsc_aux, stream, enable_dsc);
 856
 857		port = aconnector->mst_output_port;
 858
 859		if (enable) {
 860			if (port->passthrough_aux) {
 861				ret = drm_dp_dpcd_write(port->passthrough_aux,
 862							DP_DSC_ENABLE,
 863							&enable_passthrough, 1);
 864				drm_dbg_dp(dev,
 865					   "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 866					   ret);
 867			}
 868
 869			ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 870						DP_DSC_ENABLE, &enable_dsc, 1);
 871			drm_dbg_dp(dev,
 872				   "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n",
 873				   (port->passthrough_aux) ? "remote RX" :
 874				   "virtual dpcd",
 875				   ret);
 876		} else {
 877			ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 878						DP_DSC_ENABLE, &enable_dsc, 1);
 879			drm_dbg_dp(dev,
 880				   "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n",
 881				   (port->passthrough_aux) ? "remote RX" :
 882				   "virtual dpcd",
 883				   ret);
 884
 885			if (port->passthrough_aux) {
 886				ret = drm_dp_dpcd_write(port->passthrough_aux,
 887							DP_DSC_ENABLE,
 888							&enable_passthrough, 1);
 889				drm_dbg_dp(dev,
 890					   "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 891					   ret);
 892			}
 893		}
 894	}
 895
 896	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 897		if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 898			ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 899			drm_dbg_dp(dev,
 900				   "SST_DSC Send DSC %s to SST RX\n",
 901				   enable_dsc ? "enable" : "disable");
 902		} else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 903			ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 904			drm_dbg_dp(dev,
 905				   "SST_DSC Send DSC %s to DP-HDMI PCON\n",
 906				   enable_dsc ? "enable" : "disable");
 907		}
 908	}
 909
 910	return ret;
 911}
 912
 913bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream)
 914{
 915	// TODO
 916	return false;
 917}
 918
 919bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 920{
 921	bool dp_sink_present;
 922	struct amdgpu_dm_connector *aconnector = link->priv;
 923
 924	if (!aconnector) {
 925		BUG_ON("Failed to find connector for link!");
 926		return true;
 927	}
 928
 929	mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 930	dp_sink_present = dc_link_is_dp_sink_present(link);
 931	mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 932	return dp_sink_present;
 933}
 934
 935static int
 936dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)
 937{
 938	struct drm_connector *connector = data;
 939	struct acpi_device *acpidev = ACPI_COMPANION(connector->dev->dev);
 940	unsigned short start = block * EDID_LENGTH;
 941	struct edid *edid;
 942	int r;
 943
 944	if (!acpidev)
 945		return -ENODEV;
 946
 947	/* fetch the entire edid from BIOS */
 948	r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, (void *)&edid);
 949	if (r < 0) {
 950		drm_dbg(connector->dev, "Failed to get EDID from ACPI: %d\n", r);
 951		return r;
 952	}
 953	if (len > r || start > r || start + len > r) {
 954		r = -EINVAL;
 955		goto cleanup;
 956	}
 957
 958	/* sanity check */
 959	if (edid->revision < 4 || !(edid->input & DRM_EDID_INPUT_DIGITAL) ||
 960	    (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_UNDEF) {
 961		r = -EINVAL;
 962		goto cleanup;
 963	}
 964
 965	memcpy(buf, (void *)edid + start, len);
 966	r = 0;
 967
 968cleanup:
 969	kfree(edid);
 970
 971	return r;
 972}
 973
 974static const struct drm_edid *
 975dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)
 976{
 977	struct drm_connector *connector = &aconnector->base;
 978
 979	if (amdgpu_dc_debug_mask & DC_DISABLE_ACPI_EDID)
 980		return NULL;
 981
 982	switch (connector->connector_type) {
 983	case DRM_MODE_CONNECTOR_LVDS:
 984	case DRM_MODE_CONNECTOR_eDP:
 985		break;
 986	default:
 987		return NULL;
 988	}
 989
 990	if (connector->force == DRM_FORCE_OFF)
 991		return NULL;
 992
 993	return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector);
 994}
 995
 996void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps)
 997{
 998	edid_caps->scdc_present = hdmi->scdc.supported;
 999}
1000
1001enum dc_edid_status dm_helpers_read_local_edid(
1002		struct dc_context *ctx,
1003		struct dc_link *link,
1004		struct dc_sink *sink)
1005{
1006	struct amdgpu_dm_connector *aconnector = link->priv;
1007	struct drm_connector *connector = &aconnector->base;
1008	struct i2c_adapter *ddc;
1009	int retry = 25;
1010	enum dc_edid_status edid_status = EDID_NO_RESPONSE;
1011	const struct drm_edid *drm_edid;
1012	const struct edid *edid;
1013
1014	if (link->aux_mode)
1015		ddc = &aconnector->dm_dp_aux.aux.ddc;
1016	else
1017		ddc = &aconnector->i2c->base;
1018
1019	/* some dongles read edid incorrectly the first time,
1020	 * do check sum and retry to make sure read correct edid.
1021	 */
1022	do {
1023		drm_edid = dm_helpers_read_acpi_edid(aconnector);
1024		if (drm_edid)
1025			drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name);
1026		else
1027			drm_edid = drm_edid_read_ddc(connector, ddc);
1028		drm_edid_connector_update(connector, drm_edid);
1029
1030		/* DP Compliance Test 4.2.2.6 */
1031		if (link->aux_mode && connector->edid_corrupt)
1032			drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
1033
1034		if (!drm_edid && connector->edid_corrupt) {
1035			connector->edid_corrupt = false;
1036			return EDID_BAD_CHECKSUM;
1037		}
1038
1039		if (!drm_edid)
1040			continue;
1041
1042		edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
1043		if (!edid ||
1044		    edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH)
1045			return EDID_BAD_INPUT;
1046
1047		sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
1048		memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
1049
1050		/* We don't need the original edid anymore */
1051		drm_edid_free(drm_edid);
1052
1053		edid_status = dm_helpers_parse_edid_caps(
1054						link,
1055						&sink->dc_edid,
1056						&sink->edid_caps);
1057
1058	} while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) && --retry > 0);
1059
1060	if (edid_status != EDID_OK)
1061		DRM_ERROR("EDID err: %d, on connector: %s",
1062				edid_status,
1063				aconnector->base.name);
1064	if (link->aux_mode) {
1065		union test_request test_request = {0};
1066		union test_response test_response = {0};
1067
1068		dm_helpers_dp_read_dpcd(ctx,
1069					link,
1070					DP_TEST_REQUEST,
1071					&test_request.raw,
1072					sizeof(union test_request));
1073
1074		if (!test_request.bits.EDID_READ)
1075			return edid_status;
1076
1077		test_response.bits.EDID_CHECKSUM_WRITE = 1;
1078
1079		dm_helpers_dp_write_dpcd(ctx,
1080					link,
1081					DP_TEST_EDID_CHECKSUM,
1082					&sink->dc_edid.raw_edid[sink->dc_edid.length-1],
1083					1);
1084
1085		dm_helpers_dp_write_dpcd(ctx,
1086					link,
1087					DP_TEST_RESPONSE,
1088					&test_response.raw,
1089					sizeof(test_response));
1090
1091	}
1092
1093	return edid_status;
1094}
1095int dm_helper_dmub_aux_transfer_sync(
1096		struct dc_context *ctx,
1097		const struct dc_link *link,
1098		struct aux_payload *payload,
1099		enum aux_return_code_type *operation_result)
1100{
1101	if (!link->hpd_status) {
1102		*operation_result = AUX_RET_ERROR_HPD_DISCON;
1103		return -1;
1104	}
1105
1106	return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
1107			operation_result);
1108}
1109
1110int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
1111		const struct dc_link *link,
1112		struct set_config_cmd_payload *payload,
1113		enum set_config_status *operation_result)
1114{
1115	return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
1116			operation_result);
1117}
1118
1119void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
1120{
1121	/* TODO: something */
1122}
1123
1124void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
1125{
1126	// TODO:
1127	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
1128}
1129
1130void dm_helpers_init_panel_settings(
1131	struct dc_context *ctx,
1132	struct dc_panel_config *panel_config,
1133	struct dc_sink *sink)
1134{
1135	// Extra Panel Power Sequence
1136	panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
1137	panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
1138	panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
1139	panel_config->pps.extra_post_t7_ms = 0;
1140	panel_config->pps.extra_pre_t11_ms = 0;
1141	panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
1142	panel_config->pps.extra_post_OUI_ms = 0;
1143	// Feature DSC
1144	panel_config->dsc.disable_dsc_edp = false;
1145	panel_config->dsc.force_dsc_edp_policy = 0;
1146}
1147
1148void dm_helpers_override_panel_settings(
1149	struct dc_context *ctx,
1150	struct dc_panel_config *panel_config)
1151{
1152	// Feature DSC
1153	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1154		panel_config->dsc.disable_dsc_edp = true;
1155}
1156
1157void *dm_helpers_allocate_gpu_mem(
1158		struct dc_context *ctx,
1159		enum dc_gpu_mem_alloc_type type,
1160		size_t size,
1161		long long *addr)
1162{
1163	struct amdgpu_device *adev = ctx->driver_context;
1164
1165	return dm_allocate_gpu_mem(adev, type, size, addr);
1166}
1167
1168void dm_helpers_free_gpu_mem(
1169		struct dc_context *ctx,
1170		enum dc_gpu_mem_alloc_type type,
1171		void *pvMem)
1172{
1173	struct amdgpu_device *adev = ctx->driver_context;
1174
1175	dm_free_gpu_mem(adev, type, pvMem);
1176}
1177
1178bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1179{
1180	enum dc_irq_source irq_source;
1181	bool ret;
1182
1183	irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1184
1185	ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1186
1187	DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1188			 enable ? "en" : "dis", ret);
1189	return ret;
1190}
1191
1192void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1193{
1194	/* TODO: virtual DPCD */
1195	struct dc_link *link = stream->link;
1196	union down_spread_ctrl old_downspread;
1197	union down_spread_ctrl new_downspread;
1198
1199	if (link->aux_access_disabled)
1200		return;
1201
1202	if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1203				     &old_downspread.raw,
1204				     sizeof(old_downspread)))
1205		return;
1206
1207	new_downspread.raw = old_downspread.raw;
1208	new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1209		(stream->ignore_msa_timing_param) ? 1 : 0;
1210
1211	if (new_downspread.raw != old_downspread.raw)
1212		dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1213					 &new_downspread.raw,
1214					 sizeof(new_downspread));
1215}
1216
1217bool dm_helpers_dp_handle_test_pattern_request(
1218		struct dc_context *ctx,
1219		const struct dc_link *link,
1220		union link_test_pattern dpcd_test_pattern,
1221		union test_misc dpcd_test_params)
1222{
1223	enum dp_test_pattern test_pattern;
1224	enum dp_test_pattern_color_space test_pattern_color_space =
1225			DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1226	enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1227	enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1228	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1229	struct pipe_ctx *pipe_ctx = NULL;
1230	struct amdgpu_dm_connector *aconnector = link->priv;
1231	struct drm_device *dev = aconnector->base.dev;
1232	struct dc_state *dc_state = ctx->dc->current_state;
1233	struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
1234	int i;
1235
1236	for (i = 0; i < MAX_PIPES; i++) {
1237		if (pipes[i].stream == NULL)
1238			continue;
1239
1240		if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1241			!pipes[i].prev_odm_pipe) {
1242			pipe_ctx = &pipes[i];
1243			break;
1244		}
1245	}
1246
1247	if (pipe_ctx == NULL)
1248		return false;
1249
1250	switch (dpcd_test_pattern.bits.PATTERN) {
1251	case LINK_TEST_PATTERN_COLOR_RAMP:
1252		test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1253	break;
1254	case LINK_TEST_PATTERN_VERTICAL_BARS:
1255		test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1256	break; /* black and white */
1257	case LINK_TEST_PATTERN_COLOR_SQUARES:
1258		test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1259				TEST_DYN_RANGE_VESA ?
1260				DP_TEST_PATTERN_COLOR_SQUARES :
1261				DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1262	break;
1263	default:
1264		test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1265	break;
1266	}
1267
1268	if (dpcd_test_params.bits.CLR_FORMAT == 0)
1269		test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1270	else
1271		test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1272				DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1273				DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1274
1275	switch (dpcd_test_params.bits.BPC) {
1276	case 0: // 6 bits
1277		requestColorDepth = COLOR_DEPTH_666;
1278		break;
1279	case 1: // 8 bits
1280		requestColorDepth = COLOR_DEPTH_888;
1281		break;
1282	case 2: // 10 bits
1283		requestColorDepth = COLOR_DEPTH_101010;
1284		break;
1285	case 3: // 12 bits
1286		requestColorDepth = COLOR_DEPTH_121212;
1287		break;
1288	default:
1289		break;
1290	}
1291
1292	switch (dpcd_test_params.bits.CLR_FORMAT) {
1293	case 0:
1294		requestPixelEncoding = PIXEL_ENCODING_RGB;
1295		break;
1296	case 1:
1297		requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1298		break;
1299	case 2:
1300		requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1301		break;
1302	default:
1303		requestPixelEncoding = PIXEL_ENCODING_RGB;
1304		break;
1305	}
1306
1307	if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1308		&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1309		|| (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1310		&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1311		drm_dbg(dev,
1312			"original bpc %d pix encoding %d, changing to %d  %d\n",
1313			pipe_ctx->stream->timing.display_color_depth,
1314			pipe_ctx->stream->timing.pixel_encoding,
1315			requestColorDepth,
1316			requestPixelEncoding);
1317		pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1318		pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1319
1320		dc_link_update_dsc_config(pipe_ctx);
1321
1322		aconnector->timing_changed = true;
1323		/* store current timing */
1324		if (aconnector->timing_requested)
1325			*aconnector->timing_requested = pipe_ctx->stream->timing;
1326		else
1327			drm_err(dev, "timing storage failed\n");
1328
1329	}
1330
1331	pipe_ctx->stream->test_pattern.type = test_pattern;
1332	pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
1333
1334	/* Temp W/A for compliance test failure */
1335	dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1336	dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
1337		clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
1338	dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
1339	ctx->dc->clk_mgr->funcs->update_clocks(
1340			ctx->dc->clk_mgr,
1341			dc_state,
1342			false);
1343
1344	dc_link_dp_set_test_pattern(
1345		(struct dc_link *) link,
1346		test_pattern,
1347		test_pattern_color_space,
1348		NULL,
1349		NULL,
1350		0);
1351
1352	return false;
1353}
1354
1355void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1356{
1357       // TODO
1358}
1359
1360void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1361{
1362	struct amdgpu_device *adev = ctx->driver_context;
1363
1364	if (adev->dm.idle_workqueue) {
1365		adev->dm.idle_workqueue->enable = enable;
1366		if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev))
1367			schedule_work(&adev->dm.idle_workqueue->work);
1368	}
1369}
1370
1371void dm_helpers_dp_mst_update_branch_bandwidth(
1372		struct dc_context *ctx,
1373		struct dc_link *link)
1374{
1375	// TODO
1376}
1377
1378static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1379{
1380	bool ret_val = false;
1381
1382	switch (branch_dev_id) {
1383	case DP_BRANCH_DEVICE_ID_0060AD:
1384	case DP_BRANCH_DEVICE_ID_00E04C:
1385	case DP_BRANCH_DEVICE_ID_90CC24:
1386		ret_val = true;
1387		break;
1388	default:
1389		break;
1390	}
1391
1392	return ret_val;
1393}
1394
1395enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1396{
1397	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1398	enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1399
1400	switch (dpcd_caps->dongle_type) {
1401	case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1402		if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1403			dpcd_caps->allow_invalid_MSA_timing_param == true &&
1404			dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1405			as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1406		break;
1407	default:
1408		break;
1409	}
1410
1411	return as_type;
1412}
1413
1414bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)
1415{
1416	// TODO
1417	return false;
1418}
1419
1420bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)
1421{
1422	// TODO
1423	return false;
1424}