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amdgpu_dm.c
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linux-6.19.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2015 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27/* The caprices of the preprocessor require that this be declared right here */ 28#define CREATE_TRACE_POINTS 29 30#include "dm_services_types.h" 31#include "dc.h" 32#include "link_enc_cfg.h" 33#include "dc/inc/core_types.h" 34#include "dal_asic_id.h" 35#include "dmub/dmub_srv.h" 36#include "dc/inc/hw/dmcu.h" 37#include "dc/inc/hw/abm.h" 38#include "dc/dc_dmub_srv.h" 39#include "dc/dc_edid_parser.h" 40#include "dc/dc_stat.h" 41#include "dc/dc_state.h" 42#include "amdgpu_dm_trace.h" 43#include "link/protocols/link_dpcd.h" 44#include "link_service_types.h" 45#include "link/protocols/link_dp_capability.h" 46#include "link/protocols/link_ddc.h" 47 48#include "amdgpu.h" 49#include "amdgpu_display.h" 50#include "amdgpu_ucode.h" 51#include "atom.h" 52#include "amdgpu_dm.h" 53#include "amdgpu_dm_plane.h" 54#include "amdgpu_dm_crtc.h" 55#include "amdgpu_dm_hdcp.h" 56#include <drm/display/drm_hdcp_helper.h> 57#include "amdgpu_dm_wb.h" 58#include "amdgpu_atombios.h" 59 60#include "amd_shared.h" 61#include "amdgpu_dm_irq.h" 62#include "dm_helpers.h" 63#include "amdgpu_dm_mst_types.h" 64#if defined(CONFIG_DEBUG_FS) 65#include "amdgpu_dm_debugfs.h" 66#endif 67#include "amdgpu_dm_psr.h" 68#include "amdgpu_dm_replay.h" 69 70#include "ivsrcid/ivsrcid_vislands30.h" 71 72#include <linux/backlight.h> 73#include <linux/module.h> 74#include <linux/moduleparam.h> 75#include <linux/types.h> 76#include <linux/pm_runtime.h> 77#include <linux/pci.h> 78#include <linux/power_supply.h> 79#include <linux/firmware.h> 80#include <linux/component.h> 81#include <linux/sort.h> 82 83#include <drm/drm_privacy_screen_consumer.h> 84#include <drm/display/drm_dp_mst_helper.h> 85#include <drm/display/drm_hdmi_helper.h> 86#include <drm/drm_atomic.h> 87#include <drm/drm_atomic_uapi.h> 88#include <drm/drm_atomic_helper.h> 89#include <drm/drm_blend.h> 90#include <drm/drm_fixed.h> 91#include <drm/drm_fourcc.h> 92#include <drm/drm_edid.h> 93#include <drm/drm_eld.h> 94#include <drm/drm_utils.h> 95#include <drm/drm_vblank.h> 96#include <drm/drm_audio_component.h> 97#include <drm/drm_gem_atomic_helper.h> 98 99#include <media/cec-notifier.h> 100#include <acpi/video.h> 101 102#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 103 104#include "modules/inc/mod_freesync.h" 105#include "modules/power/power_helpers.h" 106 107static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch"); 108 109#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 110MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 111#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 112MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 113#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 114MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 115#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 116MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 117#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 118MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 119#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 120MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 121#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 122MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 123#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 124MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 125#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 126MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 127#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 128MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 129#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 130MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 131 132#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 133MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 134#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 135MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 136 137#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 138MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 139 140#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 141MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 142 143#define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 144MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); 145 146#define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 147MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); 148 149#define FIRMWARE_DCN_36_DMUB "amdgpu/dcn_3_6_dmcub.bin" 150MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB); 151 152#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 153MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); 154 155/* Number of bytes in PSP header for firmware. */ 156#define PSP_HEADER_BYTES 0x100 157 158/* Number of bytes in PSP footer for firmware. */ 159#define PSP_FOOTER_BYTES 0x100 160 161/** 162 * DOC: overview 163 * 164 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 165 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 166 * requests into DC requests, and DC responses into DRM responses. 167 * 168 * The root control structure is &struct amdgpu_display_manager. 169 */ 170 171/* basic init/fini API */ 172static int amdgpu_dm_init(struct amdgpu_device *adev); 173static void amdgpu_dm_fini(struct amdgpu_device *adev); 174static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 175static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); 176static struct amdgpu_i2c_adapter * 177create_i2c(struct ddc_service *ddc_service, bool oem); 178 179static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 180{ 181 switch (link->dpcd_caps.dongle_type) { 182 case DISPLAY_DONGLE_NONE: 183 return DRM_MODE_SUBCONNECTOR_Native; 184 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 185 return DRM_MODE_SUBCONNECTOR_VGA; 186 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 187 case DISPLAY_DONGLE_DP_DVI_DONGLE: 188 return DRM_MODE_SUBCONNECTOR_DVID; 189 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 190 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 191 return DRM_MODE_SUBCONNECTOR_HDMIA; 192 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 193 default: 194 return DRM_MODE_SUBCONNECTOR_Unknown; 195 } 196} 197 198static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 199{ 200 struct dc_link *link = aconnector->dc_link; 201 struct drm_connector *connector = &aconnector->base; 202 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 203 204 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 205 return; 206 207 if (aconnector->dc_sink) 208 subconnector = get_subconnector_type(link); 209 210 drm_object_property_set_value(&connector->base, 211 connector->dev->mode_config.dp_subconnector_property, 212 subconnector); 213} 214 215/* 216 * initializes drm_device display related structures, based on the information 217 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 218 * drm_encoder, drm_mode_config 219 * 220 * Returns 0 on success 221 */ 222static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 223/* removes and deallocates the drm structures, created by the above function */ 224static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 225 226static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 227 struct amdgpu_dm_connector *amdgpu_dm_connector, 228 u32 link_index, 229 struct amdgpu_encoder *amdgpu_encoder); 230static int amdgpu_dm_encoder_init(struct drm_device *dev, 231 struct amdgpu_encoder *aencoder, 232 uint32_t link_index); 233 234static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 235 236static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); 237static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 238 239static int amdgpu_dm_atomic_check(struct drm_device *dev, 240 struct drm_atomic_state *state); 241 242static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 243static void handle_hpd_rx_irq(void *param); 244 245static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 246 int bl_idx, 247 u32 user_brightness); 248 249static bool 250is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 251 struct drm_crtc_state *new_crtc_state); 252/* 253 * dm_vblank_get_counter 254 * 255 * @brief 256 * Get counter for number of vertical blanks 257 * 258 * @param 259 * struct amdgpu_device *adev - [in] desired amdgpu device 260 * int disp_idx - [in] which CRTC to get the counter from 261 * 262 * @return 263 * Counter for vertical blanks 264 */ 265static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 266{ 267 struct amdgpu_crtc *acrtc = NULL; 268 269 if (crtc >= adev->mode_info.num_crtc) 270 return 0; 271 272 acrtc = adev->mode_info.crtcs[crtc]; 273 274 if (!acrtc->dm_irq_params.stream) { 275 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 276 crtc); 277 return 0; 278 } 279 280 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 281} 282 283static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 284 u32 *vbl, u32 *position) 285{ 286 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 287 struct amdgpu_crtc *acrtc = NULL; 288 struct dc *dc = adev->dm.dc; 289 290 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 291 return -EINVAL; 292 293 acrtc = adev->mode_info.crtcs[crtc]; 294 295 if (!acrtc->dm_irq_params.stream) { 296 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 297 crtc); 298 return 0; 299 } 300 301 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 302 dc_allow_idle_optimizations(dc, false); 303 304 /* 305 * TODO rework base driver to use values directly. 306 * for now parse it back into reg-format 307 */ 308 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 309 &v_blank_start, 310 &v_blank_end, 311 &h_position, 312 &v_position); 313 314 *position = v_position | (h_position << 16); 315 *vbl = v_blank_start | (v_blank_end << 16); 316 317 return 0; 318} 319 320static bool dm_is_idle(struct amdgpu_ip_block *ip_block) 321{ 322 /* XXX todo */ 323 return true; 324} 325 326static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 327{ 328 /* XXX todo */ 329 return 0; 330} 331 332static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block) 333{ 334 return false; 335} 336 337static int dm_soft_reset(struct amdgpu_ip_block *ip_block) 338{ 339 /* XXX todo */ 340 return 0; 341} 342 343static struct amdgpu_crtc * 344get_crtc_by_otg_inst(struct amdgpu_device *adev, 345 int otg_inst) 346{ 347 struct drm_device *dev = adev_to_drm(adev); 348 struct drm_crtc *crtc; 349 struct amdgpu_crtc *amdgpu_crtc; 350 351 if (WARN_ON(otg_inst == -1)) 352 return adev->mode_info.crtcs[0]; 353 354 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 355 amdgpu_crtc = to_amdgpu_crtc(crtc); 356 357 if (amdgpu_crtc->otg_inst == otg_inst) 358 return amdgpu_crtc; 359 } 360 361 return NULL; 362} 363 364static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 365 struct dm_crtc_state *new_state) 366{ 367 if (new_state->stream->adjust.timing_adjust_pending) 368 return true; 369 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 370 return true; 371 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 372 return true; 373 else 374 return false; 375} 376 377/* 378 * DC will program planes with their z-order determined by their ordering 379 * in the dc_surface_updates array. This comparator is used to sort them 380 * by descending zpos. 381 */ 382static int dm_plane_layer_index_cmp(const void *a, const void *b) 383{ 384 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 385 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 386 387 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 388 return sb->surface->layer_index - sa->surface->layer_index; 389} 390 391/** 392 * update_planes_and_stream_adapter() - Send planes to be updated in DC 393 * 394 * DC has a generic way to update planes and stream via 395 * dc_update_planes_and_stream function; however, DM might need some 396 * adjustments and preparation before calling it. This function is a wrapper 397 * for the dc_update_planes_and_stream that does any required configuration 398 * before passing control to DC. 399 * 400 * @dc: Display Core control structure 401 * @update_type: specify whether it is FULL/MEDIUM/FAST update 402 * @planes_count: planes count to update 403 * @stream: stream state 404 * @stream_update: stream update 405 * @array_of_surface_update: dc surface update pointer 406 * 407 */ 408static inline bool update_planes_and_stream_adapter(struct dc *dc, 409 int update_type, 410 int planes_count, 411 struct dc_stream_state *stream, 412 struct dc_stream_update *stream_update, 413 struct dc_surface_update *array_of_surface_update) 414{ 415 sort(array_of_surface_update, planes_count, 416 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 417 418 /* 419 * Previous frame finished and HW is ready for optimization. 420 */ 421 dc_post_update_surfaces_to_stream(dc); 422 423 return dc_update_planes_and_stream(dc, 424 array_of_surface_update, 425 planes_count, 426 stream, 427 stream_update); 428} 429 430/** 431 * dm_pflip_high_irq() - Handle pageflip interrupt 432 * @interrupt_params: ignored 433 * 434 * Handles the pageflip interrupt by notifying all interested parties 435 * that the pageflip has been completed. 436 */ 437static void dm_pflip_high_irq(void *interrupt_params) 438{ 439 struct amdgpu_crtc *amdgpu_crtc; 440 struct common_irq_params *irq_params = interrupt_params; 441 struct amdgpu_device *adev = irq_params->adev; 442 struct drm_device *dev = adev_to_drm(adev); 443 unsigned long flags; 444 struct drm_pending_vblank_event *e; 445 u32 vpos, hpos, v_blank_start, v_blank_end; 446 bool vrr_active; 447 448 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 449 450 /* IRQ could occur when in initial stage */ 451 /* TODO work and BO cleanup */ 452 if (amdgpu_crtc == NULL) { 453 drm_dbg_state(dev, "CRTC is null, returning.\n"); 454 return; 455 } 456 457 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 458 459 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 460 drm_dbg_state(dev, 461 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 462 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, 463 amdgpu_crtc->crtc_id, amdgpu_crtc); 464 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 465 return; 466 } 467 468 /* page flip completed. */ 469 e = amdgpu_crtc->event; 470 amdgpu_crtc->event = NULL; 471 472 WARN_ON(!e); 473 474 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 475 476 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 477 if (!vrr_active || 478 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 479 &v_blank_end, &hpos, &vpos) || 480 (vpos < v_blank_start)) { 481 /* Update to correct count and vblank timestamp if racing with 482 * vblank irq. This also updates to the correct vblank timestamp 483 * even in VRR mode, as scanout is past the front-porch atm. 484 */ 485 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 486 487 /* Wake up userspace by sending the pageflip event with proper 488 * count and timestamp of vblank of flip completion. 489 */ 490 if (e) { 491 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 492 493 /* Event sent, so done with vblank for this flip */ 494 drm_crtc_vblank_put(&amdgpu_crtc->base); 495 } 496 } else if (e) { 497 /* VRR active and inside front-porch: vblank count and 498 * timestamp for pageflip event will only be up to date after 499 * drm_crtc_handle_vblank() has been executed from late vblank 500 * irq handler after start of back-porch (vline 0). We queue the 501 * pageflip event for send-out by drm_crtc_handle_vblank() with 502 * updated timestamp and count, once it runs after us. 503 * 504 * We need to open-code this instead of using the helper 505 * drm_crtc_arm_vblank_event(), as that helper would 506 * call drm_crtc_accurate_vblank_count(), which we must 507 * not call in VRR mode while we are in front-porch! 508 */ 509 510 /* sequence will be replaced by real count during send-out. */ 511 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 512 e->pipe = amdgpu_crtc->crtc_id; 513 514 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 515 e = NULL; 516 } 517 518 /* Keep track of vblank of this flip for flip throttling. We use the 519 * cooked hw counter, as that one incremented at start of this vblank 520 * of pageflip completion, so last_flip_vblank is the forbidden count 521 * for queueing new pageflips if vsync + VRR is enabled. 522 */ 523 amdgpu_crtc->dm_irq_params.last_flip_vblank = 524 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 525 526 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 527 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 528 529 drm_dbg_state(dev, 530 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 531 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); 532} 533 534static void dm_handle_vmin_vmax_update(struct work_struct *offload_work) 535{ 536 struct vupdate_offload_work *work = container_of(offload_work, struct vupdate_offload_work, work); 537 struct amdgpu_device *adev = work->adev; 538 struct dc_stream_state *stream = work->stream; 539 struct dc_crtc_timing_adjust *adjust = work->adjust; 540 541 mutex_lock(&adev->dm.dc_lock); 542 dc_stream_adjust_vmin_vmax(adev->dm.dc, stream, adjust); 543 mutex_unlock(&adev->dm.dc_lock); 544 545 dc_stream_release(stream); 546 kfree(work->adjust); 547 kfree(work); 548} 549 550static void schedule_dc_vmin_vmax(struct amdgpu_device *adev, 551 struct dc_stream_state *stream, 552 struct dc_crtc_timing_adjust *adjust) 553{ 554 struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_NOWAIT); 555 if (!offload_work) { 556 drm_dbg_driver(adev_to_drm(adev), "Failed to allocate vupdate_offload_work\n"); 557 return; 558 } 559 560 struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_NOWAIT); 561 if (!adjust_copy) { 562 drm_dbg_driver(adev_to_drm(adev), "Failed to allocate adjust_copy\n"); 563 kfree(offload_work); 564 return; 565 } 566 567 dc_stream_retain(stream); 568 memcpy(adjust_copy, adjust, sizeof(*adjust_copy)); 569 570 INIT_WORK(&offload_work->work, dm_handle_vmin_vmax_update); 571 offload_work->adev = adev; 572 offload_work->stream = stream; 573 offload_work->adjust = adjust_copy; 574 575 queue_work(system_wq, &offload_work->work); 576} 577 578static void dm_vupdate_high_irq(void *interrupt_params) 579{ 580 struct common_irq_params *irq_params = interrupt_params; 581 struct amdgpu_device *adev = irq_params->adev; 582 struct amdgpu_crtc *acrtc; 583 struct drm_device *drm_dev; 584 struct drm_vblank_crtc *vblank; 585 ktime_t frame_duration_ns, previous_timestamp; 586 unsigned long flags; 587 int vrr_active; 588 589 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 590 591 if (acrtc) { 592 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 593 drm_dev = acrtc->base.dev; 594 vblank = drm_crtc_vblank_crtc(&acrtc->base); 595 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 596 frame_duration_ns = vblank->time - previous_timestamp; 597 598 if (frame_duration_ns > 0) { 599 trace_amdgpu_refresh_rate_track(acrtc->base.index, 600 frame_duration_ns, 601 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 602 atomic64_set(&irq_params->previous_timestamp, vblank->time); 603 } 604 605 drm_dbg_vbl(drm_dev, 606 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 607 vrr_active); 608 609 /* Core vblank handling is done here after end of front-porch in 610 * vrr mode, as vblank timestamping will give valid results 611 * while now done after front-porch. This will also deliver 612 * page-flip completion events that have been queued to us 613 * if a pageflip happened inside front-porch. 614 */ 615 if (vrr_active && acrtc->dm_irq_params.stream) { 616 bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; 617 bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; 618 bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state 619 == VRR_STATE_ACTIVE_VARIABLE; 620 621 amdgpu_dm_crtc_handle_vblank(acrtc); 622 623 /* BTR processing for pre-DCE12 ASICs */ 624 if (adev->family < AMDGPU_FAMILY_AI) { 625 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 626 mod_freesync_handle_v_update( 627 adev->dm.freesync_module, 628 acrtc->dm_irq_params.stream, 629 &acrtc->dm_irq_params.vrr_params); 630 631 if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { 632 schedule_dc_vmin_vmax(adev, 633 acrtc->dm_irq_params.stream, 634 &acrtc->dm_irq_params.vrr_params.adjust); 635 } 636 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 637 } 638 } 639 } 640} 641 642/** 643 * dm_crtc_high_irq() - Handles CRTC interrupt 644 * @interrupt_params: used for determining the CRTC instance 645 * 646 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 647 * event handler. 648 */ 649static void dm_crtc_high_irq(void *interrupt_params) 650{ 651 struct common_irq_params *irq_params = interrupt_params; 652 struct amdgpu_device *adev = irq_params->adev; 653 struct drm_writeback_job *job; 654 struct amdgpu_crtc *acrtc; 655 unsigned long flags; 656 int vrr_active; 657 658 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 659 if (!acrtc) 660 return; 661 662 if (acrtc->wb_conn) { 663 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 664 665 if (acrtc->wb_pending) { 666 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, 667 struct drm_writeback_job, 668 list_entry); 669 acrtc->wb_pending = false; 670 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 671 672 if (job) { 673 unsigned int v_total, refresh_hz; 674 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; 675 676 v_total = stream->adjust.v_total_max ? 677 stream->adjust.v_total_max : stream->timing.v_total; 678 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * 679 100LL, (v_total * stream->timing.h_total)); 680 mdelay(1000 / refresh_hz); 681 682 drm_writeback_signal_completion(acrtc->wb_conn, 0); 683 dc_stream_fc_disable_writeback(adev->dm.dc, 684 acrtc->dm_irq_params.stream, 0); 685 } 686 } else 687 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 688 } 689 690 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 691 692 drm_dbg_vbl(adev_to_drm(adev), 693 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 694 vrr_active, acrtc->dm_irq_params.active_planes); 695 696 /** 697 * Core vblank handling at start of front-porch is only possible 698 * in non-vrr mode, as only there vblank timestamping will give 699 * valid results while done in front-porch. Otherwise defer it 700 * to dm_vupdate_high_irq after end of front-porch. 701 */ 702 if (!vrr_active) 703 amdgpu_dm_crtc_handle_vblank(acrtc); 704 705 /** 706 * Following stuff must happen at start of vblank, for crc 707 * computation and below-the-range btr support in vrr mode. 708 */ 709 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 710 711 /* BTR updates need to happen before VUPDATE on Vega and above. */ 712 if (adev->family < AMDGPU_FAMILY_AI) 713 return; 714 715 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 716 717 if (acrtc->dm_irq_params.stream && 718 acrtc->dm_irq_params.vrr_params.supported) { 719 bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; 720 bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; 721 bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; 722 723 mod_freesync_handle_v_update(adev->dm.freesync_module, 724 acrtc->dm_irq_params.stream, 725 &acrtc->dm_irq_params.vrr_params); 726 727 /* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */ 728 if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { 729 schedule_dc_vmin_vmax(adev, acrtc->dm_irq_params.stream, 730 &acrtc->dm_irq_params.vrr_params.adjust); 731 } 732 } 733 734 /* 735 * If there aren't any active_planes then DCH HUBP may be clock-gated. 736 * In that case, pageflip completion interrupts won't fire and pageflip 737 * completion events won't get delivered. Prevent this by sending 738 * pending pageflip events from here if a flip is still pending. 739 * 740 * If any planes are enabled, use dm_pflip_high_irq() instead, to 741 * avoid race conditions between flip programming and completion, 742 * which could cause too early flip completion events. 743 */ 744 if (adev->family >= AMDGPU_FAMILY_RV && 745 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 746 acrtc->dm_irq_params.active_planes == 0) { 747 if (acrtc->event) { 748 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 749 acrtc->event = NULL; 750 drm_crtc_vblank_put(&acrtc->base); 751 } 752 acrtc->pflip_status = AMDGPU_FLIP_NONE; 753 } 754 755 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 756} 757 758#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 759/** 760 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 761 * DCN generation ASICs 762 * @interrupt_params: interrupt parameters 763 * 764 * Used to set crc window/read out crc value at vertical line 0 position 765 */ 766static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 767{ 768 struct common_irq_params *irq_params = interrupt_params; 769 struct amdgpu_device *adev = irq_params->adev; 770 struct amdgpu_crtc *acrtc; 771 772 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 773 774 if (!acrtc) 775 return; 776 777 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 778} 779#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 780 781/** 782 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 783 * @adev: amdgpu_device pointer 784 * @notify: dmub notification structure 785 * 786 * Dmub AUX or SET_CONFIG command completion processing callback 787 * Copies dmub notification to DM which is to be read by AUX command. 788 * issuing thread and also signals the event to wake up the thread. 789 */ 790static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 791 struct dmub_notification *notify) 792{ 793 if (adev->dm.dmub_notify) 794 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 795 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 796 complete(&adev->dm.dmub_aux_transfer_done); 797} 798 799static void dmub_aux_fused_io_callback(struct amdgpu_device *adev, 800 struct dmub_notification *notify) 801{ 802 if (!adev || !notify) { 803 ASSERT(false); 804 return; 805 } 806 807 const struct dmub_cmd_fused_request *req = ¬ify->fused_request; 808 const uint8_t ddc_line = req->u.aux.ddc_line; 809 810 if (ddc_line >= ARRAY_SIZE(adev->dm.fused_io)) { 811 ASSERT(false); 812 return; 813 } 814 815 struct fused_io_sync *sync = &adev->dm.fused_io[ddc_line]; 816 817 static_assert(sizeof(*req) <= sizeof(sync->reply_data), "Size mismatch"); 818 memcpy(sync->reply_data, req, sizeof(*req)); 819 complete(&sync->replied); 820} 821 822/** 823 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 824 * @adev: amdgpu_device pointer 825 * @notify: dmub notification structure 826 * 827 * Dmub Hpd interrupt processing callback. Gets displayindex through the 828 * ink index and calls helper to do the processing. 829 */ 830static void dmub_hpd_callback(struct amdgpu_device *adev, 831 struct dmub_notification *notify) 832{ 833 struct amdgpu_dm_connector *aconnector; 834 struct amdgpu_dm_connector *hpd_aconnector = NULL; 835 struct drm_connector *connector; 836 struct drm_connector_list_iter iter; 837 struct dc_link *link; 838 u8 link_index = 0; 839 struct drm_device *dev; 840 841 if (adev == NULL) 842 return; 843 844 if (notify == NULL) { 845 drm_err(adev_to_drm(adev), "DMUB HPD callback notification was NULL"); 846 return; 847 } 848 849 if (notify->link_index > adev->dm.dc->link_count) { 850 drm_err(adev_to_drm(adev), "DMUB HPD index (%u)is abnormal", notify->link_index); 851 return; 852 } 853 854 /* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */ 855 if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) { 856 drm_info(adev_to_drm(adev), "Skip DMUB HPD IRQ callback in suspend/resume\n"); 857 return; 858 } 859 860 link_index = notify->link_index; 861 link = adev->dm.dc->links[link_index]; 862 dev = adev->dm.ddev; 863 864 drm_connector_list_iter_begin(dev, &iter); 865 drm_for_each_connector_iter(connector, &iter) { 866 867 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 868 continue; 869 870 aconnector = to_amdgpu_dm_connector(connector); 871 if (link && aconnector->dc_link == link) { 872 if (notify->type == DMUB_NOTIFICATION_HPD) 873 drm_info(adev_to_drm(adev), "DMUB HPD IRQ callback: link_index=%u\n", link_index); 874 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 875 drm_info(adev_to_drm(adev), "DMUB HPD RX IRQ callback: link_index=%u\n", link_index); 876 else 877 drm_warn(adev_to_drm(adev), "DMUB Unknown HPD callback type %d, link_index=%u\n", 878 notify->type, link_index); 879 880 hpd_aconnector = aconnector; 881 break; 882 } 883 } 884 drm_connector_list_iter_end(&iter); 885 886 if (hpd_aconnector) { 887 if (notify->type == DMUB_NOTIFICATION_HPD) { 888 if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG)) 889 drm_warn(adev_to_drm(adev), "DMUB reported hpd status unchanged. link_index=%u\n", link_index); 890 handle_hpd_irq_helper(hpd_aconnector); 891 } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) { 892 handle_hpd_rx_irq(hpd_aconnector); 893 } 894 } 895} 896 897/** 898 * dmub_hpd_sense_callback - DMUB HPD sense processing callback. 899 * @adev: amdgpu_device pointer 900 * @notify: dmub notification structure 901 * 902 * HPD sense changes can occur during low power states and need to be 903 * notified from firmware to driver. 904 */ 905static void dmub_hpd_sense_callback(struct amdgpu_device *adev, 906 struct dmub_notification *notify) 907{ 908 drm_dbg_driver(adev_to_drm(adev), "DMUB HPD SENSE callback.\n"); 909} 910 911/** 912 * register_dmub_notify_callback - Sets callback for DMUB notify 913 * @adev: amdgpu_device pointer 914 * @type: Type of dmub notification 915 * @callback: Dmub interrupt callback function 916 * @dmub_int_thread_offload: offload indicator 917 * 918 * API to register a dmub callback handler for a dmub notification 919 * Also sets indicator whether callback processing to be offloaded. 920 * to dmub interrupt handling thread 921 * Return: true if successfully registered, false if there is existing registration 922 */ 923static bool register_dmub_notify_callback(struct amdgpu_device *adev, 924 enum dmub_notification_type type, 925 dmub_notify_interrupt_callback_t callback, 926 bool dmub_int_thread_offload) 927{ 928 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 929 adev->dm.dmub_callback[type] = callback; 930 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 931 } else 932 return false; 933 934 return true; 935} 936 937static void dm_handle_hpd_work(struct work_struct *work) 938{ 939 struct dmub_hpd_work *dmub_hpd_wrk; 940 941 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 942 943 if (!dmub_hpd_wrk->dmub_notify) { 944 drm_err(adev_to_drm(dmub_hpd_wrk->adev), "dmub_hpd_wrk dmub_notify is NULL"); 945 return; 946 } 947 948 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 949 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 950 dmub_hpd_wrk->dmub_notify); 951 } 952 953 kfree(dmub_hpd_wrk->dmub_notify); 954 kfree(dmub_hpd_wrk); 955 956} 957 958static const char *dmub_notification_type_str(enum dmub_notification_type e) 959{ 960 switch (e) { 961 case DMUB_NOTIFICATION_NO_DATA: 962 return "NO_DATA"; 963 case DMUB_NOTIFICATION_AUX_REPLY: 964 return "AUX_REPLY"; 965 case DMUB_NOTIFICATION_HPD: 966 return "HPD"; 967 case DMUB_NOTIFICATION_HPD_IRQ: 968 return "HPD_IRQ"; 969 case DMUB_NOTIFICATION_SET_CONFIG_REPLY: 970 return "SET_CONFIG_REPLY"; 971 case DMUB_NOTIFICATION_DPIA_NOTIFICATION: 972 return "DPIA_NOTIFICATION"; 973 case DMUB_NOTIFICATION_HPD_SENSE_NOTIFY: 974 return "HPD_SENSE_NOTIFY"; 975 case DMUB_NOTIFICATION_FUSED_IO: 976 return "FUSED_IO"; 977 default: 978 return "<unknown>"; 979 } 980} 981 982#define DMUB_TRACE_MAX_READ 64 983/** 984 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 985 * @interrupt_params: used for determining the Outbox instance 986 * 987 * Handles the Outbox Interrupt 988 * event handler. 989 */ 990static void dm_dmub_outbox1_low_irq(void *interrupt_params) 991{ 992 struct dmub_notification notify = {0}; 993 struct common_irq_params *irq_params = interrupt_params; 994 struct amdgpu_device *adev = irq_params->adev; 995 struct amdgpu_display_manager *dm = &adev->dm; 996 struct dmcub_trace_buf_entry entry = { 0 }; 997 u32 count = 0; 998 struct dmub_hpd_work *dmub_hpd_wrk; 999 1000 do { 1001 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 1002 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 1003 entry.param0, entry.param1); 1004 1005 drm_dbg_driver(adev_to_drm(adev), "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 1006 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 1007 } else 1008 break; 1009 1010 count++; 1011 1012 } while (count <= DMUB_TRACE_MAX_READ); 1013 1014 if (count > DMUB_TRACE_MAX_READ) 1015 drm_dbg_driver(adev_to_drm(adev), "Warning : count > DMUB_TRACE_MAX_READ"); 1016 1017 if (dc_enable_dmub_notifications(adev->dm.dc) && 1018 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 1019 1020 do { 1021 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 1022 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 1023 drm_err(adev_to_drm(adev), "DM: notify type %d invalid!", notify.type); 1024 continue; 1025 } 1026 if (!dm->dmub_callback[notify.type]) { 1027 drm_warn(adev_to_drm(adev), "DMUB notification skipped due to no handler: type=%s\n", 1028 dmub_notification_type_str(notify.type)); 1029 continue; 1030 } 1031 if (dm->dmub_thread_offload[notify.type] == true) { 1032 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 1033 if (!dmub_hpd_wrk) { 1034 drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk"); 1035 return; 1036 } 1037 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 1038 GFP_ATOMIC); 1039 if (!dmub_hpd_wrk->dmub_notify) { 1040 kfree(dmub_hpd_wrk); 1041 drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk->dmub_notify"); 1042 return; 1043 } 1044 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 1045 dmub_hpd_wrk->adev = adev; 1046 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 1047 } else { 1048 dm->dmub_callback[notify.type](adev, ¬ify); 1049 } 1050 } while (notify.pending_notification); 1051 } 1052} 1053 1054static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1055 enum amd_clockgating_state state) 1056{ 1057 return 0; 1058} 1059 1060static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 1061 enum amd_powergating_state state) 1062{ 1063 return 0; 1064} 1065 1066/* Prototypes of private functions */ 1067static int dm_early_init(struct amdgpu_ip_block *ip_block); 1068 1069/* Allocate memory for FBC compressed data */ 1070static void amdgpu_dm_fbc_init(struct drm_connector *connector) 1071{ 1072 struct amdgpu_device *adev = drm_to_adev(connector->dev); 1073 struct dm_compressor_info *compressor = &adev->dm.compressor; 1074 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 1075 struct drm_display_mode *mode; 1076 unsigned long max_size = 0; 1077 1078 if (adev->dm.dc->fbc_compressor == NULL) 1079 return; 1080 1081 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 1082 return; 1083 1084 if (compressor->bo_ptr) 1085 return; 1086 1087 1088 list_for_each_entry(mode, &connector->modes, head) { 1089 if (max_size < (unsigned long) mode->htotal * mode->vtotal) 1090 max_size = (unsigned long) mode->htotal * mode->vtotal; 1091 } 1092 1093 if (max_size) { 1094 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 1095 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 1096 &compressor->gpu_addr, &compressor->cpu_addr); 1097 1098 if (r) 1099 drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n"); 1100 else { 1101 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 1102 drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4); 1103 } 1104 1105 } 1106 1107} 1108 1109static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 1110 int pipe, bool *enabled, 1111 unsigned char *buf, int max_bytes) 1112{ 1113 struct drm_device *dev = dev_get_drvdata(kdev); 1114 struct amdgpu_device *adev = drm_to_adev(dev); 1115 struct drm_connector *connector; 1116 struct drm_connector_list_iter conn_iter; 1117 struct amdgpu_dm_connector *aconnector; 1118 int ret = 0; 1119 1120 *enabled = false; 1121 1122 mutex_lock(&adev->dm.audio_lock); 1123 1124 drm_connector_list_iter_begin(dev, &conn_iter); 1125 drm_for_each_connector_iter(connector, &conn_iter) { 1126 1127 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1128 continue; 1129 1130 aconnector = to_amdgpu_dm_connector(connector); 1131 if (aconnector->audio_inst != port) 1132 continue; 1133 1134 *enabled = true; 1135 mutex_lock(&connector->eld_mutex); 1136 ret = drm_eld_size(connector->eld); 1137 memcpy(buf, connector->eld, min(max_bytes, ret)); 1138 mutex_unlock(&connector->eld_mutex); 1139 1140 break; 1141 } 1142 drm_connector_list_iter_end(&conn_iter); 1143 1144 mutex_unlock(&adev->dm.audio_lock); 1145 1146 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1147 1148 return ret; 1149} 1150 1151static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 1152 .get_eld = amdgpu_dm_audio_component_get_eld, 1153}; 1154 1155static int amdgpu_dm_audio_component_bind(struct device *kdev, 1156 struct device *hda_kdev, void *data) 1157{ 1158 struct drm_device *dev = dev_get_drvdata(kdev); 1159 struct amdgpu_device *adev = drm_to_adev(dev); 1160 struct drm_audio_component *acomp = data; 1161 1162 acomp->ops = &amdgpu_dm_audio_component_ops; 1163 acomp->dev = kdev; 1164 adev->dm.audio_component = acomp; 1165 1166 return 0; 1167} 1168 1169static void amdgpu_dm_audio_component_unbind(struct device *kdev, 1170 struct device *hda_kdev, void *data) 1171{ 1172 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); 1173 struct drm_audio_component *acomp = data; 1174 1175 acomp->ops = NULL; 1176 acomp->dev = NULL; 1177 adev->dm.audio_component = NULL; 1178} 1179 1180static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 1181 .bind = amdgpu_dm_audio_component_bind, 1182 .unbind = amdgpu_dm_audio_component_unbind, 1183}; 1184 1185static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1186{ 1187 int i, ret; 1188 1189 if (!amdgpu_audio) 1190 return 0; 1191 1192 adev->mode_info.audio.enabled = true; 1193 1194 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1195 1196 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1197 adev->mode_info.audio.pin[i].channels = -1; 1198 adev->mode_info.audio.pin[i].rate = -1; 1199 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1200 adev->mode_info.audio.pin[i].status_bits = 0; 1201 adev->mode_info.audio.pin[i].category_code = 0; 1202 adev->mode_info.audio.pin[i].connected = false; 1203 adev->mode_info.audio.pin[i].id = 1204 adev->dm.dc->res_pool->audios[i]->inst; 1205 adev->mode_info.audio.pin[i].offset = 0; 1206 } 1207 1208 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1209 if (ret < 0) 1210 return ret; 1211 1212 adev->dm.audio_registered = true; 1213 1214 return 0; 1215} 1216 1217static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1218{ 1219 if (!amdgpu_audio) 1220 return; 1221 1222 if (!adev->mode_info.audio.enabled) 1223 return; 1224 1225 if (adev->dm.audio_registered) { 1226 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1227 adev->dm.audio_registered = false; 1228 } 1229 1230 /* TODO: Disable audio? */ 1231 1232 adev->mode_info.audio.enabled = false; 1233} 1234 1235static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1236{ 1237 struct drm_audio_component *acomp = adev->dm.audio_component; 1238 1239 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1240 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1241 1242 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1243 pin, -1); 1244 } 1245} 1246 1247static int dm_dmub_hw_init(struct amdgpu_device *adev) 1248{ 1249 const struct dmcub_firmware_header_v1_0 *hdr; 1250 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1251 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1252 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1253 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1254 struct abm *abm = adev->dm.dc->res_pool->abm; 1255 struct dc_context *ctx = adev->dm.dc->ctx; 1256 struct dmub_srv_hw_params hw_params; 1257 enum dmub_status status; 1258 const unsigned char *fw_inst_const, *fw_bss_data; 1259 u32 i, fw_inst_const_size, fw_bss_data_size; 1260 bool has_hw_support; 1261 1262 if (!dmub_srv) 1263 /* DMUB isn't supported on the ASIC. */ 1264 return 0; 1265 1266 if (!fb_info) { 1267 drm_err(adev_to_drm(adev), "No framebuffer info for DMUB service.\n"); 1268 return -EINVAL; 1269 } 1270 1271 if (!dmub_fw) { 1272 /* Firmware required for DMUB support. */ 1273 drm_err(adev_to_drm(adev), "No firmware provided for DMUB.\n"); 1274 return -EINVAL; 1275 } 1276 1277 /* initialize register offsets for ASICs with runtime initialization available */ 1278 if (dmub_srv->hw_funcs.init_reg_offsets) 1279 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); 1280 1281 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1282 if (status != DMUB_STATUS_OK) { 1283 drm_err(adev_to_drm(adev), "Error checking HW support for DMUB: %d\n", status); 1284 return -EINVAL; 1285 } 1286 1287 if (!has_hw_support) { 1288 drm_info(adev_to_drm(adev), "DMUB unsupported on ASIC\n"); 1289 return 0; 1290 } 1291 1292 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1293 status = dmub_srv_hw_reset(dmub_srv); 1294 if (status != DMUB_STATUS_OK) 1295 drm_warn(adev_to_drm(adev), "Error resetting DMUB HW: %d\n", status); 1296 1297 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1298 1299 fw_inst_const = dmub_fw->data + 1300 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1301 PSP_HEADER_BYTES; 1302 1303 fw_bss_data = dmub_fw->data + 1304 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1305 le32_to_cpu(hdr->inst_const_bytes); 1306 1307 /* Copy firmware and bios info into FB memory. */ 1308 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1309 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1310 1311 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1312 1313 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1314 * amdgpu_ucode_init_single_fw will load dmub firmware 1315 * fw_inst_const part to cw0; otherwise, the firmware back door load 1316 * will be done by dm_dmub_hw_init 1317 */ 1318 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1319 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1320 fw_inst_const_size); 1321 } 1322 1323 if (fw_bss_data_size) 1324 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1325 fw_bss_data, fw_bss_data_size); 1326 1327 /* Copy firmware bios info into FB memory. */ 1328 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1329 adev->bios_size); 1330 1331 /* Reset regions that need to be reset. */ 1332 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1333 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1334 1335 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1336 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1337 1338 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1339 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1340 1341 memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0, 1342 fb_info->fb[DMUB_WINDOW_SHARED_STATE].size); 1343 1344 /* Initialize hardware. */ 1345 memset(&hw_params, 0, sizeof(hw_params)); 1346 hw_params.fb_base = adev->gmc.fb_start; 1347 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1348 1349 /* backdoor load firmware and trigger dmub running */ 1350 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1351 hw_params.load_inst_const = true; 1352 1353 if (dmcu) 1354 hw_params.psp_version = dmcu->psp_version; 1355 1356 for (i = 0; i < fb_info->num_fb; ++i) 1357 hw_params.fb[i] = &fb_info->fb[i]; 1358 1359 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1360 case IP_VERSION(3, 1, 3): 1361 case IP_VERSION(3, 1, 4): 1362 case IP_VERSION(3, 5, 0): 1363 case IP_VERSION(3, 5, 1): 1364 case IP_VERSION(3, 6, 0): 1365 case IP_VERSION(4, 0, 1): 1366 hw_params.dpia_supported = true; 1367 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1368 break; 1369 default: 1370 break; 1371 } 1372 1373 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1374 case IP_VERSION(3, 5, 0): 1375 case IP_VERSION(3, 5, 1): 1376 case IP_VERSION(3, 6, 0): 1377 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1378 hw_params.lower_hbr3_phy_ssc = true; 1379 break; 1380 default: 1381 break; 1382 } 1383 1384 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1385 if (status != DMUB_STATUS_OK) { 1386 drm_err(adev_to_drm(adev), "Error initializing DMUB HW: %d\n", status); 1387 return -EINVAL; 1388 } 1389 1390 /* Wait for firmware load to finish. */ 1391 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1392 if (status != DMUB_STATUS_OK) 1393 drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status); 1394 1395 /* Init DMCU and ABM if available. */ 1396 if (dmcu && abm) { 1397 dmcu->funcs->dmcu_init(dmcu); 1398 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1399 } 1400 1401 if (!adev->dm.dc->ctx->dmub_srv) 1402 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1403 if (!adev->dm.dc->ctx->dmub_srv) { 1404 drm_err(adev_to_drm(adev), "Couldn't allocate DC DMUB server!\n"); 1405 return -ENOMEM; 1406 } 1407 1408 drm_info(adev_to_drm(adev), "DMUB hardware initialized: version=0x%08X\n", 1409 adev->dm.dmcub_fw_version); 1410 1411 /* Keeping sanity checks off if 1412 * DCN31 >= 4.0.59.0 1413 * DCN314 >= 8.0.16.0 1414 * Otherwise, turn on sanity checks 1415 */ 1416 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1417 case IP_VERSION(3, 1, 2): 1418 case IP_VERSION(3, 1, 3): 1419 if (adev->dm.dmcub_fw_version && 1420 adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) && 1421 adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59)) 1422 adev->dm.dc->debug.sanity_checks = true; 1423 break; 1424 case IP_VERSION(3, 1, 4): 1425 if (adev->dm.dmcub_fw_version && 1426 adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) && 1427 adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16)) 1428 adev->dm.dc->debug.sanity_checks = true; 1429 break; 1430 default: 1431 break; 1432 } 1433 1434 return 0; 1435} 1436 1437static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1438{ 1439 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1440 enum dmub_status status; 1441 bool init; 1442 int r; 1443 1444 if (!dmub_srv) { 1445 /* DMUB isn't supported on the ASIC. */ 1446 return; 1447 } 1448 1449 status = dmub_srv_is_hw_init(dmub_srv, &init); 1450 if (status != DMUB_STATUS_OK) 1451 drm_warn(adev_to_drm(adev), "DMUB hardware init check failed: %d\n", status); 1452 1453 if (status == DMUB_STATUS_OK && init) { 1454 /* Wait for firmware load to finish. */ 1455 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1456 if (status != DMUB_STATUS_OK) 1457 drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status); 1458 } else { 1459 /* Perform the full hardware initialization. */ 1460 r = dm_dmub_hw_init(adev); 1461 if (r) 1462 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 1463 } 1464} 1465 1466static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1467{ 1468 u64 pt_base; 1469 u32 logical_addr_low; 1470 u32 logical_addr_high; 1471 u32 agp_base, agp_bot, agp_top; 1472 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1473 1474 memset(pa_config, 0, sizeof(*pa_config)); 1475 1476 agp_base = 0; 1477 agp_bot = adev->gmc.agp_start >> 24; 1478 agp_top = adev->gmc.agp_end >> 24; 1479 1480 /* AGP aperture is disabled */ 1481 if (agp_bot > agp_top) { 1482 logical_addr_low = adev->gmc.fb_start >> 18; 1483 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1484 AMD_APU_IS_RENOIR | 1485 AMD_APU_IS_GREEN_SARDINE)) 1486 /* 1487 * Raven2 has a HW issue that it is unable to use the vram which 1488 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1489 * workaround that increase system aperture high address (add 1) 1490 * to get rid of the VM fault and hardware hang. 1491 */ 1492 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1493 else 1494 logical_addr_high = adev->gmc.fb_end >> 18; 1495 } else { 1496 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1497 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1498 AMD_APU_IS_RENOIR | 1499 AMD_APU_IS_GREEN_SARDINE)) 1500 /* 1501 * Raven2 has a HW issue that it is unable to use the vram which 1502 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1503 * workaround that increase system aperture high address (add 1) 1504 * to get rid of the VM fault and hardware hang. 1505 */ 1506 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1507 else 1508 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1509 } 1510 1511 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1512 1513 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1514 AMDGPU_GPU_PAGE_SHIFT); 1515 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1516 AMDGPU_GPU_PAGE_SHIFT); 1517 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1518 AMDGPU_GPU_PAGE_SHIFT); 1519 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1520 AMDGPU_GPU_PAGE_SHIFT); 1521 page_table_base.high_part = upper_32_bits(pt_base); 1522 page_table_base.low_part = lower_32_bits(pt_base); 1523 1524 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1525 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1526 1527 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1528 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1529 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1530 1531 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1532 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1533 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1534 1535 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1536 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1537 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1538 1539 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1540 1541} 1542 1543static void force_connector_state( 1544 struct amdgpu_dm_connector *aconnector, 1545 enum drm_connector_force force_state) 1546{ 1547 struct drm_connector *connector = &aconnector->base; 1548 1549 mutex_lock(&connector->dev->mode_config.mutex); 1550 aconnector->base.force = force_state; 1551 mutex_unlock(&connector->dev->mode_config.mutex); 1552 1553 mutex_lock(&aconnector->hpd_lock); 1554 drm_kms_helper_connector_hotplug_event(connector); 1555 mutex_unlock(&aconnector->hpd_lock); 1556} 1557 1558static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1559{ 1560 struct hpd_rx_irq_offload_work *offload_work; 1561 struct amdgpu_dm_connector *aconnector; 1562 struct dc_link *dc_link; 1563 struct amdgpu_device *adev; 1564 enum dc_connection_type new_connection_type = dc_connection_none; 1565 unsigned long flags; 1566 union test_response test_response; 1567 1568 memset(&test_response, 0, sizeof(test_response)); 1569 1570 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1571 aconnector = offload_work->offload_wq->aconnector; 1572 adev = offload_work->adev; 1573 1574 if (!aconnector) { 1575 drm_err(adev_to_drm(adev), "Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1576 goto skip; 1577 } 1578 1579 dc_link = aconnector->dc_link; 1580 1581 mutex_lock(&aconnector->hpd_lock); 1582 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1583 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 1584 mutex_unlock(&aconnector->hpd_lock); 1585 1586 if (new_connection_type == dc_connection_none) 1587 goto skip; 1588 1589 if (amdgpu_in_reset(adev)) 1590 goto skip; 1591 1592 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1593 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1594 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1595 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1596 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1597 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1598 goto skip; 1599 } 1600 1601 mutex_lock(&adev->dm.dc_lock); 1602 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1603 dc_link_dp_handle_automated_test(dc_link); 1604 1605 if (aconnector->timing_changed) { 1606 /* force connector disconnect and reconnect */ 1607 force_connector_state(aconnector, DRM_FORCE_OFF); 1608 msleep(100); 1609 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1610 } 1611 1612 test_response.bits.ACK = 1; 1613 1614 core_link_write_dpcd( 1615 dc_link, 1616 DP_TEST_RESPONSE, 1617 &test_response.raw, 1618 sizeof(test_response)); 1619 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1620 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1621 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1622 /* offload_work->data is from handle_hpd_rx_irq-> 1623 * schedule_hpd_rx_offload_work.this is defer handle 1624 * for hpd short pulse. upon here, link status may be 1625 * changed, need get latest link status from dpcd 1626 * registers. if link status is good, skip run link 1627 * training again. 1628 */ 1629 union hpd_irq_data irq_data; 1630 1631 memset(&irq_data, 0, sizeof(irq_data)); 1632 1633 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1634 * request be added to work queue if link lost at end of dc_link_ 1635 * dp_handle_link_loss 1636 */ 1637 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1638 offload_work->offload_wq->is_handling_link_loss = false; 1639 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1640 1641 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1642 dc_link_check_link_loss_status(dc_link, &irq_data)) 1643 dc_link_dp_handle_link_loss(dc_link); 1644 } 1645 mutex_unlock(&adev->dm.dc_lock); 1646 1647skip: 1648 kfree(offload_work); 1649 1650} 1651 1652static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct amdgpu_device *adev) 1653{ 1654 struct dc *dc = adev->dm.dc; 1655 int max_caps = dc->caps.max_links; 1656 int i = 0; 1657 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1658 1659 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1660 1661 if (!hpd_rx_offload_wq) 1662 return NULL; 1663 1664 1665 for (i = 0; i < max_caps; i++) { 1666 hpd_rx_offload_wq[i].wq = 1667 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1668 1669 if (hpd_rx_offload_wq[i].wq == NULL) { 1670 drm_err(adev_to_drm(adev), "create amdgpu_dm_hpd_rx_offload_wq fail!"); 1671 goto out_err; 1672 } 1673 1674 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1675 } 1676 1677 return hpd_rx_offload_wq; 1678 1679out_err: 1680 for (i = 0; i < max_caps; i++) { 1681 if (hpd_rx_offload_wq[i].wq) 1682 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1683 } 1684 kfree(hpd_rx_offload_wq); 1685 return NULL; 1686} 1687 1688struct amdgpu_stutter_quirk { 1689 u16 chip_vendor; 1690 u16 chip_device; 1691 u16 subsys_vendor; 1692 u16 subsys_device; 1693 u8 revision; 1694}; 1695 1696static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1697 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1698 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1699 { 0, 0, 0, 0, 0 }, 1700}; 1701 1702static bool dm_should_disable_stutter(struct pci_dev *pdev) 1703{ 1704 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1705 1706 while (p && p->chip_device != 0) { 1707 if (pdev->vendor == p->chip_vendor && 1708 pdev->device == p->chip_device && 1709 pdev->subsystem_vendor == p->subsys_vendor && 1710 pdev->subsystem_device == p->subsys_device && 1711 pdev->revision == p->revision) { 1712 return true; 1713 } 1714 ++p; 1715 } 1716 return false; 1717} 1718 1719 1720void* 1721dm_allocate_gpu_mem( 1722 struct amdgpu_device *adev, 1723 enum dc_gpu_mem_alloc_type type, 1724 size_t size, 1725 long long *addr) 1726{ 1727 struct dal_allocation *da; 1728 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1729 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1730 int ret; 1731 1732 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1733 if (!da) 1734 return NULL; 1735 1736 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1737 domain, &da->bo, 1738 &da->gpu_addr, &da->cpu_ptr); 1739 1740 *addr = da->gpu_addr; 1741 1742 if (ret) { 1743 kfree(da); 1744 return NULL; 1745 } 1746 1747 /* add da to list in dm */ 1748 list_add(&da->list, &adev->dm.da_list); 1749 1750 return da->cpu_ptr; 1751} 1752 1753void 1754dm_free_gpu_mem( 1755 struct amdgpu_device *adev, 1756 enum dc_gpu_mem_alloc_type type, 1757 void *pvMem) 1758{ 1759 struct dal_allocation *da; 1760 1761 /* walk the da list in DM */ 1762 list_for_each_entry(da, &adev->dm.da_list, list) { 1763 if (pvMem == da->cpu_ptr) { 1764 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1765 list_del(&da->list); 1766 kfree(da); 1767 break; 1768 } 1769 } 1770 1771} 1772 1773static enum dmub_status 1774dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, 1775 enum dmub_gpint_command command_code, 1776 uint16_t param, 1777 uint32_t timeout_us) 1778{ 1779 union dmub_gpint_data_register reg, test; 1780 uint32_t i; 1781 1782 /* Assume that VBIOS DMUB is ready to take commands */ 1783 1784 reg.bits.status = 1; 1785 reg.bits.command_code = command_code; 1786 reg.bits.param = param; 1787 1788 cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all); 1789 1790 for (i = 0; i < timeout_us; ++i) { 1791 udelay(1); 1792 1793 /* Check if our GPINT got acked */ 1794 reg.bits.status = 0; 1795 test = (union dmub_gpint_data_register) 1796 cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8); 1797 1798 if (test.all == reg.all) 1799 return DMUB_STATUS_OK; 1800 } 1801 1802 return DMUB_STATUS_TIMEOUT; 1803} 1804 1805static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) 1806{ 1807 void *bb; 1808 long long addr; 1809 unsigned int bb_size; 1810 int i = 0; 1811 uint16_t chunk; 1812 enum dmub_gpint_command send_addrs[] = { 1813 DMUB_GPINT__SET_BB_ADDR_WORD0, 1814 DMUB_GPINT__SET_BB_ADDR_WORD1, 1815 DMUB_GPINT__SET_BB_ADDR_WORD2, 1816 DMUB_GPINT__SET_BB_ADDR_WORD3, 1817 }; 1818 enum dmub_status ret; 1819 1820 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1821 case IP_VERSION(4, 0, 1): 1822 bb_size = sizeof(struct dml2_soc_bb); 1823 break; 1824 default: 1825 return NULL; 1826 } 1827 1828 bb = dm_allocate_gpu_mem(adev, 1829 DC_MEM_ALLOC_TYPE_GART, 1830 bb_size, 1831 &addr); 1832 if (!bb) 1833 return NULL; 1834 1835 for (i = 0; i < 4; i++) { 1836 /* Extract 16-bit chunk */ 1837 chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF; 1838 /* Send the chunk */ 1839 ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000); 1840 if (ret != DMUB_STATUS_OK) 1841 goto free_bb; 1842 } 1843 1844 /* Now ask DMUB to copy the bb */ 1845 ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000); 1846 if (ret != DMUB_STATUS_OK) 1847 goto free_bb; 1848 1849 return bb; 1850 1851free_bb: 1852 dm_free_gpu_mem(adev, DC_MEM_ALLOC_TYPE_GART, (void *) bb); 1853 return NULL; 1854 1855} 1856 1857static enum dmub_ips_disable_type dm_get_default_ips_mode( 1858 struct amdgpu_device *adev) 1859{ 1860 enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE; 1861 1862 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1863 case IP_VERSION(3, 5, 0): 1864 case IP_VERSION(3, 6, 0): 1865 case IP_VERSION(3, 5, 1): 1866 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 1867 break; 1868 default: 1869 /* ASICs older than DCN35 do not have IPSs */ 1870 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) 1871 ret = DMUB_IPS_DISABLE_ALL; 1872 break; 1873 } 1874 1875 return ret; 1876} 1877 1878static int amdgpu_dm_init(struct amdgpu_device *adev) 1879{ 1880 struct dc_init_data init_data; 1881 struct dc_callback_init init_params; 1882 int r; 1883 1884 adev->dm.ddev = adev_to_drm(adev); 1885 adev->dm.adev = adev; 1886 1887 /* Zero all the fields */ 1888 memset(&init_data, 0, sizeof(init_data)); 1889 memset(&init_params, 0, sizeof(init_params)); 1890 1891 mutex_init(&adev->dm.dpia_aux_lock); 1892 mutex_init(&adev->dm.dc_lock); 1893 mutex_init(&adev->dm.audio_lock); 1894 1895 if (amdgpu_dm_irq_init(adev)) { 1896 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 1897 goto error; 1898 } 1899 1900 init_data.asic_id.chip_family = adev->family; 1901 1902 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1903 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1904 init_data.asic_id.chip_id = adev->pdev->device; 1905 1906 init_data.asic_id.vram_width = adev->gmc.vram_width; 1907 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1908 init_data.asic_id.atombios_base_address = 1909 adev->mode_info.atom_context->bios; 1910 1911 init_data.driver = adev; 1912 1913 /* cgs_device was created in dm_sw_init() */ 1914 init_data.cgs_device = adev->dm.cgs_device; 1915 1916 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1917 1918 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1919 case IP_VERSION(2, 1, 0): 1920 switch (adev->dm.dmcub_fw_version) { 1921 case 0: /* development */ 1922 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1923 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1924 init_data.flags.disable_dmcu = false; 1925 break; 1926 default: 1927 init_data.flags.disable_dmcu = true; 1928 } 1929 break; 1930 case IP_VERSION(2, 0, 3): 1931 init_data.flags.disable_dmcu = true; 1932 break; 1933 default: 1934 break; 1935 } 1936 1937 /* APU support S/G display by default except: 1938 * ASICs before Carrizo, 1939 * RAVEN1 (Users reported stability issue) 1940 */ 1941 1942 if (adev->asic_type < CHIP_CARRIZO) { 1943 init_data.flags.gpu_vm_support = false; 1944 } else if (adev->asic_type == CHIP_RAVEN) { 1945 if (adev->apu_flags & AMD_APU_IS_RAVEN) 1946 init_data.flags.gpu_vm_support = false; 1947 else 1948 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 1949 } else { 1950 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 1951 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 1952 else 1953 init_data.flags.gpu_vm_support = 1954 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 1955 } 1956 1957 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 1958 1959 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1960 init_data.flags.fbc_support = true; 1961 1962 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1963 init_data.flags.multi_mon_pp_mclk_switch = true; 1964 1965 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1966 init_data.flags.disable_fractional_pwm = true; 1967 1968 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1969 init_data.flags.edp_no_power_sequencing = true; 1970 1971 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1972 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1973 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1974 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1975 1976 init_data.flags.seamless_boot_edp_requested = false; 1977 1978 if (amdgpu_device_seamless_boot_supported(adev)) { 1979 init_data.flags.seamless_boot_edp_requested = true; 1980 init_data.flags.allow_seamless_boot_optimization = true; 1981 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 1982 } 1983 1984 init_data.flags.enable_mipi_converter_optimization = true; 1985 1986 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1987 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1988 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 1989 1990 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 1991 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 1992 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 1993 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 1994 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 1995 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 1996 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 1997 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 1998 else 1999 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 2000 2001 init_data.flags.disable_ips_in_vpb = 0; 2002 2003 /* DCN35 and above supports dynamic DTBCLK switch */ 2004 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 2005 init_data.flags.allow_0_dtb_clk = true; 2006 2007 /* Enable DWB for tested platforms only */ 2008 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 2009 init_data.num_virtual_links = 1; 2010 2011 retrieve_dmi_info(&adev->dm); 2012 if (adev->dm.edp0_on_dp1_quirk) 2013 init_data.flags.support_edp0_on_dp1 = true; 2014 2015 if (adev->dm.bb_from_dmub) 2016 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 2017 else 2018 init_data.bb_from_dmub = NULL; 2019 2020 /* Display Core create. */ 2021 adev->dm.dc = dc_create(&init_data); 2022 2023 if (adev->dm.dc) { 2024 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 2025 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 2026 } else { 2027 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 2028 goto error; 2029 } 2030 2031 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 2032 adev->dm.dc->debug.force_single_disp_pipe_split = false; 2033 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 2034 } 2035 2036 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2037 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2038 if (dm_should_disable_stutter(adev->pdev)) 2039 adev->dm.dc->debug.disable_stutter = true; 2040 2041 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 2042 adev->dm.dc->debug.disable_stutter = true; 2043 2044 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 2045 adev->dm.dc->debug.disable_dsc = true; 2046 2047 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 2048 adev->dm.dc->debug.disable_clock_gate = true; 2049 2050 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 2051 adev->dm.dc->debug.force_subvp_mclk_switch = true; 2052 2053 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 2054 adev->dm.dc->debug.force_disable_subvp = true; 2055 adev->dm.dc->debug.fams2_config.bits.enable = false; 2056 } 2057 2058 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 2059 adev->dm.dc->debug.using_dml2 = true; 2060 adev->dm.dc->debug.using_dml21 = true; 2061 } 2062 2063 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 2064 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 2065 2066 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 2067 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 2068 2069 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 2070 adev->dm.dc->debug.skip_detection_link_training = true; 2071 2072 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 2073 2074 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 2075 adev->dm.dc->debug.ignore_cable_id = true; 2076 2077 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 2078 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 2079 2080 r = dm_dmub_hw_init(adev); 2081 if (r) { 2082 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 2083 goto error; 2084 } 2085 2086 dc_hardware_init(adev->dm.dc); 2087 2088 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev); 2089 if (!adev->dm.hpd_rx_offload_wq) { 2090 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 2091 goto error; 2092 } 2093 2094 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 2095 struct dc_phy_addr_space_config pa_config; 2096 2097 mmhub_read_system_context(adev, &pa_config); 2098 2099 // Call the DC init_memory func 2100 dc_setup_system_context(adev->dm.dc, &pa_config); 2101 } 2102 2103 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 2104 if (!adev->dm.freesync_module) { 2105 drm_err(adev_to_drm(adev), 2106 "failed to initialize freesync_module.\n"); 2107 } else 2108 drm_dbg_driver(adev_to_drm(adev), "amdgpu: freesync_module init done %p.\n", 2109 adev->dm.freesync_module); 2110 2111 amdgpu_dm_init_color_mod(); 2112 2113 if (adev->dm.dc->caps.max_links > 0) { 2114 adev->dm.vblank_control_workqueue = 2115 create_singlethread_workqueue("dm_vblank_control_workqueue"); 2116 if (!adev->dm.vblank_control_workqueue) 2117 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 2118 } 2119 2120 if (adev->dm.dc->caps.ips_support && 2121 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 2122 adev->dm.idle_workqueue = idle_create_workqueue(adev); 2123 2124 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 2125 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 2126 2127 if (!adev->dm.hdcp_workqueue) 2128 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 2129 else 2130 drm_dbg_driver(adev_to_drm(adev), "amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 2131 2132 dc_init_callbacks(adev->dm.dc, &init_params); 2133 } 2134 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2135 init_completion(&adev->dm.dmub_aux_transfer_done); 2136 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 2137 if (!adev->dm.dmub_notify) { 2138 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 2139 goto error; 2140 } 2141 2142 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 2143 if (!adev->dm.delayed_hpd_wq) { 2144 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 2145 goto error; 2146 } 2147 2148 amdgpu_dm_outbox_init(adev); 2149 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 2150 dmub_aux_setconfig_callback, false)) { 2151 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 2152 goto error; 2153 } 2154 2155 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 2156 init_completion(&adev->dm.fused_io[i].replied); 2157 2158 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 2159 dmub_aux_fused_io_callback, false)) { 2160 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 2161 goto error; 2162 } 2163 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 2164 * It is expected that DMUB will resend any pending notifications at this point. Note 2165 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 2166 * align legacy interface initialization sequence. Connection status will be proactivly 2167 * detected once in the amdgpu_dm_initialize_drm_device. 2168 */ 2169 dc_enable_dmub_outbox(adev->dm.dc); 2170 2171 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 2172 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 2173 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 2174 } 2175 2176 if (amdgpu_dm_initialize_drm_device(adev)) { 2177 drm_err(adev_to_drm(adev), 2178 "failed to initialize sw for display support.\n"); 2179 goto error; 2180 } 2181 2182 /* create fake encoders for MST */ 2183 dm_dp_create_fake_mst_encoders(adev); 2184 2185 /* TODO: Add_display_info? */ 2186 2187 /* TODO use dynamic cursor width */ 2188 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 2189 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 2190 2191 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 2192 drm_err(adev_to_drm(adev), 2193 "failed to initialize vblank for display support.\n"); 2194 goto error; 2195 } 2196 2197#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2198 amdgpu_dm_crtc_secure_display_create_contexts(adev); 2199 if (!adev->dm.secure_display_ctx.crtc_ctx) 2200 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 2201 2202 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 2203 adev->dm.secure_display_ctx.support_mul_roi = true; 2204 2205#endif 2206 2207 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 2208 2209 return 0; 2210error: 2211 amdgpu_dm_fini(adev); 2212 2213 return -EINVAL; 2214} 2215 2216static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 2217{ 2218 struct amdgpu_device *adev = ip_block->adev; 2219 2220 amdgpu_dm_audio_fini(adev); 2221 2222 return 0; 2223} 2224 2225static void amdgpu_dm_fini(struct amdgpu_device *adev) 2226{ 2227 int i; 2228 2229 if (adev->dm.vblank_control_workqueue) { 2230 destroy_workqueue(adev->dm.vblank_control_workqueue); 2231 adev->dm.vblank_control_workqueue = NULL; 2232 } 2233 2234 if (adev->dm.idle_workqueue) { 2235 if (adev->dm.idle_workqueue->running) { 2236 adev->dm.idle_workqueue->enable = false; 2237 flush_work(&adev->dm.idle_workqueue->work); 2238 } 2239 2240 kfree(adev->dm.idle_workqueue); 2241 adev->dm.idle_workqueue = NULL; 2242 } 2243 2244 amdgpu_dm_destroy_drm_device(&adev->dm); 2245 2246#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2247 if (adev->dm.secure_display_ctx.crtc_ctx) { 2248 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2249 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 2250 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 2251 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 2252 } 2253 } 2254 kfree(adev->dm.secure_display_ctx.crtc_ctx); 2255 adev->dm.secure_display_ctx.crtc_ctx = NULL; 2256 } 2257#endif 2258 if (adev->dm.hdcp_workqueue) { 2259 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 2260 adev->dm.hdcp_workqueue = NULL; 2261 } 2262 2263 if (adev->dm.dc) { 2264 dc_deinit_callbacks(adev->dm.dc); 2265 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 2266 if (dc_enable_dmub_notifications(adev->dm.dc)) { 2267 kfree(adev->dm.dmub_notify); 2268 adev->dm.dmub_notify = NULL; 2269 destroy_workqueue(adev->dm.delayed_hpd_wq); 2270 adev->dm.delayed_hpd_wq = NULL; 2271 } 2272 } 2273 2274 if (adev->dm.dmub_bo) 2275 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 2276 &adev->dm.dmub_bo_gpu_addr, 2277 &adev->dm.dmub_bo_cpu_addr); 2278 2279 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 2280 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 2281 if (adev->dm.hpd_rx_offload_wq[i].wq) { 2282 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 2283 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 2284 } 2285 } 2286 2287 kfree(adev->dm.hpd_rx_offload_wq); 2288 adev->dm.hpd_rx_offload_wq = NULL; 2289 } 2290 2291 /* DC Destroy TODO: Replace destroy DAL */ 2292 if (adev->dm.dc) 2293 dc_destroy(&adev->dm.dc); 2294 /* 2295 * TODO: pageflip, vlank interrupt 2296 * 2297 * amdgpu_dm_irq_fini(adev); 2298 */ 2299 2300 if (adev->dm.cgs_device) { 2301 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 2302 adev->dm.cgs_device = NULL; 2303 } 2304 if (adev->dm.freesync_module) { 2305 mod_freesync_destroy(adev->dm.freesync_module); 2306 adev->dm.freesync_module = NULL; 2307 } 2308 2309 mutex_destroy(&adev->dm.audio_lock); 2310 mutex_destroy(&adev->dm.dc_lock); 2311 mutex_destroy(&adev->dm.dpia_aux_lock); 2312} 2313 2314static int load_dmcu_fw(struct amdgpu_device *adev) 2315{ 2316 const char *fw_name_dmcu = NULL; 2317 int r; 2318 const struct dmcu_firmware_header_v1_0 *hdr; 2319 2320 switch (adev->asic_type) { 2321#if defined(CONFIG_DRM_AMD_DC_SI) 2322 case CHIP_TAHITI: 2323 case CHIP_PITCAIRN: 2324 case CHIP_VERDE: 2325 case CHIP_OLAND: 2326#endif 2327 case CHIP_BONAIRE: 2328 case CHIP_HAWAII: 2329 case CHIP_KAVERI: 2330 case CHIP_KABINI: 2331 case CHIP_MULLINS: 2332 case CHIP_TONGA: 2333 case CHIP_FIJI: 2334 case CHIP_CARRIZO: 2335 case CHIP_STONEY: 2336 case CHIP_POLARIS11: 2337 case CHIP_POLARIS10: 2338 case CHIP_POLARIS12: 2339 case CHIP_VEGAM: 2340 case CHIP_VEGA10: 2341 case CHIP_VEGA12: 2342 case CHIP_VEGA20: 2343 return 0; 2344 case CHIP_NAVI12: 2345 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 2346 break; 2347 case CHIP_RAVEN: 2348 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 2349 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2350 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 2351 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2352 else 2353 return 0; 2354 break; 2355 default: 2356 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2357 case IP_VERSION(2, 0, 2): 2358 case IP_VERSION(2, 0, 3): 2359 case IP_VERSION(2, 0, 0): 2360 case IP_VERSION(2, 1, 0): 2361 case IP_VERSION(3, 0, 0): 2362 case IP_VERSION(3, 0, 2): 2363 case IP_VERSION(3, 0, 3): 2364 case IP_VERSION(3, 0, 1): 2365 case IP_VERSION(3, 1, 2): 2366 case IP_VERSION(3, 1, 3): 2367 case IP_VERSION(3, 1, 4): 2368 case IP_VERSION(3, 1, 5): 2369 case IP_VERSION(3, 1, 6): 2370 case IP_VERSION(3, 2, 0): 2371 case IP_VERSION(3, 2, 1): 2372 case IP_VERSION(3, 5, 0): 2373 case IP_VERSION(3, 5, 1): 2374 case IP_VERSION(3, 6, 0): 2375 case IP_VERSION(4, 0, 1): 2376 return 0; 2377 default: 2378 break; 2379 } 2380 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 2381 return -EINVAL; 2382 } 2383 2384 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2385 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2386 return 0; 2387 } 2388 2389 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 2390 "%s", fw_name_dmcu); 2391 if (r == -ENODEV) { 2392 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2393 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2394 adev->dm.fw_dmcu = NULL; 2395 return 0; 2396 } 2397 if (r) { 2398 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 2399 fw_name_dmcu); 2400 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2401 return r; 2402 } 2403 2404 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2405 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2406 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2407 adev->firmware.fw_size += 2408 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2409 2410 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2411 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2412 adev->firmware.fw_size += 2413 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2414 2415 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2416 2417 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2418 2419 return 0; 2420} 2421 2422static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2423{ 2424 struct amdgpu_device *adev = ctx; 2425 2426 return dm_read_reg(adev->dm.dc->ctx, address); 2427} 2428 2429static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2430 uint32_t value) 2431{ 2432 struct amdgpu_device *adev = ctx; 2433 2434 return dm_write_reg(adev->dm.dc->ctx, address, value); 2435} 2436 2437static int dm_dmub_sw_init(struct amdgpu_device *adev) 2438{ 2439 struct dmub_srv_create_params create_params; 2440 struct dmub_srv_region_params region_params; 2441 struct dmub_srv_region_info region_info; 2442 struct dmub_srv_memory_params memory_params; 2443 struct dmub_srv_fb_info *fb_info; 2444 struct dmub_srv *dmub_srv; 2445 const struct dmcub_firmware_header_v1_0 *hdr; 2446 enum dmub_asic dmub_asic; 2447 enum dmub_status status; 2448 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { 2449 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST 2450 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK 2451 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA 2452 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS 2453 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX 2454 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF 2455 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE 2456 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM 2457 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_IB_MEM 2458 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE 2459 }; 2460 int r; 2461 2462 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2463 case IP_VERSION(2, 1, 0): 2464 dmub_asic = DMUB_ASIC_DCN21; 2465 break; 2466 case IP_VERSION(3, 0, 0): 2467 dmub_asic = DMUB_ASIC_DCN30; 2468 break; 2469 case IP_VERSION(3, 0, 1): 2470 dmub_asic = DMUB_ASIC_DCN301; 2471 break; 2472 case IP_VERSION(3, 0, 2): 2473 dmub_asic = DMUB_ASIC_DCN302; 2474 break; 2475 case IP_VERSION(3, 0, 3): 2476 dmub_asic = DMUB_ASIC_DCN303; 2477 break; 2478 case IP_VERSION(3, 1, 2): 2479 case IP_VERSION(3, 1, 3): 2480 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2481 break; 2482 case IP_VERSION(3, 1, 4): 2483 dmub_asic = DMUB_ASIC_DCN314; 2484 break; 2485 case IP_VERSION(3, 1, 5): 2486 dmub_asic = DMUB_ASIC_DCN315; 2487 break; 2488 case IP_VERSION(3, 1, 6): 2489 dmub_asic = DMUB_ASIC_DCN316; 2490 break; 2491 case IP_VERSION(3, 2, 0): 2492 dmub_asic = DMUB_ASIC_DCN32; 2493 break; 2494 case IP_VERSION(3, 2, 1): 2495 dmub_asic = DMUB_ASIC_DCN321; 2496 break; 2497 case IP_VERSION(3, 5, 0): 2498 case IP_VERSION(3, 5, 1): 2499 dmub_asic = DMUB_ASIC_DCN35; 2500 break; 2501 case IP_VERSION(3, 6, 0): 2502 dmub_asic = DMUB_ASIC_DCN36; 2503 break; 2504 case IP_VERSION(4, 0, 1): 2505 dmub_asic = DMUB_ASIC_DCN401; 2506 break; 2507 2508 default: 2509 /* ASIC doesn't support DMUB. */ 2510 return 0; 2511 } 2512 2513 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2514 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2515 2516 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2517 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2518 AMDGPU_UCODE_ID_DMCUB; 2519 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2520 adev->dm.dmub_fw; 2521 adev->firmware.fw_size += 2522 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2523 2524 drm_info(adev_to_drm(adev), "Loading DMUB firmware via PSP: version=0x%08X\n", 2525 adev->dm.dmcub_fw_version); 2526 } 2527 2528 2529 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2530 dmub_srv = adev->dm.dmub_srv; 2531 2532 if (!dmub_srv) { 2533 drm_err(adev_to_drm(adev), "Failed to allocate DMUB service!\n"); 2534 return -ENOMEM; 2535 } 2536 2537 memset(&create_params, 0, sizeof(create_params)); 2538 create_params.user_ctx = adev; 2539 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2540 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2541 create_params.asic = dmub_asic; 2542 2543 /* Create the DMUB service. */ 2544 status = dmub_srv_create(dmub_srv, &create_params); 2545 if (status != DMUB_STATUS_OK) { 2546 drm_err(adev_to_drm(adev), "Error creating DMUB service: %d\n", status); 2547 return -EINVAL; 2548 } 2549 2550 /* Calculate the size of all the regions for the DMUB service. */ 2551 memset(®ion_params, 0, sizeof(region_params)); 2552 2553 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2554 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2555 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2556 region_params.vbios_size = adev->bios_size; 2557 region_params.fw_bss_data = region_params.bss_data_size ? 2558 adev->dm.dmub_fw->data + 2559 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2560 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2561 region_params.fw_inst_const = 2562 adev->dm.dmub_fw->data + 2563 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2564 PSP_HEADER_BYTES; 2565 region_params.window_memory_type = window_memory_type; 2566 2567 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2568 ®ion_info); 2569 2570 if (status != DMUB_STATUS_OK) { 2571 drm_err(adev_to_drm(adev), "Error calculating DMUB region info: %d\n", status); 2572 return -EINVAL; 2573 } 2574 2575 /* 2576 * Allocate a framebuffer based on the total size of all the regions. 2577 * TODO: Move this into GART. 2578 */ 2579 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2580 AMDGPU_GEM_DOMAIN_VRAM | 2581 AMDGPU_GEM_DOMAIN_GTT, 2582 &adev->dm.dmub_bo, 2583 &adev->dm.dmub_bo_gpu_addr, 2584 &adev->dm.dmub_bo_cpu_addr); 2585 if (r) 2586 return r; 2587 2588 /* Rebase the regions on the framebuffer address. */ 2589 memset(&memory_params, 0, sizeof(memory_params)); 2590 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2591 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2592 memory_params.region_info = ®ion_info; 2593 memory_params.window_memory_type = window_memory_type; 2594 2595 adev->dm.dmub_fb_info = 2596 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2597 fb_info = adev->dm.dmub_fb_info; 2598 2599 if (!fb_info) { 2600 drm_err(adev_to_drm(adev), 2601 "Failed to allocate framebuffer info for DMUB service!\n"); 2602 return -ENOMEM; 2603 } 2604 2605 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2606 if (status != DMUB_STATUS_OK) { 2607 drm_err(adev_to_drm(adev), "Error calculating DMUB FB info: %d\n", status); 2608 return -EINVAL; 2609 } 2610 2611 adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev); 2612 2613 return 0; 2614} 2615 2616static int dm_sw_init(struct amdgpu_ip_block *ip_block) 2617{ 2618 struct amdgpu_device *adev = ip_block->adev; 2619 int r; 2620 2621 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 2622 2623 if (!adev->dm.cgs_device) { 2624 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 2625 return -EINVAL; 2626 } 2627 2628 /* Moved from dm init since we need to use allocations for storing bounding box data */ 2629 INIT_LIST_HEAD(&adev->dm.da_list); 2630 2631 r = dm_dmub_sw_init(adev); 2632 if (r) 2633 return r; 2634 2635 return load_dmcu_fw(adev); 2636} 2637 2638static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 2639{ 2640 struct amdgpu_device *adev = ip_block->adev; 2641 struct dal_allocation *da; 2642 2643 list_for_each_entry(da, &adev->dm.da_list, list) { 2644 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 2645 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 2646 list_del(&da->list); 2647 kfree(da); 2648 adev->dm.bb_from_dmub = NULL; 2649 break; 2650 } 2651 } 2652 2653 2654 kfree(adev->dm.dmub_fb_info); 2655 adev->dm.dmub_fb_info = NULL; 2656 2657 if (adev->dm.dmub_srv) { 2658 dmub_srv_destroy(adev->dm.dmub_srv); 2659 kfree(adev->dm.dmub_srv); 2660 adev->dm.dmub_srv = NULL; 2661 } 2662 2663 amdgpu_ucode_release(&adev->dm.dmub_fw); 2664 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2665 2666 return 0; 2667} 2668 2669static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2670{ 2671 struct amdgpu_dm_connector *aconnector; 2672 struct drm_connector *connector; 2673 struct drm_connector_list_iter iter; 2674 int ret = 0; 2675 2676 drm_connector_list_iter_begin(dev, &iter); 2677 drm_for_each_connector_iter(connector, &iter) { 2678 2679 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2680 continue; 2681 2682 aconnector = to_amdgpu_dm_connector(connector); 2683 if (aconnector->dc_link->type == dc_connection_mst_branch && 2684 aconnector->mst_mgr.aux) { 2685 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", 2686 aconnector, 2687 aconnector->base.base.id); 2688 2689 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2690 if (ret < 0) { 2691 drm_err(dev, "DM_MST: Failed to start MST\n"); 2692 aconnector->dc_link->type = 2693 dc_connection_single; 2694 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2695 aconnector->dc_link); 2696 break; 2697 } 2698 } 2699 } 2700 drm_connector_list_iter_end(&iter); 2701 2702 return ret; 2703} 2704 2705static int dm_late_init(struct amdgpu_ip_block *ip_block) 2706{ 2707 struct amdgpu_device *adev = ip_block->adev; 2708 2709 struct dmcu_iram_parameters params; 2710 unsigned int linear_lut[16]; 2711 int i; 2712 struct dmcu *dmcu = NULL; 2713 2714 dmcu = adev->dm.dc->res_pool->dmcu; 2715 2716 for (i = 0; i < 16; i++) 2717 linear_lut[i] = 0xFFFF * i / 15; 2718 2719 params.set = 0; 2720 params.backlight_ramping_override = false; 2721 params.backlight_ramping_start = 0xCCCC; 2722 params.backlight_ramping_reduction = 0xCCCCCCCC; 2723 params.backlight_lut_array_size = 16; 2724 params.backlight_lut_array = linear_lut; 2725 2726 /* Min backlight level after ABM reduction, Don't allow below 1% 2727 * 0xFFFF x 0.01 = 0x28F 2728 */ 2729 params.min_abm_backlight = 0x28F; 2730 /* In the case where abm is implemented on dmcub, 2731 * dmcu object will be null. 2732 * ABM 2.4 and up are implemented on dmcub. 2733 */ 2734 if (dmcu) { 2735 if (!dmcu_load_iram(dmcu, params)) 2736 return -EINVAL; 2737 } else if (adev->dm.dc->ctx->dmub_srv) { 2738 struct dc_link *edp_links[MAX_NUM_EDP]; 2739 int edp_num; 2740 2741 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2742 for (i = 0; i < edp_num; i++) { 2743 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2744 return -EINVAL; 2745 } 2746 } 2747 2748 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2749} 2750 2751static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2752{ 2753 u8 buf[UUID_SIZE]; 2754 guid_t guid; 2755 int ret; 2756 2757 mutex_lock(&mgr->lock); 2758 if (!mgr->mst_primary) 2759 goto out_fail; 2760 2761 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2762 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2763 goto out_fail; 2764 } 2765 2766 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2767 DP_MST_EN | 2768 DP_UP_REQ_EN | 2769 DP_UPSTREAM_IS_SRC); 2770 if (ret < 0) { 2771 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2772 goto out_fail; 2773 } 2774 2775 /* Some hubs forget their guids after they resume */ 2776 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 2777 if (ret != sizeof(buf)) { 2778 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2779 goto out_fail; 2780 } 2781 2782 import_guid(&guid, buf); 2783 2784 if (guid_is_null(&guid)) { 2785 guid_gen(&guid); 2786 export_guid(buf, &guid); 2787 2788 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 2789 2790 if (ret != sizeof(buf)) { 2791 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2792 goto out_fail; 2793 } 2794 } 2795 2796 guid_copy(&mgr->mst_primary->guid, &guid); 2797 2798out_fail: 2799 mutex_unlock(&mgr->lock); 2800} 2801 2802void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector) 2803{ 2804 struct cec_notifier *n = aconnector->notifier; 2805 2806 if (!n) 2807 return; 2808 2809 cec_notifier_phys_addr_invalidate(n); 2810} 2811 2812void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) 2813{ 2814 struct drm_connector *connector = &aconnector->base; 2815 struct cec_notifier *n = aconnector->notifier; 2816 2817 if (!n) 2818 return; 2819 2820 cec_notifier_set_phys_addr(n, 2821 connector->display_info.source_physical_address); 2822} 2823 2824static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) 2825{ 2826 struct amdgpu_dm_connector *aconnector; 2827 struct drm_connector *connector; 2828 struct drm_connector_list_iter conn_iter; 2829 2830 drm_connector_list_iter_begin(ddev, &conn_iter); 2831 drm_for_each_connector_iter(connector, &conn_iter) { 2832 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2833 continue; 2834 2835 aconnector = to_amdgpu_dm_connector(connector); 2836 if (suspend) 2837 hdmi_cec_unset_edid(aconnector); 2838 else 2839 hdmi_cec_set_edid(aconnector); 2840 } 2841 drm_connector_list_iter_end(&conn_iter); 2842} 2843 2844static void s3_handle_mst(struct drm_device *dev, bool suspend) 2845{ 2846 struct amdgpu_dm_connector *aconnector; 2847 struct drm_connector *connector; 2848 struct drm_connector_list_iter iter; 2849 struct drm_dp_mst_topology_mgr *mgr; 2850 2851 drm_connector_list_iter_begin(dev, &iter); 2852 drm_for_each_connector_iter(connector, &iter) { 2853 2854 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2855 continue; 2856 2857 aconnector = to_amdgpu_dm_connector(connector); 2858 if (aconnector->dc_link->type != dc_connection_mst_branch || 2859 aconnector->mst_root) 2860 continue; 2861 2862 mgr = &aconnector->mst_mgr; 2863 2864 if (suspend) { 2865 drm_dp_mst_topology_mgr_suspend(mgr); 2866 } else { 2867 /* if extended timeout is supported in hardware, 2868 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2869 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2870 */ 2871 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2872 if (!dp_is_lttpr_present(aconnector->dc_link)) 2873 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2874 2875 /* TODO: move resume_mst_branch_status() into drm mst resume again 2876 * once topology probing work is pulled out from mst resume into mst 2877 * resume 2nd step. mst resume 2nd step should be called after old 2878 * state getting restored (i.e. drm_atomic_helper_resume()). 2879 */ 2880 resume_mst_branch_status(mgr); 2881 } 2882 } 2883 drm_connector_list_iter_end(&iter); 2884} 2885 2886static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2887{ 2888 int ret = 0; 2889 2890 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2891 * on window driver dc implementation. 2892 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2893 * should be passed to smu during boot up and resume from s3. 2894 * boot up: dc calculate dcn watermark clock settings within dc_create, 2895 * dcn20_resource_construct 2896 * then call pplib functions below to pass the settings to smu: 2897 * smu_set_watermarks_for_clock_ranges 2898 * smu_set_watermarks_table 2899 * navi10_set_watermarks_table 2900 * smu_write_watermarks_table 2901 * 2902 * For Renoir, clock settings of dcn watermark are also fixed values. 2903 * dc has implemented different flow for window driver: 2904 * dc_hardware_init / dc_set_power_state 2905 * dcn10_init_hw 2906 * notify_wm_ranges 2907 * set_wm_ranges 2908 * -- Linux 2909 * smu_set_watermarks_for_clock_ranges 2910 * renoir_set_watermarks_table 2911 * smu_write_watermarks_table 2912 * 2913 * For Linux, 2914 * dc_hardware_init -> amdgpu_dm_init 2915 * dc_set_power_state --> dm_resume 2916 * 2917 * therefore, this function apply to navi10/12/14 but not Renoir 2918 * * 2919 */ 2920 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2921 case IP_VERSION(2, 0, 2): 2922 case IP_VERSION(2, 0, 0): 2923 break; 2924 default: 2925 return 0; 2926 } 2927 2928 ret = amdgpu_dpm_write_watermarks_table(adev); 2929 if (ret) { 2930 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); 2931 return ret; 2932 } 2933 2934 return 0; 2935} 2936 2937static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 2938{ 2939 struct amdgpu_display_manager *dm = &adev->dm; 2940 struct amdgpu_i2c_adapter *oem_i2c; 2941 struct ddc_service *oem_ddc_service; 2942 int r; 2943 2944 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 2945 if (oem_ddc_service) { 2946 oem_i2c = create_i2c(oem_ddc_service, true); 2947 if (!oem_i2c) { 2948 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 2949 return -ENOMEM; 2950 } 2951 2952 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 2953 if (r) { 2954 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 2955 kfree(oem_i2c); 2956 return r; 2957 } 2958 dm->oem_i2c = oem_i2c; 2959 } 2960 2961 return 0; 2962} 2963 2964/** 2965 * dm_hw_init() - Initialize DC device 2966 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 2967 * 2968 * Initialize the &struct amdgpu_display_manager device. This involves calling 2969 * the initializers of each DM component, then populating the struct with them. 2970 * 2971 * Although the function implies hardware initialization, both hardware and 2972 * software are initialized here. Splitting them out to their relevant init 2973 * hooks is a future TODO item. 2974 * 2975 * Some notable things that are initialized here: 2976 * 2977 * - Display Core, both software and hardware 2978 * - DC modules that we need (freesync and color management) 2979 * - DRM software states 2980 * - Interrupt sources and handlers 2981 * - Vblank support 2982 * - Debug FS entries, if enabled 2983 */ 2984static int dm_hw_init(struct amdgpu_ip_block *ip_block) 2985{ 2986 struct amdgpu_device *adev = ip_block->adev; 2987 int r; 2988 2989 /* Create DAL display manager */ 2990 r = amdgpu_dm_init(adev); 2991 if (r) 2992 return r; 2993 amdgpu_dm_hpd_init(adev); 2994 2995 r = dm_oem_i2c_hw_init(adev); 2996 if (r) 2997 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 2998 2999 return 0; 3000} 3001 3002/** 3003 * dm_hw_fini() - Teardown DC device 3004 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 3005 * 3006 * Teardown components within &struct amdgpu_display_manager that require 3007 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 3008 * were loaded. Also flush IRQ workqueues and disable them. 3009 */ 3010static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 3011{ 3012 struct amdgpu_device *adev = ip_block->adev; 3013 3014 amdgpu_dm_hpd_fini(adev); 3015 3016 amdgpu_dm_irq_fini(adev); 3017 amdgpu_dm_fini(adev); 3018 return 0; 3019} 3020 3021 3022static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 3023 struct dc_state *state, bool enable) 3024{ 3025 enum dc_irq_source irq_source; 3026 struct amdgpu_crtc *acrtc; 3027 int rc = -EBUSY; 3028 int i = 0; 3029 3030 for (i = 0; i < state->stream_count; i++) { 3031 acrtc = get_crtc_by_otg_inst( 3032 adev, state->stream_status[i].primary_otg_inst); 3033 3034 if (acrtc && state->stream_status[i].plane_count != 0) { 3035 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 3036 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3037 if (rc) 3038 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 3039 enable ? "enable" : "disable"); 3040 3041 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 3042 if (enable) { 3043 if (amdgpu_dm_crtc_vrr_active( 3044 to_dm_crtc_state(acrtc->base.state))) 3045 rc = amdgpu_dm_crtc_set_vupdate_irq( 3046 &acrtc->base, true); 3047 } else 3048 rc = amdgpu_dm_crtc_set_vupdate_irq( 3049 &acrtc->base, false); 3050 3051 if (rc) 3052 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 3053 enable ? "en" : "dis"); 3054 } 3055 3056 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3057 /* During gpu-reset we disable and then enable vblank irq, so 3058 * don't use amdgpu_irq_get/put() to avoid refcount change. 3059 */ 3060 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 3061 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 3062 } 3063 } 3064 3065} 3066 3067DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 3068 3069static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 3070{ 3071 struct dc_state *context __free(state_release) = NULL; 3072 int i; 3073 struct dc_stream_state *del_streams[MAX_PIPES]; 3074 int del_streams_count = 0; 3075 struct dc_commit_streams_params params = {}; 3076 3077 memset(del_streams, 0, sizeof(del_streams)); 3078 3079 context = dc_state_create_current_copy(dc); 3080 if (context == NULL) 3081 return DC_ERROR_UNEXPECTED; 3082 3083 /* First remove from context all streams */ 3084 for (i = 0; i < context->stream_count; i++) { 3085 struct dc_stream_state *stream = context->streams[i]; 3086 3087 del_streams[del_streams_count++] = stream; 3088 } 3089 3090 /* Remove all planes for removed streams and then remove the streams */ 3091 for (i = 0; i < del_streams_count; i++) { 3092 enum dc_status res; 3093 3094 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 3095 return DC_FAIL_DETACH_SURFACES; 3096 3097 res = dc_state_remove_stream(dc, context, del_streams[i]); 3098 if (res != DC_OK) 3099 return res; 3100 } 3101 3102 params.streams = context->streams; 3103 params.stream_count = context->stream_count; 3104 3105 return dc_commit_streams(dc, ¶ms); 3106} 3107 3108static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 3109{ 3110 int i; 3111 3112 if (dm->hpd_rx_offload_wq) { 3113 for (i = 0; i < dm->dc->caps.max_links; i++) 3114 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 3115 } 3116} 3117 3118static int dm_cache_state(struct amdgpu_device *adev) 3119{ 3120 int r; 3121 3122 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 3123 if (IS_ERR(adev->dm.cached_state)) { 3124 r = PTR_ERR(adev->dm.cached_state); 3125 adev->dm.cached_state = NULL; 3126 } 3127 3128 return adev->dm.cached_state ? 0 : r; 3129} 3130 3131static void dm_destroy_cached_state(struct amdgpu_device *adev) 3132{ 3133 struct amdgpu_display_manager *dm = &adev->dm; 3134 struct drm_device *ddev = adev_to_drm(adev); 3135 struct dm_plane_state *dm_new_plane_state; 3136 struct drm_plane_state *new_plane_state; 3137 struct dm_crtc_state *dm_new_crtc_state; 3138 struct drm_crtc_state *new_crtc_state; 3139 struct drm_plane *plane; 3140 struct drm_crtc *crtc; 3141 int i; 3142 3143 if (!dm->cached_state) 3144 return; 3145 3146 /* Force mode set in atomic commit */ 3147 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3148 new_crtc_state->active_changed = true; 3149 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3150 reset_freesync_config_for_crtc(dm_new_crtc_state); 3151 } 3152 3153 /* 3154 * atomic_check is expected to create the dc states. We need to release 3155 * them here, since they were duplicated as part of the suspend 3156 * procedure. 3157 */ 3158 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3159 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3160 if (dm_new_crtc_state->stream) { 3161 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 3162 dc_stream_release(dm_new_crtc_state->stream); 3163 dm_new_crtc_state->stream = NULL; 3164 } 3165 dm_new_crtc_state->base.color_mgmt_changed = true; 3166 } 3167 3168 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 3169 dm_new_plane_state = to_dm_plane_state(new_plane_state); 3170 if (dm_new_plane_state->dc_state) { 3171 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 3172 dc_plane_state_release(dm_new_plane_state->dc_state); 3173 dm_new_plane_state->dc_state = NULL; 3174 } 3175 } 3176 3177 drm_atomic_helper_resume(ddev, dm->cached_state); 3178 3179 dm->cached_state = NULL; 3180} 3181 3182static int dm_suspend(struct amdgpu_ip_block *ip_block) 3183{ 3184 struct amdgpu_device *adev = ip_block->adev; 3185 struct amdgpu_display_manager *dm = &adev->dm; 3186 3187 if (amdgpu_in_reset(adev)) { 3188 enum dc_status res; 3189 3190 mutex_lock(&dm->dc_lock); 3191 3192 dc_allow_idle_optimizations(adev->dm.dc, false); 3193 3194 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 3195 3196 if (dm->cached_dc_state) 3197 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 3198 3199 res = amdgpu_dm_commit_zero_streams(dm->dc); 3200 if (res != DC_OK) { 3201 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 3202 return -EINVAL; 3203 } 3204 3205 amdgpu_dm_irq_suspend(adev); 3206 3207 hpd_rx_irq_work_suspend(dm); 3208 3209 return 0; 3210 } 3211 3212 if (!adev->dm.cached_state) { 3213 int r = dm_cache_state(adev); 3214 3215 if (r) 3216 return r; 3217 } 3218 3219 s3_handle_hdmi_cec(adev_to_drm(adev), true); 3220 3221 s3_handle_mst(adev_to_drm(adev), true); 3222 3223 amdgpu_dm_irq_suspend(adev); 3224 3225 hpd_rx_irq_work_suspend(dm); 3226 3227 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 3228 3229 if (dm->dc->caps.ips_support && adev->in_s0ix) 3230 dc_allow_idle_optimizations(dm->dc, true); 3231 3232 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 3233 3234 return 0; 3235} 3236 3237struct drm_connector * 3238amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 3239 struct drm_crtc *crtc) 3240{ 3241 u32 i; 3242 struct drm_connector_state *new_con_state; 3243 struct drm_connector *connector; 3244 struct drm_crtc *crtc_from_state; 3245 3246 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3247 crtc_from_state = new_con_state->crtc; 3248 3249 if (crtc_from_state == crtc) 3250 return connector; 3251 } 3252 3253 return NULL; 3254} 3255 3256static void emulated_link_detect(struct dc_link *link) 3257{ 3258 struct dc_sink_init_data sink_init_data = { 0 }; 3259 struct display_sink_capability sink_caps = { 0 }; 3260 enum dc_edid_status edid_status; 3261 struct dc_context *dc_ctx = link->ctx; 3262 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 3263 struct dc_sink *sink = NULL; 3264 struct dc_sink *prev_sink = NULL; 3265 3266 link->type = dc_connection_none; 3267 prev_sink = link->local_sink; 3268 3269 if (prev_sink) 3270 dc_sink_release(prev_sink); 3271 3272 switch (link->connector_signal) { 3273 case SIGNAL_TYPE_HDMI_TYPE_A: { 3274 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 3275 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 3276 break; 3277 } 3278 3279 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 3280 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 3281 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 3282 break; 3283 } 3284 3285 case SIGNAL_TYPE_DVI_DUAL_LINK: { 3286 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 3287 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 3288 break; 3289 } 3290 3291 case SIGNAL_TYPE_LVDS: { 3292 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 3293 sink_caps.signal = SIGNAL_TYPE_LVDS; 3294 break; 3295 } 3296 3297 case SIGNAL_TYPE_EDP: { 3298 sink_caps.transaction_type = 3299 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 3300 sink_caps.signal = SIGNAL_TYPE_EDP; 3301 break; 3302 } 3303 3304 case SIGNAL_TYPE_DISPLAY_PORT: { 3305 sink_caps.transaction_type = 3306 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 3307 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 3308 break; 3309 } 3310 3311 default: 3312 drm_err(dev, "Invalid connector type! signal:%d\n", 3313 link->connector_signal); 3314 return; 3315 } 3316 3317 sink_init_data.link = link; 3318 sink_init_data.sink_signal = sink_caps.signal; 3319 3320 sink = dc_sink_create(&sink_init_data); 3321 if (!sink) { 3322 drm_err(dev, "Failed to create sink!\n"); 3323 return; 3324 } 3325 3326 /* dc_sink_create returns a new reference */ 3327 link->local_sink = sink; 3328 3329 edid_status = dm_helpers_read_local_edid( 3330 link->ctx, 3331 link, 3332 sink); 3333 3334 if (edid_status != EDID_OK) 3335 drm_err(dev, "Failed to read EDID\n"); 3336 3337} 3338 3339static void dm_gpureset_commit_state(struct dc_state *dc_state, 3340 struct amdgpu_display_manager *dm) 3341{ 3342 struct { 3343 struct dc_surface_update surface_updates[MAX_SURFACES]; 3344 struct dc_plane_info plane_infos[MAX_SURFACES]; 3345 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3346 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3347 struct dc_stream_update stream_update; 3348 } *bundle __free(kfree); 3349 int k, m; 3350 3351 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 3352 3353 if (!bundle) { 3354 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 3355 return; 3356 } 3357 3358 for (k = 0; k < dc_state->stream_count; k++) { 3359 bundle->stream_update.stream = dc_state->streams[k]; 3360 3361 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 3362 bundle->surface_updates[m].surface = 3363 dc_state->stream_status[k].plane_states[m]; 3364 bundle->surface_updates[m].surface->force_full_update = 3365 true; 3366 } 3367 3368 update_planes_and_stream_adapter(dm->dc, 3369 UPDATE_TYPE_FULL, 3370 dc_state->stream_status[k].plane_count, 3371 dc_state->streams[k], 3372 &bundle->stream_update, 3373 bundle->surface_updates); 3374 } 3375} 3376 3377static void apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 3378 struct dc_sink *sink) 3379{ 3380 struct dc_panel_patch *ppatch = NULL; 3381 3382 if (!sink) 3383 return; 3384 3385 ppatch = &sink->edid_caps.panel_patch; 3386 if (ppatch->wait_after_dpcd_poweroff_ms) { 3387 msleep(ppatch->wait_after_dpcd_poweroff_ms); 3388 drm_dbg_driver(adev_to_drm(adev), 3389 "%s: adding a %ds delay as w/a for panel\n", 3390 __func__, 3391 ppatch->wait_after_dpcd_poweroff_ms / 1000); 3392 } 3393} 3394 3395/** 3396 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 3397 * @adev: amdgpu device pointer 3398 * 3399 * Iterates through all DC links and dumps information about local and remote 3400 * (MST) sinks. Should be called after connector detection is complete to see 3401 * the final state of all links. 3402 */ 3403static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 3404{ 3405 struct dc *dc = adev->dm.dc; 3406 struct drm_device *dev = adev_to_drm(adev); 3407 int li; 3408 3409 if (!dc) 3410 return; 3411 3412 for (li = 0; li < dc->link_count; li++) { 3413 struct dc_link *l = dc->links[li]; 3414 const char *name = NULL; 3415 int rs; 3416 3417 if (!l) 3418 continue; 3419 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 3420 name = l->local_sink->edid_caps.display_name; 3421 else 3422 name = "n/a"; 3423 3424 drm_dbg_kms(dev, 3425 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 3426 li, 3427 l->local_sink, 3428 l->type, 3429 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 3430 l->sink_count, 3431 name, 3432 l->dpcd_caps.is_mst_capable, 3433 l->mst_stream_alloc_table.stream_count); 3434 3435 /* Dump remote (MST) sinks if any */ 3436 for (rs = 0; rs < l->sink_count; rs++) { 3437 struct dc_sink *rsink = l->remote_sinks[rs]; 3438 const char *rname = NULL; 3439 3440 if (!rsink) 3441 continue; 3442 if (rsink->edid_caps.display_name[0]) 3443 rname = rsink->edid_caps.display_name; 3444 else 3445 rname = "n/a"; 3446 drm_dbg_kms(dev, 3447 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 3448 li, rs, 3449 rsink, 3450 rsink->sink_signal, 3451 rname); 3452 } 3453 } 3454} 3455 3456static int dm_resume(struct amdgpu_ip_block *ip_block) 3457{ 3458 struct amdgpu_device *adev = ip_block->adev; 3459 struct drm_device *ddev = adev_to_drm(adev); 3460 struct amdgpu_display_manager *dm = &adev->dm; 3461 struct amdgpu_dm_connector *aconnector; 3462 struct drm_connector *connector; 3463 struct drm_connector_list_iter iter; 3464 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 3465 enum dc_connection_type new_connection_type = dc_connection_none; 3466 struct dc_state *dc_state; 3467 int i, r, j; 3468 struct dc_commit_streams_params commit_params = {}; 3469 3470 if (dm->dc->caps.ips_support) { 3471 if (!amdgpu_in_reset(adev)) 3472 mutex_lock(&dm->dc_lock); 3473 3474 /* Need to set POWER_STATE_D0 first or it will not execute 3475 * idle_power_optimizations command to DMUB. 3476 */ 3477 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3478 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 3479 3480 if (!amdgpu_in_reset(adev)) 3481 mutex_unlock(&dm->dc_lock); 3482 } 3483 3484 if (amdgpu_in_reset(adev)) { 3485 dc_state = dm->cached_dc_state; 3486 3487 /* 3488 * The dc->current_state is backed up into dm->cached_dc_state 3489 * before we commit 0 streams. 3490 * 3491 * DC will clear link encoder assignments on the real state 3492 * but the changes won't propagate over to the copy we made 3493 * before the 0 streams commit. 3494 * 3495 * DC expects that link encoder assignments are *not* valid 3496 * when committing a state, so as a workaround we can copy 3497 * off of the current state. 3498 * 3499 * We lose the previous assignments, but we had already 3500 * commit 0 streams anyway. 3501 */ 3502 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 3503 3504 r = dm_dmub_hw_init(adev); 3505 if (r) { 3506 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 3507 return r; 3508 } 3509 3510 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3511 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3512 3513 dc_resume(dm->dc); 3514 3515 amdgpu_dm_irq_resume_early(adev); 3516 3517 for (i = 0; i < dc_state->stream_count; i++) { 3518 dc_state->streams[i]->mode_changed = true; 3519 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 3520 dc_state->stream_status[i].plane_states[j]->update_flags.raw 3521 = 0xffffffff; 3522 } 3523 } 3524 3525 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3526 amdgpu_dm_outbox_init(adev); 3527 dc_enable_dmub_outbox(adev->dm.dc); 3528 } 3529 3530 commit_params.streams = dc_state->streams; 3531 commit_params.stream_count = dc_state->stream_count; 3532 dc_exit_ips_for_hw_access(dm->dc); 3533 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 3534 3535 dm_gpureset_commit_state(dm->cached_dc_state, dm); 3536 3537 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 3538 3539 dc_state_release(dm->cached_dc_state); 3540 dm->cached_dc_state = NULL; 3541 3542 amdgpu_dm_irq_resume_late(adev); 3543 3544 mutex_unlock(&dm->dc_lock); 3545 3546 /* set the backlight after a reset */ 3547 for (i = 0; i < dm->num_of_edps; i++) { 3548 if (dm->backlight_dev[i]) 3549 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 3550 } 3551 3552 return 0; 3553 } 3554 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 3555 dc_state_release(dm_state->context); 3556 dm_state->context = dc_state_create(dm->dc, NULL); 3557 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 3558 3559 /* Before powering on DC we need to re-initialize DMUB. */ 3560 dm_dmub_hw_resume(adev); 3561 3562 /* Re-enable outbox interrupts for DPIA. */ 3563 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3564 amdgpu_dm_outbox_init(adev); 3565 dc_enable_dmub_outbox(adev->dm.dc); 3566 } 3567 3568 /* power on hardware */ 3569 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3570 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3571 3572 /* program HPD filter */ 3573 dc_resume(dm->dc); 3574 3575 /* 3576 * early enable HPD Rx IRQ, should be done before set mode as short 3577 * pulse interrupts are used for MST 3578 */ 3579 amdgpu_dm_irq_resume_early(adev); 3580 3581 s3_handle_hdmi_cec(ddev, false); 3582 3583 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 3584 s3_handle_mst(ddev, false); 3585 3586 /* Do detection*/ 3587 drm_connector_list_iter_begin(ddev, &iter); 3588 drm_for_each_connector_iter(connector, &iter) { 3589 bool ret; 3590 3591 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3592 continue; 3593 3594 aconnector = to_amdgpu_dm_connector(connector); 3595 3596 if (!aconnector->dc_link) 3597 continue; 3598 3599 /* 3600 * this is the case when traversing through already created end sink 3601 * MST connectors, should be skipped 3602 */ 3603 if (aconnector->mst_root) 3604 continue; 3605 3606 guard(mutex)(&aconnector->hpd_lock); 3607 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3608 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 3609 3610 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3611 emulated_link_detect(aconnector->dc_link); 3612 } else { 3613 guard(mutex)(&dm->dc_lock); 3614 dc_exit_ips_for_hw_access(dm->dc); 3615 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 3616 if (ret) { 3617 /* w/a delay for certain panels */ 3618 apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 3619 } 3620 } 3621 3622 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 3623 aconnector->fake_enable = false; 3624 3625 if (aconnector->dc_sink) 3626 dc_sink_release(aconnector->dc_sink); 3627 aconnector->dc_sink = NULL; 3628 amdgpu_dm_update_connector_after_detect(aconnector); 3629 } 3630 drm_connector_list_iter_end(&iter); 3631 3632 dm_destroy_cached_state(adev); 3633 3634 /* Do mst topology probing after resuming cached state*/ 3635 drm_connector_list_iter_begin(ddev, &iter); 3636 drm_for_each_connector_iter(connector, &iter) { 3637 bool init = false; 3638 3639 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3640 continue; 3641 3642 aconnector = to_amdgpu_dm_connector(connector); 3643 if (aconnector->dc_link->type != dc_connection_mst_branch || 3644 aconnector->mst_root) 3645 continue; 3646 3647 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 3648 init = !aconnector->mst_mgr.mst_primary; 3649 } 3650 if (init) 3651 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 3652 aconnector->dc_link, false); 3653 else 3654 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3655 } 3656 drm_connector_list_iter_end(&iter); 3657 3658 /* Debug dump: list all DC links and their associated sinks after detection 3659 * is complete for all connectors. This provides a comprehensive view of the 3660 * final state without repeating the dump for each connector. 3661 */ 3662 amdgpu_dm_dump_links_and_sinks(adev); 3663 3664 amdgpu_dm_irq_resume_late(adev); 3665 3666 amdgpu_dm_smu_write_watermarks_table(adev); 3667 3668 drm_kms_helper_hotplug_event(ddev); 3669 3670 return 0; 3671} 3672 3673/** 3674 * DOC: DM Lifecycle 3675 * 3676 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3677 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3678 * the base driver's device list to be initialized and torn down accordingly. 3679 * 3680 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3681 */ 3682 3683static const struct amd_ip_funcs amdgpu_dm_funcs = { 3684 .name = "dm", 3685 .early_init = dm_early_init, 3686 .late_init = dm_late_init, 3687 .sw_init = dm_sw_init, 3688 .sw_fini = dm_sw_fini, 3689 .early_fini = amdgpu_dm_early_fini, 3690 .hw_init = dm_hw_init, 3691 .hw_fini = dm_hw_fini, 3692 .suspend = dm_suspend, 3693 .resume = dm_resume, 3694 .is_idle = dm_is_idle, 3695 .wait_for_idle = dm_wait_for_idle, 3696 .check_soft_reset = dm_check_soft_reset, 3697 .soft_reset = dm_soft_reset, 3698 .set_clockgating_state = dm_set_clockgating_state, 3699 .set_powergating_state = dm_set_powergating_state, 3700}; 3701 3702const struct amdgpu_ip_block_version dm_ip_block = { 3703 .type = AMD_IP_BLOCK_TYPE_DCE, 3704 .major = 1, 3705 .minor = 0, 3706 .rev = 0, 3707 .funcs = &amdgpu_dm_funcs, 3708}; 3709 3710 3711/** 3712 * DOC: atomic 3713 * 3714 * *WIP* 3715 */ 3716 3717static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3718 .fb_create = amdgpu_display_user_framebuffer_create, 3719 .get_format_info = amdgpu_dm_plane_get_format_info, 3720 .atomic_check = amdgpu_dm_atomic_check, 3721 .atomic_commit = drm_atomic_helper_commit, 3722}; 3723 3724static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3725 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3726 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 3727}; 3728 3729static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3730{ 3731 const struct drm_panel_backlight_quirk *panel_backlight_quirk; 3732 struct amdgpu_dm_backlight_caps *caps; 3733 struct drm_connector *conn_base; 3734 struct amdgpu_device *adev; 3735 struct drm_luminance_range_info *luminance_range; 3736 struct drm_device *drm; 3737 3738 if (aconnector->bl_idx == -1 || 3739 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3740 return; 3741 3742 conn_base = &aconnector->base; 3743 drm = conn_base->dev; 3744 adev = drm_to_adev(drm); 3745 3746 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3747 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3748 caps->aux_support = false; 3749 3750 if (caps->ext_caps->bits.oled == 1 3751 /* 3752 * || 3753 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3754 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3755 */) 3756 caps->aux_support = true; 3757 3758 if (amdgpu_backlight == 0) 3759 caps->aux_support = false; 3760 else if (amdgpu_backlight == 1) 3761 caps->aux_support = true; 3762 if (caps->aux_support) 3763 aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX; 3764 3765 luminance_range = &conn_base->display_info.luminance_range; 3766 3767 if (luminance_range->max_luminance) 3768 caps->aux_max_input_signal = luminance_range->max_luminance; 3769 else 3770 caps->aux_max_input_signal = 512; 3771 3772 if (luminance_range->min_luminance) 3773 caps->aux_min_input_signal = luminance_range->min_luminance; 3774 else 3775 caps->aux_min_input_signal = 1; 3776 3777 panel_backlight_quirk = 3778 drm_get_panel_backlight_quirk(aconnector->drm_edid); 3779 if (!IS_ERR_OR_NULL(panel_backlight_quirk)) { 3780 if (panel_backlight_quirk->min_brightness) { 3781 caps->min_input_signal = 3782 panel_backlight_quirk->min_brightness - 1; 3783 drm_info(drm, 3784 "Applying panel backlight quirk, min_brightness: %d\n", 3785 caps->min_input_signal); 3786 } 3787 if (panel_backlight_quirk->brightness_mask) { 3788 drm_info(drm, 3789 "Applying panel backlight quirk, brightness_mask: 0x%X\n", 3790 panel_backlight_quirk->brightness_mask); 3791 caps->brightness_mask = 3792 panel_backlight_quirk->brightness_mask; 3793 } 3794 } 3795} 3796 3797DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) 3798 3799void amdgpu_dm_update_connector_after_detect( 3800 struct amdgpu_dm_connector *aconnector) 3801{ 3802 struct drm_connector *connector = &aconnector->base; 3803 struct dc_sink *sink __free(sink_release) = NULL; 3804 struct drm_device *dev = connector->dev; 3805 3806 /* MST handled by drm_mst framework */ 3807 if (aconnector->mst_mgr.mst_state == true) 3808 return; 3809 3810 sink = aconnector->dc_link->local_sink; 3811 if (sink) 3812 dc_sink_retain(sink); 3813 3814 /* 3815 * Edid mgmt connector gets first update only in mode_valid hook and then 3816 * the connector sink is set to either fake or physical sink depends on link status. 3817 * Skip if already done during boot. 3818 */ 3819 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3820 && aconnector->dc_em_sink) { 3821 3822 /* 3823 * For S3 resume with headless use eml_sink to fake stream 3824 * because on resume connector->sink is set to NULL 3825 */ 3826 guard(mutex)(&dev->mode_config.mutex); 3827 3828 if (sink) { 3829 if (aconnector->dc_sink) { 3830 amdgpu_dm_update_freesync_caps(connector, NULL); 3831 /* 3832 * retain and release below are used to 3833 * bump up refcount for sink because the link doesn't point 3834 * to it anymore after disconnect, so on next crtc to connector 3835 * reshuffle by UMD we will get into unwanted dc_sink release 3836 */ 3837 dc_sink_release(aconnector->dc_sink); 3838 } 3839 aconnector->dc_sink = sink; 3840 dc_sink_retain(aconnector->dc_sink); 3841 amdgpu_dm_update_freesync_caps(connector, 3842 aconnector->drm_edid); 3843 } else { 3844 amdgpu_dm_update_freesync_caps(connector, NULL); 3845 if (!aconnector->dc_sink) { 3846 aconnector->dc_sink = aconnector->dc_em_sink; 3847 dc_sink_retain(aconnector->dc_sink); 3848 } 3849 } 3850 3851 return; 3852 } 3853 3854 /* 3855 * TODO: temporary guard to look for proper fix 3856 * if this sink is MST sink, we should not do anything 3857 */ 3858 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 3859 return; 3860 3861 if (aconnector->dc_sink == sink) { 3862 /* 3863 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3864 * Do nothing!! 3865 */ 3866 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", 3867 aconnector->connector_id); 3868 return; 3869 } 3870 3871 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3872 aconnector->connector_id, aconnector->dc_sink, sink); 3873 3874 /* When polling, DRM has already locked the mutex for us. */ 3875 if (!drm_kms_helper_is_poll_worker()) 3876 mutex_lock(&dev->mode_config.mutex); 3877 3878 /* 3879 * 1. Update status of the drm connector 3880 * 2. Send an event and let userspace tell us what to do 3881 */ 3882 if (sink) { 3883 /* 3884 * TODO: check if we still need the S3 mode update workaround. 3885 * If yes, put it here. 3886 */ 3887 if (aconnector->dc_sink) { 3888 amdgpu_dm_update_freesync_caps(connector, NULL); 3889 dc_sink_release(aconnector->dc_sink); 3890 } 3891 3892 aconnector->dc_sink = sink; 3893 dc_sink_retain(aconnector->dc_sink); 3894 drm_edid_free(aconnector->drm_edid); 3895 aconnector->drm_edid = NULL; 3896 if (sink->dc_edid.length == 0) { 3897 hdmi_cec_unset_edid(aconnector); 3898 if (aconnector->dc_link->aux_mode) { 3899 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3900 } 3901 } else { 3902 const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; 3903 3904 aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); 3905 drm_edid_connector_update(connector, aconnector->drm_edid); 3906 3907 hdmi_cec_set_edid(aconnector); 3908 if (aconnector->dc_link->aux_mode) 3909 drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, 3910 connector->display_info.source_physical_address); 3911 } 3912 3913 if (!aconnector->timing_requested) { 3914 aconnector->timing_requested = 3915 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3916 if (!aconnector->timing_requested) 3917 drm_err(dev, 3918 "failed to create aconnector->requested_timing\n"); 3919 } 3920 3921 amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); 3922 update_connector_ext_caps(aconnector); 3923 } else { 3924 hdmi_cec_unset_edid(aconnector); 3925 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3926 amdgpu_dm_update_freesync_caps(connector, NULL); 3927 aconnector->num_modes = 0; 3928 dc_sink_release(aconnector->dc_sink); 3929 aconnector->dc_sink = NULL; 3930 drm_edid_free(aconnector->drm_edid); 3931 aconnector->drm_edid = NULL; 3932 kfree(aconnector->timing_requested); 3933 aconnector->timing_requested = NULL; 3934 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3935 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3936 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3937 } 3938 3939 update_subconnector_property(aconnector); 3940 3941 /* When polling, the mutex will be unlocked for us by DRM. */ 3942 if (!drm_kms_helper_is_poll_worker()) 3943 mutex_unlock(&dev->mode_config.mutex); 3944} 3945 3946static bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2) 3947{ 3948 if (!sink1 || !sink2) 3949 return false; 3950 if (sink1->sink_signal != sink2->sink_signal) 3951 return false; 3952 3953 if (sink1->dc_edid.length != sink2->dc_edid.length) 3954 return false; 3955 3956 if (memcmp(sink1->dc_edid.raw_edid, sink2->dc_edid.raw_edid, 3957 sink1->dc_edid.length) != 0) 3958 return false; 3959 return true; 3960} 3961 3962 3963/** 3964 * DOC: hdmi_hpd_debounce_work 3965 * 3966 * HDMI HPD debounce delay in milliseconds. When an HDMI display toggles HPD 3967 * (such as during power save transitions), this delay determines how long to 3968 * wait before processing the HPD event. This allows distinguishing between a 3969 * physical unplug (>hdmi_hpd_debounce_delay) 3970 * and a spontaneous RX HPD toggle (<hdmi_hpd_debounce_delay). 3971 * 3972 * If the toggle is less than this delay, the driver compares sink capabilities 3973 * and permits a hotplug event if they changed. 3974 * 3975 * The default value of 1500ms was chosen based on experimental testing with 3976 * various monitors that exhibit spontaneous HPD toggling behavior. 3977 */ 3978static void hdmi_hpd_debounce_work(struct work_struct *work) 3979{ 3980 struct amdgpu_dm_connector *aconnector = 3981 container_of(to_delayed_work(work), struct amdgpu_dm_connector, 3982 hdmi_hpd_debounce_work); 3983 struct drm_connector *connector = &aconnector->base; 3984 struct drm_device *dev = connector->dev; 3985 struct amdgpu_device *adev = drm_to_adev(dev); 3986 struct dc *dc = aconnector->dc_link->ctx->dc; 3987 bool fake_reconnect = false; 3988 bool reallow_idle = false; 3989 bool ret = false; 3990 guard(mutex)(&aconnector->hpd_lock); 3991 3992 /* Re-detect the display */ 3993 scoped_guard(mutex, &adev->dm.dc_lock) { 3994 if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) { 3995 dc_allow_idle_optimizations(dc, false); 3996 reallow_idle = true; 3997 } 3998 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3999 } 4000 4001 if (ret) { 4002 /* Apply workaround delay for certain panels */ 4003 apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 4004 /* Compare sinks to determine if this was a spontaneous HPD toggle */ 4005 if (are_sinks_equal(aconnector->dc_link->local_sink, aconnector->hdmi_prev_sink)) { 4006 /* 4007 * Sinks match - this was a spontaneous HDMI HPD toggle. 4008 */ 4009 drm_dbg_kms(dev, "HDMI HPD: Sink unchanged after debounce, internal re-enable\n"); 4010 fake_reconnect = true; 4011 } 4012 4013 /* Update connector state */ 4014 amdgpu_dm_update_connector_after_detect(aconnector); 4015 4016 drm_modeset_lock_all(dev); 4017 dm_restore_drm_connector_state(dev, connector); 4018 drm_modeset_unlock_all(dev); 4019 4020 /* Only notify OS if sink actually changed */ 4021 if (!fake_reconnect && aconnector->base.force == DRM_FORCE_UNSPECIFIED) 4022 drm_kms_helper_hotplug_event(dev); 4023 } 4024 4025 /* Release the cached sink reference */ 4026 if (aconnector->hdmi_prev_sink) { 4027 dc_sink_release(aconnector->hdmi_prev_sink); 4028 aconnector->hdmi_prev_sink = NULL; 4029 } 4030 4031 scoped_guard(mutex, &adev->dm.dc_lock) { 4032 if (reallow_idle && dc->caps.ips_support) 4033 dc_allow_idle_optimizations(dc, true); 4034 } 4035} 4036 4037static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 4038{ 4039 struct drm_connector *connector = &aconnector->base; 4040 struct drm_device *dev = connector->dev; 4041 enum dc_connection_type new_connection_type = dc_connection_none; 4042 struct amdgpu_device *adev = drm_to_adev(dev); 4043 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 4044 struct dc *dc = aconnector->dc_link->ctx->dc; 4045 bool ret = false; 4046 bool debounce_required = false; 4047 4048 if (adev->dm.disable_hpd_irq) 4049 return; 4050 4051 /* 4052 * In case of failure or MST no need to update connector status or notify the OS 4053 * since (for MST case) MST does this in its own context. 4054 */ 4055 guard(mutex)(&aconnector->hpd_lock); 4056 4057 if (adev->dm.hdcp_workqueue) { 4058 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 4059 dm_con_state->update_hdcp = true; 4060 } 4061 if (aconnector->fake_enable) 4062 aconnector->fake_enable = false; 4063 4064 aconnector->timing_changed = false; 4065 4066 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 4067 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 4068 4069 /* 4070 * Check for HDMI disconnect with debounce enabled. 4071 */ 4072 debounce_required = (aconnector->hdmi_hpd_debounce_delay_ms > 0 && 4073 dc_is_hdmi_signal(aconnector->dc_link->connector_signal) && 4074 new_connection_type == dc_connection_none && 4075 aconnector->dc_link->local_sink != NULL); 4076 4077 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4078 emulated_link_detect(aconnector->dc_link); 4079 4080 drm_modeset_lock_all(dev); 4081 dm_restore_drm_connector_state(dev, connector); 4082 drm_modeset_unlock_all(dev); 4083 4084 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 4085 drm_kms_helper_connector_hotplug_event(connector); 4086 } else if (debounce_required) { 4087 /* 4088 * HDMI disconnect detected - schedule delayed work instead of 4089 * processing immediately. This allows us to coalesce spurious 4090 * HDMI signals from physical unplugs. 4091 */ 4092 drm_dbg_kms(dev, "HDMI HPD: Disconnect detected, scheduling debounce work (%u ms)\n", 4093 aconnector->hdmi_hpd_debounce_delay_ms); 4094 4095 /* Cache the current sink for later comparison */ 4096 if (aconnector->hdmi_prev_sink) 4097 dc_sink_release(aconnector->hdmi_prev_sink); 4098 aconnector->hdmi_prev_sink = aconnector->dc_link->local_sink; 4099 if (aconnector->hdmi_prev_sink) 4100 dc_sink_retain(aconnector->hdmi_prev_sink); 4101 4102 /* Schedule delayed detection. */ 4103 if (mod_delayed_work(system_wq, 4104 &aconnector->hdmi_hpd_debounce_work, 4105 msecs_to_jiffies(aconnector->hdmi_hpd_debounce_delay_ms))) 4106 drm_dbg_kms(dev, "HDMI HPD: Re-scheduled debounce work\n"); 4107 4108 } else { 4109 4110 /* If the aconnector->hdmi_hpd_debounce_work is scheduled, exit early */ 4111 if (delayed_work_pending(&aconnector->hdmi_hpd_debounce_work)) 4112 return; 4113 4114 scoped_guard(mutex, &adev->dm.dc_lock) { 4115 dc_exit_ips_for_hw_access(dc); 4116 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 4117 } 4118 if (ret) { 4119 /* w/a delay for certain panels */ 4120 apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 4121 amdgpu_dm_update_connector_after_detect(aconnector); 4122 4123 drm_modeset_lock_all(dev); 4124 dm_restore_drm_connector_state(dev, connector); 4125 drm_modeset_unlock_all(dev); 4126 4127 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 4128 drm_kms_helper_connector_hotplug_event(connector); 4129 } 4130 } 4131} 4132 4133static void handle_hpd_irq(void *param) 4134{ 4135 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 4136 4137 handle_hpd_irq_helper(aconnector); 4138 4139} 4140 4141static void schedule_hpd_rx_offload_work(struct amdgpu_device *adev, struct hpd_rx_irq_offload_work_queue *offload_wq, 4142 union hpd_irq_data hpd_irq_data) 4143{ 4144 struct hpd_rx_irq_offload_work *offload_work = 4145 kzalloc(sizeof(*offload_work), GFP_KERNEL); 4146 4147 if (!offload_work) { 4148 drm_err(adev_to_drm(adev), "Failed to allocate hpd_rx_irq_offload_work.\n"); 4149 return; 4150 } 4151 4152 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 4153 offload_work->data = hpd_irq_data; 4154 offload_work->offload_wq = offload_wq; 4155 offload_work->adev = adev; 4156 4157 queue_work(offload_wq->wq, &offload_work->work); 4158 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 4159} 4160 4161static void handle_hpd_rx_irq(void *param) 4162{ 4163 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 4164 struct drm_connector *connector = &aconnector->base; 4165 struct drm_device *dev = connector->dev; 4166 struct dc_link *dc_link = aconnector->dc_link; 4167 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 4168 bool result = false; 4169 enum dc_connection_type new_connection_type = dc_connection_none; 4170 struct amdgpu_device *adev = drm_to_adev(dev); 4171 union hpd_irq_data hpd_irq_data; 4172 bool link_loss = false; 4173 bool has_left_work = false; 4174 int idx = dc_link->link_index; 4175 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 4176 struct dc *dc = aconnector->dc_link->ctx->dc; 4177 4178 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 4179 4180 if (adev->dm.disable_hpd_irq) 4181 return; 4182 4183 /* 4184 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 4185 * conflict, after implement i2c helper, this mutex should be 4186 * retired. 4187 */ 4188 mutex_lock(&aconnector->hpd_lock); 4189 4190 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 4191 &link_loss, true, &has_left_work); 4192 4193 if (!has_left_work) 4194 goto out; 4195 4196 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 4197 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data); 4198 goto out; 4199 } 4200 4201 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 4202 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 4203 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 4204 bool skip = false; 4205 4206 /* 4207 * DOWN_REP_MSG_RDY is also handled by polling method 4208 * mgr->cbs->poll_hpd_irq() 4209 */ 4210 spin_lock(&offload_wq->offload_lock); 4211 skip = offload_wq->is_handling_mst_msg_rdy_event; 4212 4213 if (!skip) 4214 offload_wq->is_handling_mst_msg_rdy_event = true; 4215 4216 spin_unlock(&offload_wq->offload_lock); 4217 4218 if (!skip) 4219 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data); 4220 4221 goto out; 4222 } 4223 4224 if (link_loss) { 4225 bool skip = false; 4226 4227 spin_lock(&offload_wq->offload_lock); 4228 skip = offload_wq->is_handling_link_loss; 4229 4230 if (!skip) 4231 offload_wq->is_handling_link_loss = true; 4232 4233 spin_unlock(&offload_wq->offload_lock); 4234 4235 if (!skip) 4236 schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data); 4237 4238 goto out; 4239 } 4240 } 4241 4242out: 4243 if (result && !is_mst_root_connector) { 4244 /* Downstream Port status changed. */ 4245 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 4246 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 4247 4248 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4249 emulated_link_detect(dc_link); 4250 4251 if (aconnector->fake_enable) 4252 aconnector->fake_enable = false; 4253 4254 amdgpu_dm_update_connector_after_detect(aconnector); 4255 4256 4257 drm_modeset_lock_all(dev); 4258 dm_restore_drm_connector_state(dev, connector); 4259 drm_modeset_unlock_all(dev); 4260 4261 drm_kms_helper_connector_hotplug_event(connector); 4262 } else { 4263 bool ret = false; 4264 4265 mutex_lock(&adev->dm.dc_lock); 4266 dc_exit_ips_for_hw_access(dc); 4267 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 4268 mutex_unlock(&adev->dm.dc_lock); 4269 4270 if (ret) { 4271 if (aconnector->fake_enable) 4272 aconnector->fake_enable = false; 4273 4274 amdgpu_dm_update_connector_after_detect(aconnector); 4275 4276 drm_modeset_lock_all(dev); 4277 dm_restore_drm_connector_state(dev, connector); 4278 drm_modeset_unlock_all(dev); 4279 4280 drm_kms_helper_connector_hotplug_event(connector); 4281 } 4282 } 4283 } 4284 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 4285 if (adev->dm.hdcp_workqueue) 4286 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 4287 } 4288 4289 if (dc_link->type != dc_connection_mst_branch) 4290 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 4291 4292 mutex_unlock(&aconnector->hpd_lock); 4293} 4294 4295static int register_hpd_handlers(struct amdgpu_device *adev) 4296{ 4297 struct drm_device *dev = adev_to_drm(adev); 4298 struct drm_connector *connector; 4299 struct amdgpu_dm_connector *aconnector; 4300 const struct dc_link *dc_link; 4301 struct dc_interrupt_params int_params = {0}; 4302 4303 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4304 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4305 4306 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 4307 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, 4308 dmub_hpd_callback, true)) { 4309 drm_err(adev_to_drm(adev), "fail to register dmub hpd callback"); 4310 return -EINVAL; 4311 } 4312 4313 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, 4314 dmub_hpd_callback, true)) { 4315 drm_err(adev_to_drm(adev), "fail to register dmub hpd callback"); 4316 return -EINVAL; 4317 } 4318 4319 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, 4320 dmub_hpd_sense_callback, true)) { 4321 drm_err(adev_to_drm(adev), "fail to register dmub hpd sense callback"); 4322 return -EINVAL; 4323 } 4324 } 4325 4326 list_for_each_entry(connector, 4327 &dev->mode_config.connector_list, head) { 4328 4329 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 4330 continue; 4331 4332 aconnector = to_amdgpu_dm_connector(connector); 4333 dc_link = aconnector->dc_link; 4334 4335 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 4336 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4337 int_params.irq_source = dc_link->irq_source_hpd; 4338 4339 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4340 int_params.irq_source < DC_IRQ_SOURCE_HPD1 || 4341 int_params.irq_source > DC_IRQ_SOURCE_HPD6) { 4342 drm_err(adev_to_drm(adev), "Failed to register hpd irq!\n"); 4343 return -EINVAL; 4344 } 4345 4346 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4347 handle_hpd_irq, (void *) aconnector)) 4348 return -ENOMEM; 4349 } 4350 4351 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 4352 4353 /* Also register for DP short pulse (hpd_rx). */ 4354 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4355 int_params.irq_source = dc_link->irq_source_hpd_rx; 4356 4357 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4358 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX || 4359 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) { 4360 drm_err(adev_to_drm(adev), "Failed to register hpd rx irq!\n"); 4361 return -EINVAL; 4362 } 4363 4364 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4365 handle_hpd_rx_irq, (void *) aconnector)) 4366 return -ENOMEM; 4367 } 4368 } 4369 return 0; 4370} 4371 4372#if defined(CONFIG_DRM_AMD_DC_SI) 4373/* Register IRQ sources and initialize IRQ callbacks */ 4374static int dce60_register_irq_handlers(struct amdgpu_device *adev) 4375{ 4376 struct dc *dc = adev->dm.dc; 4377 struct common_irq_params *c_irq_params; 4378 struct dc_interrupt_params int_params = {0}; 4379 int r; 4380 int i; 4381 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 4382 4383 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4384 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4385 4386 /* 4387 * Actions of amdgpu_irq_add_id(): 4388 * 1. Register a set() function with base driver. 4389 * Base driver will call set() function to enable/disable an 4390 * interrupt in DC hardware. 4391 * 2. Register amdgpu_dm_irq_handler(). 4392 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 4393 * coming from DC hardware. 4394 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 4395 * for acknowledging and handling. 4396 */ 4397 4398 /* Use VBLANK interrupt */ 4399 for (i = 0; i < adev->mode_info.num_crtc; i++) { 4400 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 4401 if (r) { 4402 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); 4403 return r; 4404 } 4405 4406 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4407 int_params.irq_source = 4408 dc_interrupt_to_irq_source(dc, i + 1, 0); 4409 4410 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4411 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 4412 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 4413 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n"); 4414 return -EINVAL; 4415 } 4416 4417 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 4418 4419 c_irq_params->adev = adev; 4420 c_irq_params->irq_src = int_params.irq_source; 4421 4422 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4423 dm_crtc_high_irq, c_irq_params)) 4424 return -ENOMEM; 4425 } 4426 4427 /* Use GRPH_PFLIP interrupt */ 4428 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 4429 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 4430 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 4431 if (r) { 4432 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n"); 4433 return r; 4434 } 4435 4436 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4437 int_params.irq_source = 4438 dc_interrupt_to_irq_source(dc, i, 0); 4439 4440 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4441 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4442 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4443 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n"); 4444 return -EINVAL; 4445 } 4446 4447 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4448 4449 c_irq_params->adev = adev; 4450 c_irq_params->irq_src = int_params.irq_source; 4451 4452 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4453 dm_pflip_high_irq, c_irq_params)) 4454 return -ENOMEM; 4455 } 4456 4457 /* HPD */ 4458 r = amdgpu_irq_add_id(adev, client_id, 4459 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 4460 if (r) { 4461 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n"); 4462 return r; 4463 } 4464 4465 r = register_hpd_handlers(adev); 4466 4467 return r; 4468} 4469#endif 4470 4471/* Register IRQ sources and initialize IRQ callbacks */ 4472static int dce110_register_irq_handlers(struct amdgpu_device *adev) 4473{ 4474 struct dc *dc = adev->dm.dc; 4475 struct common_irq_params *c_irq_params; 4476 struct dc_interrupt_params int_params = {0}; 4477 int r; 4478 int i; 4479 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 4480 4481 if (adev->family >= AMDGPU_FAMILY_AI) 4482 client_id = SOC15_IH_CLIENTID_DCE; 4483 4484 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4485 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4486 4487 /* 4488 * Actions of amdgpu_irq_add_id(): 4489 * 1. Register a set() function with base driver. 4490 * Base driver will call set() function to enable/disable an 4491 * interrupt in DC hardware. 4492 * 2. Register amdgpu_dm_irq_handler(). 4493 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 4494 * coming from DC hardware. 4495 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 4496 * for acknowledging and handling. 4497 */ 4498 4499 /* Use VBLANK interrupt */ 4500 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 4501 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 4502 if (r) { 4503 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); 4504 return r; 4505 } 4506 4507 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4508 int_params.irq_source = 4509 dc_interrupt_to_irq_source(dc, i, 0); 4510 4511 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4512 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 4513 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 4514 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n"); 4515 return -EINVAL; 4516 } 4517 4518 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 4519 4520 c_irq_params->adev = adev; 4521 c_irq_params->irq_src = int_params.irq_source; 4522 4523 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4524 dm_crtc_high_irq, c_irq_params)) 4525 return -ENOMEM; 4526 } 4527 4528 /* Use VUPDATE interrupt */ 4529 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 4530 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 4531 if (r) { 4532 drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); 4533 return r; 4534 } 4535 4536 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4537 int_params.irq_source = 4538 dc_interrupt_to_irq_source(dc, i, 0); 4539 4540 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4541 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 4542 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 4543 drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); 4544 return -EINVAL; 4545 } 4546 4547 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 4548 4549 c_irq_params->adev = adev; 4550 c_irq_params->irq_src = int_params.irq_source; 4551 4552 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4553 dm_vupdate_high_irq, c_irq_params)) 4554 return -ENOMEM; 4555 } 4556 4557 /* Use GRPH_PFLIP interrupt */ 4558 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 4559 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 4560 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 4561 if (r) { 4562 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n"); 4563 return r; 4564 } 4565 4566 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4567 int_params.irq_source = 4568 dc_interrupt_to_irq_source(dc, i, 0); 4569 4570 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4571 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4572 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4573 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n"); 4574 return -EINVAL; 4575 } 4576 4577 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4578 4579 c_irq_params->adev = adev; 4580 c_irq_params->irq_src = int_params.irq_source; 4581 4582 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4583 dm_pflip_high_irq, c_irq_params)) 4584 return -ENOMEM; 4585 } 4586 4587 /* HPD */ 4588 r = amdgpu_irq_add_id(adev, client_id, 4589 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 4590 if (r) { 4591 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n"); 4592 return r; 4593 } 4594 4595 r = register_hpd_handlers(adev); 4596 4597 return r; 4598} 4599 4600/* Register IRQ sources and initialize IRQ callbacks */ 4601static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 4602{ 4603 struct dc *dc = adev->dm.dc; 4604 struct common_irq_params *c_irq_params; 4605 struct dc_interrupt_params int_params = {0}; 4606 int r; 4607 int i; 4608#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4609 static const unsigned int vrtl_int_srcid[] = { 4610 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 4611 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 4612 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 4613 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 4614 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 4615 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 4616 }; 4617#endif 4618 4619 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4620 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4621 4622 /* 4623 * Actions of amdgpu_irq_add_id(): 4624 * 1. Register a set() function with base driver. 4625 * Base driver will call set() function to enable/disable an 4626 * interrupt in DC hardware. 4627 * 2. Register amdgpu_dm_irq_handler(). 4628 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 4629 * coming from DC hardware. 4630 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 4631 * for acknowledging and handling. 4632 */ 4633 4634 /* Use VSTARTUP interrupt */ 4635 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 4636 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 4637 i++) { 4638 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 4639 4640 if (r) { 4641 drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); 4642 return r; 4643 } 4644 4645 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4646 int_params.irq_source = 4647 dc_interrupt_to_irq_source(dc, i, 0); 4648 4649 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4650 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 4651 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 4652 drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n"); 4653 return -EINVAL; 4654 } 4655 4656 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 4657 4658 c_irq_params->adev = adev; 4659 c_irq_params->irq_src = int_params.irq_source; 4660 4661 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4662 dm_crtc_high_irq, c_irq_params)) 4663 return -ENOMEM; 4664 } 4665 4666 /* Use otg vertical line interrupt */ 4667#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4668 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 4669 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 4670 vrtl_int_srcid[i], &adev->vline0_irq); 4671 4672 if (r) { 4673 drm_err(adev_to_drm(adev), "Failed to add vline0 irq id!\n"); 4674 return r; 4675 } 4676 4677 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4678 int_params.irq_source = 4679 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 4680 4681 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4682 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 || 4683 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) { 4684 drm_err(adev_to_drm(adev), "Failed to register vline0 irq!\n"); 4685 return -EINVAL; 4686 } 4687 4688 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 4689 - DC_IRQ_SOURCE_DC1_VLINE0]; 4690 4691 c_irq_params->adev = adev; 4692 c_irq_params->irq_src = int_params.irq_source; 4693 4694 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4695 dm_dcn_vertical_interrupt0_high_irq, 4696 c_irq_params)) 4697 return -ENOMEM; 4698 } 4699#endif 4700 4701 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 4702 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 4703 * to trigger at end of each vblank, regardless of state of the lock, 4704 * matching DCE behaviour. 4705 */ 4706 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 4707 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 4708 i++) { 4709 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 4710 4711 if (r) { 4712 drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); 4713 return r; 4714 } 4715 4716 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4717 int_params.irq_source = 4718 dc_interrupt_to_irq_source(dc, i, 0); 4719 4720 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4721 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 4722 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 4723 drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); 4724 return -EINVAL; 4725 } 4726 4727 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 4728 4729 c_irq_params->adev = adev; 4730 c_irq_params->irq_src = int_params.irq_source; 4731 4732 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4733 dm_vupdate_high_irq, c_irq_params)) 4734 return -ENOMEM; 4735 } 4736 4737 /* Use GRPH_PFLIP interrupt */ 4738 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 4739 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 4740 i++) { 4741 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 4742 if (r) { 4743 drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n"); 4744 return r; 4745 } 4746 4747 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4748 int_params.irq_source = 4749 dc_interrupt_to_irq_source(dc, i, 0); 4750 4751 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4752 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4753 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4754 drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n"); 4755 return -EINVAL; 4756 } 4757 4758 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4759 4760 c_irq_params->adev = adev; 4761 c_irq_params->irq_src = int_params.irq_source; 4762 4763 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4764 dm_pflip_high_irq, c_irq_params)) 4765 return -ENOMEM; 4766 } 4767 4768 /* HPD */ 4769 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 4770 &adev->hpd_irq); 4771 if (r) { 4772 drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n"); 4773 return r; 4774 } 4775 4776 r = register_hpd_handlers(adev); 4777 4778 return r; 4779} 4780/* Register Outbox IRQ sources and initialize IRQ callbacks */ 4781static int register_outbox_irq_handlers(struct amdgpu_device *adev) 4782{ 4783 struct dc *dc = adev->dm.dc; 4784 struct common_irq_params *c_irq_params; 4785 struct dc_interrupt_params int_params = {0}; 4786 int r, i; 4787 4788 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4789 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4790 4791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 4792 &adev->dmub_outbox_irq); 4793 if (r) { 4794 drm_err(adev_to_drm(adev), "Failed to add outbox irq id!\n"); 4795 return r; 4796 } 4797 4798 if (dc->ctx->dmub_srv) { 4799 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 4800 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4801 int_params.irq_source = 4802 dc_interrupt_to_irq_source(dc, i, 0); 4803 4804 c_irq_params = &adev->dm.dmub_outbox_params[0]; 4805 4806 c_irq_params->adev = adev; 4807 c_irq_params->irq_src = int_params.irq_source; 4808 4809 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4810 dm_dmub_outbox1_low_irq, c_irq_params)) 4811 return -ENOMEM; 4812 } 4813 4814 return 0; 4815} 4816 4817/* 4818 * Acquires the lock for the atomic state object and returns 4819 * the new atomic state. 4820 * 4821 * This should only be called during atomic check. 4822 */ 4823int dm_atomic_get_state(struct drm_atomic_state *state, 4824 struct dm_atomic_state **dm_state) 4825{ 4826 struct drm_device *dev = state->dev; 4827 struct amdgpu_device *adev = drm_to_adev(dev); 4828 struct amdgpu_display_manager *dm = &adev->dm; 4829 struct drm_private_state *priv_state; 4830 4831 if (*dm_state) 4832 return 0; 4833 4834 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 4835 if (IS_ERR(priv_state)) 4836 return PTR_ERR(priv_state); 4837 4838 *dm_state = to_dm_atomic_state(priv_state); 4839 4840 return 0; 4841} 4842 4843static struct dm_atomic_state * 4844dm_atomic_get_new_state(struct drm_atomic_state *state) 4845{ 4846 struct drm_device *dev = state->dev; 4847 struct amdgpu_device *adev = drm_to_adev(dev); 4848 struct amdgpu_display_manager *dm = &adev->dm; 4849 struct drm_private_obj *obj; 4850 struct drm_private_state *new_obj_state; 4851 int i; 4852 4853 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 4854 if (obj->funcs == dm->atomic_obj.funcs) 4855 return to_dm_atomic_state(new_obj_state); 4856 } 4857 4858 return NULL; 4859} 4860 4861static struct drm_private_state * 4862dm_atomic_duplicate_state(struct drm_private_obj *obj) 4863{ 4864 struct dm_atomic_state *old_state, *new_state; 4865 4866 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 4867 if (!new_state) 4868 return NULL; 4869 4870 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 4871 4872 old_state = to_dm_atomic_state(obj->state); 4873 4874 if (old_state && old_state->context) 4875 new_state->context = dc_state_create_copy(old_state->context); 4876 4877 if (!new_state->context) { 4878 kfree(new_state); 4879 return NULL; 4880 } 4881 4882 return &new_state->base; 4883} 4884 4885static void dm_atomic_destroy_state(struct drm_private_obj *obj, 4886 struct drm_private_state *state) 4887{ 4888 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4889 4890 if (dm_state && dm_state->context) 4891 dc_state_release(dm_state->context); 4892 4893 kfree(dm_state); 4894} 4895 4896static struct drm_private_state_funcs dm_atomic_state_funcs = { 4897 .atomic_duplicate_state = dm_atomic_duplicate_state, 4898 .atomic_destroy_state = dm_atomic_destroy_state, 4899}; 4900 4901static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 4902{ 4903 struct dm_atomic_state *state; 4904 int r; 4905 4906 adev->mode_info.mode_config_initialized = true; 4907 4908 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 4909 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 4910 4911 adev_to_drm(adev)->mode_config.max_width = 16384; 4912 adev_to_drm(adev)->mode_config.max_height = 16384; 4913 4914 adev_to_drm(adev)->mode_config.preferred_depth = 24; 4915 if (adev->asic_type == CHIP_HAWAII) 4916 /* disable prefer shadow for now due to hibernation issues */ 4917 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 4918 else 4919 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4920 /* indicates support for immediate flip */ 4921 adev_to_drm(adev)->mode_config.async_page_flip = true; 4922 4923 state = kzalloc(sizeof(*state), GFP_KERNEL); 4924 if (!state) 4925 return -ENOMEM; 4926 4927 state->context = dc_state_create_current_copy(adev->dm.dc); 4928 if (!state->context) { 4929 kfree(state); 4930 return -ENOMEM; 4931 } 4932 4933 drm_atomic_private_obj_init(adev_to_drm(adev), 4934 &adev->dm.atomic_obj, 4935 &state->base, 4936 &dm_atomic_state_funcs); 4937 4938 r = amdgpu_display_modeset_create_props(adev); 4939 if (r) { 4940 dc_state_release(state->context); 4941 kfree(state); 4942 return r; 4943 } 4944 4945#ifdef AMD_PRIVATE_COLOR 4946 if (amdgpu_dm_create_color_properties(adev)) { 4947 dc_state_release(state->context); 4948 kfree(state); 4949 return -ENOMEM; 4950 } 4951#endif 4952 4953 r = amdgpu_dm_audio_init(adev); 4954 if (r) { 4955 dc_state_release(state->context); 4956 kfree(state); 4957 return r; 4958 } 4959 4960 return 0; 4961} 4962 4963#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4964#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4965#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) 4966#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4967 4968static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4969 int bl_idx) 4970{ 4971 struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx]; 4972 4973 if (caps->caps_valid) 4974 return; 4975 4976#if defined(CONFIG_ACPI) 4977 amdgpu_acpi_get_backlight_caps(caps); 4978 4979 /* validate the firmware value is sane */ 4980 if (caps->caps_valid) { 4981 int spread = caps->max_input_signal - caps->min_input_signal; 4982 4983 if (caps->max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || 4984 caps->min_input_signal < 0 || 4985 spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || 4986 spread < AMDGPU_DM_MIN_SPREAD) { 4987 DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", 4988 caps->min_input_signal, caps->max_input_signal); 4989 caps->caps_valid = false; 4990 } 4991 } 4992 4993 if (!caps->caps_valid) { 4994 caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4995 caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4996 caps->caps_valid = true; 4997 } 4998#else 4999 if (caps->aux_support) 5000 return; 5001 5002 caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 5003 caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 5004 caps->caps_valid = true; 5005#endif 5006} 5007 5008static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 5009 unsigned int *min, unsigned int *max) 5010{ 5011 if (!caps) 5012 return 0; 5013 5014 if (caps->aux_support) { 5015 // Firmware limits are in nits, DC API wants millinits. 5016 *max = 1000 * caps->aux_max_input_signal; 5017 *min = 1000 * caps->aux_min_input_signal; 5018 } else { 5019 // Firmware limits are 8-bit, PWM control is 16-bit. 5020 *max = 0x101 * caps->max_input_signal; 5021 *min = 0x101 * caps->min_input_signal; 5022 } 5023 return 1; 5024} 5025 5026/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */ 5027static inline u32 scale_input_to_fw(int min, int max, u64 input) 5028{ 5029 return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min); 5030} 5031 5032/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */ 5033static inline u32 scale_fw_to_input(int min, int max, u64 input) 5034{ 5035 return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL); 5036} 5037 5038static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps, 5039 unsigned int min, unsigned int max, 5040 uint32_t *user_brightness) 5041{ 5042 u32 brightness = scale_input_to_fw(min, max, *user_brightness); 5043 u8 lower_signal, upper_signal, upper_lum, lower_lum, lum; 5044 int left, right; 5045 5046 if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE) 5047 return; 5048 5049 if (!caps->data_points) 5050 return; 5051 5052 /* 5053 * Handle the case where brightness is below the first data point 5054 * Interpolate between (0,0) and (first_signal, first_lum) 5055 */ 5056 if (brightness < caps->luminance_data[0].input_signal) { 5057 lum = DIV_ROUND_CLOSEST(caps->luminance_data[0].luminance * brightness, 5058 caps->luminance_data[0].input_signal); 5059 goto scale; 5060 } 5061 5062 left = 0; 5063 right = caps->data_points - 1; 5064 while (left <= right) { 5065 int mid = left + (right - left) / 2; 5066 u8 signal = caps->luminance_data[mid].input_signal; 5067 5068 /* Exact match found */ 5069 if (signal == brightness) { 5070 lum = caps->luminance_data[mid].luminance; 5071 goto scale; 5072 } 5073 5074 if (signal < brightness) 5075 left = mid + 1; 5076 else 5077 right = mid - 1; 5078 } 5079 5080 /* verify bound */ 5081 if (left >= caps->data_points) 5082 left = caps->data_points - 1; 5083 5084 /* At this point, left > right */ 5085 lower_signal = caps->luminance_data[right].input_signal; 5086 upper_signal = caps->luminance_data[left].input_signal; 5087 lower_lum = caps->luminance_data[right].luminance; 5088 upper_lum = caps->luminance_data[left].luminance; 5089 5090 /* interpolate */ 5091 if (right == left || !lower_lum) 5092 lum = upper_lum; 5093 else 5094 lum = lower_lum + DIV_ROUND_CLOSEST((upper_lum - lower_lum) * 5095 (brightness - lower_signal), 5096 upper_signal - lower_signal); 5097scale: 5098 *user_brightness = scale_fw_to_input(min, max, 5099 DIV_ROUND_CLOSEST(lum * brightness, 101)); 5100} 5101 5102static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 5103 uint32_t brightness) 5104{ 5105 unsigned int min, max; 5106 5107 if (!get_brightness_range(caps, &min, &max)) 5108 return brightness; 5109 5110 convert_custom_brightness(caps, min, max, &brightness); 5111 5112 // Rescale 0..max to min..max 5113 return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max); 5114} 5115 5116static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 5117 uint32_t brightness) 5118{ 5119 unsigned int min, max; 5120 5121 if (!get_brightness_range(caps, &min, &max)) 5122 return brightness; 5123 5124 if (brightness < min) 5125 return 0; 5126 // Rescale min..max to 0..max 5127 return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min), 5128 max - min); 5129} 5130 5131static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 5132 int bl_idx, 5133 u32 user_brightness) 5134{ 5135 struct amdgpu_dm_backlight_caps *caps; 5136 struct dc_link *link; 5137 u32 brightness; 5138 bool rc, reallow_idle = false; 5139 struct drm_connector *connector; 5140 5141 list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) { 5142 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5143 5144 if (aconnector->bl_idx != bl_idx) 5145 continue; 5146 5147 /* if connector is off, save the brightness for next time it's on */ 5148 if (!aconnector->base.encoder) { 5149 dm->brightness[bl_idx] = user_brightness; 5150 dm->actual_brightness[bl_idx] = 0; 5151 return; 5152 } 5153 } 5154 5155 amdgpu_dm_update_backlight_caps(dm, bl_idx); 5156 caps = &dm->backlight_caps[bl_idx]; 5157 5158 dm->brightness[bl_idx] = user_brightness; 5159 /* update scratch register */ 5160 if (bl_idx == 0) 5161 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 5162 brightness = convert_brightness_from_user(caps, dm->brightness[bl_idx]); 5163 link = (struct dc_link *)dm->backlight_link[bl_idx]; 5164 5165 /* Apply brightness quirk */ 5166 if (caps->brightness_mask) 5167 brightness |= caps->brightness_mask; 5168 5169 /* Change brightness based on AUX property */ 5170 mutex_lock(&dm->dc_lock); 5171 if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { 5172 dc_allow_idle_optimizations(dm->dc, false); 5173 reallow_idle = true; 5174 } 5175 5176 if (trace_amdgpu_dm_brightness_enabled()) { 5177 trace_amdgpu_dm_brightness(__builtin_return_address(0), 5178 user_brightness, 5179 brightness, 5180 caps->aux_support, 5181 power_supply_is_system_supplied() > 0); 5182 } 5183 5184 if (caps->aux_support) { 5185 rc = dc_link_set_backlight_level_nits(link, true, brightness, 5186 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 5187 if (!rc) 5188 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 5189 } else { 5190 struct set_backlight_level_params backlight_level_params = { 0 }; 5191 5192 backlight_level_params.backlight_pwm_u16_16 = brightness; 5193 backlight_level_params.transition_time_in_ms = 0; 5194 5195 rc = dc_link_set_backlight_level(link, &backlight_level_params); 5196 if (!rc) 5197 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 5198 } 5199 5200 if (dm->dc->caps.ips_support && reallow_idle) 5201 dc_allow_idle_optimizations(dm->dc, true); 5202 5203 mutex_unlock(&dm->dc_lock); 5204 5205 if (rc) 5206 dm->actual_brightness[bl_idx] = user_brightness; 5207} 5208 5209static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 5210{ 5211 struct amdgpu_display_manager *dm = bl_get_data(bd); 5212 int i; 5213 5214 for (i = 0; i < dm->num_of_edps; i++) { 5215 if (bd == dm->backlight_dev[i]) 5216 break; 5217 } 5218 if (i >= AMDGPU_DM_MAX_NUM_EDP) 5219 i = 0; 5220 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 5221 5222 return 0; 5223} 5224 5225static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 5226 int bl_idx) 5227{ 5228 int ret; 5229 struct amdgpu_dm_backlight_caps caps; 5230 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 5231 5232 amdgpu_dm_update_backlight_caps(dm, bl_idx); 5233 caps = dm->backlight_caps[bl_idx]; 5234 5235 if (caps.aux_support) { 5236 u32 avg, peak; 5237 5238 if (!dc_link_get_backlight_level_nits(link, &avg, &peak)) 5239 return dm->brightness[bl_idx]; 5240 return convert_brightness_to_user(&caps, avg); 5241 } 5242 5243 ret = dc_link_get_backlight_level(link); 5244 5245 if (ret == DC_ERROR_UNEXPECTED) 5246 return dm->brightness[bl_idx]; 5247 5248 return convert_brightness_to_user(&caps, ret); 5249} 5250 5251static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 5252{ 5253 struct amdgpu_display_manager *dm = bl_get_data(bd); 5254 int i; 5255 5256 for (i = 0; i < dm->num_of_edps; i++) { 5257 if (bd == dm->backlight_dev[i]) 5258 break; 5259 } 5260 if (i >= AMDGPU_DM_MAX_NUM_EDP) 5261 i = 0; 5262 return amdgpu_dm_backlight_get_level(dm, i); 5263} 5264 5265static const struct backlight_ops amdgpu_dm_backlight_ops = { 5266 .options = BL_CORE_SUSPENDRESUME, 5267 .get_brightness = amdgpu_dm_backlight_get_brightness, 5268 .update_status = amdgpu_dm_backlight_update_status, 5269}; 5270 5271static void 5272amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 5273{ 5274 struct drm_device *drm = aconnector->base.dev; 5275 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 5276 struct backlight_properties props = { 0 }; 5277 struct amdgpu_dm_backlight_caps *caps; 5278 char bl_name[16]; 5279 int min, max; 5280 int real_brightness; 5281 int init_brightness; 5282 5283 if (aconnector->bl_idx == -1) 5284 return; 5285 5286 if (!acpi_video_backlight_use_native()) { 5287 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 5288 /* Try registering an ACPI video backlight device instead. */ 5289 acpi_video_register_backlight(); 5290 return; 5291 } 5292 5293 caps = &dm->backlight_caps[aconnector->bl_idx]; 5294 if (get_brightness_range(caps, &min, &max)) { 5295 if (power_supply_is_system_supplied() > 0) 5296 props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->ac_level, 100); 5297 else 5298 props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->dc_level, 100); 5299 /* min is zero, so max needs to be adjusted */ 5300 props.max_brightness = max - min; 5301 drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max, 5302 caps->ac_level, caps->dc_level); 5303 } else 5304 props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL; 5305 5306 init_brightness = props.brightness; 5307 5308 if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) { 5309 drm_info(drm, "Using custom brightness curve\n"); 5310 props.scale = BACKLIGHT_SCALE_NON_LINEAR; 5311 } else 5312 props.scale = BACKLIGHT_SCALE_LINEAR; 5313 props.type = BACKLIGHT_RAW; 5314 5315 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 5316 drm->primary->index + aconnector->bl_idx); 5317 5318 dm->backlight_dev[aconnector->bl_idx] = 5319 backlight_device_register(bl_name, aconnector->base.kdev, dm, 5320 &amdgpu_dm_backlight_ops, &props); 5321 dm->brightness[aconnector->bl_idx] = props.brightness; 5322 5323 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 5324 drm_err(drm, "DM: Backlight registration failed!\n"); 5325 dm->backlight_dev[aconnector->bl_idx] = NULL; 5326 } else { 5327 /* 5328 * dm->brightness[x] can be inconsistent just after startup until 5329 * ops.get_brightness is called. 5330 */ 5331 real_brightness = 5332 amdgpu_dm_backlight_ops.get_brightness(dm->backlight_dev[aconnector->bl_idx]); 5333 5334 if (real_brightness != init_brightness) { 5335 dm->actual_brightness[aconnector->bl_idx] = real_brightness; 5336 dm->brightness[aconnector->bl_idx] = real_brightness; 5337 } 5338 drm_dbg_driver(drm, "DM: Registered Backlight device: %s\n", bl_name); 5339 } 5340} 5341 5342static int initialize_plane(struct amdgpu_display_manager *dm, 5343 struct amdgpu_mode_info *mode_info, int plane_id, 5344 enum drm_plane_type plane_type, 5345 const struct dc_plane_cap *plane_cap) 5346{ 5347 struct drm_plane *plane; 5348 unsigned long possible_crtcs; 5349 int ret = 0; 5350 5351 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 5352 if (!plane) { 5353 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 5354 return -ENOMEM; 5355 } 5356 plane->type = plane_type; 5357 5358 /* 5359 * HACK: IGT tests expect that the primary plane for a CRTC 5360 * can only have one possible CRTC. Only expose support for 5361 * any CRTC if they're not going to be used as a primary plane 5362 * for a CRTC - like overlay or underlay planes. 5363 */ 5364 possible_crtcs = 1 << plane_id; 5365 if (plane_id >= dm->dc->caps.max_streams) 5366 possible_crtcs = 0xff; 5367 5368 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 5369 5370 if (ret) { 5371 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 5372 kfree(plane); 5373 return ret; 5374 } 5375 5376 if (mode_info) 5377 mode_info->planes[plane_id] = plane; 5378 5379 return ret; 5380} 5381 5382 5383static void setup_backlight_device(struct amdgpu_display_manager *dm, 5384 struct amdgpu_dm_connector *aconnector) 5385{ 5386 struct amdgpu_dm_backlight_caps *caps; 5387 struct dc_link *link = aconnector->dc_link; 5388 int bl_idx = dm->num_of_edps; 5389 5390 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 5391 link->type == dc_connection_none) 5392 return; 5393 5394 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 5395 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 5396 return; 5397 } 5398 5399 aconnector->bl_idx = bl_idx; 5400 5401 amdgpu_dm_update_backlight_caps(dm, bl_idx); 5402 dm->backlight_link[bl_idx] = link; 5403 dm->num_of_edps++; 5404 5405 update_connector_ext_caps(aconnector); 5406 caps = &dm->backlight_caps[aconnector->bl_idx]; 5407 5408 /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ 5409 if (caps->ext_caps && !caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) 5410 drm_object_attach_property(&aconnector->base.base, 5411 dm->adev->mode_info.abm_level_property, 5412 ABM_SYSFS_CONTROL); 5413} 5414 5415static void amdgpu_set_panel_orientation(struct drm_connector *connector); 5416 5417/* 5418 * In this architecture, the association 5419 * connector -> encoder -> crtc 5420 * id not really requried. The crtc and connector will hold the 5421 * display_index as an abstraction to use with DAL component 5422 * 5423 * Returns 0 on success 5424 */ 5425static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 5426{ 5427 struct amdgpu_display_manager *dm = &adev->dm; 5428 s32 i; 5429 struct amdgpu_dm_connector *aconnector = NULL; 5430 struct amdgpu_encoder *aencoder = NULL; 5431 struct amdgpu_mode_info *mode_info = &adev->mode_info; 5432 u32 link_cnt; 5433 s32 primary_planes; 5434 enum dc_connection_type new_connection_type = dc_connection_none; 5435 const struct dc_plane_cap *plane; 5436 bool psr_feature_enabled = false; 5437 bool replay_feature_enabled = false; 5438 int max_overlay = dm->dc->caps.max_slave_planes; 5439 5440 dm->display_indexes_num = dm->dc->caps.max_streams; 5441 /* Update the actual used number of crtc */ 5442 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 5443 5444 amdgpu_dm_set_irq_funcs(adev); 5445 5446 link_cnt = dm->dc->caps.max_links; 5447 if (amdgpu_dm_mode_config_init(dm->adev)) { 5448 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 5449 return -EINVAL; 5450 } 5451 5452 /* There is one primary plane per CRTC */ 5453 primary_planes = dm->dc->caps.max_streams; 5454 if (primary_planes > AMDGPU_MAX_PLANES) { 5455 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 5456 return -EINVAL; 5457 } 5458 5459 /* 5460 * Initialize primary planes, implicit planes for legacy IOCTLS. 5461 * Order is reversed to match iteration order in atomic check. 5462 */ 5463 for (i = (primary_planes - 1); i >= 0; i--) { 5464 plane = &dm->dc->caps.planes[i]; 5465 5466 if (initialize_plane(dm, mode_info, i, 5467 DRM_PLANE_TYPE_PRIMARY, plane)) { 5468 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 5469 goto fail; 5470 } 5471 } 5472 5473 /* 5474 * Initialize overlay planes, index starting after primary planes. 5475 * These planes have a higher DRM index than the primary planes since 5476 * they should be considered as having a higher z-order. 5477 * Order is reversed to match iteration order in atomic check. 5478 * 5479 * Only support DCN for now, and only expose one so we don't encourage 5480 * userspace to use up all the pipes. 5481 */ 5482 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 5483 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 5484 5485 /* Do not create overlay if MPO disabled */ 5486 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 5487 break; 5488 5489 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 5490 continue; 5491 5492 if (!plane->pixel_format_support.argb8888) 5493 continue; 5494 5495 if (max_overlay-- == 0) 5496 break; 5497 5498 if (initialize_plane(dm, NULL, primary_planes + i, 5499 DRM_PLANE_TYPE_OVERLAY, plane)) { 5500 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 5501 goto fail; 5502 } 5503 } 5504 5505 for (i = 0; i < dm->dc->caps.max_streams; i++) 5506 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 5507 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 5508 goto fail; 5509 } 5510 5511 /* Use Outbox interrupt */ 5512 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5513 case IP_VERSION(3, 0, 0): 5514 case IP_VERSION(3, 1, 2): 5515 case IP_VERSION(3, 1, 3): 5516 case IP_VERSION(3, 1, 4): 5517 case IP_VERSION(3, 1, 5): 5518 case IP_VERSION(3, 1, 6): 5519 case IP_VERSION(3, 2, 0): 5520 case IP_VERSION(3, 2, 1): 5521 case IP_VERSION(2, 1, 0): 5522 case IP_VERSION(3, 5, 0): 5523 case IP_VERSION(3, 5, 1): 5524 case IP_VERSION(3, 6, 0): 5525 case IP_VERSION(4, 0, 1): 5526 if (register_outbox_irq_handlers(dm->adev)) { 5527 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5528 goto fail; 5529 } 5530 break; 5531 default: 5532 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 5533 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5534 } 5535 5536 /* Determine whether to enable PSR support by default. */ 5537 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 5538 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5539 case IP_VERSION(3, 1, 2): 5540 case IP_VERSION(3, 1, 3): 5541 case IP_VERSION(3, 1, 4): 5542 case IP_VERSION(3, 1, 5): 5543 case IP_VERSION(3, 1, 6): 5544 case IP_VERSION(3, 2, 0): 5545 case IP_VERSION(3, 2, 1): 5546 case IP_VERSION(3, 5, 0): 5547 case IP_VERSION(3, 5, 1): 5548 case IP_VERSION(3, 6, 0): 5549 case IP_VERSION(4, 0, 1): 5550 psr_feature_enabled = true; 5551 break; 5552 default: 5553 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 5554 break; 5555 } 5556 } 5557 5558 /* Determine whether to enable Replay support by default. */ 5559 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 5560 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5561 case IP_VERSION(3, 1, 4): 5562 case IP_VERSION(3, 2, 0): 5563 case IP_VERSION(3, 2, 1): 5564 case IP_VERSION(3, 5, 0): 5565 case IP_VERSION(3, 5, 1): 5566 case IP_VERSION(3, 6, 0): 5567 replay_feature_enabled = true; 5568 break; 5569 5570 default: 5571 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 5572 break; 5573 } 5574 } 5575 5576 if (link_cnt > MAX_LINKS) { 5577 drm_err(adev_to_drm(adev), 5578 "KMS: Cannot support more than %d display indexes\n", 5579 MAX_LINKS); 5580 goto fail; 5581 } 5582 5583 /* loops over all connectors on the board */ 5584 for (i = 0; i < link_cnt; i++) { 5585 struct dc_link *link = NULL; 5586 5587 link = dc_get_link_at_index(dm->dc, i); 5588 5589 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 5590 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); 5591 5592 if (!wbcon) { 5593 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 5594 continue; 5595 } 5596 5597 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 5598 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 5599 kfree(wbcon); 5600 continue; 5601 } 5602 5603 link->psr_settings.psr_feature_enabled = false; 5604 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 5605 5606 continue; 5607 } 5608 5609 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 5610 if (!aconnector) 5611 goto fail; 5612 5613 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 5614 if (!aencoder) 5615 goto fail; 5616 5617 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 5618 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 5619 goto fail; 5620 } 5621 5622 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 5623 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 5624 goto fail; 5625 } 5626 5627 if (dm->hpd_rx_offload_wq) 5628 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 5629 aconnector; 5630 5631 if (!dc_link_detect_connection_type(link, &new_connection_type)) 5632 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 5633 5634 if (aconnector->base.force && new_connection_type == dc_connection_none) { 5635 emulated_link_detect(link); 5636 amdgpu_dm_update_connector_after_detect(aconnector); 5637 } else { 5638 bool ret = false; 5639 5640 mutex_lock(&dm->dc_lock); 5641 dc_exit_ips_for_hw_access(dm->dc); 5642 ret = dc_link_detect(link, DETECT_REASON_BOOT); 5643 mutex_unlock(&dm->dc_lock); 5644 5645 if (ret) { 5646 amdgpu_dm_update_connector_after_detect(aconnector); 5647 setup_backlight_device(dm, aconnector); 5648 5649 /* Disable PSR if Replay can be enabled */ 5650 if (replay_feature_enabled) 5651 if (amdgpu_dm_set_replay_caps(link, aconnector)) 5652 psr_feature_enabled = false; 5653 5654 if (psr_feature_enabled) { 5655 amdgpu_dm_set_psr_caps(link); 5656 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 5657 aconnector->base.name, 5658 link->psr_settings.psr_feature_enabled, 5659 link->psr_settings.psr_version, 5660 link->dpcd_caps.psr_info.psr_version, 5661 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 5662 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 5663 } 5664 } 5665 } 5666 amdgpu_set_panel_orientation(&aconnector->base); 5667 } 5668 5669 /* Debug dump: list all DC links and their associated sinks after detection 5670 * is complete for all connectors. This provides a comprehensive view of the 5671 * final state without repeating the dump for each connector. 5672 */ 5673 amdgpu_dm_dump_links_and_sinks(adev); 5674 5675 /* Software is initialized. Now we can register interrupt handlers. */ 5676 switch (adev->asic_type) { 5677#if defined(CONFIG_DRM_AMD_DC_SI) 5678 case CHIP_TAHITI: 5679 case CHIP_PITCAIRN: 5680 case CHIP_VERDE: 5681 case CHIP_OLAND: 5682 if (dce60_register_irq_handlers(dm->adev)) { 5683 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5684 goto fail; 5685 } 5686 break; 5687#endif 5688 case CHIP_BONAIRE: 5689 case CHIP_HAWAII: 5690 case CHIP_KAVERI: 5691 case CHIP_KABINI: 5692 case CHIP_MULLINS: 5693 case CHIP_TONGA: 5694 case CHIP_FIJI: 5695 case CHIP_CARRIZO: 5696 case CHIP_STONEY: 5697 case CHIP_POLARIS11: 5698 case CHIP_POLARIS10: 5699 case CHIP_POLARIS12: 5700 case CHIP_VEGAM: 5701 case CHIP_VEGA10: 5702 case CHIP_VEGA12: 5703 case CHIP_VEGA20: 5704 if (dce110_register_irq_handlers(dm->adev)) { 5705 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5706 goto fail; 5707 } 5708 break; 5709 default: 5710 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5711 case IP_VERSION(1, 0, 0): 5712 case IP_VERSION(1, 0, 1): 5713 case IP_VERSION(2, 0, 2): 5714 case IP_VERSION(2, 0, 3): 5715 case IP_VERSION(2, 0, 0): 5716 case IP_VERSION(2, 1, 0): 5717 case IP_VERSION(3, 0, 0): 5718 case IP_VERSION(3, 0, 2): 5719 case IP_VERSION(3, 0, 3): 5720 case IP_VERSION(3, 0, 1): 5721 case IP_VERSION(3, 1, 2): 5722 case IP_VERSION(3, 1, 3): 5723 case IP_VERSION(3, 1, 4): 5724 case IP_VERSION(3, 1, 5): 5725 case IP_VERSION(3, 1, 6): 5726 case IP_VERSION(3, 2, 0): 5727 case IP_VERSION(3, 2, 1): 5728 case IP_VERSION(3, 5, 0): 5729 case IP_VERSION(3, 5, 1): 5730 case IP_VERSION(3, 6, 0): 5731 case IP_VERSION(4, 0, 1): 5732 if (dcn10_register_irq_handlers(dm->adev)) { 5733 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5734 goto fail; 5735 } 5736 break; 5737 default: 5738 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 5739 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5740 goto fail; 5741 } 5742 break; 5743 } 5744 5745 return 0; 5746fail: 5747 kfree(aencoder); 5748 kfree(aconnector); 5749 5750 return -EINVAL; 5751} 5752 5753static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 5754{ 5755 if (dm->atomic_obj.state) 5756 drm_atomic_private_obj_fini(&dm->atomic_obj); 5757} 5758 5759/****************************************************************************** 5760 * amdgpu_display_funcs functions 5761 *****************************************************************************/ 5762 5763/* 5764 * dm_bandwidth_update - program display watermarks 5765 * 5766 * @adev: amdgpu_device pointer 5767 * 5768 * Calculate and program the display watermarks and line buffer allocation. 5769 */ 5770static void dm_bandwidth_update(struct amdgpu_device *adev) 5771{ 5772 /* TODO: implement later */ 5773} 5774 5775static const struct amdgpu_display_funcs dm_display_funcs = { 5776 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 5777 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 5778 .backlight_set_level = NULL, /* never called for DC */ 5779 .backlight_get_level = NULL, /* never called for DC */ 5780 .hpd_sense = NULL,/* called unconditionally */ 5781 .hpd_set_polarity = NULL, /* called unconditionally */ 5782 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 5783 .page_flip_get_scanoutpos = 5784 dm_crtc_get_scanoutpos,/* called unconditionally */ 5785 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 5786 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 5787}; 5788 5789#if defined(CONFIG_DEBUG_KERNEL_DC) 5790 5791static ssize_t s3_debug_store(struct device *device, 5792 struct device_attribute *attr, 5793 const char *buf, 5794 size_t count) 5795{ 5796 int ret; 5797 int s3_state; 5798 struct drm_device *drm_dev = dev_get_drvdata(device); 5799 struct amdgpu_device *adev = drm_to_adev(drm_dev); 5800 struct amdgpu_ip_block *ip_block; 5801 5802 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 5803 if (!ip_block) 5804 return -EINVAL; 5805 5806 ret = kstrtoint(buf, 0, &s3_state); 5807 5808 if (ret == 0) { 5809 if (s3_state) { 5810 dm_resume(ip_block); 5811 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 5812 } else 5813 dm_suspend(ip_block); 5814 } 5815 5816 return ret == 0 ? count : 0; 5817} 5818 5819DEVICE_ATTR_WO(s3_debug); 5820 5821#endif 5822 5823static int dm_init_microcode(struct amdgpu_device *adev) 5824{ 5825 char *fw_name_dmub; 5826 int r; 5827 5828 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5829 case IP_VERSION(2, 1, 0): 5830 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 5831 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 5832 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 5833 break; 5834 case IP_VERSION(3, 0, 0): 5835 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 5836 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 5837 else 5838 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 5839 break; 5840 case IP_VERSION(3, 0, 1): 5841 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 5842 break; 5843 case IP_VERSION(3, 0, 2): 5844 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 5845 break; 5846 case IP_VERSION(3, 0, 3): 5847 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 5848 break; 5849 case IP_VERSION(3, 1, 2): 5850 case IP_VERSION(3, 1, 3): 5851 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 5852 break; 5853 case IP_VERSION(3, 1, 4): 5854 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 5855 break; 5856 case IP_VERSION(3, 1, 5): 5857 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 5858 break; 5859 case IP_VERSION(3, 1, 6): 5860 fw_name_dmub = FIRMWARE_DCN316_DMUB; 5861 break; 5862 case IP_VERSION(3, 2, 0): 5863 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 5864 break; 5865 case IP_VERSION(3, 2, 1): 5866 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 5867 break; 5868 case IP_VERSION(3, 5, 0): 5869 fw_name_dmub = FIRMWARE_DCN_35_DMUB; 5870 break; 5871 case IP_VERSION(3, 5, 1): 5872 fw_name_dmub = FIRMWARE_DCN_351_DMUB; 5873 break; 5874 case IP_VERSION(3, 6, 0): 5875 fw_name_dmub = FIRMWARE_DCN_36_DMUB; 5876 break; 5877 case IP_VERSION(4, 0, 1): 5878 fw_name_dmub = FIRMWARE_DCN_401_DMUB; 5879 break; 5880 default: 5881 /* ASIC doesn't support DMUB. */ 5882 return 0; 5883 } 5884 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, AMDGPU_UCODE_REQUIRED, 5885 "%s", fw_name_dmub); 5886 return r; 5887} 5888 5889static int dm_early_init(struct amdgpu_ip_block *ip_block) 5890{ 5891 struct amdgpu_device *adev = ip_block->adev; 5892 struct amdgpu_mode_info *mode_info = &adev->mode_info; 5893 struct atom_context *ctx = mode_info->atom_context; 5894 int index = GetIndexIntoMasterTable(DATA, Object_Header); 5895 u16 data_offset; 5896 5897 /* if there is no object header, skip DM */ 5898 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 5899 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 5900 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 5901 return -ENOENT; 5902 } 5903 5904 switch (adev->asic_type) { 5905#if defined(CONFIG_DRM_AMD_DC_SI) 5906 case CHIP_TAHITI: 5907 case CHIP_PITCAIRN: 5908 case CHIP_VERDE: 5909 adev->mode_info.num_crtc = 6; 5910 adev->mode_info.num_hpd = 6; 5911 adev->mode_info.num_dig = 6; 5912 break; 5913 case CHIP_OLAND: 5914 adev->mode_info.num_crtc = 2; 5915 adev->mode_info.num_hpd = 2; 5916 adev->mode_info.num_dig = 2; 5917 break; 5918#endif 5919 case CHIP_BONAIRE: 5920 case CHIP_HAWAII: 5921 adev->mode_info.num_crtc = 6; 5922 adev->mode_info.num_hpd = 6; 5923 adev->mode_info.num_dig = 6; 5924 break; 5925 case CHIP_KAVERI: 5926 adev->mode_info.num_crtc = 4; 5927 adev->mode_info.num_hpd = 6; 5928 adev->mode_info.num_dig = 7; 5929 break; 5930 case CHIP_KABINI: 5931 case CHIP_MULLINS: 5932 adev->mode_info.num_crtc = 2; 5933 adev->mode_info.num_hpd = 6; 5934 adev->mode_info.num_dig = 6; 5935 break; 5936 case CHIP_FIJI: 5937 case CHIP_TONGA: 5938 adev->mode_info.num_crtc = 6; 5939 adev->mode_info.num_hpd = 6; 5940 adev->mode_info.num_dig = 7; 5941 break; 5942 case CHIP_CARRIZO: 5943 adev->mode_info.num_crtc = 3; 5944 adev->mode_info.num_hpd = 6; 5945 adev->mode_info.num_dig = 9; 5946 break; 5947 case CHIP_STONEY: 5948 adev->mode_info.num_crtc = 2; 5949 adev->mode_info.num_hpd = 6; 5950 adev->mode_info.num_dig = 9; 5951 break; 5952 case CHIP_POLARIS11: 5953 case CHIP_POLARIS12: 5954 adev->mode_info.num_crtc = 5; 5955 adev->mode_info.num_hpd = 5; 5956 adev->mode_info.num_dig = 5; 5957 break; 5958 case CHIP_POLARIS10: 5959 case CHIP_VEGAM: 5960 adev->mode_info.num_crtc = 6; 5961 adev->mode_info.num_hpd = 6; 5962 adev->mode_info.num_dig = 6; 5963 break; 5964 case CHIP_VEGA10: 5965 case CHIP_VEGA12: 5966 case CHIP_VEGA20: 5967 adev->mode_info.num_crtc = 6; 5968 adev->mode_info.num_hpd = 6; 5969 adev->mode_info.num_dig = 6; 5970 break; 5971 default: 5972 5973 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5974 case IP_VERSION(2, 0, 2): 5975 case IP_VERSION(3, 0, 0): 5976 adev->mode_info.num_crtc = 6; 5977 adev->mode_info.num_hpd = 6; 5978 adev->mode_info.num_dig = 6; 5979 break; 5980 case IP_VERSION(2, 0, 0): 5981 case IP_VERSION(3, 0, 2): 5982 adev->mode_info.num_crtc = 5; 5983 adev->mode_info.num_hpd = 5; 5984 adev->mode_info.num_dig = 5; 5985 break; 5986 case IP_VERSION(2, 0, 3): 5987 case IP_VERSION(3, 0, 3): 5988 adev->mode_info.num_crtc = 2; 5989 adev->mode_info.num_hpd = 2; 5990 adev->mode_info.num_dig = 2; 5991 break; 5992 case IP_VERSION(1, 0, 0): 5993 case IP_VERSION(1, 0, 1): 5994 case IP_VERSION(3, 0, 1): 5995 case IP_VERSION(2, 1, 0): 5996 case IP_VERSION(3, 1, 2): 5997 case IP_VERSION(3, 1, 3): 5998 case IP_VERSION(3, 1, 4): 5999 case IP_VERSION(3, 1, 5): 6000 case IP_VERSION(3, 1, 6): 6001 case IP_VERSION(3, 2, 0): 6002 case IP_VERSION(3, 2, 1): 6003 case IP_VERSION(3, 5, 0): 6004 case IP_VERSION(3, 5, 1): 6005 case IP_VERSION(3, 6, 0): 6006 case IP_VERSION(4, 0, 1): 6007 adev->mode_info.num_crtc = 4; 6008 adev->mode_info.num_hpd = 4; 6009 adev->mode_info.num_dig = 4; 6010 break; 6011 default: 6012 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 6013 amdgpu_ip_version(adev, DCE_HWIP, 0)); 6014 return -EINVAL; 6015 } 6016 break; 6017 } 6018 6019 if (adev->mode_info.funcs == NULL) 6020 adev->mode_info.funcs = &dm_display_funcs; 6021 6022 /* 6023 * Note: Do NOT change adev->audio_endpt_rreg and 6024 * adev->audio_endpt_wreg because they are initialised in 6025 * amdgpu_device_init() 6026 */ 6027#if defined(CONFIG_DEBUG_KERNEL_DC) 6028 device_create_file( 6029 adev_to_drm(adev)->dev, 6030 &dev_attr_s3_debug); 6031#endif 6032 adev->dc_enabled = true; 6033 6034 return dm_init_microcode(adev); 6035} 6036 6037static bool modereset_required(struct drm_crtc_state *crtc_state) 6038{ 6039 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 6040} 6041 6042static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 6043{ 6044 drm_encoder_cleanup(encoder); 6045 kfree(encoder); 6046} 6047 6048static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 6049 .destroy = amdgpu_dm_encoder_destroy, 6050}; 6051 6052static int 6053fill_plane_color_attributes(const struct drm_plane_state *plane_state, 6054 const enum surface_pixel_format format, 6055 enum dc_color_space *color_space) 6056{ 6057 bool full_range; 6058 6059 *color_space = COLOR_SPACE_SRGB; 6060 6061 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 6062 if (plane_state->state && plane_state->state->plane_color_pipeline) 6063 return 0; 6064 6065 /* DRM color properties only affect non-RGB formats. */ 6066 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 6067 return 0; 6068 6069 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 6070 6071 switch (plane_state->color_encoding) { 6072 case DRM_COLOR_YCBCR_BT601: 6073 if (full_range) 6074 *color_space = COLOR_SPACE_YCBCR601; 6075 else 6076 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 6077 break; 6078 6079 case DRM_COLOR_YCBCR_BT709: 6080 if (full_range) 6081 *color_space = COLOR_SPACE_YCBCR709; 6082 else 6083 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 6084 break; 6085 6086 case DRM_COLOR_YCBCR_BT2020: 6087 if (full_range) 6088 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 6089 else 6090 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 6091 break; 6092 6093 default: 6094 return -EINVAL; 6095 } 6096 6097 return 0; 6098} 6099 6100static int 6101fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 6102 const struct drm_plane_state *plane_state, 6103 const u64 tiling_flags, 6104 struct dc_plane_info *plane_info, 6105 struct dc_plane_address *address, 6106 bool tmz_surface) 6107{ 6108 const struct drm_framebuffer *fb = plane_state->fb; 6109 const struct amdgpu_framebuffer *afb = 6110 to_amdgpu_framebuffer(plane_state->fb); 6111 int ret; 6112 6113 memset(plane_info, 0, sizeof(*plane_info)); 6114 6115 switch (fb->format->format) { 6116 case DRM_FORMAT_C8: 6117 plane_info->format = 6118 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 6119 break; 6120 case DRM_FORMAT_RGB565: 6121 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 6122 break; 6123 case DRM_FORMAT_XRGB8888: 6124 case DRM_FORMAT_ARGB8888: 6125 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6126 break; 6127 case DRM_FORMAT_XRGB2101010: 6128 case DRM_FORMAT_ARGB2101010: 6129 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 6130 break; 6131 case DRM_FORMAT_XBGR2101010: 6132 case DRM_FORMAT_ABGR2101010: 6133 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 6134 break; 6135 case DRM_FORMAT_XBGR8888: 6136 case DRM_FORMAT_ABGR8888: 6137 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 6138 break; 6139 case DRM_FORMAT_NV21: 6140 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 6141 break; 6142 case DRM_FORMAT_NV12: 6143 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 6144 break; 6145 case DRM_FORMAT_P010: 6146 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 6147 break; 6148 case DRM_FORMAT_XRGB16161616F: 6149 case DRM_FORMAT_ARGB16161616F: 6150 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 6151 break; 6152 case DRM_FORMAT_XBGR16161616F: 6153 case DRM_FORMAT_ABGR16161616F: 6154 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 6155 break; 6156 case DRM_FORMAT_XRGB16161616: 6157 case DRM_FORMAT_ARGB16161616: 6158 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 6159 break; 6160 case DRM_FORMAT_XBGR16161616: 6161 case DRM_FORMAT_ABGR16161616: 6162 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 6163 break; 6164 default: 6165 drm_err(adev_to_drm(adev), 6166 "Unsupported screen format %p4cc\n", 6167 &fb->format->format); 6168 return -EINVAL; 6169 } 6170 6171 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 6172 case DRM_MODE_ROTATE_0: 6173 plane_info->rotation = ROTATION_ANGLE_0; 6174 break; 6175 case DRM_MODE_ROTATE_90: 6176 plane_info->rotation = ROTATION_ANGLE_90; 6177 break; 6178 case DRM_MODE_ROTATE_180: 6179 plane_info->rotation = ROTATION_ANGLE_180; 6180 break; 6181 case DRM_MODE_ROTATE_270: 6182 plane_info->rotation = ROTATION_ANGLE_270; 6183 break; 6184 default: 6185 plane_info->rotation = ROTATION_ANGLE_0; 6186 break; 6187 } 6188 6189 6190 plane_info->visible = true; 6191 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 6192 6193 plane_info->layer_index = plane_state->normalized_zpos; 6194 6195 ret = fill_plane_color_attributes(plane_state, plane_info->format, 6196 &plane_info->color_space); 6197 if (ret) 6198 return ret; 6199 6200 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 6201 plane_info->rotation, tiling_flags, 6202 &plane_info->tiling_info, 6203 &plane_info->plane_size, 6204 &plane_info->dcc, address, 6205 tmz_surface); 6206 if (ret) 6207 return ret; 6208 6209 amdgpu_dm_plane_fill_blending_from_plane_state( 6210 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 6211 &plane_info->global_alpha, &plane_info->global_alpha_value); 6212 6213 return 0; 6214} 6215 6216static int fill_dc_plane_attributes(struct amdgpu_device *adev, 6217 struct dc_plane_state *dc_plane_state, 6218 struct drm_plane_state *plane_state, 6219 struct drm_crtc_state *crtc_state) 6220{ 6221 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 6222 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 6223 struct dc_scaling_info scaling_info; 6224 struct dc_plane_info plane_info; 6225 int ret; 6226 6227 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 6228 if (ret) 6229 return ret; 6230 6231 dc_plane_state->src_rect = scaling_info.src_rect; 6232 dc_plane_state->dst_rect = scaling_info.dst_rect; 6233 dc_plane_state->clip_rect = scaling_info.clip_rect; 6234 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 6235 6236 ret = fill_dc_plane_info_and_addr(adev, plane_state, 6237 afb->tiling_flags, 6238 &plane_info, 6239 &dc_plane_state->address, 6240 afb->tmz_surface); 6241 if (ret) 6242 return ret; 6243 6244 dc_plane_state->format = plane_info.format; 6245 dc_plane_state->color_space = plane_info.color_space; 6246 dc_plane_state->format = plane_info.format; 6247 dc_plane_state->plane_size = plane_info.plane_size; 6248 dc_plane_state->rotation = plane_info.rotation; 6249 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 6250 dc_plane_state->stereo_format = plane_info.stereo_format; 6251 dc_plane_state->tiling_info = plane_info.tiling_info; 6252 dc_plane_state->visible = plane_info.visible; 6253 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 6254 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 6255 dc_plane_state->global_alpha = plane_info.global_alpha; 6256 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 6257 dc_plane_state->dcc = plane_info.dcc; 6258 dc_plane_state->layer_index = plane_info.layer_index; 6259 dc_plane_state->flip_int_enabled = true; 6260 6261 /* 6262 * Always set input transfer function, since plane state is refreshed 6263 * every time. 6264 */ 6265 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 6266 plane_state, 6267 dc_plane_state); 6268 if (ret) 6269 return ret; 6270 6271 return 0; 6272} 6273 6274static inline void fill_dc_dirty_rect(struct drm_plane *plane, 6275 struct rect *dirty_rect, int32_t x, 6276 s32 y, s32 width, s32 height, 6277 int *i, bool ffu) 6278{ 6279 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 6280 6281 dirty_rect->x = x; 6282 dirty_rect->y = y; 6283 dirty_rect->width = width; 6284 dirty_rect->height = height; 6285 6286 if (ffu) 6287 drm_dbg(plane->dev, 6288 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 6289 plane->base.id, width, height); 6290 else 6291 drm_dbg(plane->dev, 6292 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 6293 plane->base.id, x, y, width, height); 6294 6295 (*i)++; 6296} 6297 6298/** 6299 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 6300 * 6301 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 6302 * remote fb 6303 * @old_plane_state: Old state of @plane 6304 * @new_plane_state: New state of @plane 6305 * @crtc_state: New state of CRTC connected to the @plane 6306 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 6307 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 6308 * If PSR SU is enabled and damage clips are available, only the regions of the screen 6309 * that have changed will be updated. If PSR SU is not enabled, 6310 * or if damage clips are not available, the entire screen will be updated. 6311 * @dirty_regions_changed: dirty regions changed 6312 * 6313 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 6314 * (referred to as "damage clips" in DRM nomenclature) that require updating on 6315 * the eDP remote buffer. The responsibility of specifying the dirty regions is 6316 * amdgpu_dm's. 6317 * 6318 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 6319 * plane with regions that require flushing to the eDP remote buffer. In 6320 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 6321 * implicitly provide damage clips without any client support via the plane 6322 * bounds. 6323 */ 6324static void fill_dc_dirty_rects(struct drm_plane *plane, 6325 struct drm_plane_state *old_plane_state, 6326 struct drm_plane_state *new_plane_state, 6327 struct drm_crtc_state *crtc_state, 6328 struct dc_flip_addrs *flip_addrs, 6329 bool is_psr_su, 6330 bool *dirty_regions_changed) 6331{ 6332 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 6333 struct rect *dirty_rects = flip_addrs->dirty_rects; 6334 u32 num_clips; 6335 struct drm_mode_rect *clips; 6336 bool bb_changed; 6337 bool fb_changed; 6338 u32 i = 0; 6339 *dirty_regions_changed = false; 6340 6341 /* 6342 * Cursor plane has it's own dirty rect update interface. See 6343 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 6344 */ 6345 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6346 return; 6347 6348 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 6349 goto ffu; 6350 6351 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 6352 clips = drm_plane_get_damage_clips(new_plane_state); 6353 6354 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 6355 is_psr_su))) 6356 goto ffu; 6357 6358 if (!dm_crtc_state->mpo_requested) { 6359 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 6360 goto ffu; 6361 6362 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 6363 fill_dc_dirty_rect(new_plane_state->plane, 6364 &dirty_rects[flip_addrs->dirty_rect_count], 6365 clips->x1, clips->y1, 6366 clips->x2 - clips->x1, clips->y2 - clips->y1, 6367 &flip_addrs->dirty_rect_count, 6368 false); 6369 return; 6370 } 6371 6372 /* 6373 * MPO is requested. Add entire plane bounding box to dirty rects if 6374 * flipped to or damaged. 6375 * 6376 * If plane is moved or resized, also add old bounding box to dirty 6377 * rects. 6378 */ 6379 fb_changed = old_plane_state->fb->base.id != 6380 new_plane_state->fb->base.id; 6381 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 6382 old_plane_state->crtc_y != new_plane_state->crtc_y || 6383 old_plane_state->crtc_w != new_plane_state->crtc_w || 6384 old_plane_state->crtc_h != new_plane_state->crtc_h); 6385 6386 drm_dbg(plane->dev, 6387 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 6388 new_plane_state->plane->base.id, 6389 bb_changed, fb_changed, num_clips); 6390 6391 *dirty_regions_changed = bb_changed; 6392 6393 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 6394 goto ffu; 6395 6396 if (bb_changed) { 6397 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 6398 new_plane_state->crtc_x, 6399 new_plane_state->crtc_y, 6400 new_plane_state->crtc_w, 6401 new_plane_state->crtc_h, &i, false); 6402 6403 /* Add old plane bounding-box if plane is moved or resized */ 6404 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 6405 old_plane_state->crtc_x, 6406 old_plane_state->crtc_y, 6407 old_plane_state->crtc_w, 6408 old_plane_state->crtc_h, &i, false); 6409 } 6410 6411 if (num_clips) { 6412 for (; i < num_clips; clips++) 6413 fill_dc_dirty_rect(new_plane_state->plane, 6414 &dirty_rects[i], clips->x1, 6415 clips->y1, clips->x2 - clips->x1, 6416 clips->y2 - clips->y1, &i, false); 6417 } else if (fb_changed && !bb_changed) { 6418 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 6419 new_plane_state->crtc_x, 6420 new_plane_state->crtc_y, 6421 new_plane_state->crtc_w, 6422 new_plane_state->crtc_h, &i, false); 6423 } 6424 6425 flip_addrs->dirty_rect_count = i; 6426 return; 6427 6428ffu: 6429 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 6430 dm_crtc_state->base.mode.crtc_hdisplay, 6431 dm_crtc_state->base.mode.crtc_vdisplay, 6432 &flip_addrs->dirty_rect_count, true); 6433} 6434 6435static void update_stream_scaling_settings(const struct drm_display_mode *mode, 6436 const struct dm_connector_state *dm_state, 6437 struct dc_stream_state *stream) 6438{ 6439 enum amdgpu_rmx_type rmx_type; 6440 6441 struct rect src = { 0 }; /* viewport in composition space*/ 6442 struct rect dst = { 0 }; /* stream addressable area */ 6443 6444 /* no mode. nothing to be done */ 6445 if (!mode) 6446 return; 6447 6448 /* Full screen scaling by default */ 6449 src.width = mode->hdisplay; 6450 src.height = mode->vdisplay; 6451 dst.width = stream->timing.h_addressable; 6452 dst.height = stream->timing.v_addressable; 6453 6454 if (dm_state) { 6455 rmx_type = dm_state->scaling; 6456 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 6457 if (src.width * dst.height < 6458 src.height * dst.width) { 6459 /* height needs less upscaling/more downscaling */ 6460 dst.width = src.width * 6461 dst.height / src.height; 6462 } else { 6463 /* width needs less upscaling/more downscaling */ 6464 dst.height = src.height * 6465 dst.width / src.width; 6466 } 6467 } else if (rmx_type == RMX_CENTER) { 6468 dst = src; 6469 } 6470 6471 dst.x = (stream->timing.h_addressable - dst.width) / 2; 6472 dst.y = (stream->timing.v_addressable - dst.height) / 2; 6473 6474 if (dm_state->underscan_enable) { 6475 dst.x += dm_state->underscan_hborder / 2; 6476 dst.y += dm_state->underscan_vborder / 2; 6477 dst.width -= dm_state->underscan_hborder; 6478 dst.height -= dm_state->underscan_vborder; 6479 } 6480 } 6481 6482 stream->src = src; 6483 stream->dst = dst; 6484 6485 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 6486 dst.x, dst.y, dst.width, dst.height); 6487 6488} 6489 6490static enum dc_color_depth 6491convert_color_depth_from_display_info(const struct drm_connector *connector, 6492 bool is_y420, int requested_bpc) 6493{ 6494 u8 bpc; 6495 6496 if (is_y420) { 6497 bpc = 8; 6498 6499 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 6500 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 6501 bpc = 16; 6502 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 6503 bpc = 12; 6504 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 6505 bpc = 10; 6506 } else { 6507 bpc = (uint8_t)connector->display_info.bpc; 6508 /* Assume 8 bpc by default if no bpc is specified. */ 6509 bpc = bpc ? bpc : 8; 6510 } 6511 6512 if (requested_bpc > 0) { 6513 /* 6514 * Cap display bpc based on the user requested value. 6515 * 6516 * The value for state->max_bpc may not correctly updated 6517 * depending on when the connector gets added to the state 6518 * or if this was called outside of atomic check, so it 6519 * can't be used directly. 6520 */ 6521 bpc = min_t(u8, bpc, requested_bpc); 6522 6523 /* Round down to the nearest even number. */ 6524 bpc = bpc - (bpc & 1); 6525 } 6526 6527 switch (bpc) { 6528 case 0: 6529 /* 6530 * Temporary Work around, DRM doesn't parse color depth for 6531 * EDID revision before 1.4 6532 * TODO: Fix edid parsing 6533 */ 6534 return COLOR_DEPTH_888; 6535 case 6: 6536 return COLOR_DEPTH_666; 6537 case 8: 6538 return COLOR_DEPTH_888; 6539 case 10: 6540 return COLOR_DEPTH_101010; 6541 case 12: 6542 return COLOR_DEPTH_121212; 6543 case 14: 6544 return COLOR_DEPTH_141414; 6545 case 16: 6546 return COLOR_DEPTH_161616; 6547 default: 6548 return COLOR_DEPTH_UNDEFINED; 6549 } 6550} 6551 6552static enum dc_aspect_ratio 6553get_aspect_ratio(const struct drm_display_mode *mode_in) 6554{ 6555 /* 1-1 mapping, since both enums follow the HDMI spec. */ 6556 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 6557} 6558 6559static enum dc_color_space 6560get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 6561 const struct drm_connector_state *connector_state) 6562{ 6563 enum dc_color_space color_space = COLOR_SPACE_SRGB; 6564 6565 switch (connector_state->colorspace) { 6566 case DRM_MODE_COLORIMETRY_BT601_YCC: 6567 if (dc_crtc_timing->flags.Y_ONLY) 6568 color_space = COLOR_SPACE_YCBCR601_LIMITED; 6569 else 6570 color_space = COLOR_SPACE_YCBCR601; 6571 break; 6572 case DRM_MODE_COLORIMETRY_BT709_YCC: 6573 if (dc_crtc_timing->flags.Y_ONLY) 6574 color_space = COLOR_SPACE_YCBCR709_LIMITED; 6575 else 6576 color_space = COLOR_SPACE_YCBCR709; 6577 break; 6578 case DRM_MODE_COLORIMETRY_OPRGB: 6579 color_space = COLOR_SPACE_ADOBERGB; 6580 break; 6581 case DRM_MODE_COLORIMETRY_BT2020_RGB: 6582 case DRM_MODE_COLORIMETRY_BT2020_YCC: 6583 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 6584 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 6585 else 6586 color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 6587 break; 6588 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 6589 default: 6590 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 6591 color_space = COLOR_SPACE_SRGB; 6592 if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) 6593 color_space = COLOR_SPACE_SRGB_LIMITED; 6594 /* 6595 * 27030khz is the separation point between HDTV and SDTV 6596 * according to HDMI spec, we use YCbCr709 and YCbCr601 6597 * respectively 6598 */ 6599 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 6600 if (dc_crtc_timing->flags.Y_ONLY) 6601 color_space = 6602 COLOR_SPACE_YCBCR709_LIMITED; 6603 else 6604 color_space = COLOR_SPACE_YCBCR709; 6605 } else { 6606 if (dc_crtc_timing->flags.Y_ONLY) 6607 color_space = 6608 COLOR_SPACE_YCBCR601_LIMITED; 6609 else 6610 color_space = COLOR_SPACE_YCBCR601; 6611 } 6612 break; 6613 } 6614 6615 return color_space; 6616} 6617 6618static enum display_content_type 6619get_output_content_type(const struct drm_connector_state *connector_state) 6620{ 6621 switch (connector_state->content_type) { 6622 default: 6623 case DRM_MODE_CONTENT_TYPE_NO_DATA: 6624 return DISPLAY_CONTENT_TYPE_NO_DATA; 6625 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 6626 return DISPLAY_CONTENT_TYPE_GRAPHICS; 6627 case DRM_MODE_CONTENT_TYPE_PHOTO: 6628 return DISPLAY_CONTENT_TYPE_PHOTO; 6629 case DRM_MODE_CONTENT_TYPE_CINEMA: 6630 return DISPLAY_CONTENT_TYPE_CINEMA; 6631 case DRM_MODE_CONTENT_TYPE_GAME: 6632 return DISPLAY_CONTENT_TYPE_GAME; 6633 } 6634} 6635 6636static bool adjust_colour_depth_from_display_info( 6637 struct dc_crtc_timing *timing_out, 6638 const struct drm_display_info *info) 6639{ 6640 enum dc_color_depth depth = timing_out->display_color_depth; 6641 int normalized_clk; 6642 6643 do { 6644 normalized_clk = timing_out->pix_clk_100hz / 10; 6645 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 6646 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 6647 normalized_clk /= 2; 6648 /* Adjusting pix clock following on HDMI spec based on colour depth */ 6649 switch (depth) { 6650 case COLOR_DEPTH_888: 6651 break; 6652 case COLOR_DEPTH_101010: 6653 normalized_clk = (normalized_clk * 30) / 24; 6654 break; 6655 case COLOR_DEPTH_121212: 6656 normalized_clk = (normalized_clk * 36) / 24; 6657 break; 6658 case COLOR_DEPTH_161616: 6659 normalized_clk = (normalized_clk * 48) / 24; 6660 break; 6661 default: 6662 /* The above depths are the only ones valid for HDMI. */ 6663 return false; 6664 } 6665 if (normalized_clk <= info->max_tmds_clock) { 6666 timing_out->display_color_depth = depth; 6667 return true; 6668 } 6669 } while (--depth > COLOR_DEPTH_666); 6670 return false; 6671} 6672 6673static void fill_stream_properties_from_drm_display_mode( 6674 struct dc_stream_state *stream, 6675 const struct drm_display_mode *mode_in, 6676 const struct drm_connector *connector, 6677 const struct drm_connector_state *connector_state, 6678 const struct dc_stream_state *old_stream, 6679 int requested_bpc) 6680{ 6681 struct dc_crtc_timing *timing_out = &stream->timing; 6682 const struct drm_display_info *info = &connector->display_info; 6683 struct amdgpu_dm_connector *aconnector = NULL; 6684 struct hdmi_vendor_infoframe hv_frame; 6685 struct hdmi_avi_infoframe avi_frame; 6686 ssize_t err; 6687 6688 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 6689 aconnector = to_amdgpu_dm_connector(connector); 6690 6691 memset(&hv_frame, 0, sizeof(hv_frame)); 6692 memset(&avi_frame, 0, sizeof(avi_frame)); 6693 6694 timing_out->h_border_left = 0; 6695 timing_out->h_border_right = 0; 6696 timing_out->v_border_top = 0; 6697 timing_out->v_border_bottom = 0; 6698 /* TODO: un-hardcode */ 6699 if (drm_mode_is_420_only(info, mode_in) 6700 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6701 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 6702 else if (drm_mode_is_420_also(info, mode_in) 6703 && aconnector 6704 && aconnector->force_yuv420_output) 6705 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 6706 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR422) 6707 && aconnector 6708 && aconnector->force_yuv422_output) 6709 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR422; 6710 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 6711 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6712 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 6713 else 6714 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 6715 6716 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 6717 timing_out->display_color_depth = convert_color_depth_from_display_info( 6718 connector, 6719 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 6720 requested_bpc); 6721 timing_out->scan_type = SCANNING_TYPE_NODATA; 6722 timing_out->hdmi_vic = 0; 6723 6724 if (old_stream) { 6725 timing_out->vic = old_stream->timing.vic; 6726 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 6727 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 6728 } else { 6729 timing_out->vic = drm_match_cea_mode(mode_in); 6730 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 6731 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 6732 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 6733 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 6734 } 6735 6736 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 6737 err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, 6738 (struct drm_connector *)connector, 6739 mode_in); 6740 if (err < 0) 6741 drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", 6742 connector->name, err); 6743 timing_out->vic = avi_frame.video_code; 6744 err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, 6745 (struct drm_connector *)connector, 6746 mode_in); 6747 if (err < 0) 6748 drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", 6749 connector->name, err); 6750 timing_out->hdmi_vic = hv_frame.vic; 6751 } 6752 6753 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { 6754 timing_out->h_addressable = mode_in->hdisplay; 6755 timing_out->h_total = mode_in->htotal; 6756 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 6757 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 6758 timing_out->v_total = mode_in->vtotal; 6759 timing_out->v_addressable = mode_in->vdisplay; 6760 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 6761 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 6762 timing_out->pix_clk_100hz = mode_in->clock * 10; 6763 } else { 6764 timing_out->h_addressable = mode_in->crtc_hdisplay; 6765 timing_out->h_total = mode_in->crtc_htotal; 6766 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 6767 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 6768 timing_out->v_total = mode_in->crtc_vtotal; 6769 timing_out->v_addressable = mode_in->crtc_vdisplay; 6770 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 6771 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 6772 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 6773 } 6774 6775 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 6776 6777 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 6778 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 6779 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 6780 if (!adjust_colour_depth_from_display_info(timing_out, info) && 6781 drm_mode_is_420_also(info, mode_in) && 6782 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 6783 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 6784 adjust_colour_depth_from_display_info(timing_out, info); 6785 } 6786 } 6787 6788 stream->output_color_space = get_output_color_space(timing_out, connector_state); 6789 stream->content_type = get_output_content_type(connector_state); 6790} 6791 6792static void fill_audio_info(struct audio_info *audio_info, 6793 const struct drm_connector *drm_connector, 6794 const struct dc_sink *dc_sink) 6795{ 6796 int i = 0; 6797 int cea_revision = 0; 6798 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 6799 6800 audio_info->manufacture_id = edid_caps->manufacturer_id; 6801 audio_info->product_id = edid_caps->product_id; 6802 6803 cea_revision = drm_connector->display_info.cea_rev; 6804 6805 strscpy(audio_info->display_name, 6806 edid_caps->display_name, 6807 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 6808 6809 if (cea_revision >= 3) { 6810 audio_info->mode_count = edid_caps->audio_mode_count; 6811 6812 for (i = 0; i < audio_info->mode_count; ++i) { 6813 audio_info->modes[i].format_code = 6814 (enum audio_format_code) 6815 (edid_caps->audio_modes[i].format_code); 6816 audio_info->modes[i].channel_count = 6817 edid_caps->audio_modes[i].channel_count; 6818 audio_info->modes[i].sample_rates.all = 6819 edid_caps->audio_modes[i].sample_rate; 6820 audio_info->modes[i].sample_size = 6821 edid_caps->audio_modes[i].sample_size; 6822 } 6823 } 6824 6825 audio_info->flags.all = edid_caps->speaker_flags; 6826 6827 /* TODO: We only check for the progressive mode, check for interlace mode too */ 6828 if (drm_connector->latency_present[0]) { 6829 audio_info->video_latency = drm_connector->video_latency[0]; 6830 audio_info->audio_latency = drm_connector->audio_latency[0]; 6831 } 6832 6833 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 6834 6835} 6836 6837static void 6838copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 6839 struct drm_display_mode *dst_mode) 6840{ 6841 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 6842 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 6843 dst_mode->crtc_clock = src_mode->crtc_clock; 6844 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 6845 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 6846 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 6847 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 6848 dst_mode->crtc_htotal = src_mode->crtc_htotal; 6849 dst_mode->crtc_hskew = src_mode->crtc_hskew; 6850 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 6851 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 6852 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 6853 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 6854 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 6855} 6856 6857static void 6858decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 6859 const struct drm_display_mode *native_mode, 6860 bool scale_enabled) 6861{ 6862 if (scale_enabled || ( 6863 native_mode->clock == drm_mode->clock && 6864 native_mode->htotal == drm_mode->htotal && 6865 native_mode->vtotal == drm_mode->vtotal)) { 6866 if (native_mode->crtc_clock) 6867 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6868 } else { 6869 /* no scaling nor amdgpu inserted, no need to patch */ 6870 } 6871} 6872 6873static struct dc_sink * 6874create_fake_sink(struct drm_device *dev, struct dc_link *link) 6875{ 6876 struct dc_sink_init_data sink_init_data = { 0 }; 6877 struct dc_sink *sink = NULL; 6878 6879 sink_init_data.link = link; 6880 sink_init_data.sink_signal = link->connector_signal; 6881 6882 sink = dc_sink_create(&sink_init_data); 6883 if (!sink) { 6884 drm_err(dev, "Failed to create sink!\n"); 6885 return NULL; 6886 } 6887 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 6888 6889 return sink; 6890} 6891 6892static void set_multisync_trigger_params( 6893 struct dc_stream_state *stream) 6894{ 6895 struct dc_stream_state *master = NULL; 6896 6897 if (stream->triggered_crtc_reset.enabled) { 6898 master = stream->triggered_crtc_reset.event_source; 6899 stream->triggered_crtc_reset.event = 6900 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 6901 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 6902 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 6903 } 6904} 6905 6906static void set_master_stream(struct dc_stream_state *stream_set[], 6907 int stream_count) 6908{ 6909 int j, highest_rfr = 0, master_stream = 0; 6910 6911 for (j = 0; j < stream_count; j++) { 6912 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 6913 int refresh_rate = 0; 6914 6915 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 6916 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 6917 if (refresh_rate > highest_rfr) { 6918 highest_rfr = refresh_rate; 6919 master_stream = j; 6920 } 6921 } 6922 } 6923 for (j = 0; j < stream_count; j++) { 6924 if (stream_set[j]) 6925 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 6926 } 6927} 6928 6929static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 6930{ 6931 int i = 0; 6932 struct dc_stream_state *stream; 6933 6934 if (context->stream_count < 2) 6935 return; 6936 for (i = 0; i < context->stream_count ; i++) { 6937 if (!context->streams[i]) 6938 continue; 6939 /* 6940 * TODO: add a function to read AMD VSDB bits and set 6941 * crtc_sync_master.multi_sync_enabled flag 6942 * For now it's set to false 6943 */ 6944 } 6945 6946 set_master_stream(context->streams, context->stream_count); 6947 6948 for (i = 0; i < context->stream_count ; i++) { 6949 stream = context->streams[i]; 6950 6951 if (!stream) 6952 continue; 6953 6954 set_multisync_trigger_params(stream); 6955 } 6956} 6957 6958/** 6959 * DOC: FreeSync Video 6960 * 6961 * When a userspace application wants to play a video, the content follows a 6962 * standard format definition that usually specifies the FPS for that format. 6963 * The below list illustrates some video format and the expected FPS, 6964 * respectively: 6965 * 6966 * - TV/NTSC (23.976 FPS) 6967 * - Cinema (24 FPS) 6968 * - TV/PAL (25 FPS) 6969 * - TV/NTSC (29.97 FPS) 6970 * - TV/NTSC (30 FPS) 6971 * - Cinema HFR (48 FPS) 6972 * - TV/PAL (50 FPS) 6973 * - Commonly used (60 FPS) 6974 * - Multiples of 24 (48,72,96 FPS) 6975 * 6976 * The list of standards video format is not huge and can be added to the 6977 * connector modeset list beforehand. With that, userspace can leverage 6978 * FreeSync to extends the front porch in order to attain the target refresh 6979 * rate. Such a switch will happen seamlessly, without screen blanking or 6980 * reprogramming of the output in any other way. If the userspace requests a 6981 * modesetting change compatible with FreeSync modes that only differ in the 6982 * refresh rate, DC will skip the full update and avoid blink during the 6983 * transition. For example, the video player can change the modesetting from 6984 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 6985 * causing any display blink. This same concept can be applied to a mode 6986 * setting change. 6987 */ 6988static struct drm_display_mode * 6989get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 6990 bool use_probed_modes) 6991{ 6992 struct drm_display_mode *m, *m_pref = NULL; 6993 u16 current_refresh, highest_refresh; 6994 struct list_head *list_head = use_probed_modes ? 6995 &aconnector->base.probed_modes : 6996 &aconnector->base.modes; 6997 6998 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6999 return NULL; 7000 7001 if (aconnector->freesync_vid_base.clock != 0) 7002 return &aconnector->freesync_vid_base; 7003 7004 /* Find the preferred mode */ 7005 list_for_each_entry(m, list_head, head) { 7006 if (m->type & DRM_MODE_TYPE_PREFERRED) { 7007 m_pref = m; 7008 break; 7009 } 7010 } 7011 7012 if (!m_pref) { 7013 /* Probably an EDID with no preferred mode. Fallback to first entry */ 7014 m_pref = list_first_entry_or_null( 7015 &aconnector->base.modes, struct drm_display_mode, head); 7016 if (!m_pref) { 7017 drm_dbg_driver(aconnector->base.dev, "No preferred mode found in EDID\n"); 7018 return NULL; 7019 } 7020 } 7021 7022 highest_refresh = drm_mode_vrefresh(m_pref); 7023 7024 /* 7025 * Find the mode with highest refresh rate with same resolution. 7026 * For some monitors, preferred mode is not the mode with highest 7027 * supported refresh rate. 7028 */ 7029 list_for_each_entry(m, list_head, head) { 7030 current_refresh = drm_mode_vrefresh(m); 7031 7032 if (m->hdisplay == m_pref->hdisplay && 7033 m->vdisplay == m_pref->vdisplay && 7034 highest_refresh < current_refresh) { 7035 highest_refresh = current_refresh; 7036 m_pref = m; 7037 } 7038 } 7039 7040 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 7041 return m_pref; 7042} 7043 7044static bool is_freesync_video_mode(const struct drm_display_mode *mode, 7045 struct amdgpu_dm_connector *aconnector) 7046{ 7047 struct drm_display_mode *high_mode; 7048 int timing_diff; 7049 7050 high_mode = get_highest_refresh_rate_mode(aconnector, false); 7051 if (!high_mode || !mode) 7052 return false; 7053 7054 timing_diff = high_mode->vtotal - mode->vtotal; 7055 7056 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 7057 high_mode->hdisplay != mode->hdisplay || 7058 high_mode->vdisplay != mode->vdisplay || 7059 high_mode->hsync_start != mode->hsync_start || 7060 high_mode->hsync_end != mode->hsync_end || 7061 high_mode->htotal != mode->htotal || 7062 high_mode->hskew != mode->hskew || 7063 high_mode->vscan != mode->vscan || 7064 high_mode->vsync_start - mode->vsync_start != timing_diff || 7065 high_mode->vsync_end - mode->vsync_end != timing_diff) 7066 return false; 7067 else 7068 return true; 7069} 7070 7071#if defined(CONFIG_DRM_AMD_DC_FP) 7072static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 7073 struct dc_sink *sink, struct dc_stream_state *stream, 7074 struct dsc_dec_dpcd_caps *dsc_caps) 7075{ 7076 stream->timing.flags.DSC = 0; 7077 dsc_caps->is_dsc_supported = false; 7078 7079 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 7080 sink->sink_signal == SIGNAL_TYPE_EDP)) { 7081 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 7082 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 7083 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 7084 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 7085 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 7086 dsc_caps); 7087 } 7088} 7089 7090static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 7091 struct dc_sink *sink, struct dc_stream_state *stream, 7092 struct dsc_dec_dpcd_caps *dsc_caps, 7093 uint32_t max_dsc_target_bpp_limit_override) 7094{ 7095 const struct dc_link_settings *verified_link_cap = NULL; 7096 u32 link_bw_in_kbps; 7097 u32 edp_min_bpp_x16, edp_max_bpp_x16; 7098 struct dc *dc = sink->ctx->dc; 7099 struct dc_dsc_bw_range bw_range = {0}; 7100 struct dc_dsc_config dsc_cfg = {0}; 7101 struct dc_dsc_config_options dsc_options = {0}; 7102 7103 dc_dsc_get_default_config_option(dc, &dsc_options); 7104 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 7105 7106 verified_link_cap = dc_link_get_link_cap(stream->link); 7107 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 7108 edp_min_bpp_x16 = 8 * 16; 7109 edp_max_bpp_x16 = 8 * 16; 7110 7111 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 7112 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 7113 7114 if (edp_max_bpp_x16 < edp_min_bpp_x16) 7115 edp_min_bpp_x16 = edp_max_bpp_x16; 7116 7117 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 7118 dc->debug.dsc_min_slice_height_override, 7119 edp_min_bpp_x16, edp_max_bpp_x16, 7120 dsc_caps, 7121 &stream->timing, 7122 dc_link_get_highest_encoding_format(aconnector->dc_link), 7123 &bw_range)) { 7124 7125 if (bw_range.max_kbps < link_bw_in_kbps) { 7126 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 7127 dsc_caps, 7128 &dsc_options, 7129 0, 7130 &stream->timing, 7131 dc_link_get_highest_encoding_format(aconnector->dc_link), 7132 &dsc_cfg)) { 7133 stream->timing.dsc_cfg = dsc_cfg; 7134 stream->timing.flags.DSC = 1; 7135 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 7136 } 7137 return; 7138 } 7139 } 7140 7141 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 7142 dsc_caps, 7143 &dsc_options, 7144 link_bw_in_kbps, 7145 &stream->timing, 7146 dc_link_get_highest_encoding_format(aconnector->dc_link), 7147 &dsc_cfg)) { 7148 stream->timing.dsc_cfg = dsc_cfg; 7149 stream->timing.flags.DSC = 1; 7150 } 7151} 7152 7153static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 7154 struct dc_sink *sink, struct dc_stream_state *stream, 7155 struct dsc_dec_dpcd_caps *dsc_caps) 7156{ 7157 struct drm_connector *drm_connector = &aconnector->base; 7158 u32 link_bandwidth_kbps; 7159 struct dc *dc = sink->ctx->dc; 7160 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 7161 u32 dsc_max_supported_bw_in_kbps; 7162 u32 max_dsc_target_bpp_limit_override = 7163 drm_connector->display_info.max_dsc_bpp; 7164 struct dc_dsc_config_options dsc_options = {0}; 7165 7166 dc_dsc_get_default_config_option(dc, &dsc_options); 7167 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 7168 7169 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 7170 dc_link_get_link_cap(aconnector->dc_link)); 7171 7172 /* Set DSC policy according to dsc_clock_en */ 7173 dc_dsc_policy_set_enable_dsc_when_not_needed( 7174 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 7175 7176 if (sink->sink_signal == SIGNAL_TYPE_EDP && 7177 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 7178 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 7179 7180 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 7181 7182 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 7183 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 7184 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 7185 dsc_caps, 7186 &dsc_options, 7187 link_bandwidth_kbps, 7188 &stream->timing, 7189 dc_link_get_highest_encoding_format(aconnector->dc_link), 7190 &stream->timing.dsc_cfg)) { 7191 stream->timing.flags.DSC = 1; 7192 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from SST RX\n", 7193 __func__, drm_connector->name); 7194 } 7195 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 7196 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 7197 dc_link_get_highest_encoding_format(aconnector->dc_link)); 7198 max_supported_bw_in_kbps = link_bandwidth_kbps; 7199 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 7200 7201 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 7202 max_supported_bw_in_kbps > 0 && 7203 dsc_max_supported_bw_in_kbps > 0) 7204 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 7205 dsc_caps, 7206 &dsc_options, 7207 dsc_max_supported_bw_in_kbps, 7208 &stream->timing, 7209 dc_link_get_highest_encoding_format(aconnector->dc_link), 7210 &stream->timing.dsc_cfg)) { 7211 stream->timing.flags.DSC = 1; 7212 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n", 7213 __func__, drm_connector->name); 7214 } 7215 } 7216 } 7217 7218 /* Overwrite the stream flag if DSC is enabled through debugfs */ 7219 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 7220 stream->timing.flags.DSC = 1; 7221 7222 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 7223 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 7224 7225 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 7226 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 7227 7228 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 7229 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 7230} 7231#endif 7232 7233static struct dc_stream_state * 7234create_stream_for_sink(struct drm_connector *connector, 7235 const struct drm_display_mode *drm_mode, 7236 const struct dm_connector_state *dm_state, 7237 const struct dc_stream_state *old_stream, 7238 int requested_bpc) 7239{ 7240 struct drm_device *dev = connector->dev; 7241 struct amdgpu_dm_connector *aconnector = NULL; 7242 struct drm_display_mode *preferred_mode = NULL; 7243 const struct drm_connector_state *con_state = &dm_state->base; 7244 struct dc_stream_state *stream = NULL; 7245 struct drm_display_mode mode; 7246 struct drm_display_mode saved_mode; 7247 struct drm_display_mode *freesync_mode = NULL; 7248 bool native_mode_found = false; 7249 bool recalculate_timing = false; 7250 bool scale = dm_state->scaling != RMX_OFF; 7251 int mode_refresh; 7252 int preferred_refresh = 0; 7253 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 7254#if defined(CONFIG_DRM_AMD_DC_FP) 7255 struct dsc_dec_dpcd_caps dsc_caps; 7256#endif 7257 struct dc_link *link = NULL; 7258 struct dc_sink *sink = NULL; 7259 7260 drm_mode_init(&mode, drm_mode); 7261 memset(&saved_mode, 0, sizeof(saved_mode)); 7262 7263 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 7264 aconnector = NULL; 7265 aconnector = to_amdgpu_dm_connector(connector); 7266 link = aconnector->dc_link; 7267 } else { 7268 struct drm_writeback_connector *wbcon = NULL; 7269 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 7270 7271 wbcon = drm_connector_to_writeback(connector); 7272 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 7273 link = dm_wbcon->link; 7274 } 7275 7276 if (!aconnector || !aconnector->dc_sink) { 7277 sink = create_fake_sink(dev, link); 7278 if (!sink) 7279 return stream; 7280 7281 } else { 7282 sink = aconnector->dc_sink; 7283 dc_sink_retain(sink); 7284 } 7285 7286 stream = dc_create_stream_for_sink(sink); 7287 7288 if (stream == NULL) { 7289 drm_err(dev, "Failed to create stream for sink!\n"); 7290 goto finish; 7291 } 7292 7293 /* We leave this NULL for writeback connectors */ 7294 stream->dm_stream_context = aconnector; 7295 7296 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 7297 connector->display_info.hdmi.scdc.scrambling.low_rates; 7298 7299 list_for_each_entry(preferred_mode, &connector->modes, head) { 7300 /* Search for preferred mode */ 7301 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 7302 native_mode_found = true; 7303 break; 7304 } 7305 } 7306 if (!native_mode_found) 7307 preferred_mode = list_first_entry_or_null( 7308 &connector->modes, 7309 struct drm_display_mode, 7310 head); 7311 7312 mode_refresh = drm_mode_vrefresh(&mode); 7313 7314 if (preferred_mode == NULL) { 7315 /* 7316 * This may not be an error, the use case is when we have no 7317 * usermode calls to reset and set mode upon hotplug. In this 7318 * case, we call set mode ourselves to restore the previous mode 7319 * and the modelist may not be filled in time. 7320 */ 7321 drm_dbg_driver(dev, "No preferred mode found\n"); 7322 } else if (aconnector) { 7323 recalculate_timing = amdgpu_freesync_vid_mode && 7324 is_freesync_video_mode(&mode, aconnector); 7325 if (recalculate_timing) { 7326 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 7327 drm_mode_copy(&saved_mode, &mode); 7328 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 7329 drm_mode_copy(&mode, freesync_mode); 7330 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 7331 } else { 7332 decide_crtc_timing_for_drm_display_mode( 7333 &mode, preferred_mode, scale); 7334 7335 preferred_refresh = drm_mode_vrefresh(preferred_mode); 7336 } 7337 } 7338 7339 if (recalculate_timing) 7340 drm_mode_set_crtcinfo(&saved_mode, 0); 7341 7342 /* 7343 * If scaling is enabled and refresh rate didn't change 7344 * we copy the vic and polarities of the old timings 7345 */ 7346 if (!scale || mode_refresh != preferred_refresh) 7347 fill_stream_properties_from_drm_display_mode( 7348 stream, &mode, connector, con_state, NULL, 7349 requested_bpc); 7350 else 7351 fill_stream_properties_from_drm_display_mode( 7352 stream, &mode, connector, con_state, old_stream, 7353 requested_bpc); 7354 7355 /* The rest isn't needed for writeback connectors */ 7356 if (!aconnector) 7357 goto finish; 7358 7359 if (aconnector->timing_changed) { 7360 drm_dbg(aconnector->base.dev, 7361 "overriding timing for automated test, bpc %d, changing to %d\n", 7362 stream->timing.display_color_depth, 7363 aconnector->timing_requested->display_color_depth); 7364 stream->timing = *aconnector->timing_requested; 7365 } 7366 7367#if defined(CONFIG_DRM_AMD_DC_FP) 7368 /* SST DSC determination policy */ 7369 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 7370 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 7371 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 7372#endif 7373 7374 update_stream_scaling_settings(&mode, dm_state, stream); 7375 7376 fill_audio_info( 7377 &stream->audio_info, 7378 connector, 7379 sink); 7380 7381 update_stream_signal(stream, sink); 7382 7383 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 7384 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 7385 7386 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 7387 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 7388 stream->signal == SIGNAL_TYPE_EDP) { 7389 const struct dc_edid_caps *edid_caps; 7390 unsigned int disable_colorimetry = 0; 7391 7392 if (aconnector->dc_sink) { 7393 edid_caps = &aconnector->dc_sink->edid_caps; 7394 disable_colorimetry = edid_caps->panel_patch.disable_colorimetry; 7395 } 7396 7397 // 7398 // should decide stream support vsc sdp colorimetry capability 7399 // before building vsc info packet 7400 // 7401 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 7402 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && 7403 !disable_colorimetry; 7404 7405 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 7406 tf = TRANSFER_FUNC_GAMMA_22; 7407 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 7408 aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 7409 7410 } 7411finish: 7412 dc_sink_release(sink); 7413 7414 return stream; 7415} 7416 7417/** 7418 * amdgpu_dm_connector_poll - Poll a connector to see if it's connected to a display 7419 * @aconnector: DM connector to poll (owns @base drm_connector and @dc_link) 7420 * @force: if true, force polling even when DAC load detection was used 7421 * 7422 * Used for connectors that don't support HPD (hotplug detection) to 7423 * periodically check whether the connector is connected to a display. 7424 * 7425 * When connection was determined via DAC load detection, we avoid 7426 * re-running it on normal polls to prevent visible glitches, unless 7427 * @force is set. 7428 * 7429 * Return: The probed connector status (connected/disconnected/unknown). 7430 */ 7431static enum drm_connector_status 7432amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) 7433{ 7434 struct drm_connector *connector = &aconnector->base; 7435 struct drm_device *dev = connector->dev; 7436 struct amdgpu_device *adev = drm_to_adev(dev); 7437 struct dc_link *link = aconnector->dc_link; 7438 enum dc_connection_type conn_type = dc_connection_none; 7439 enum drm_connector_status status = connector_status_disconnected; 7440 7441 /* When we determined the connection using DAC load detection, 7442 * do NOT poll the connector do detect disconnect because 7443 * that would run DAC load detection again which can cause 7444 * visible visual glitches. 7445 * 7446 * Only allow to poll such a connector again when forcing. 7447 */ 7448 if (!force && link->local_sink && link->type == dc_connection_analog_load) 7449 return connector->status; 7450 7451 mutex_lock(&aconnector->hpd_lock); 7452 7453 if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && 7454 conn_type != dc_connection_none) { 7455 mutex_lock(&adev->dm.dc_lock); 7456 7457 /* Only call full link detection when a sink isn't created yet, 7458 * ie. just when the display is plugged in, otherwise we risk flickering. 7459 */ 7460 if (link->local_sink || 7461 dc_link_detect(link, DETECT_REASON_HPD)) 7462 status = connector_status_connected; 7463 7464 mutex_unlock(&adev->dm.dc_lock); 7465 } 7466 7467 if (connector->status != status) { 7468 if (status == connector_status_disconnected) { 7469 if (link->local_sink) 7470 dc_sink_release(link->local_sink); 7471 7472 link->local_sink = NULL; 7473 link->dpcd_sink_count = 0; 7474 link->type = dc_connection_none; 7475 } 7476 7477 amdgpu_dm_update_connector_after_detect(aconnector); 7478 } 7479 7480 mutex_unlock(&aconnector->hpd_lock); 7481 return status; 7482} 7483 7484/** 7485 * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display 7486 * 7487 * A connector is considered connected when it has a sink that is not NULL. 7488 * For connectors that support HPD (hotplug detection), the connection is 7489 * handled in the HPD interrupt. 7490 * For connectors that may not support HPD, such as analog connectors, 7491 * DRM will call this function repeatedly to poll them. 7492 * 7493 * Notes: 7494 * 1. This interface is NOT called in context of HPD irq. 7495 * 2. This interface *is called* in context of user-mode ioctl. Which 7496 * makes it a bad place for *any* MST-related activity. 7497 * 7498 * @connector: The DRM connector we are checking. We convert it to 7499 * amdgpu_dm_connector so we can read the DC link and state. 7500 * @force: If true, do a full detect again. This is used even when 7501 * a lighter check would normally be used to avoid flicker. 7502 * 7503 * Return: The connector status (connected, disconnected, or unknown). 7504 * 7505 */ 7506static enum drm_connector_status 7507amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 7508{ 7509 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7510 7511 update_subconnector_property(aconnector); 7512 7513 if (aconnector->base.force == DRM_FORCE_ON || 7514 aconnector->base.force == DRM_FORCE_ON_DIGITAL) 7515 return connector_status_connected; 7516 else if (aconnector->base.force == DRM_FORCE_OFF) 7517 return connector_status_disconnected; 7518 7519 /* Poll analog connectors and only when either 7520 * disconnected or connected to an analog display. 7521 */ 7522 if (drm_kms_helper_is_poll_worker() && 7523 dc_connector_supports_analog(aconnector->dc_link->link_id.id) && 7524 (!aconnector->dc_sink || aconnector->dc_sink->edid_caps.analog)) 7525 return amdgpu_dm_connector_poll(aconnector, force); 7526 7527 return (aconnector->dc_sink ? connector_status_connected : 7528 connector_status_disconnected); 7529} 7530 7531int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 7532 struct drm_connector_state *connector_state, 7533 struct drm_property *property, 7534 uint64_t val) 7535{ 7536 struct drm_device *dev = connector->dev; 7537 struct amdgpu_device *adev = drm_to_adev(dev); 7538 struct dm_connector_state *dm_old_state = 7539 to_dm_connector_state(connector->state); 7540 struct dm_connector_state *dm_new_state = 7541 to_dm_connector_state(connector_state); 7542 7543 int ret = -EINVAL; 7544 7545 if (property == dev->mode_config.scaling_mode_property) { 7546 enum amdgpu_rmx_type rmx_type; 7547 7548 switch (val) { 7549 case DRM_MODE_SCALE_CENTER: 7550 rmx_type = RMX_CENTER; 7551 break; 7552 case DRM_MODE_SCALE_ASPECT: 7553 rmx_type = RMX_ASPECT; 7554 break; 7555 case DRM_MODE_SCALE_FULLSCREEN: 7556 rmx_type = RMX_FULL; 7557 break; 7558 case DRM_MODE_SCALE_NONE: 7559 default: 7560 rmx_type = RMX_OFF; 7561 break; 7562 } 7563 7564 if (dm_old_state->scaling == rmx_type) 7565 return 0; 7566 7567 dm_new_state->scaling = rmx_type; 7568 ret = 0; 7569 } else if (property == adev->mode_info.underscan_hborder_property) { 7570 dm_new_state->underscan_hborder = val; 7571 ret = 0; 7572 } else if (property == adev->mode_info.underscan_vborder_property) { 7573 dm_new_state->underscan_vborder = val; 7574 ret = 0; 7575 } else if (property == adev->mode_info.underscan_property) { 7576 dm_new_state->underscan_enable = val; 7577 ret = 0; 7578 } else if (property == adev->mode_info.abm_level_property) { 7579 switch (val) { 7580 case ABM_SYSFS_CONTROL: 7581 dm_new_state->abm_sysfs_forbidden = false; 7582 break; 7583 case ABM_LEVEL_OFF: 7584 dm_new_state->abm_sysfs_forbidden = true; 7585 dm_new_state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 7586 break; 7587 default: 7588 dm_new_state->abm_sysfs_forbidden = true; 7589 dm_new_state->abm_level = val; 7590 } 7591 ret = 0; 7592 } 7593 7594 return ret; 7595} 7596 7597int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 7598 const struct drm_connector_state *state, 7599 struct drm_property *property, 7600 uint64_t *val) 7601{ 7602 struct drm_device *dev = connector->dev; 7603 struct amdgpu_device *adev = drm_to_adev(dev); 7604 struct dm_connector_state *dm_state = 7605 to_dm_connector_state(state); 7606 int ret = -EINVAL; 7607 7608 if (property == dev->mode_config.scaling_mode_property) { 7609 switch (dm_state->scaling) { 7610 case RMX_CENTER: 7611 *val = DRM_MODE_SCALE_CENTER; 7612 break; 7613 case RMX_ASPECT: 7614 *val = DRM_MODE_SCALE_ASPECT; 7615 break; 7616 case RMX_FULL: 7617 *val = DRM_MODE_SCALE_FULLSCREEN; 7618 break; 7619 case RMX_OFF: 7620 default: 7621 *val = DRM_MODE_SCALE_NONE; 7622 break; 7623 } 7624 ret = 0; 7625 } else if (property == adev->mode_info.underscan_hborder_property) { 7626 *val = dm_state->underscan_hborder; 7627 ret = 0; 7628 } else if (property == adev->mode_info.underscan_vborder_property) { 7629 *val = dm_state->underscan_vborder; 7630 ret = 0; 7631 } else if (property == adev->mode_info.underscan_property) { 7632 *val = dm_state->underscan_enable; 7633 ret = 0; 7634 } else if (property == adev->mode_info.abm_level_property) { 7635 if (!dm_state->abm_sysfs_forbidden) 7636 *val = ABM_SYSFS_CONTROL; 7637 else 7638 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 7639 dm_state->abm_level : 0; 7640 ret = 0; 7641 } 7642 7643 return ret; 7644} 7645 7646/** 7647 * DOC: panel power savings 7648 * 7649 * The display manager allows you to set your desired **panel power savings** 7650 * level (between 0-4, with 0 representing off), e.g. using the following:: 7651 * 7652 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings 7653 * 7654 * Modifying this value can have implications on color accuracy, so tread 7655 * carefully. 7656 */ 7657 7658static ssize_t panel_power_savings_show(struct device *device, 7659 struct device_attribute *attr, 7660 char *buf) 7661{ 7662 struct drm_connector *connector = dev_get_drvdata(device); 7663 struct drm_device *dev = connector->dev; 7664 u8 val; 7665 7666 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 7667 val = to_dm_connector_state(connector->state)->abm_level == 7668 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : 7669 to_dm_connector_state(connector->state)->abm_level; 7670 drm_modeset_unlock(&dev->mode_config.connection_mutex); 7671 7672 return sysfs_emit(buf, "%u\n", val); 7673} 7674 7675static ssize_t panel_power_savings_store(struct device *device, 7676 struct device_attribute *attr, 7677 const char *buf, size_t count) 7678{ 7679 struct drm_connector *connector = dev_get_drvdata(device); 7680 struct drm_device *dev = connector->dev; 7681 long val; 7682 int ret; 7683 7684 ret = kstrtol(buf, 0, &val); 7685 7686 if (ret) 7687 return ret; 7688 7689 if (val < 0 || val > 4) 7690 return -EINVAL; 7691 7692 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 7693 if (to_dm_connector_state(connector->state)->abm_sysfs_forbidden) 7694 ret = -EBUSY; 7695 else 7696 to_dm_connector_state(connector->state)->abm_level = val ?: 7697 ABM_LEVEL_IMMEDIATE_DISABLE; 7698 drm_modeset_unlock(&dev->mode_config.connection_mutex); 7699 7700 if (ret) 7701 return ret; 7702 7703 drm_kms_helper_hotplug_event(dev); 7704 7705 return count; 7706} 7707 7708static DEVICE_ATTR_RW(panel_power_savings); 7709 7710static struct attribute *amdgpu_attrs[] = { 7711 &dev_attr_panel_power_savings.attr, 7712 NULL 7713}; 7714 7715static const struct attribute_group amdgpu_group = { 7716 .name = "amdgpu", 7717 .attrs = amdgpu_attrs 7718}; 7719 7720static bool 7721amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) 7722{ 7723 if (amdgpu_dm_abm_level >= 0) 7724 return false; 7725 7726 if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 7727 return false; 7728 7729 /* check for OLED panels */ 7730 if (amdgpu_dm_connector->bl_idx >= 0) { 7731 struct drm_device *drm = amdgpu_dm_connector->base.dev; 7732 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 7733 struct amdgpu_dm_backlight_caps *caps; 7734 7735 caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx]; 7736 if (caps->aux_support) 7737 return false; 7738 } 7739 7740 return true; 7741} 7742 7743static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 7744{ 7745 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 7746 7747 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) 7748 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 7749 7750 cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); 7751 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 7752} 7753 7754static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 7755{ 7756 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7757 struct amdgpu_device *adev = drm_to_adev(connector->dev); 7758 struct amdgpu_display_manager *dm = &adev->dm; 7759 7760 /* 7761 * Call only if mst_mgr was initialized before since it's not done 7762 * for all connector types. 7763 */ 7764 if (aconnector->mst_mgr.dev) 7765 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 7766 7767 /* Cancel and flush any pending HDMI HPD debounce work */ 7768 if (aconnector->hdmi_hpd_debounce_delay_ms) { 7769 cancel_delayed_work_sync(&aconnector->hdmi_hpd_debounce_work); 7770 if (aconnector->hdmi_prev_sink) { 7771 dc_sink_release(aconnector->hdmi_prev_sink); 7772 aconnector->hdmi_prev_sink = NULL; 7773 } 7774 } 7775 7776 if (aconnector->bl_idx != -1) { 7777 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 7778 dm->backlight_dev[aconnector->bl_idx] = NULL; 7779 } 7780 7781 if (aconnector->dc_em_sink) 7782 dc_sink_release(aconnector->dc_em_sink); 7783 aconnector->dc_em_sink = NULL; 7784 if (aconnector->dc_sink) 7785 dc_sink_release(aconnector->dc_sink); 7786 aconnector->dc_sink = NULL; 7787 7788 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 7789 drm_connector_unregister(connector); 7790 drm_connector_cleanup(connector); 7791 kfree(aconnector->dm_dp_aux.aux.name); 7792 7793 kfree(connector); 7794} 7795 7796void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 7797{ 7798 struct dm_connector_state *state = 7799 to_dm_connector_state(connector->state); 7800 7801 if (connector->state) 7802 __drm_atomic_helper_connector_destroy_state(connector->state); 7803 7804 kfree(state); 7805 7806 state = kzalloc(sizeof(*state), GFP_KERNEL); 7807 7808 if (state) { 7809 state->scaling = RMX_OFF; 7810 state->underscan_enable = false; 7811 state->underscan_hborder = 0; 7812 state->underscan_vborder = 0; 7813 state->base.max_requested_bpc = 8; 7814 state->vcpi_slots = 0; 7815 state->pbn = 0; 7816 7817 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 7818 if (amdgpu_dm_abm_level <= 0) 7819 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 7820 else 7821 state->abm_level = amdgpu_dm_abm_level; 7822 } 7823 7824 __drm_atomic_helper_connector_reset(connector, &state->base); 7825 } 7826} 7827 7828struct drm_connector_state * 7829amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 7830{ 7831 struct dm_connector_state *state = 7832 to_dm_connector_state(connector->state); 7833 7834 struct dm_connector_state *new_state = 7835 kmemdup(state, sizeof(*state), GFP_KERNEL); 7836 7837 if (!new_state) 7838 return NULL; 7839 7840 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 7841 7842 new_state->freesync_capable = state->freesync_capable; 7843 new_state->abm_level = state->abm_level; 7844 new_state->scaling = state->scaling; 7845 new_state->underscan_enable = state->underscan_enable; 7846 new_state->underscan_hborder = state->underscan_hborder; 7847 new_state->underscan_vborder = state->underscan_vborder; 7848 new_state->vcpi_slots = state->vcpi_slots; 7849 new_state->pbn = state->pbn; 7850 return &new_state->base; 7851} 7852 7853static int 7854amdgpu_dm_connector_late_register(struct drm_connector *connector) 7855{ 7856 struct amdgpu_dm_connector *amdgpu_dm_connector = 7857 to_amdgpu_dm_connector(connector); 7858 int r; 7859 7860 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { 7861 r = sysfs_create_group(&connector->kdev->kobj, 7862 &amdgpu_group); 7863 if (r) 7864 return r; 7865 } 7866 7867 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 7868 7869 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 7870 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 7871 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 7872 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 7873 if (r) 7874 return r; 7875 } 7876 7877#if defined(CONFIG_DEBUG_FS) 7878 connector_debugfs_init(amdgpu_dm_connector); 7879#endif 7880 7881 return 0; 7882} 7883 7884static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 7885{ 7886 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7887 struct dc_link *dc_link = aconnector->dc_link; 7888 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 7889 const struct drm_edid *drm_edid; 7890 struct i2c_adapter *ddc; 7891 struct drm_device *dev = connector->dev; 7892 7893 if (dc_link && dc_link->aux_mode) 7894 ddc = &aconnector->dm_dp_aux.aux.ddc; 7895 else 7896 ddc = &aconnector->i2c->base; 7897 7898 drm_edid = drm_edid_read_ddc(connector, ddc); 7899 drm_edid_connector_update(connector, drm_edid); 7900 if (!drm_edid) { 7901 drm_err(dev, "No EDID found on connector: %s.\n", connector->name); 7902 return; 7903 } 7904 7905 aconnector->drm_edid = drm_edid; 7906 /* Update emulated (virtual) sink's EDID */ 7907 if (dc_em_sink && dc_link) { 7908 // FIXME: Get rid of drm_edid_raw() 7909 const struct edid *edid = drm_edid_raw(drm_edid); 7910 7911 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 7912 memmove(dc_em_sink->dc_edid.raw_edid, edid, 7913 (edid->extensions + 1) * EDID_LENGTH); 7914 dm_helpers_parse_edid_caps( 7915 dc_link, 7916 &dc_em_sink->dc_edid, 7917 &dc_em_sink->edid_caps); 7918 } 7919} 7920 7921static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 7922 .reset = amdgpu_dm_connector_funcs_reset, 7923 .detect = amdgpu_dm_connector_detect, 7924 .fill_modes = drm_helper_probe_single_connector_modes, 7925 .destroy = amdgpu_dm_connector_destroy, 7926 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 7927 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 7928 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 7929 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 7930 .late_register = amdgpu_dm_connector_late_register, 7931 .early_unregister = amdgpu_dm_connector_unregister, 7932 .force = amdgpu_dm_connector_funcs_force 7933}; 7934 7935static int get_modes(struct drm_connector *connector) 7936{ 7937 return amdgpu_dm_connector_get_modes(connector); 7938} 7939 7940static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 7941{ 7942 struct drm_connector *connector = &aconnector->base; 7943 struct dc_link *dc_link = aconnector->dc_link; 7944 struct dc_sink_init_data init_params = { 7945 .link = aconnector->dc_link, 7946 .sink_signal = SIGNAL_TYPE_VIRTUAL 7947 }; 7948 const struct drm_edid *drm_edid; 7949 const struct edid *edid; 7950 struct i2c_adapter *ddc; 7951 7952 if (dc_link && dc_link->aux_mode) 7953 ddc = &aconnector->dm_dp_aux.aux.ddc; 7954 else 7955 ddc = &aconnector->i2c->base; 7956 7957 drm_edid = drm_edid_read_ddc(connector, ddc); 7958 drm_edid_connector_update(connector, drm_edid); 7959 if (!drm_edid) { 7960 drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); 7961 return; 7962 } 7963 7964 if (connector->display_info.is_hdmi) 7965 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 7966 7967 aconnector->drm_edid = drm_edid; 7968 7969 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() 7970 aconnector->dc_em_sink = dc_link_add_remote_sink( 7971 aconnector->dc_link, 7972 (uint8_t *)edid, 7973 (edid->extensions + 1) * EDID_LENGTH, 7974 &init_params); 7975 7976 if (aconnector->base.force == DRM_FORCE_ON) { 7977 aconnector->dc_sink = aconnector->dc_link->local_sink ? 7978 aconnector->dc_link->local_sink : 7979 aconnector->dc_em_sink; 7980 if (aconnector->dc_sink) 7981 dc_sink_retain(aconnector->dc_sink); 7982 } 7983} 7984 7985static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 7986{ 7987 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 7988 7989 /* 7990 * In case of headless boot with force on for DP managed connector 7991 * Those settings have to be != 0 to get initial modeset 7992 */ 7993 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 7994 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 7995 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 7996 } 7997 7998 create_eml_sink(aconnector); 7999} 8000 8001static enum dc_status dm_validate_stream_and_context(struct dc *dc, 8002 struct dc_stream_state *stream) 8003{ 8004 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 8005 struct dc_plane_state *dc_plane_state = NULL; 8006 struct dc_state *dc_state = NULL; 8007 8008 if (!stream) 8009 goto cleanup; 8010 8011 dc_plane_state = dc_create_plane_state(dc); 8012 if (!dc_plane_state) 8013 goto cleanup; 8014 8015 dc_state = dc_state_create(dc, NULL); 8016 if (!dc_state) 8017 goto cleanup; 8018 8019 /* populate stream to plane */ 8020 dc_plane_state->src_rect.height = stream->src.height; 8021 dc_plane_state->src_rect.width = stream->src.width; 8022 dc_plane_state->dst_rect.height = stream->src.height; 8023 dc_plane_state->dst_rect.width = stream->src.width; 8024 dc_plane_state->clip_rect.height = stream->src.height; 8025 dc_plane_state->clip_rect.width = stream->src.width; 8026 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 8027 dc_plane_state->plane_size.surface_size.height = stream->src.height; 8028 dc_plane_state->plane_size.surface_size.width = stream->src.width; 8029 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 8030 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 8031 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 8032 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 8033 dc_plane_state->rotation = ROTATION_ANGLE_0; 8034 dc_plane_state->is_tiling_rotated = false; 8035 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 8036 8037 dc_result = dc_validate_stream(dc, stream); 8038 if (dc_result == DC_OK) 8039 dc_result = dc_validate_plane(dc, dc_plane_state); 8040 8041 if (dc_result == DC_OK) 8042 dc_result = dc_state_add_stream(dc, dc_state, stream); 8043 8044 if (dc_result == DC_OK && !dc_state_add_plane( 8045 dc, 8046 stream, 8047 dc_plane_state, 8048 dc_state)) 8049 dc_result = DC_FAIL_ATTACH_SURFACES; 8050 8051 if (dc_result == DC_OK) 8052 dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY); 8053 8054cleanup: 8055 if (dc_state) 8056 dc_state_release(dc_state); 8057 8058 if (dc_plane_state) 8059 dc_plane_state_release(dc_plane_state); 8060 8061 return dc_result; 8062} 8063 8064struct dc_stream_state * 8065create_validate_stream_for_sink(struct drm_connector *connector, 8066 const struct drm_display_mode *drm_mode, 8067 const struct dm_connector_state *dm_state, 8068 const struct dc_stream_state *old_stream) 8069{ 8070 struct amdgpu_dm_connector *aconnector = NULL; 8071 struct amdgpu_device *adev = drm_to_adev(connector->dev); 8072 struct dc_stream_state *stream; 8073 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 8074 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 8075 enum dc_status dc_result = DC_OK; 8076 uint8_t bpc_limit = 6; 8077 8078 if (!dm_state) 8079 return NULL; 8080 8081 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 8082 aconnector = to_amdgpu_dm_connector(connector); 8083 8084 if (aconnector && 8085 (aconnector->dc_link->connector_signal == SIGNAL_TYPE_HDMI_TYPE_A || 8086 aconnector->dc_link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 8087 bpc_limit = 8; 8088 8089 do { 8090 drm_dbg_kms(connector->dev, "Trying with %d bpc\n", requested_bpc); 8091 stream = create_stream_for_sink(connector, drm_mode, 8092 dm_state, old_stream, 8093 requested_bpc); 8094 if (stream == NULL) { 8095 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n"); 8096 break; 8097 } 8098 8099 dc_result = dc_validate_stream(adev->dm.dc, stream); 8100 8101 if (!aconnector) /* writeback connector */ 8102 return stream; 8103 8104 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 8105 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 8106 8107 if (dc_result == DC_OK) 8108 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 8109 8110 if (dc_result != DC_OK) { 8111 DRM_DEBUG_KMS("Pruned mode %d x %d (clk %d) %s %s -- %s\n", 8112 drm_mode->hdisplay, 8113 drm_mode->vdisplay, 8114 drm_mode->clock, 8115 dc_pixel_encoding_to_str(stream->timing.pixel_encoding), 8116 dc_color_depth_to_str(stream->timing.display_color_depth), 8117 dc_status_to_str(dc_result)); 8118 8119 dc_stream_release(stream); 8120 stream = NULL; 8121 requested_bpc -= 2; /* lower bpc to retry validation */ 8122 } 8123 8124 } while (stream == NULL && requested_bpc >= bpc_limit); 8125 8126 switch (dc_result) { 8127 /* 8128 * If we failed to validate DP bandwidth stream with the requested RGB color depth, 8129 * we try to fallback and configure in order: 8130 * YUV422 (8bpc, 6bpc) 8131 * YUV420 (8bpc, 6bpc) 8132 */ 8133 case DC_FAIL_ENC_VALIDATE: 8134 case DC_EXCEED_DONGLE_CAP: 8135 case DC_NO_DP_LINK_BANDWIDTH: 8136 /* recursively entered twice and already tried both YUV422 and YUV420 */ 8137 if (aconnector->force_yuv422_output && aconnector->force_yuv420_output) 8138 break; 8139 /* first failure; try YUV422 */ 8140 if (!aconnector->force_yuv422_output) { 8141 drm_dbg_kms(connector->dev, "%s:%d Validation failed with %d, retrying w/ YUV422\n", 8142 __func__, __LINE__, dc_result); 8143 aconnector->force_yuv422_output = true; 8144 /* recursively entered and YUV422 failed, try YUV420 */ 8145 } else if (!aconnector->force_yuv420_output) { 8146 drm_dbg_kms(connector->dev, "%s:%d Validation failed with %d, retrying w/ YUV420\n", 8147 __func__, __LINE__, dc_result); 8148 aconnector->force_yuv420_output = true; 8149 } 8150 stream = create_validate_stream_for_sink(connector, drm_mode, 8151 dm_state, old_stream); 8152 aconnector->force_yuv422_output = false; 8153 aconnector->force_yuv420_output = false; 8154 break; 8155 case DC_OK: 8156 break; 8157 default: 8158 drm_dbg_kms(connector->dev, "%s:%d Unhandled validation failure %d\n", 8159 __func__, __LINE__, dc_result); 8160 break; 8161 } 8162 8163 return stream; 8164} 8165 8166enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 8167 const struct drm_display_mode *mode) 8168{ 8169 int result = MODE_ERROR; 8170 struct dc_sink *dc_sink; 8171 struct drm_display_mode *test_mode; 8172 /* TODO: Unhardcode stream count */ 8173 struct dc_stream_state *stream; 8174 /* we always have an amdgpu_dm_connector here since we got 8175 * here via the amdgpu_dm_connector_helper_funcs 8176 */ 8177 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8178 8179 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 8180 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 8181 return result; 8182 8183 /* 8184 * Only run this the first time mode_valid is called to initilialize 8185 * EDID mgmt 8186 */ 8187 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 8188 !aconnector->dc_em_sink) 8189 handle_edid_mgmt(aconnector); 8190 8191 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 8192 8193 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 8194 aconnector->base.force != DRM_FORCE_ON) { 8195 drm_err(connector->dev, "dc_sink is NULL!\n"); 8196 goto fail; 8197 } 8198 8199 test_mode = drm_mode_duplicate(connector->dev, mode); 8200 if (!test_mode) 8201 goto fail; 8202 8203 drm_mode_set_crtcinfo(test_mode, 0); 8204 8205 stream = create_validate_stream_for_sink(connector, test_mode, 8206 to_dm_connector_state(connector->state), 8207 NULL); 8208 drm_mode_destroy(connector->dev, test_mode); 8209 if (stream) { 8210 dc_stream_release(stream); 8211 result = MODE_OK; 8212 } 8213 8214fail: 8215 /* TODO: error handling*/ 8216 return result; 8217} 8218 8219static int fill_hdr_info_packet(const struct drm_connector_state *state, 8220 struct dc_info_packet *out) 8221{ 8222 struct hdmi_drm_infoframe frame; 8223 unsigned char buf[30]; /* 26 + 4 */ 8224 ssize_t len; 8225 int ret, i; 8226 8227 memset(out, 0, sizeof(*out)); 8228 8229 if (!state->hdr_output_metadata) 8230 return 0; 8231 8232 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 8233 if (ret) 8234 return ret; 8235 8236 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 8237 if (len < 0) 8238 return (int)len; 8239 8240 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 8241 if (len != 30) 8242 return -EINVAL; 8243 8244 /* Prepare the infopacket for DC. */ 8245 switch (state->connector->connector_type) { 8246 case DRM_MODE_CONNECTOR_HDMIA: 8247 out->hb0 = 0x87; /* type */ 8248 out->hb1 = 0x01; /* version */ 8249 out->hb2 = 0x1A; /* length */ 8250 out->sb[0] = buf[3]; /* checksum */ 8251 i = 1; 8252 break; 8253 8254 case DRM_MODE_CONNECTOR_DisplayPort: 8255 case DRM_MODE_CONNECTOR_eDP: 8256 out->hb0 = 0x00; /* sdp id, zero */ 8257 out->hb1 = 0x87; /* type */ 8258 out->hb2 = 0x1D; /* payload len - 1 */ 8259 out->hb3 = (0x13 << 2); /* sdp version */ 8260 out->sb[0] = 0x01; /* version */ 8261 out->sb[1] = 0x1A; /* length */ 8262 i = 2; 8263 break; 8264 8265 default: 8266 return -EINVAL; 8267 } 8268 8269 memcpy(&out->sb[i], &buf[4], 26); 8270 out->valid = true; 8271 8272 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 8273 sizeof(out->sb), false); 8274 8275 return 0; 8276} 8277 8278static int 8279amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 8280 struct drm_atomic_state *state) 8281{ 8282 struct drm_connector_state *new_con_state = 8283 drm_atomic_get_new_connector_state(state, conn); 8284 struct drm_connector_state *old_con_state = 8285 drm_atomic_get_old_connector_state(state, conn); 8286 struct drm_crtc *crtc = new_con_state->crtc; 8287 struct drm_crtc_state *new_crtc_state; 8288 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 8289 int ret; 8290 8291 if (WARN_ON(unlikely(!old_con_state || !new_con_state))) 8292 return -EINVAL; 8293 8294 trace_amdgpu_dm_connector_atomic_check(new_con_state); 8295 8296 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 8297 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 8298 if (ret < 0) 8299 return ret; 8300 } 8301 8302 if (!crtc) 8303 return 0; 8304 8305 if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { 8306 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 8307 if (IS_ERR(new_crtc_state)) 8308 return PTR_ERR(new_crtc_state); 8309 8310 new_crtc_state->mode_changed = true; 8311 } 8312 8313 if (new_con_state->colorspace != old_con_state->colorspace) { 8314 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 8315 if (IS_ERR(new_crtc_state)) 8316 return PTR_ERR(new_crtc_state); 8317 8318 new_crtc_state->mode_changed = true; 8319 } 8320 8321 if (new_con_state->content_type != old_con_state->content_type) { 8322 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 8323 if (IS_ERR(new_crtc_state)) 8324 return PTR_ERR(new_crtc_state); 8325 8326 new_crtc_state->mode_changed = true; 8327 } 8328 8329 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 8330 struct dc_info_packet hdr_infopacket; 8331 8332 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 8333 if (ret) 8334 return ret; 8335 8336 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 8337 if (IS_ERR(new_crtc_state)) 8338 return PTR_ERR(new_crtc_state); 8339 8340 /* 8341 * DC considers the stream backends changed if the 8342 * static metadata changes. Forcing the modeset also 8343 * gives a simple way for userspace to switch from 8344 * 8bpc to 10bpc when setting the metadata to enter 8345 * or exit HDR. 8346 * 8347 * Changing the static metadata after it's been 8348 * set is permissible, however. So only force a 8349 * modeset if we're entering or exiting HDR. 8350 */ 8351 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 8352 !old_con_state->hdr_output_metadata || 8353 !new_con_state->hdr_output_metadata; 8354 } 8355 8356 return 0; 8357} 8358 8359static const struct drm_connector_helper_funcs 8360amdgpu_dm_connector_helper_funcs = { 8361 /* 8362 * If hotplugging a second bigger display in FB Con mode, bigger resolution 8363 * modes will be filtered by drm_mode_validate_size(), and those modes 8364 * are missing after user start lightdm. So we need to renew modes list. 8365 * in get_modes call back, not just return the modes count 8366 */ 8367 .get_modes = get_modes, 8368 .mode_valid = amdgpu_dm_connector_mode_valid, 8369 .atomic_check = amdgpu_dm_connector_atomic_check, 8370}; 8371 8372static void dm_encoder_helper_disable(struct drm_encoder *encoder) 8373{ 8374 8375} 8376 8377int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 8378{ 8379 switch (display_color_depth) { 8380 case COLOR_DEPTH_666: 8381 return 6; 8382 case COLOR_DEPTH_888: 8383 return 8; 8384 case COLOR_DEPTH_101010: 8385 return 10; 8386 case COLOR_DEPTH_121212: 8387 return 12; 8388 case COLOR_DEPTH_141414: 8389 return 14; 8390 case COLOR_DEPTH_161616: 8391 return 16; 8392 default: 8393 break; 8394 } 8395 return 0; 8396} 8397 8398static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 8399 struct drm_crtc_state *crtc_state, 8400 struct drm_connector_state *conn_state) 8401{ 8402 struct drm_atomic_state *state = crtc_state->state; 8403 struct drm_connector *connector = conn_state->connector; 8404 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8405 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 8406 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 8407 struct drm_dp_mst_topology_mgr *mst_mgr; 8408 struct drm_dp_mst_port *mst_port; 8409 struct drm_dp_mst_topology_state *mst_state; 8410 enum dc_color_depth color_depth; 8411 int clock, bpp = 0; 8412 bool is_y420 = false; 8413 8414 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 8415 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 8416 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 8417 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 8418 enum drm_mode_status result; 8419 8420 result = drm_crtc_helper_mode_valid_fixed(encoder->crtc, adjusted_mode, native_mode); 8421 if (result != MODE_OK && dm_new_connector_state->scaling == RMX_OFF) { 8422 drm_dbg_driver(encoder->dev, 8423 "mode %dx%d@%dHz is not native, enabling scaling\n", 8424 adjusted_mode->hdisplay, adjusted_mode->vdisplay, 8425 drm_mode_vrefresh(adjusted_mode)); 8426 dm_new_connector_state->scaling = RMX_ASPECT; 8427 } 8428 return 0; 8429 } 8430 8431 if (!aconnector->mst_output_port) 8432 return 0; 8433 8434 mst_port = aconnector->mst_output_port; 8435 mst_mgr = &aconnector->mst_root->mst_mgr; 8436 8437 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 8438 return 0; 8439 8440 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 8441 if (IS_ERR(mst_state)) 8442 return PTR_ERR(mst_state); 8443 8444 mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 8445 8446 if (!state->duplicated) { 8447 int max_bpc = conn_state->max_requested_bpc; 8448 8449 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 8450 aconnector->force_yuv420_output; 8451 color_depth = convert_color_depth_from_display_info(connector, 8452 is_y420, 8453 max_bpc); 8454 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 8455 clock = adjusted_mode->clock; 8456 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 8457 } 8458 8459 dm_new_connector_state->vcpi_slots = 8460 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 8461 dm_new_connector_state->pbn); 8462 if (dm_new_connector_state->vcpi_slots < 0) { 8463 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 8464 return dm_new_connector_state->vcpi_slots; 8465 } 8466 return 0; 8467} 8468 8469const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 8470 .disable = dm_encoder_helper_disable, 8471 .atomic_check = dm_encoder_helper_atomic_check 8472}; 8473 8474static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 8475 struct dc_state *dc_state, 8476 struct dsc_mst_fairness_vars *vars) 8477{ 8478 struct dc_stream_state *stream = NULL; 8479 struct drm_connector *connector; 8480 struct drm_connector_state *new_con_state; 8481 struct amdgpu_dm_connector *aconnector; 8482 struct dm_connector_state *dm_conn_state; 8483 int i, j, ret; 8484 int vcpi, pbn_div, pbn = 0, slot_num = 0; 8485 8486 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8487 8488 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 8489 continue; 8490 8491 aconnector = to_amdgpu_dm_connector(connector); 8492 8493 if (!aconnector->mst_output_port) 8494 continue; 8495 8496 if (!new_con_state || !new_con_state->crtc) 8497 continue; 8498 8499 dm_conn_state = to_dm_connector_state(new_con_state); 8500 8501 for (j = 0; j < dc_state->stream_count; j++) { 8502 stream = dc_state->streams[j]; 8503 if (!stream) 8504 continue; 8505 8506 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 8507 break; 8508 8509 stream = NULL; 8510 } 8511 8512 if (!stream) 8513 continue; 8514 8515 pbn_div = dm_mst_get_pbn_divider(stream->link); 8516 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 8517 for (j = 0; j < dc_state->stream_count; j++) { 8518 if (vars[j].aconnector == aconnector) { 8519 pbn = vars[j].pbn; 8520 break; 8521 } 8522 } 8523 8524 if (j == dc_state->stream_count || pbn_div == 0) 8525 continue; 8526 8527 slot_num = DIV_ROUND_UP(pbn, pbn_div); 8528 8529 if (stream->timing.flags.DSC != 1) { 8530 dm_conn_state->pbn = pbn; 8531 dm_conn_state->vcpi_slots = slot_num; 8532 8533 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 8534 dm_conn_state->pbn, false); 8535 if (ret < 0) 8536 return ret; 8537 8538 continue; 8539 } 8540 8541 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 8542 if (vcpi < 0) 8543 return vcpi; 8544 8545 dm_conn_state->pbn = pbn; 8546 dm_conn_state->vcpi_slots = vcpi; 8547 } 8548 return 0; 8549} 8550 8551static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) 8552{ 8553 switch (st) { 8554 case SIGNAL_TYPE_HDMI_TYPE_A: 8555 return DRM_MODE_CONNECTOR_HDMIA; 8556 case SIGNAL_TYPE_EDP: 8557 return DRM_MODE_CONNECTOR_eDP; 8558 case SIGNAL_TYPE_LVDS: 8559 return DRM_MODE_CONNECTOR_LVDS; 8560 case SIGNAL_TYPE_RGB: 8561 return DRM_MODE_CONNECTOR_VGA; 8562 case SIGNAL_TYPE_DISPLAY_PORT: 8563 case SIGNAL_TYPE_DISPLAY_PORT_MST: 8564 return DRM_MODE_CONNECTOR_DisplayPort; 8565 case SIGNAL_TYPE_DVI_DUAL_LINK: 8566 case SIGNAL_TYPE_DVI_SINGLE_LINK: 8567 if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII || 8568 connector_id == CONNECTOR_ID_DUAL_LINK_DVII) 8569 return DRM_MODE_CONNECTOR_DVII; 8570 8571 return DRM_MODE_CONNECTOR_DVID; 8572 case SIGNAL_TYPE_VIRTUAL: 8573 return DRM_MODE_CONNECTOR_VIRTUAL; 8574 8575 default: 8576 return DRM_MODE_CONNECTOR_Unknown; 8577 } 8578} 8579 8580static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 8581{ 8582 struct drm_encoder *encoder; 8583 8584 /* There is only one encoder per connector */ 8585 drm_connector_for_each_possible_encoder(connector, encoder) 8586 return encoder; 8587 8588 return NULL; 8589} 8590 8591static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 8592{ 8593 struct drm_encoder *encoder; 8594 struct amdgpu_encoder *amdgpu_encoder; 8595 8596 encoder = amdgpu_dm_connector_to_encoder(connector); 8597 8598 if (encoder == NULL) 8599 return; 8600 8601 amdgpu_encoder = to_amdgpu_encoder(encoder); 8602 8603 amdgpu_encoder->native_mode.clock = 0; 8604 8605 if (!list_empty(&connector->probed_modes)) { 8606 struct drm_display_mode *preferred_mode = NULL; 8607 8608 list_for_each_entry(preferred_mode, 8609 &connector->probed_modes, 8610 head) { 8611 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 8612 amdgpu_encoder->native_mode = *preferred_mode; 8613 8614 break; 8615 } 8616 8617 } 8618} 8619 8620static struct drm_display_mode * 8621amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 8622 const char *name, 8623 int hdisplay, int vdisplay) 8624{ 8625 struct drm_device *dev = encoder->dev; 8626 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 8627 struct drm_display_mode *mode = NULL; 8628 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 8629 8630 mode = drm_mode_duplicate(dev, native_mode); 8631 8632 if (mode == NULL) 8633 return NULL; 8634 8635 mode->hdisplay = hdisplay; 8636 mode->vdisplay = vdisplay; 8637 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 8638 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 8639 8640 return mode; 8641 8642} 8643 8644static const struct amdgpu_dm_mode_size { 8645 char name[DRM_DISPLAY_MODE_LEN]; 8646 int w; 8647 int h; 8648} common_modes[] = { 8649 { "640x480", 640, 480}, 8650 { "800x600", 800, 600}, 8651 { "1024x768", 1024, 768}, 8652 { "1280x720", 1280, 720}, 8653 { "1280x800", 1280, 800}, 8654 {"1280x1024", 1280, 1024}, 8655 { "1440x900", 1440, 900}, 8656 {"1680x1050", 1680, 1050}, 8657 {"1600x1200", 1600, 1200}, 8658 {"1920x1080", 1920, 1080}, 8659 {"1920x1200", 1920, 1200} 8660}; 8661 8662static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 8663 struct drm_connector *connector) 8664{ 8665 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 8666 struct drm_display_mode *mode = NULL; 8667 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 8668 struct amdgpu_dm_connector *amdgpu_dm_connector = 8669 to_amdgpu_dm_connector(connector); 8670 int i; 8671 int n; 8672 8673 if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && 8674 (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) 8675 return; 8676 8677 n = ARRAY_SIZE(common_modes); 8678 8679 for (i = 0; i < n; i++) { 8680 struct drm_display_mode *curmode = NULL; 8681 bool mode_existed = false; 8682 8683 if (common_modes[i].w > native_mode->hdisplay || 8684 common_modes[i].h > native_mode->vdisplay || 8685 (common_modes[i].w == native_mode->hdisplay && 8686 common_modes[i].h == native_mode->vdisplay)) 8687 continue; 8688 8689 list_for_each_entry(curmode, &connector->probed_modes, head) { 8690 if (common_modes[i].w == curmode->hdisplay && 8691 common_modes[i].h == curmode->vdisplay) { 8692 mode_existed = true; 8693 break; 8694 } 8695 } 8696 8697 if (mode_existed) 8698 continue; 8699 8700 mode = amdgpu_dm_create_common_mode(encoder, 8701 common_modes[i].name, common_modes[i].w, 8702 common_modes[i].h); 8703 if (!mode) 8704 continue; 8705 8706 drm_mode_probed_add(connector, mode); 8707 amdgpu_dm_connector->num_modes++; 8708 } 8709} 8710 8711static void amdgpu_set_panel_orientation(struct drm_connector *connector) 8712{ 8713 struct drm_encoder *encoder; 8714 struct amdgpu_encoder *amdgpu_encoder; 8715 const struct drm_display_mode *native_mode; 8716 8717 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 8718 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 8719 return; 8720 8721 mutex_lock(&connector->dev->mode_config.mutex); 8722 amdgpu_dm_connector_get_modes(connector); 8723 mutex_unlock(&connector->dev->mode_config.mutex); 8724 8725 encoder = amdgpu_dm_connector_to_encoder(connector); 8726 if (!encoder) 8727 return; 8728 8729 amdgpu_encoder = to_amdgpu_encoder(encoder); 8730 8731 native_mode = &amdgpu_encoder->native_mode; 8732 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 8733 return; 8734 8735 drm_connector_set_panel_orientation_with_quirk(connector, 8736 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 8737 native_mode->hdisplay, 8738 native_mode->vdisplay); 8739} 8740 8741static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 8742 const struct drm_edid *drm_edid) 8743{ 8744 struct amdgpu_dm_connector *amdgpu_dm_connector = 8745 to_amdgpu_dm_connector(connector); 8746 8747 if (drm_edid) { 8748 /* empty probed_modes */ 8749 INIT_LIST_HEAD(&connector->probed_modes); 8750 amdgpu_dm_connector->num_modes = 8751 drm_edid_connector_add_modes(connector); 8752 8753 /* sorting the probed modes before calling function 8754 * amdgpu_dm_get_native_mode() since EDID can have 8755 * more than one preferred mode. The modes that are 8756 * later in the probed mode list could be of higher 8757 * and preferred resolution. For example, 3840x2160 8758 * resolution in base EDID preferred timing and 4096x2160 8759 * preferred resolution in DID extension block later. 8760 */ 8761 drm_mode_sort(&connector->probed_modes); 8762 amdgpu_dm_get_native_mode(connector); 8763 8764 /* Freesync capabilities are reset by calling 8765 * drm_edid_connector_add_modes() and need to be 8766 * restored here. 8767 */ 8768 amdgpu_dm_update_freesync_caps(connector, drm_edid); 8769 } else { 8770 amdgpu_dm_connector->num_modes = 0; 8771 } 8772} 8773 8774static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 8775 struct drm_display_mode *mode) 8776{ 8777 struct drm_display_mode *m; 8778 8779 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 8780 if (drm_mode_equal(m, mode)) 8781 return true; 8782 } 8783 8784 return false; 8785} 8786 8787static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 8788{ 8789 const struct drm_display_mode *m; 8790 struct drm_display_mode *new_mode; 8791 uint i; 8792 u32 new_modes_count = 0; 8793 8794 /* Standard FPS values 8795 * 8796 * 23.976 - TV/NTSC 8797 * 24 - Cinema 8798 * 25 - TV/PAL 8799 * 29.97 - TV/NTSC 8800 * 30 - TV/NTSC 8801 * 48 - Cinema HFR 8802 * 50 - TV/PAL 8803 * 60 - Commonly used 8804 * 48,72,96,120 - Multiples of 24 8805 */ 8806 static const u32 common_rates[] = { 8807 23976, 24000, 25000, 29970, 30000, 8808 48000, 50000, 60000, 72000, 96000, 120000 8809 }; 8810 8811 /* 8812 * Find mode with highest refresh rate with the same resolution 8813 * as the preferred mode. Some monitors report a preferred mode 8814 * with lower resolution than the highest refresh rate supported. 8815 */ 8816 8817 m = get_highest_refresh_rate_mode(aconnector, true); 8818 if (!m) 8819 return 0; 8820 8821 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 8822 u64 target_vtotal, target_vtotal_diff; 8823 u64 num, den; 8824 8825 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 8826 continue; 8827 8828 if (common_rates[i] < aconnector->min_vfreq * 1000 || 8829 common_rates[i] > aconnector->max_vfreq * 1000) 8830 continue; 8831 8832 num = (unsigned long long)m->clock * 1000 * 1000; 8833 den = common_rates[i] * (unsigned long long)m->htotal; 8834 target_vtotal = div_u64(num, den); 8835 target_vtotal_diff = target_vtotal - m->vtotal; 8836 8837 /* Check for illegal modes */ 8838 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 8839 m->vsync_end + target_vtotal_diff < m->vsync_start || 8840 m->vtotal + target_vtotal_diff < m->vsync_end) 8841 continue; 8842 8843 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 8844 if (!new_mode) 8845 goto out; 8846 8847 new_mode->vtotal += (u16)target_vtotal_diff; 8848 new_mode->vsync_start += (u16)target_vtotal_diff; 8849 new_mode->vsync_end += (u16)target_vtotal_diff; 8850 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 8851 new_mode->type |= DRM_MODE_TYPE_DRIVER; 8852 8853 if (!is_duplicate_mode(aconnector, new_mode)) { 8854 drm_mode_probed_add(&aconnector->base, new_mode); 8855 new_modes_count += 1; 8856 } else 8857 drm_mode_destroy(aconnector->base.dev, new_mode); 8858 } 8859 out: 8860 return new_modes_count; 8861} 8862 8863static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 8864 const struct drm_edid *drm_edid) 8865{ 8866 struct amdgpu_dm_connector *amdgpu_dm_connector = 8867 to_amdgpu_dm_connector(connector); 8868 8869 if (!(amdgpu_freesync_vid_mode && drm_edid)) 8870 return; 8871 8872 if (!amdgpu_dm_connector->dc_sink || !amdgpu_dm_connector->dc_link) 8873 return; 8874 8875 if (!dc_supports_vrr(amdgpu_dm_connector->dc_sink->ctx->dce_version)) 8876 return; 8877 8878 if (dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id) && 8879 amdgpu_dm_connector->dc_sink->edid_caps.analog) 8880 return; 8881 8882 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 8883 amdgpu_dm_connector->num_modes += 8884 add_fs_modes(amdgpu_dm_connector); 8885} 8886 8887static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 8888{ 8889 struct amdgpu_dm_connector *amdgpu_dm_connector = 8890 to_amdgpu_dm_connector(connector); 8891 struct dc_link *dc_link = amdgpu_dm_connector->dc_link; 8892 struct drm_encoder *encoder; 8893 const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; 8894 struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap; 8895 const struct dc *dc = dc_link->dc; 8896 8897 encoder = amdgpu_dm_connector_to_encoder(connector); 8898 8899 if (!drm_edid) { 8900 amdgpu_dm_connector->num_modes = 8901 drm_add_modes_noedid(connector, 640, 480); 8902 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 8903 amdgpu_dm_connector->num_modes += 8904 drm_add_modes_noedid(connector, 1920, 1080); 8905 8906 if (amdgpu_dm_connector->dc_sink && 8907 amdgpu_dm_connector->dc_sink->edid_caps.analog && 8908 dc_connector_supports_analog(dc_link->link_id.id)) { 8909 /* Analog monitor connected by DAC load detection. 8910 * Add common modes. It will be up to the user to select one that works. 8911 */ 8912 for (int i = 0; i < ARRAY_SIZE(common_modes); i++) 8913 amdgpu_dm_connector->num_modes += drm_add_modes_noedid( 8914 connector, common_modes[i].w, common_modes[i].h); 8915 } 8916 } else { 8917 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); 8918 if (encoder) 8919 amdgpu_dm_connector_add_common_modes(encoder, connector); 8920 amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); 8921 } 8922 amdgpu_dm_fbc_init(connector); 8923 8924 return amdgpu_dm_connector->num_modes; 8925} 8926 8927static const u32 supported_colorspaces = 8928 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 8929 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 8930 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 8931 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 8932 8933void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 8934 struct amdgpu_dm_connector *aconnector, 8935 int connector_type, 8936 struct dc_link *link, 8937 int link_index) 8938{ 8939 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 8940 8941 /* 8942 * Some of the properties below require access to state, like bpc. 8943 * Allocate some default initial connector state with our reset helper. 8944 */ 8945 if (aconnector->base.funcs->reset) 8946 aconnector->base.funcs->reset(&aconnector->base); 8947 8948 aconnector->connector_id = link_index; 8949 aconnector->bl_idx = -1; 8950 aconnector->dc_link = link; 8951 aconnector->base.interlace_allowed = false; 8952 aconnector->base.doublescan_allowed = false; 8953 aconnector->base.stereo_allowed = false; 8954 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 8955 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 8956 aconnector->audio_inst = -1; 8957 aconnector->pack_sdp_v1_3 = false; 8958 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 8959 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 8960 mutex_init(&aconnector->hpd_lock); 8961 mutex_init(&aconnector->handle_mst_msg_ready); 8962 8963 /* 8964 * If HDMI HPD debounce delay is set, use the minimum between selected 8965 * value and AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 8966 */ 8967 if (amdgpu_hdmi_hpd_debounce_delay_ms) { 8968 aconnector->hdmi_hpd_debounce_delay_ms = min(amdgpu_hdmi_hpd_debounce_delay_ms, 8969 AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS); 8970 INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, hdmi_hpd_debounce_work); 8971 aconnector->hdmi_prev_sink = NULL; 8972 } else { 8973 aconnector->hdmi_hpd_debounce_delay_ms = 0; 8974 } 8975 8976 /* 8977 * configure support HPD hot plug connector_>polled default value is 0 8978 * which means HPD hot plug not supported 8979 */ 8980 switch (connector_type) { 8981 case DRM_MODE_CONNECTOR_HDMIA: 8982 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8983 aconnector->base.ycbcr_420_allowed = 8984 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 8985 break; 8986 case DRM_MODE_CONNECTOR_DisplayPort: 8987 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8988 link->link_enc = link_enc_cfg_get_link_enc(link); 8989 ASSERT(link->link_enc); 8990 if (link->link_enc) 8991 aconnector->base.ycbcr_420_allowed = 8992 link->link_enc->features.dp_ycbcr420_supported ? true : false; 8993 break; 8994 case DRM_MODE_CONNECTOR_DVID: 8995 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8996 break; 8997 case DRM_MODE_CONNECTOR_DVII: 8998 case DRM_MODE_CONNECTOR_VGA: 8999 aconnector->base.polled = 9000 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 9001 break; 9002 default: 9003 break; 9004 } 9005 9006 drm_object_attach_property(&aconnector->base.base, 9007 dm->ddev->mode_config.scaling_mode_property, 9008 DRM_MODE_SCALE_NONE); 9009 9010 if (connector_type == DRM_MODE_CONNECTOR_HDMIA 9011 || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) 9012 drm_connector_attach_broadcast_rgb_property(&aconnector->base); 9013 9014 drm_object_attach_property(&aconnector->base.base, 9015 adev->mode_info.underscan_property, 9016 UNDERSCAN_OFF); 9017 drm_object_attach_property(&aconnector->base.base, 9018 adev->mode_info.underscan_hborder_property, 9019 0); 9020 drm_object_attach_property(&aconnector->base.base, 9021 adev->mode_info.underscan_vborder_property, 9022 0); 9023 9024 if (!aconnector->mst_root) 9025 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 9026 9027 aconnector->base.state->max_bpc = 16; 9028 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 9029 9030 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 9031 /* Content Type is currently only implemented for HDMI. */ 9032 drm_connector_attach_content_type_property(&aconnector->base); 9033 } 9034 9035 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 9036 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 9037 drm_connector_attach_colorspace_property(&aconnector->base); 9038 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 9039 connector_type == DRM_MODE_CONNECTOR_eDP) { 9040 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 9041 drm_connector_attach_colorspace_property(&aconnector->base); 9042 } 9043 9044 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 9045 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 9046 connector_type == DRM_MODE_CONNECTOR_eDP) { 9047 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 9048 9049 if (!aconnector->mst_root) 9050 drm_connector_attach_vrr_capable_property(&aconnector->base); 9051 9052 if (adev->dm.hdcp_workqueue) 9053 drm_connector_attach_content_protection_property(&aconnector->base, true); 9054 } 9055 9056 if (connector_type == DRM_MODE_CONNECTOR_eDP) { 9057 struct drm_privacy_screen *privacy_screen; 9058 9059 privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); 9060 if (!IS_ERR(privacy_screen)) { 9061 drm_connector_attach_privacy_screen_provider(&aconnector->base, 9062 privacy_screen); 9063 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 9064 drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); 9065 } 9066 } 9067} 9068 9069static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 9070 struct i2c_msg *msgs, int num) 9071{ 9072 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 9073 struct ddc_service *ddc_service = i2c->ddc_service; 9074 struct i2c_command cmd; 9075 int i; 9076 int result = -EIO; 9077 9078 if (!ddc_service->ddc_pin) 9079 return result; 9080 9081 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 9082 9083 if (!cmd.payloads) 9084 return result; 9085 9086 cmd.number_of_payloads = num; 9087 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 9088 cmd.speed = 100; 9089 9090 for (i = 0; i < num; i++) { 9091 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 9092 cmd.payloads[i].address = msgs[i].addr; 9093 cmd.payloads[i].length = msgs[i].len; 9094 cmd.payloads[i].data = msgs[i].buf; 9095 } 9096 9097 if (i2c->oem) { 9098 if (dc_submit_i2c_oem( 9099 ddc_service->ctx->dc, 9100 &cmd)) 9101 result = num; 9102 } else { 9103 if (dc_submit_i2c( 9104 ddc_service->ctx->dc, 9105 ddc_service->link->link_index, 9106 &cmd)) 9107 result = num; 9108 } 9109 9110 kfree(cmd.payloads); 9111 return result; 9112} 9113 9114static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 9115{ 9116 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 9117} 9118 9119static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 9120 .master_xfer = amdgpu_dm_i2c_xfer, 9121 .functionality = amdgpu_dm_i2c_func, 9122}; 9123 9124static struct amdgpu_i2c_adapter * 9125create_i2c(struct ddc_service *ddc_service, bool oem) 9126{ 9127 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 9128 struct amdgpu_i2c_adapter *i2c; 9129 9130 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 9131 if (!i2c) 9132 return NULL; 9133 i2c->base.owner = THIS_MODULE; 9134 i2c->base.dev.parent = &adev->pdev->dev; 9135 i2c->base.algo = &amdgpu_dm_i2c_algo; 9136 if (oem) 9137 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c OEM bus"); 9138 else 9139 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", 9140 ddc_service->link->link_index); 9141 i2c_set_adapdata(&i2c->base, i2c); 9142 i2c->ddc_service = ddc_service; 9143 i2c->oem = oem; 9144 9145 return i2c; 9146} 9147 9148int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) 9149{ 9150 struct cec_connector_info conn_info; 9151 struct drm_device *ddev = aconnector->base.dev; 9152 struct device *hdmi_dev = ddev->dev; 9153 9154 if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) { 9155 drm_info(ddev, "HDMI-CEC feature masked\n"); 9156 return -EINVAL; 9157 } 9158 9159 cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); 9160 aconnector->notifier = 9161 cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); 9162 if (!aconnector->notifier) { 9163 drm_err(ddev, "Failed to create cec notifier\n"); 9164 return -ENOMEM; 9165 } 9166 9167 return 0; 9168} 9169 9170/* 9171 * Note: this function assumes that dc_link_detect() was called for the 9172 * dc_link which will be represented by this aconnector. 9173 */ 9174static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 9175 struct amdgpu_dm_connector *aconnector, 9176 u32 link_index, 9177 struct amdgpu_encoder *aencoder) 9178{ 9179 int res = 0; 9180 int connector_type; 9181 struct dc *dc = dm->dc; 9182 struct dc_link *link = dc_get_link_at_index(dc, link_index); 9183 struct amdgpu_i2c_adapter *i2c; 9184 9185 /* Not needed for writeback connector */ 9186 link->priv = aconnector; 9187 9188 9189 i2c = create_i2c(link->ddc, false); 9190 if (!i2c) { 9191 drm_err(adev_to_drm(dm->adev), "Failed to create i2c adapter data\n"); 9192 return -ENOMEM; 9193 } 9194 9195 aconnector->i2c = i2c; 9196 res = devm_i2c_add_adapter(dm->adev->dev, &i2c->base); 9197 9198 if (res) { 9199 drm_err(adev_to_drm(dm->adev), "Failed to register hw i2c %d\n", link->link_index); 9200 goto out_free; 9201 } 9202 9203 connector_type = to_drm_connector_type(link->connector_signal, link->link_id.id); 9204 9205 res = drm_connector_init_with_ddc( 9206 dm->ddev, 9207 &aconnector->base, 9208 &amdgpu_dm_connector_funcs, 9209 connector_type, 9210 &i2c->base); 9211 9212 if (res) { 9213 drm_err(adev_to_drm(dm->adev), "connector_init failed\n"); 9214 aconnector->connector_id = -1; 9215 goto out_free; 9216 } 9217 9218 drm_connector_helper_add( 9219 &aconnector->base, 9220 &amdgpu_dm_connector_helper_funcs); 9221 9222 amdgpu_dm_connector_init_helper( 9223 dm, 9224 aconnector, 9225 connector_type, 9226 link, 9227 link_index); 9228 9229 drm_connector_attach_encoder( 9230 &aconnector->base, &aencoder->base); 9231 9232 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 9233 connector_type == DRM_MODE_CONNECTOR_HDMIB) 9234 amdgpu_dm_initialize_hdmi_connector(aconnector); 9235 9236 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 9237 || connector_type == DRM_MODE_CONNECTOR_eDP) 9238 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 9239 9240out_free: 9241 if (res) { 9242 kfree(i2c); 9243 aconnector->i2c = NULL; 9244 } 9245 return res; 9246} 9247 9248int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 9249{ 9250 switch (adev->mode_info.num_crtc) { 9251 case 1: 9252 return 0x1; 9253 case 2: 9254 return 0x3; 9255 case 3: 9256 return 0x7; 9257 case 4: 9258 return 0xf; 9259 case 5: 9260 return 0x1f; 9261 case 6: 9262 default: 9263 return 0x3f; 9264 } 9265} 9266 9267static int amdgpu_dm_encoder_init(struct drm_device *dev, 9268 struct amdgpu_encoder *aencoder, 9269 uint32_t link_index) 9270{ 9271 struct amdgpu_device *adev = drm_to_adev(dev); 9272 9273 int res = drm_encoder_init(dev, 9274 &aencoder->base, 9275 &amdgpu_dm_encoder_funcs, 9276 DRM_MODE_ENCODER_TMDS, 9277 NULL); 9278 9279 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 9280 9281 if (!res) 9282 aencoder->encoder_id = link_index; 9283 else 9284 aencoder->encoder_id = -1; 9285 9286 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 9287 9288 return res; 9289} 9290 9291static void manage_dm_interrupts(struct amdgpu_device *adev, 9292 struct amdgpu_crtc *acrtc, 9293 struct dm_crtc_state *acrtc_state) 9294{ /* 9295 * We cannot be sure that the frontend index maps to the same 9296 * backend index - some even map to more than one. 9297 * So we have to go through the CRTC to find the right IRQ. 9298 */ 9299 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 9300 adev, 9301 acrtc->crtc_id); 9302 struct drm_device *dev = adev_to_drm(adev); 9303 9304 struct drm_vblank_crtc_config config = {0}; 9305 struct dc_crtc_timing *timing; 9306 int offdelay; 9307 9308 if (acrtc_state) { 9309 timing = &acrtc_state->stream->timing; 9310 9311 /* 9312 * Depending on when the HW latching event of double-buffered 9313 * registers happen relative to the PSR SDP deadline, and how 9314 * bad the Panel clock has drifted since the last ALPM off 9315 * event, there can be up to 3 frames of delay between sending 9316 * the PSR exit cmd to DMUB fw, and when the panel starts 9317 * displaying live frames. 9318 * 9319 * We can set: 9320 * 9321 * 20/100 * offdelay_ms = 3_frames_ms 9322 * => offdelay_ms = 5 * 3_frames_ms 9323 * 9324 * This ensures that `3_frames_ms` will only be experienced as a 9325 * 20% delay on top how long the display has been static, and 9326 * thus make the delay less perceivable. 9327 */ 9328 if (acrtc_state->stream->link->psr_settings.psr_version < 9329 DC_PSR_VERSION_UNSUPPORTED) { 9330 offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 * 9331 timing->v_total * 9332 timing->h_total, 9333 timing->pix_clk_100hz); 9334 config.offdelay_ms = offdelay ?: 30; 9335 } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 9336 IP_VERSION(3, 5, 0) || 9337 !(adev->flags & AMD_IS_APU)) { 9338 /* 9339 * Older HW and DGPU have issues with instant off; 9340 * use a 2 frame offdelay. 9341 */ 9342 offdelay = DIV64_U64_ROUND_UP((u64)20 * 9343 timing->v_total * 9344 timing->h_total, 9345 timing->pix_clk_100hz); 9346 9347 config.offdelay_ms = offdelay ?: 30; 9348 } else { 9349 /* offdelay_ms = 0 will never disable vblank */ 9350 config.offdelay_ms = 1; 9351 config.disable_immediate = true; 9352 } 9353 9354 drm_crtc_vblank_on_config(&acrtc->base, 9355 &config); 9356 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_get.*/ 9357 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 9358 case IP_VERSION(3, 0, 0): 9359 case IP_VERSION(3, 0, 2): 9360 case IP_VERSION(3, 0, 3): 9361 case IP_VERSION(3, 2, 0): 9362 if (amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type)) 9363 drm_err(dev, "DM_IRQ: Cannot get pageflip irq!\n"); 9364#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9365 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 9366 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 9367#endif 9368 } 9369 9370 } else { 9371 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 9372 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 9373 case IP_VERSION(3, 0, 0): 9374 case IP_VERSION(3, 0, 2): 9375 case IP_VERSION(3, 0, 3): 9376 case IP_VERSION(3, 2, 0): 9377#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9378 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 9379 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 9380#endif 9381 if (amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type)) 9382 drm_err(dev, "DM_IRQ: Cannot put pageflip irq!\n"); 9383 } 9384 9385 drm_crtc_vblank_off(&acrtc->base); 9386 } 9387} 9388 9389static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 9390 struct amdgpu_crtc *acrtc) 9391{ 9392 int irq_type = 9393 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 9394 9395 /** 9396 * This reads the current state for the IRQ and force reapplies 9397 * the setting to hardware. 9398 */ 9399 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 9400} 9401 9402static bool 9403is_scaling_state_different(const struct dm_connector_state *dm_state, 9404 const struct dm_connector_state *old_dm_state) 9405{ 9406 if (dm_state->scaling != old_dm_state->scaling) 9407 return true; 9408 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 9409 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 9410 return true; 9411 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 9412 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 9413 return true; 9414 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 9415 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 9416 return true; 9417 return false; 9418} 9419 9420static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 9421 struct drm_crtc_state *old_crtc_state, 9422 struct drm_connector_state *new_conn_state, 9423 struct drm_connector_state *old_conn_state, 9424 const struct drm_connector *connector, 9425 struct hdcp_workqueue *hdcp_w) 9426{ 9427 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9428 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 9429 9430 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 9431 connector->index, connector->status, connector->dpms); 9432 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 9433 old_conn_state->content_protection, new_conn_state->content_protection); 9434 9435 if (old_crtc_state) 9436 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9437 old_crtc_state->enable, 9438 old_crtc_state->active, 9439 old_crtc_state->mode_changed, 9440 old_crtc_state->active_changed, 9441 old_crtc_state->connectors_changed); 9442 9443 if (new_crtc_state) 9444 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9445 new_crtc_state->enable, 9446 new_crtc_state->active, 9447 new_crtc_state->mode_changed, 9448 new_crtc_state->active_changed, 9449 new_crtc_state->connectors_changed); 9450 9451 /* hdcp content type change */ 9452 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 9453 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 9454 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9455 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 9456 return true; 9457 } 9458 9459 /* CP is being re enabled, ignore this */ 9460 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 9461 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 9462 if (new_crtc_state && new_crtc_state->mode_changed) { 9463 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9464 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 9465 return true; 9466 } 9467 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 9468 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 9469 return false; 9470 } 9471 9472 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 9473 * 9474 * Handles: UNDESIRED -> ENABLED 9475 */ 9476 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 9477 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 9478 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9479 9480 /* Stream removed and re-enabled 9481 * 9482 * Can sometimes overlap with the HPD case, 9483 * thus set update_hdcp to false to avoid 9484 * setting HDCP multiple times. 9485 * 9486 * Handles: DESIRED -> DESIRED (Special case) 9487 */ 9488 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 9489 new_conn_state->crtc && new_conn_state->crtc->enabled && 9490 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 9491 dm_con_state->update_hdcp = false; 9492 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 9493 __func__); 9494 return true; 9495 } 9496 9497 /* Hot-plug, headless s3, dpms 9498 * 9499 * Only start HDCP if the display is connected/enabled. 9500 * update_hdcp flag will be set to false until the next 9501 * HPD comes in. 9502 * 9503 * Handles: DESIRED -> DESIRED (Special case) 9504 */ 9505 if (dm_con_state->update_hdcp && 9506 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 9507 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 9508 dm_con_state->update_hdcp = false; 9509 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 9510 __func__); 9511 return true; 9512 } 9513 9514 if (old_conn_state->content_protection == new_conn_state->content_protection) { 9515 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 9516 if (new_crtc_state && new_crtc_state->mode_changed) { 9517 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 9518 __func__); 9519 return true; 9520 } 9521 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 9522 __func__); 9523 return false; 9524 } 9525 9526 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 9527 return false; 9528 } 9529 9530 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9531 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 9532 __func__); 9533 return true; 9534 } 9535 9536 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 9537 return false; 9538} 9539 9540static void remove_stream(struct amdgpu_device *adev, 9541 struct amdgpu_crtc *acrtc, 9542 struct dc_stream_state *stream) 9543{ 9544 /* this is the update mode case */ 9545 9546 acrtc->otg_inst = -1; 9547 acrtc->enabled = false; 9548} 9549 9550static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 9551{ 9552 9553 assert_spin_locked(&acrtc->base.dev->event_lock); 9554 WARN_ON(acrtc->event); 9555 9556 acrtc->event = acrtc->base.state->event; 9557 9558 /* Set the flip status */ 9559 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 9560 9561 /* Mark this event as consumed */ 9562 acrtc->base.state->event = NULL; 9563 9564 drm_dbg_state(acrtc->base.dev, 9565 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 9566 acrtc->crtc_id); 9567} 9568 9569static void update_freesync_state_on_stream( 9570 struct amdgpu_display_manager *dm, 9571 struct dm_crtc_state *new_crtc_state, 9572 struct dc_stream_state *new_stream, 9573 struct dc_plane_state *surface, 9574 u32 flip_timestamp_in_us) 9575{ 9576 struct mod_vrr_params vrr_params; 9577 struct dc_info_packet vrr_infopacket = {0}; 9578 struct amdgpu_device *adev = dm->adev; 9579 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 9580 unsigned long flags; 9581 bool pack_sdp_v1_3 = false; 9582 struct amdgpu_dm_connector *aconn; 9583 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 9584 9585 if (!new_stream) 9586 return; 9587 9588 /* 9589 * TODO: Determine why min/max totals and vrefresh can be 0 here. 9590 * For now it's sufficient to just guard against these conditions. 9591 */ 9592 9593 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 9594 return; 9595 9596 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9597 vrr_params = acrtc->dm_irq_params.vrr_params; 9598 9599 if (surface) { 9600 mod_freesync_handle_preflip( 9601 dm->freesync_module, 9602 surface, 9603 new_stream, 9604 flip_timestamp_in_us, 9605 &vrr_params); 9606 9607 if (adev->family < AMDGPU_FAMILY_AI && 9608 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 9609 mod_freesync_handle_v_update(dm->freesync_module, 9610 new_stream, &vrr_params); 9611 9612 /* Need to call this before the frame ends. */ 9613 dc_stream_adjust_vmin_vmax(dm->dc, 9614 new_crtc_state->stream, 9615 &vrr_params.adjust); 9616 } 9617 } 9618 9619 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 9620 9621 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 9622 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 9623 9624 if (aconn->vsdb_info.amd_vsdb_version == 1) 9625 packet_type = PACKET_TYPE_FS_V1; 9626 else if (aconn->vsdb_info.amd_vsdb_version == 2) 9627 packet_type = PACKET_TYPE_FS_V2; 9628 else if (aconn->vsdb_info.amd_vsdb_version == 3) 9629 packet_type = PACKET_TYPE_FS_V3; 9630 9631 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 9632 &new_stream->adaptive_sync_infopacket); 9633 } 9634 9635 mod_freesync_build_vrr_infopacket( 9636 dm->freesync_module, 9637 new_stream, 9638 &vrr_params, 9639 packet_type, 9640 TRANSFER_FUNC_UNKNOWN, 9641 &vrr_infopacket, 9642 pack_sdp_v1_3); 9643 9644 new_crtc_state->freesync_vrr_info_changed |= 9645 (memcmp(&new_crtc_state->vrr_infopacket, 9646 &vrr_infopacket, 9647 sizeof(vrr_infopacket)) != 0); 9648 9649 acrtc->dm_irq_params.vrr_params = vrr_params; 9650 new_crtc_state->vrr_infopacket = vrr_infopacket; 9651 9652 new_stream->vrr_infopacket = vrr_infopacket; 9653 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 9654 9655 if (new_crtc_state->freesync_vrr_info_changed) 9656 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 9657 new_crtc_state->base.crtc->base.id, 9658 (int)new_crtc_state->base.vrr_enabled, 9659 (int)vrr_params.state); 9660 9661 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9662} 9663 9664static void update_stream_irq_parameters( 9665 struct amdgpu_display_manager *dm, 9666 struct dm_crtc_state *new_crtc_state) 9667{ 9668 struct dc_stream_state *new_stream = new_crtc_state->stream; 9669 struct mod_vrr_params vrr_params; 9670 struct mod_freesync_config config = new_crtc_state->freesync_config; 9671 struct amdgpu_device *adev = dm->adev; 9672 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 9673 unsigned long flags; 9674 9675 if (!new_stream) 9676 return; 9677 9678 /* 9679 * TODO: Determine why min/max totals and vrefresh can be 0 here. 9680 * For now it's sufficient to just guard against these conditions. 9681 */ 9682 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 9683 return; 9684 9685 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9686 vrr_params = acrtc->dm_irq_params.vrr_params; 9687 9688 if (new_crtc_state->vrr_supported && 9689 config.min_refresh_in_uhz && 9690 config.max_refresh_in_uhz) { 9691 /* 9692 * if freesync compatible mode was set, config.state will be set 9693 * in atomic check 9694 */ 9695 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 9696 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 9697 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 9698 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 9699 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 9700 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 9701 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 9702 } else { 9703 config.state = new_crtc_state->base.vrr_enabled ? 9704 VRR_STATE_ACTIVE_VARIABLE : 9705 VRR_STATE_INACTIVE; 9706 } 9707 } else { 9708 config.state = VRR_STATE_UNSUPPORTED; 9709 } 9710 9711 mod_freesync_build_vrr_params(dm->freesync_module, 9712 new_stream, 9713 &config, &vrr_params); 9714 9715 new_crtc_state->freesync_config = config; 9716 /* Copy state for access from DM IRQ handler */ 9717 acrtc->dm_irq_params.freesync_config = config; 9718 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 9719 acrtc->dm_irq_params.vrr_params = vrr_params; 9720 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9721} 9722 9723static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 9724 struct dm_crtc_state *new_state) 9725{ 9726 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 9727 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 9728 9729 if (!old_vrr_active && new_vrr_active) { 9730 /* Transition VRR inactive -> active: 9731 * While VRR is active, we must not disable vblank irq, as a 9732 * reenable after disable would compute bogus vblank/pflip 9733 * timestamps if it likely happened inside display front-porch. 9734 * 9735 * We also need vupdate irq for the actual core vblank handling 9736 * at end of vblank. 9737 */ 9738 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 9739 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 9740 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", 9741 __func__, new_state->base.crtc->base.id); 9742 } else if (old_vrr_active && !new_vrr_active) { 9743 /* Transition VRR active -> inactive: 9744 * Allow vblank irq disable again for fixed refresh rate. 9745 */ 9746 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 9747 drm_crtc_vblank_put(new_state->base.crtc); 9748 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", 9749 __func__, new_state->base.crtc->base.id); 9750 } 9751} 9752 9753static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 9754{ 9755 struct drm_plane *plane; 9756 struct drm_plane_state *old_plane_state; 9757 int i; 9758 9759 /* 9760 * TODO: Make this per-stream so we don't issue redundant updates for 9761 * commits with multiple streams. 9762 */ 9763 for_each_old_plane_in_state(state, plane, old_plane_state, i) 9764 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9765 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 9766} 9767 9768static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 9769{ 9770 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 9771 9772 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 9773} 9774 9775static void amdgpu_dm_update_cursor(struct drm_plane *plane, 9776 struct drm_plane_state *old_plane_state, 9777 struct dc_stream_update *update) 9778{ 9779 struct amdgpu_device *adev = drm_to_adev(plane->dev); 9780 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 9781 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 9782 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 9783 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 9784 uint64_t address = afb ? afb->address : 0; 9785 struct dc_cursor_position position = {0}; 9786 struct dc_cursor_attributes attributes; 9787 int ret; 9788 9789 if (!plane->state->fb && !old_plane_state->fb) 9790 return; 9791 9792 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 9793 amdgpu_crtc->crtc_id, plane->state->crtc_w, 9794 plane->state->crtc_h); 9795 9796 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 9797 if (ret) 9798 return; 9799 9800 if (!position.enable) { 9801 /* turn off cursor */ 9802 if (crtc_state && crtc_state->stream) { 9803 dc_stream_set_cursor_position(crtc_state->stream, 9804 &position); 9805 update->cursor_position = &crtc_state->stream->cursor_position; 9806 } 9807 return; 9808 } 9809 9810 amdgpu_crtc->cursor_width = plane->state->crtc_w; 9811 amdgpu_crtc->cursor_height = plane->state->crtc_h; 9812 9813 memset(&attributes, 0, sizeof(attributes)); 9814 attributes.address.high_part = upper_32_bits(address); 9815 attributes.address.low_part = lower_32_bits(address); 9816 attributes.width = plane->state->crtc_w; 9817 attributes.height = plane->state->crtc_h; 9818 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 9819 attributes.rotation_angle = 0; 9820 attributes.attribute_flags.value = 0; 9821 9822 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 9823 * legacy gamma setup. 9824 */ 9825 if (crtc_state->cm_is_degamma_srgb && 9826 adev->dm.dc->caps.color.dpp.gamma_corr) 9827 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 9828 9829 if (afb) 9830 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 9831 9832 if (crtc_state->stream) { 9833 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 9834 &attributes)) 9835 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 9836 9837 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 9838 9839 if (!dc_stream_set_cursor_position(crtc_state->stream, 9840 &position)) 9841 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 9842 9843 update->cursor_position = &crtc_state->stream->cursor_position; 9844 } 9845} 9846 9847static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, 9848 const struct dm_crtc_state *acrtc_state, 9849 const u64 current_ts) 9850{ 9851 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 9852 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 9853 struct amdgpu_dm_connector *aconn = 9854 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9855 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 9856 9857 if (acrtc_state->update_type > UPDATE_TYPE_FAST) { 9858 if (pr->config.replay_supported && !pr->replay_feature_enabled) 9859 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); 9860 else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED && 9861 !psr->psr_feature_enabled) 9862 if (!aconn->disallow_edp_enter_psr) 9863 amdgpu_dm_link_setup_psr(acrtc_state->stream); 9864 } 9865 9866 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 9867 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 9868 (psr->psr_feature_enabled || pr->config.replay_supported)) { 9869 if (aconn->sr_skip_count > 0) 9870 aconn->sr_skip_count--; 9871 9872 /* Allow SR when skip count is 0. */ 9873 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 9874 9875 /* 9876 * If sink supports PSR SU/Panel Replay, there is no need to rely on 9877 * a vblank event disable request to enable PSR/RP. PSR SU/RP 9878 * can be enabled immediately once OS demonstrates an 9879 * adequate number of fast atomic commits to notify KMD 9880 * of update events. See `vblank_control_worker()`. 9881 */ 9882 if (!vrr_active && 9883 acrtc_attach->dm_irq_params.allow_sr_entry && 9884#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 9885 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 9886#endif 9887 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 9888 if (pr->replay_feature_enabled && !pr->replay_allow_active) 9889 amdgpu_dm_replay_enable(acrtc_state->stream, true); 9890 if (psr->psr_version == DC_PSR_VERSION_SU_1 && 9891 !psr->psr_allow_active && !aconn->disallow_edp_enter_psr) 9892 amdgpu_dm_psr_enable(acrtc_state->stream); 9893 } 9894 } else { 9895 acrtc_attach->dm_irq_params.allow_sr_entry = false; 9896 } 9897} 9898 9899static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 9900 struct drm_device *dev, 9901 struct amdgpu_display_manager *dm, 9902 struct drm_crtc *pcrtc, 9903 bool wait_for_vblank) 9904{ 9905 u32 i; 9906 u64 timestamp_ns = ktime_get_ns(); 9907 struct drm_plane *plane; 9908 struct drm_plane_state *old_plane_state, *new_plane_state; 9909 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 9910 struct drm_crtc_state *new_pcrtc_state = 9911 drm_atomic_get_new_crtc_state(state, pcrtc); 9912 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 9913 struct dm_crtc_state *dm_old_crtc_state = 9914 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 9915 int planes_count = 0, vpos, hpos; 9916 unsigned long flags; 9917 u32 target_vblank, last_flip_vblank; 9918 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 9919 bool cursor_update = false; 9920 bool pflip_present = false; 9921 bool dirty_rects_changed = false; 9922 bool updated_planes_and_streams = false; 9923 struct { 9924 struct dc_surface_update surface_updates[MAX_SURFACES]; 9925 struct dc_plane_info plane_infos[MAX_SURFACES]; 9926 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 9927 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 9928 struct dc_stream_update stream_update; 9929 } *bundle; 9930 9931 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 9932 9933 if (!bundle) { 9934 drm_err(dev, "Failed to allocate update bundle\n"); 9935 goto cleanup; 9936 } 9937 9938 /* 9939 * Disable the cursor first if we're disabling all the planes. 9940 * It'll remain on the screen after the planes are re-enabled 9941 * if we don't. 9942 * 9943 * If the cursor is transitioning from native to overlay mode, the 9944 * native cursor needs to be disabled first. 9945 */ 9946 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 9947 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 9948 struct dc_cursor_position cursor_position = {0}; 9949 9950 if (!dc_stream_set_cursor_position(acrtc_state->stream, 9951 &cursor_position)) 9952 drm_err(dev, "DC failed to disable native cursor\n"); 9953 9954 bundle->stream_update.cursor_position = 9955 &acrtc_state->stream->cursor_position; 9956 } 9957 9958 if (acrtc_state->active_planes == 0 && 9959 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 9960 amdgpu_dm_commit_cursors(state); 9961 9962 /* update planes when needed */ 9963 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9964 struct drm_crtc *crtc = new_plane_state->crtc; 9965 struct drm_crtc_state *new_crtc_state; 9966 struct drm_framebuffer *fb = new_plane_state->fb; 9967 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 9968 bool plane_needs_flip; 9969 struct dc_plane_state *dc_plane; 9970 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 9971 9972 /* Cursor plane is handled after stream updates */ 9973 if (plane->type == DRM_PLANE_TYPE_CURSOR && 9974 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 9975 if ((fb && crtc == pcrtc) || 9976 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 9977 cursor_update = true; 9978 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 9979 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 9980 } 9981 9982 continue; 9983 } 9984 9985 if (!fb || !crtc || pcrtc != crtc) 9986 continue; 9987 9988 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 9989 if (!new_crtc_state->active) 9990 continue; 9991 9992 dc_plane = dm_new_plane_state->dc_state; 9993 if (!dc_plane) 9994 continue; 9995 9996 bundle->surface_updates[planes_count].surface = dc_plane; 9997 if (new_pcrtc_state->color_mgmt_changed) { 9998 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 9999 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 10000 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 10001 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 10002 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; 10003 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; 10004 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; 10005 } 10006 10007 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 10008 &bundle->scaling_infos[planes_count]); 10009 10010 bundle->surface_updates[planes_count].scaling_info = 10011 &bundle->scaling_infos[planes_count]; 10012 10013 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 10014 10015 pflip_present = pflip_present || plane_needs_flip; 10016 10017 if (!plane_needs_flip) { 10018 planes_count += 1; 10019 continue; 10020 } 10021 10022 fill_dc_plane_info_and_addr( 10023 dm->adev, new_plane_state, 10024 afb->tiling_flags, 10025 &bundle->plane_infos[planes_count], 10026 &bundle->flip_addrs[planes_count].address, 10027 afb->tmz_surface); 10028 10029 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 10030 new_plane_state->plane->index, 10031 bundle->plane_infos[planes_count].dcc.enable); 10032 10033 bundle->surface_updates[planes_count].plane_info = 10034 &bundle->plane_infos[planes_count]; 10035 10036 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 10037 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 10038 fill_dc_dirty_rects(plane, old_plane_state, 10039 new_plane_state, new_crtc_state, 10040 &bundle->flip_addrs[planes_count], 10041 acrtc_state->stream->link->psr_settings.psr_version == 10042 DC_PSR_VERSION_SU_1, 10043 &dirty_rects_changed); 10044 10045 /* 10046 * If the dirty regions changed, PSR-SU need to be disabled temporarily 10047 * and enabled it again after dirty regions are stable to avoid video glitch. 10048 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 10049 * during the PSR-SU was disabled. 10050 */ 10051 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 10052 acrtc_attach->dm_irq_params.allow_sr_entry && 10053#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 10054 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 10055#endif 10056 dirty_rects_changed) { 10057 mutex_lock(&dm->dc_lock); 10058 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 10059 timestamp_ns; 10060 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 10061 amdgpu_dm_psr_disable(acrtc_state->stream, true); 10062 mutex_unlock(&dm->dc_lock); 10063 } 10064 } 10065 10066 /* 10067 * Only allow immediate flips for fast updates that don't 10068 * change memory domain, FB pitch, DCC state, rotation or 10069 * mirroring. 10070 * 10071 * dm_crtc_helper_atomic_check() only accepts async flips with 10072 * fast updates. 10073 */ 10074 if (crtc->state->async_flip && 10075 (acrtc_state->update_type != UPDATE_TYPE_FAST || 10076 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 10077 drm_warn_once(state->dev, 10078 "[PLANE:%d:%s] async flip with non-fast update\n", 10079 plane->base.id, plane->name); 10080 10081 bundle->flip_addrs[planes_count].flip_immediate = 10082 crtc->state->async_flip && 10083 acrtc_state->update_type == UPDATE_TYPE_FAST && 10084 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 10085 10086 timestamp_ns = ktime_get_ns(); 10087 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 10088 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 10089 bundle->surface_updates[planes_count].surface = dc_plane; 10090 10091 if (!bundle->surface_updates[planes_count].surface) { 10092 drm_err(dev, "No surface for CRTC: id=%d\n", 10093 acrtc_attach->crtc_id); 10094 continue; 10095 } 10096 10097 if (plane == pcrtc->primary) 10098 update_freesync_state_on_stream( 10099 dm, 10100 acrtc_state, 10101 acrtc_state->stream, 10102 dc_plane, 10103 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 10104 10105 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 10106 __func__, 10107 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 10108 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 10109 10110 planes_count += 1; 10111 10112 } 10113 10114 if (pflip_present) { 10115 if (!vrr_active) { 10116 /* Use old throttling in non-vrr fixed refresh rate mode 10117 * to keep flip scheduling based on target vblank counts 10118 * working in a backwards compatible way, e.g., for 10119 * clients using the GLX_OML_sync_control extension or 10120 * DRI3/Present extension with defined target_msc. 10121 */ 10122 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 10123 } else { 10124 /* For variable refresh rate mode only: 10125 * Get vblank of last completed flip to avoid > 1 vrr 10126 * flips per video frame by use of throttling, but allow 10127 * flip programming anywhere in the possibly large 10128 * variable vrr vblank interval for fine-grained flip 10129 * timing control and more opportunity to avoid stutter 10130 * on late submission of flips. 10131 */ 10132 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 10133 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 10134 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 10135 } 10136 10137 target_vblank = last_flip_vblank + wait_for_vblank; 10138 10139 /* 10140 * Wait until we're out of the vertical blank period before the one 10141 * targeted by the flip 10142 */ 10143 while ((acrtc_attach->enabled && 10144 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 10145 0, &vpos, &hpos, NULL, 10146 NULL, &pcrtc->hwmode) 10147 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 10148 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 10149 (int)(target_vblank - 10150 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 10151 usleep_range(1000, 1100); 10152 } 10153 10154 /** 10155 * Prepare the flip event for the pageflip interrupt to handle. 10156 * 10157 * This only works in the case where we've already turned on the 10158 * appropriate hardware blocks (eg. HUBP) so in the transition case 10159 * from 0 -> n planes we have to skip a hardware generated event 10160 * and rely on sending it from software. 10161 */ 10162 if (acrtc_attach->base.state->event && 10163 acrtc_state->active_planes > 0) { 10164 drm_crtc_vblank_get(pcrtc); 10165 10166 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 10167 10168 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 10169 prepare_flip_isr(acrtc_attach); 10170 10171 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 10172 } 10173 10174 if (acrtc_state->stream) { 10175 if (acrtc_state->freesync_vrr_info_changed) 10176 bundle->stream_update.vrr_infopacket = 10177 &acrtc_state->stream->vrr_infopacket; 10178 } 10179 } else if (cursor_update && acrtc_state->active_planes > 0) { 10180 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 10181 if (acrtc_attach->base.state->event) { 10182 drm_crtc_vblank_get(pcrtc); 10183 acrtc_attach->event = acrtc_attach->base.state->event; 10184 acrtc_attach->base.state->event = NULL; 10185 } 10186 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 10187 } 10188 10189 /* Update the planes if changed or disable if we don't have any. */ 10190 if ((planes_count || acrtc_state->active_planes == 0) && 10191 acrtc_state->stream) { 10192 /* 10193 * If PSR or idle optimizations are enabled then flush out 10194 * any pending work before hardware programming. 10195 */ 10196 if (dm->vblank_control_workqueue) 10197 flush_workqueue(dm->vblank_control_workqueue); 10198 10199 bundle->stream_update.stream = acrtc_state->stream; 10200 if (new_pcrtc_state->mode_changed) { 10201 bundle->stream_update.src = acrtc_state->stream->src; 10202 bundle->stream_update.dst = acrtc_state->stream->dst; 10203 } 10204 10205 if (new_pcrtc_state->color_mgmt_changed) { 10206 /* 10207 * TODO: This isn't fully correct since we've actually 10208 * already modified the stream in place. 10209 */ 10210 bundle->stream_update.gamut_remap = 10211 &acrtc_state->stream->gamut_remap_matrix; 10212 bundle->stream_update.output_csc_transform = 10213 &acrtc_state->stream->csc_color_matrix; 10214 bundle->stream_update.out_transfer_func = 10215 &acrtc_state->stream->out_transfer_func; 10216 bundle->stream_update.lut3d_func = 10217 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 10218 bundle->stream_update.func_shaper = 10219 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 10220 } 10221 10222 acrtc_state->stream->abm_level = acrtc_state->abm_level; 10223 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 10224 bundle->stream_update.abm_level = &acrtc_state->abm_level; 10225 10226 mutex_lock(&dm->dc_lock); 10227 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) { 10228 if (acrtc_state->stream->link->replay_settings.replay_allow_active) 10229 amdgpu_dm_replay_disable(acrtc_state->stream); 10230 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 10231 amdgpu_dm_psr_disable(acrtc_state->stream, true); 10232 } 10233 mutex_unlock(&dm->dc_lock); 10234 10235 /* 10236 * If FreeSync state on the stream has changed then we need to 10237 * re-adjust the min/max bounds now that DC doesn't handle this 10238 * as part of commit. 10239 */ 10240 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 10241 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 10242 dc_stream_adjust_vmin_vmax( 10243 dm->dc, acrtc_state->stream, 10244 &acrtc_attach->dm_irq_params.vrr_params.adjust); 10245 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 10246 } 10247 mutex_lock(&dm->dc_lock); 10248 update_planes_and_stream_adapter(dm->dc, 10249 acrtc_state->update_type, 10250 planes_count, 10251 acrtc_state->stream, 10252 &bundle->stream_update, 10253 bundle->surface_updates); 10254 updated_planes_and_streams = true; 10255 10256 /** 10257 * Enable or disable the interrupts on the backend. 10258 * 10259 * Most pipes are put into power gating when unused. 10260 * 10261 * When power gating is enabled on a pipe we lose the 10262 * interrupt enablement state when power gating is disabled. 10263 * 10264 * So we need to update the IRQ control state in hardware 10265 * whenever the pipe turns on (since it could be previously 10266 * power gated) or off (since some pipes can't be power gated 10267 * on some ASICs). 10268 */ 10269 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 10270 dm_update_pflip_irq_state(drm_to_adev(dev), 10271 acrtc_attach); 10272 10273 amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns); 10274 mutex_unlock(&dm->dc_lock); 10275 } 10276 10277 /* 10278 * Update cursor state *after* programming all the planes. 10279 * This avoids redundant programming in the case where we're going 10280 * to be disabling a single plane - those pipes are being disabled. 10281 */ 10282 if (acrtc_state->active_planes && 10283 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 10284 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 10285 amdgpu_dm_commit_cursors(state); 10286 10287cleanup: 10288 kfree(bundle); 10289} 10290 10291static void amdgpu_dm_commit_audio(struct drm_device *dev, 10292 struct drm_atomic_state *state) 10293{ 10294 struct amdgpu_device *adev = drm_to_adev(dev); 10295 struct amdgpu_dm_connector *aconnector; 10296 struct drm_connector *connector; 10297 struct drm_connector_state *old_con_state, *new_con_state; 10298 struct drm_crtc_state *new_crtc_state; 10299 struct dm_crtc_state *new_dm_crtc_state; 10300 const struct dc_stream_status *status; 10301 int i, inst; 10302 10303 /* Notify device removals. */ 10304 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10305 if (old_con_state->crtc != new_con_state->crtc) { 10306 /* CRTC changes require notification. */ 10307 goto notify; 10308 } 10309 10310 if (!new_con_state->crtc) 10311 continue; 10312 10313 new_crtc_state = drm_atomic_get_new_crtc_state( 10314 state, new_con_state->crtc); 10315 10316 if (!new_crtc_state) 10317 continue; 10318 10319 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10320 continue; 10321 10322notify: 10323 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10324 continue; 10325 10326 aconnector = to_amdgpu_dm_connector(connector); 10327 10328 mutex_lock(&adev->dm.audio_lock); 10329 inst = aconnector->audio_inst; 10330 aconnector->audio_inst = -1; 10331 mutex_unlock(&adev->dm.audio_lock); 10332 10333 amdgpu_dm_audio_eld_notify(adev, inst); 10334 } 10335 10336 /* Notify audio device additions. */ 10337 for_each_new_connector_in_state(state, connector, new_con_state, i) { 10338 if (!new_con_state->crtc) 10339 continue; 10340 10341 new_crtc_state = drm_atomic_get_new_crtc_state( 10342 state, new_con_state->crtc); 10343 10344 if (!new_crtc_state) 10345 continue; 10346 10347 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10348 continue; 10349 10350 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 10351 if (!new_dm_crtc_state->stream) 10352 continue; 10353 10354 status = dc_stream_get_status(new_dm_crtc_state->stream); 10355 if (!status) 10356 continue; 10357 10358 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10359 continue; 10360 10361 aconnector = to_amdgpu_dm_connector(connector); 10362 10363 mutex_lock(&adev->dm.audio_lock); 10364 inst = status->audio_inst; 10365 aconnector->audio_inst = inst; 10366 mutex_unlock(&adev->dm.audio_lock); 10367 10368 amdgpu_dm_audio_eld_notify(adev, inst); 10369 } 10370} 10371 10372/* 10373 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 10374 * @crtc_state: the DRM CRTC state 10375 * @stream_state: the DC stream state. 10376 * 10377 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 10378 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 10379 */ 10380static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 10381 struct dc_stream_state *stream_state) 10382{ 10383 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 10384} 10385 10386static void dm_clear_writeback(struct amdgpu_display_manager *dm, 10387 struct dm_crtc_state *crtc_state) 10388{ 10389 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 10390} 10391 10392static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 10393 struct dc_state *dc_state) 10394{ 10395 struct drm_device *dev = state->dev; 10396 struct amdgpu_device *adev = drm_to_adev(dev); 10397 struct amdgpu_display_manager *dm = &adev->dm; 10398 struct drm_crtc *crtc; 10399 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10400 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10401 struct drm_connector_state *old_con_state; 10402 struct drm_connector *connector; 10403 bool mode_set_reset_required = false; 10404 u32 i; 10405 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 10406 bool set_backlight_level = false; 10407 10408 /* Disable writeback */ 10409 for_each_old_connector_in_state(state, connector, old_con_state, i) { 10410 struct dm_connector_state *dm_old_con_state; 10411 struct amdgpu_crtc *acrtc; 10412 10413 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 10414 continue; 10415 10416 old_crtc_state = NULL; 10417 10418 dm_old_con_state = to_dm_connector_state(old_con_state); 10419 if (!dm_old_con_state->base.crtc) 10420 continue; 10421 10422 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 10423 if (acrtc) 10424 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 10425 10426 if (!acrtc || !acrtc->wb_enabled) 10427 continue; 10428 10429 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10430 10431 dm_clear_writeback(dm, dm_old_crtc_state); 10432 acrtc->wb_enabled = false; 10433 } 10434 10435 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 10436 new_crtc_state, i) { 10437 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 10438 10439 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10440 10441 if (old_crtc_state->active && 10442 (!new_crtc_state->active || 10443 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 10444 manage_dm_interrupts(adev, acrtc, NULL); 10445 dc_stream_release(dm_old_crtc_state->stream); 10446 } 10447 } 10448 10449 drm_atomic_helper_calc_timestamping_constants(state); 10450 10451 /* update changed items */ 10452 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10453 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 10454 10455 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10456 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10457 10458 drm_dbg_state(state->dev, 10459 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 10460 acrtc->crtc_id, 10461 new_crtc_state->enable, 10462 new_crtc_state->active, 10463 new_crtc_state->planes_changed, 10464 new_crtc_state->mode_changed, 10465 new_crtc_state->active_changed, 10466 new_crtc_state->connectors_changed); 10467 10468 /* Disable cursor if disabling crtc */ 10469 if (old_crtc_state->active && !new_crtc_state->active) { 10470 struct dc_cursor_position position; 10471 10472 memset(&position, 0, sizeof(position)); 10473 mutex_lock(&dm->dc_lock); 10474 dc_exit_ips_for_hw_access(dm->dc); 10475 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 10476 mutex_unlock(&dm->dc_lock); 10477 } 10478 10479 /* Copy all transient state flags into dc state */ 10480 if (dm_new_crtc_state->stream) { 10481 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 10482 dm_new_crtc_state->stream); 10483 } 10484 10485 /* handles headless hotplug case, updating new_state and 10486 * aconnector as needed 10487 */ 10488 10489 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 10490 10491 drm_dbg_atomic(dev, 10492 "Atomic commit: SET crtc id %d: [%p]\n", 10493 acrtc->crtc_id, acrtc); 10494 10495 if (!dm_new_crtc_state->stream) { 10496 /* 10497 * this could happen because of issues with 10498 * userspace notifications delivery. 10499 * In this case userspace tries to set mode on 10500 * display which is disconnected in fact. 10501 * dc_sink is NULL in this case on aconnector. 10502 * We expect reset mode will come soon. 10503 * 10504 * This can also happen when unplug is done 10505 * during resume sequence ended 10506 * 10507 * In this case, we want to pretend we still 10508 * have a sink to keep the pipe running so that 10509 * hw state is consistent with the sw state 10510 */ 10511 drm_dbg_atomic(dev, 10512 "Failed to create new stream for crtc %d\n", 10513 acrtc->base.base.id); 10514 continue; 10515 } 10516 10517 if (dm_old_crtc_state->stream) 10518 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 10519 10520 pm_runtime_get_noresume(dev->dev); 10521 10522 acrtc->enabled = true; 10523 acrtc->hw_mode = new_crtc_state->mode; 10524 crtc->hwmode = new_crtc_state->mode; 10525 mode_set_reset_required = true; 10526 set_backlight_level = true; 10527 } else if (modereset_required(new_crtc_state)) { 10528 drm_dbg_atomic(dev, 10529 "Atomic commit: RESET. crtc id %d:[%p]\n", 10530 acrtc->crtc_id, acrtc); 10531 /* i.e. reset mode */ 10532 if (dm_old_crtc_state->stream) 10533 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 10534 10535 mode_set_reset_required = true; 10536 } 10537 } /* for_each_crtc_in_state() */ 10538 10539 /* if there mode set or reset, disable eDP PSR, Replay */ 10540 if (mode_set_reset_required) { 10541 if (dm->vblank_control_workqueue) 10542 flush_workqueue(dm->vblank_control_workqueue); 10543 10544 amdgpu_dm_replay_disable_all(dm); 10545 amdgpu_dm_psr_disable_all(dm); 10546 } 10547 10548 dm_enable_per_frame_crtc_master_sync(dc_state); 10549 mutex_lock(&dm->dc_lock); 10550 dc_exit_ips_for_hw_access(dm->dc); 10551 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 10552 10553 /* Allow idle optimization when vblank count is 0 for display off */ 10554 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 10555 dc_allow_idle_optimizations(dm->dc, true); 10556 mutex_unlock(&dm->dc_lock); 10557 10558 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10559 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 10560 10561 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10562 10563 if (dm_new_crtc_state->stream != NULL) { 10564 const struct dc_stream_status *status = 10565 dc_stream_get_status(dm_new_crtc_state->stream); 10566 10567 if (!status) 10568 status = dc_state_get_stream_status(dc_state, 10569 dm_new_crtc_state->stream); 10570 if (!status) 10571 drm_err(dev, 10572 "got no status for stream %p on acrtc%p\n", 10573 dm_new_crtc_state->stream, acrtc); 10574 else 10575 acrtc->otg_inst = status->primary_otg_inst; 10576 } 10577 } 10578 10579 /* During boot up and resume the DC layer will reset the panel brightness 10580 * to fix a flicker issue. 10581 * It will cause the dm->actual_brightness is not the current panel brightness 10582 * level. (the dm->brightness is the correct panel level) 10583 * So we set the backlight level with dm->brightness value after set mode 10584 */ 10585 if (set_backlight_level) { 10586 for (i = 0; i < dm->num_of_edps; i++) { 10587 if (dm->backlight_dev[i]) 10588 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 10589 } 10590 } 10591} 10592 10593static void dm_set_writeback(struct amdgpu_display_manager *dm, 10594 struct dm_crtc_state *crtc_state, 10595 struct drm_connector *connector, 10596 struct drm_connector_state *new_con_state) 10597{ 10598 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 10599 struct amdgpu_device *adev = dm->adev; 10600 struct amdgpu_crtc *acrtc; 10601 struct dc_writeback_info *wb_info; 10602 struct pipe_ctx *pipe = NULL; 10603 struct amdgpu_framebuffer *afb; 10604 int i = 0; 10605 10606 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 10607 if (!wb_info) { 10608 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 10609 return; 10610 } 10611 10612 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 10613 if (!acrtc) { 10614 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 10615 kfree(wb_info); 10616 return; 10617 } 10618 10619 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 10620 if (!afb) { 10621 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 10622 kfree(wb_info); 10623 return; 10624 } 10625 10626 for (i = 0; i < MAX_PIPES; i++) { 10627 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 10628 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 10629 break; 10630 } 10631 } 10632 10633 /* fill in wb_info */ 10634 wb_info->wb_enabled = true; 10635 10636 wb_info->dwb_pipe_inst = 0; 10637 wb_info->dwb_params.dwbscl_black_color = 0; 10638 wb_info->dwb_params.hdr_mult = 0x1F000; 10639 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 10640 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 10641 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 10642 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 10643 10644 /* width & height from crtc */ 10645 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 10646 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 10647 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 10648 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 10649 10650 wb_info->dwb_params.cnv_params.crop_en = false; 10651 wb_info->dwb_params.stereo_params.stereo_enabled = false; 10652 10653 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 10654 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 10655 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 10656 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 10657 10658 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 10659 10660 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 10661 10662 wb_info->dwb_params.scaler_taps.h_taps = 1; 10663 wb_info->dwb_params.scaler_taps.v_taps = 1; 10664 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 10665 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 10666 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 10667 10668 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 10669 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 10670 10671 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 10672 wb_info->mcif_buf_params.luma_address[i] = afb->address; 10673 wb_info->mcif_buf_params.chroma_address[i] = 0; 10674 } 10675 10676 wb_info->mcif_buf_params.p_vmid = 1; 10677 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 10678 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 10679 wb_info->mcif_warmup_params.region_size = 10680 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 10681 } 10682 wb_info->mcif_warmup_params.p_vmid = 1; 10683 wb_info->writeback_source_plane = pipe->plane_state; 10684 10685 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 10686 10687 acrtc->wb_pending = true; 10688 acrtc->wb_conn = wb_conn; 10689 drm_writeback_queue_job(wb_conn, new_con_state); 10690} 10691 10692static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) 10693{ 10694 struct drm_connector_state *old_con_state, *new_con_state; 10695 struct drm_device *dev = state->dev; 10696 struct drm_connector *connector; 10697 struct amdgpu_device *adev = drm_to_adev(dev); 10698 int i; 10699 10700 if (!adev->dm.hdcp_workqueue) 10701 return; 10702 10703 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10704 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10705 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10706 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10707 struct dm_crtc_state *dm_new_crtc_state; 10708 struct amdgpu_dm_connector *aconnector; 10709 10710 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10711 continue; 10712 10713 aconnector = to_amdgpu_dm_connector(connector); 10714 10715 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 10716 10717 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 10718 connector->index, connector->status, connector->dpms); 10719 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 10720 old_con_state->content_protection, new_con_state->content_protection); 10721 10722 if (aconnector->dc_sink) { 10723 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 10724 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 10725 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 10726 aconnector->dc_sink->edid_caps.display_name); 10727 } 10728 } 10729 10730 new_crtc_state = NULL; 10731 old_crtc_state = NULL; 10732 10733 if (acrtc) { 10734 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 10735 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 10736 } 10737 10738 if (old_crtc_state) 10739 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 10740 old_crtc_state->enable, 10741 old_crtc_state->active, 10742 old_crtc_state->mode_changed, 10743 old_crtc_state->active_changed, 10744 old_crtc_state->connectors_changed); 10745 10746 if (new_crtc_state) 10747 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 10748 new_crtc_state->enable, 10749 new_crtc_state->active, 10750 new_crtc_state->mode_changed, 10751 new_crtc_state->active_changed, 10752 new_crtc_state->connectors_changed); 10753 10754 10755 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10756 10757 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 10758 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 10759 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 10760 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 10761 dm_new_con_state->update_hdcp = true; 10762 continue; 10763 } 10764 10765 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 10766 old_con_state, connector, adev->dm.hdcp_workqueue)) { 10767 /* when display is unplugged from mst hub, connctor will 10768 * be destroyed within dm_dp_mst_connector_destroy. connector 10769 * hdcp perperties, like type, undesired, desired, enabled, 10770 * will be lost. So, save hdcp properties into hdcp_work within 10771 * amdgpu_dm_atomic_commit_tail. if the same display is 10772 * plugged back with same display index, its hdcp properties 10773 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 10774 */ 10775 10776 bool enable_encryption = false; 10777 10778 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 10779 enable_encryption = true; 10780 10781 if (aconnector->dc_link && aconnector->dc_sink && 10782 aconnector->dc_link->type == dc_connection_mst_branch) { 10783 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 10784 struct hdcp_workqueue *hdcp_w = 10785 &hdcp_work[aconnector->dc_link->link_index]; 10786 10787 hdcp_w->hdcp_content_type[connector->index] = 10788 new_con_state->hdcp_content_type; 10789 hdcp_w->content_protection[connector->index] = 10790 new_con_state->content_protection; 10791 } 10792 10793 if (new_crtc_state && new_crtc_state->mode_changed && 10794 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 10795 enable_encryption = true; 10796 10797 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 10798 10799 if (aconnector->dc_link) 10800 hdcp_update_display( 10801 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 10802 new_con_state->hdcp_content_type, enable_encryption); 10803 } 10804 } 10805} 10806 10807static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) 10808{ 10809 struct drm_crtc *crtc; 10810 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10811 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10812 int i, ret; 10813 10814 ret = drm_dp_mst_atomic_setup_commit(state); 10815 if (ret) 10816 return ret; 10817 10818 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10819 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10820 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10821 /* 10822 * Color management settings. We also update color properties 10823 * when a modeset is needed, to ensure it gets reprogrammed. 10824 */ 10825 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 10826 (dm_new_crtc_state->base.color_mgmt_changed || 10827 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 10828 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 10829 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10830 if (ret) { 10831 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 10832 return ret; 10833 } 10834 } 10835 } 10836 10837 return 0; 10838} 10839 10840/** 10841 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 10842 * @state: The atomic state to commit 10843 * 10844 * This will tell DC to commit the constructed DC state from atomic_check, 10845 * programming the hardware. Any failures here implies a hardware failure, since 10846 * atomic check should have filtered anything non-kosher. 10847 */ 10848static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 10849{ 10850 struct drm_device *dev = state->dev; 10851 struct amdgpu_device *adev = drm_to_adev(dev); 10852 struct amdgpu_display_manager *dm = &adev->dm; 10853 struct dm_atomic_state *dm_state; 10854 struct dc_state *dc_state = NULL; 10855 u32 i, j; 10856 struct drm_crtc *crtc; 10857 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10858 unsigned long flags; 10859 bool wait_for_vblank = true; 10860 struct drm_connector *connector; 10861 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 10862 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10863 int crtc_disable_count = 0; 10864 10865 trace_amdgpu_dm_atomic_commit_tail_begin(state); 10866 10867 drm_atomic_helper_update_legacy_modeset_state(dev, state); 10868 drm_dp_mst_atomic_wait_for_dependencies(state); 10869 10870 dm_state = dm_atomic_get_new_state(state); 10871 if (dm_state && dm_state->context) { 10872 dc_state = dm_state->context; 10873 amdgpu_dm_commit_streams(state, dc_state); 10874 } 10875 10876 amdgpu_dm_update_hdcp(state); 10877 10878 /* Handle connector state changes */ 10879 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10880 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10881 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10882 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10883 struct dc_surface_update *dummy_updates; 10884 struct dc_stream_update stream_update; 10885 struct dc_info_packet hdr_packet; 10886 struct dc_stream_status *status = NULL; 10887 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 10888 10889 memset(&stream_update, 0, sizeof(stream_update)); 10890 10891 if (acrtc) { 10892 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 10893 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 10894 } 10895 10896 /* Skip any modesets/resets */ 10897 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 10898 continue; 10899 10900 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10901 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10902 10903 scaling_changed = is_scaling_state_different(dm_new_con_state, 10904 dm_old_con_state); 10905 10906 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 10907 (dm_old_crtc_state->stream->output_color_space != 10908 get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 10909 output_color_space_changed = true; 10910 10911 abm_changed = dm_new_crtc_state->abm_level != 10912 dm_old_crtc_state->abm_level; 10913 10914 hdr_changed = 10915 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 10916 10917 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 10918 continue; 10919 10920 stream_update.stream = dm_new_crtc_state->stream; 10921 if (scaling_changed) { 10922 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 10923 dm_new_con_state, dm_new_crtc_state->stream); 10924 10925 stream_update.src = dm_new_crtc_state->stream->src; 10926 stream_update.dst = dm_new_crtc_state->stream->dst; 10927 } 10928 10929 if (output_color_space_changed) { 10930 dm_new_crtc_state->stream->output_color_space 10931 = get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 10932 10933 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 10934 } 10935 10936 if (abm_changed) { 10937 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 10938 10939 stream_update.abm_level = &dm_new_crtc_state->abm_level; 10940 } 10941 10942 if (hdr_changed) { 10943 fill_hdr_info_packet(new_con_state, &hdr_packet); 10944 stream_update.hdr_static_metadata = &hdr_packet; 10945 } 10946 10947 status = dc_stream_get_status(dm_new_crtc_state->stream); 10948 10949 if (WARN_ON(!status)) 10950 continue; 10951 10952 WARN_ON(!status->plane_count); 10953 10954 /* 10955 * TODO: DC refuses to perform stream updates without a dc_surface_update. 10956 * Here we create an empty update on each plane. 10957 * To fix this, DC should permit updating only stream properties. 10958 */ 10959 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 10960 if (!dummy_updates) { 10961 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 10962 continue; 10963 } 10964 for (j = 0; j < status->plane_count; j++) 10965 dummy_updates[j].surface = status->plane_states[j]; 10966 10967 sort(dummy_updates, status->plane_count, 10968 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 10969 10970 mutex_lock(&dm->dc_lock); 10971 dc_exit_ips_for_hw_access(dm->dc); 10972 dc_update_planes_and_stream(dm->dc, 10973 dummy_updates, 10974 status->plane_count, 10975 dm_new_crtc_state->stream, 10976 &stream_update); 10977 mutex_unlock(&dm->dc_lock); 10978 kfree(dummy_updates); 10979 10980 drm_connector_update_privacy_screen(new_con_state); 10981 } 10982 10983 /** 10984 * Enable interrupts for CRTCs that are newly enabled or went through 10985 * a modeset. It was intentionally deferred until after the front end 10986 * state was modified to wait until the OTG was on and so the IRQ 10987 * handlers didn't access stale or invalid state. 10988 */ 10989 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10990 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 10991#ifdef CONFIG_DEBUG_FS 10992 enum amdgpu_dm_pipe_crc_source cur_crc_src; 10993#endif 10994 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 10995 if (old_crtc_state->active && !new_crtc_state->active) 10996 crtc_disable_count++; 10997 10998 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10999 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 11000 11001 /* For freesync config update on crtc state and params for irq */ 11002 update_stream_irq_parameters(dm, dm_new_crtc_state); 11003 11004#ifdef CONFIG_DEBUG_FS 11005 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 11006 cur_crc_src = acrtc->dm_irq_params.crc_src; 11007 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 11008#endif 11009 11010 if (new_crtc_state->active && 11011 (!old_crtc_state->active || 11012 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 11013 dc_stream_retain(dm_new_crtc_state->stream); 11014 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 11015 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 11016 } 11017 /* Handle vrr on->off / off->on transitions */ 11018 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 11019 11020#ifdef CONFIG_DEBUG_FS 11021 if (new_crtc_state->active && 11022 (!old_crtc_state->active || 11023 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 11024 /** 11025 * Frontend may have changed so reapply the CRC capture 11026 * settings for the stream. 11027 */ 11028 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 11029#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 11030 if (amdgpu_dm_crc_window_is_activated(crtc)) { 11031 uint8_t cnt; 11032 11033 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 11034 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 11035 if (acrtc->dm_irq_params.window_param[cnt].enable) { 11036 acrtc->dm_irq_params.window_param[cnt].update_win = true; 11037 11038 /** 11039 * It takes 2 frames for HW to stably generate CRC when 11040 * resuming from suspend, so we set skip_frame_cnt 2. 11041 */ 11042 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 11043 } 11044 } 11045 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 11046 } 11047#endif 11048 if (amdgpu_dm_crtc_configure_crc_source( 11049 crtc, dm_new_crtc_state, cur_crc_src)) 11050 drm_dbg_atomic(dev, "Failed to configure crc source"); 11051 } 11052 } 11053#endif 11054 } 11055 11056 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 11057 if (new_crtc_state->async_flip) 11058 wait_for_vblank = false; 11059 11060 /* update planes when needed per crtc*/ 11061 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 11062 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11063 11064 if (dm_new_crtc_state->stream) 11065 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 11066 } 11067 11068 /* Enable writeback */ 11069 for_each_new_connector_in_state(state, connector, new_con_state, i) { 11070 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11071 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 11072 11073 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 11074 continue; 11075 11076 if (!new_con_state->writeback_job) 11077 continue; 11078 11079 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 11080 11081 if (!new_crtc_state) 11082 continue; 11083 11084 if (acrtc->wb_enabled) 11085 continue; 11086 11087 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11088 11089 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 11090 acrtc->wb_enabled = true; 11091 } 11092 11093 /* Update audio instances for each connector. */ 11094 amdgpu_dm_commit_audio(dev, state); 11095 11096 /* restore the backlight level */ 11097 for (i = 0; i < dm->num_of_edps; i++) { 11098 if (dm->backlight_dev[i] && 11099 (dm->actual_brightness[i] != dm->brightness[i])) 11100 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 11101 } 11102 11103 /* 11104 * send vblank event on all events not handled in flip and 11105 * mark consumed event for drm_atomic_helper_commit_hw_done 11106 */ 11107 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 11108 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11109 11110 if (new_crtc_state->event) 11111 drm_send_event_locked(dev, &new_crtc_state->event->base); 11112 11113 new_crtc_state->event = NULL; 11114 } 11115 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 11116 11117 /* Signal HW programming completion */ 11118 drm_atomic_helper_commit_hw_done(state); 11119 11120 if (wait_for_vblank) 11121 drm_atomic_helper_wait_for_flip_done(dev, state); 11122 11123 drm_atomic_helper_cleanup_planes(dev, state); 11124 11125 /* Don't free the memory if we are hitting this as part of suspend. 11126 * This way we don't free any memory during suspend; see 11127 * amdgpu_bo_free_kernel(). The memory will be freed in the first 11128 * non-suspend modeset or when the driver is torn down. 11129 */ 11130 if (!adev->in_suspend) { 11131 /* return the stolen vga memory back to VRAM */ 11132 if (!adev->mman.keep_stolen_vga_memory) 11133 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 11134 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 11135 } 11136 11137 /* 11138 * Finally, drop a runtime PM reference for each newly disabled CRTC, 11139 * so we can put the GPU into runtime suspend if we're not driving any 11140 * displays anymore 11141 */ 11142 for (i = 0; i < crtc_disable_count; i++) 11143 pm_runtime_put_autosuspend(dev->dev); 11144 pm_runtime_mark_last_busy(dev->dev); 11145 11146 trace_amdgpu_dm_atomic_commit_tail_finish(state); 11147} 11148 11149static int dm_force_atomic_commit(struct drm_connector *connector) 11150{ 11151 int ret = 0; 11152 struct drm_device *ddev = connector->dev; 11153 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 11154 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 11155 struct drm_plane *plane = disconnected_acrtc->base.primary; 11156 struct drm_connector_state *conn_state; 11157 struct drm_crtc_state *crtc_state; 11158 struct drm_plane_state *plane_state; 11159 11160 if (!state) 11161 return -ENOMEM; 11162 11163 state->acquire_ctx = ddev->mode_config.acquire_ctx; 11164 11165 /* Construct an atomic state to restore previous display setting */ 11166 11167 /* 11168 * Attach connectors to drm_atomic_state 11169 */ 11170 conn_state = drm_atomic_get_connector_state(state, connector); 11171 11172 /* Check for error in getting connector state */ 11173 if (IS_ERR(conn_state)) { 11174 ret = PTR_ERR(conn_state); 11175 goto out; 11176 } 11177 11178 /* Attach crtc to drm_atomic_state*/ 11179 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 11180 11181 /* Check for error in getting crtc state */ 11182 if (IS_ERR(crtc_state)) { 11183 ret = PTR_ERR(crtc_state); 11184 goto out; 11185 } 11186 11187 /* force a restore */ 11188 crtc_state->mode_changed = true; 11189 11190 /* Attach plane to drm_atomic_state */ 11191 plane_state = drm_atomic_get_plane_state(state, plane); 11192 11193 /* Check for error in getting plane state */ 11194 if (IS_ERR(plane_state)) { 11195 ret = PTR_ERR(plane_state); 11196 goto out; 11197 } 11198 11199 /* Call commit internally with the state we just constructed */ 11200 ret = drm_atomic_commit(state); 11201 11202out: 11203 drm_atomic_state_put(state); 11204 if (ret) 11205 drm_err(ddev, "Restoring old state failed with %i\n", ret); 11206 11207 return ret; 11208} 11209 11210/* 11211 * This function handles all cases when set mode does not come upon hotplug. 11212 * This includes when a display is unplugged then plugged back into the 11213 * same port and when running without usermode desktop manager supprot 11214 */ 11215void dm_restore_drm_connector_state(struct drm_device *dev, 11216 struct drm_connector *connector) 11217{ 11218 struct amdgpu_dm_connector *aconnector; 11219 struct amdgpu_crtc *disconnected_acrtc; 11220 struct dm_crtc_state *acrtc_state; 11221 11222 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 11223 return; 11224 11225 aconnector = to_amdgpu_dm_connector(connector); 11226 11227 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 11228 return; 11229 11230 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 11231 if (!disconnected_acrtc) 11232 return; 11233 11234 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 11235 if (!acrtc_state->stream) 11236 return; 11237 11238 /* 11239 * If the previous sink is not released and different from the current, 11240 * we deduce we are in a state where we can not rely on usermode call 11241 * to turn on the display, so we do it here 11242 */ 11243 if (acrtc_state->stream->sink != aconnector->dc_sink) 11244 dm_force_atomic_commit(&aconnector->base); 11245} 11246 11247/* 11248 * Grabs all modesetting locks to serialize against any blocking commits, 11249 * Waits for completion of all non blocking commits. 11250 */ 11251static int do_aquire_global_lock(struct drm_device *dev, 11252 struct drm_atomic_state *state) 11253{ 11254 struct drm_crtc *crtc; 11255 struct drm_crtc_commit *commit; 11256 long ret; 11257 11258 /* 11259 * Adding all modeset locks to aquire_ctx will 11260 * ensure that when the framework release it the 11261 * extra locks we are locking here will get released to 11262 */ 11263 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 11264 if (ret) 11265 return ret; 11266 11267 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 11268 spin_lock(&crtc->commit_lock); 11269 commit = list_first_entry_or_null(&crtc->commit_list, 11270 struct drm_crtc_commit, commit_entry); 11271 if (commit) 11272 drm_crtc_commit_get(commit); 11273 spin_unlock(&crtc->commit_lock); 11274 11275 if (!commit) 11276 continue; 11277 11278 /* 11279 * Make sure all pending HW programming completed and 11280 * page flips done 11281 */ 11282 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 11283 11284 if (ret > 0) 11285 ret = wait_for_completion_interruptible_timeout( 11286 &commit->flip_done, 10*HZ); 11287 11288 if (ret == 0) 11289 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 11290 crtc->base.id, crtc->name); 11291 11292 drm_crtc_commit_put(commit); 11293 } 11294 11295 return ret < 0 ? ret : 0; 11296} 11297 11298static void get_freesync_config_for_crtc( 11299 struct dm_crtc_state *new_crtc_state, 11300 struct dm_connector_state *new_con_state) 11301{ 11302 struct mod_freesync_config config = {0}; 11303 struct amdgpu_dm_connector *aconnector; 11304 struct drm_display_mode *mode = &new_crtc_state->base.mode; 11305 int vrefresh = drm_mode_vrefresh(mode); 11306 bool fs_vid_mode = false; 11307 11308 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 11309 return; 11310 11311 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 11312 11313 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 11314 vrefresh >= aconnector->min_vfreq && 11315 vrefresh <= aconnector->max_vfreq; 11316 11317 if (new_crtc_state->vrr_supported) { 11318 new_crtc_state->stream->ignore_msa_timing_param = true; 11319 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 11320 11321 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 11322 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 11323 config.vsif_supported = true; 11324 config.btr = true; 11325 11326 if (fs_vid_mode) { 11327 config.state = VRR_STATE_ACTIVE_FIXED; 11328 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 11329 goto out; 11330 } else if (new_crtc_state->base.vrr_enabled) { 11331 config.state = VRR_STATE_ACTIVE_VARIABLE; 11332 } else { 11333 config.state = VRR_STATE_INACTIVE; 11334 } 11335 } else { 11336 config.state = VRR_STATE_UNSUPPORTED; 11337 } 11338out: 11339 new_crtc_state->freesync_config = config; 11340} 11341 11342static void reset_freesync_config_for_crtc( 11343 struct dm_crtc_state *new_crtc_state) 11344{ 11345 new_crtc_state->vrr_supported = false; 11346 11347 memset(&new_crtc_state->vrr_infopacket, 0, 11348 sizeof(new_crtc_state->vrr_infopacket)); 11349} 11350 11351static bool 11352is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 11353 struct drm_crtc_state *new_crtc_state) 11354{ 11355 const struct drm_display_mode *old_mode, *new_mode; 11356 11357 if (!old_crtc_state || !new_crtc_state) 11358 return false; 11359 11360 old_mode = &old_crtc_state->mode; 11361 new_mode = &new_crtc_state->mode; 11362 11363 if (old_mode->clock == new_mode->clock && 11364 old_mode->hdisplay == new_mode->hdisplay && 11365 old_mode->vdisplay == new_mode->vdisplay && 11366 old_mode->htotal == new_mode->htotal && 11367 old_mode->vtotal != new_mode->vtotal && 11368 old_mode->hsync_start == new_mode->hsync_start && 11369 old_mode->vsync_start != new_mode->vsync_start && 11370 old_mode->hsync_end == new_mode->hsync_end && 11371 old_mode->vsync_end != new_mode->vsync_end && 11372 old_mode->hskew == new_mode->hskew && 11373 old_mode->vscan == new_mode->vscan && 11374 (old_mode->vsync_end - old_mode->vsync_start) == 11375 (new_mode->vsync_end - new_mode->vsync_start)) 11376 return true; 11377 11378 return false; 11379} 11380 11381static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 11382{ 11383 u64 num, den, res; 11384 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 11385 11386 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 11387 11388 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 11389 den = (unsigned long long)new_crtc_state->mode.htotal * 11390 (unsigned long long)new_crtc_state->mode.vtotal; 11391 11392 res = div_u64(num, den); 11393 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 11394} 11395 11396static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 11397 struct drm_atomic_state *state, 11398 struct drm_crtc *crtc, 11399 struct drm_crtc_state *old_crtc_state, 11400 struct drm_crtc_state *new_crtc_state, 11401 bool enable, 11402 bool *lock_and_validation_needed) 11403{ 11404 struct dm_atomic_state *dm_state = NULL; 11405 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 11406 struct dc_stream_state *new_stream; 11407 struct amdgpu_device *adev = dm->adev; 11408 int ret = 0; 11409 11410 /* 11411 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 11412 * update changed items 11413 */ 11414 struct amdgpu_crtc *acrtc = NULL; 11415 struct drm_connector *connector = NULL; 11416 struct amdgpu_dm_connector *aconnector = NULL; 11417 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 11418 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 11419 11420 new_stream = NULL; 11421 11422 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 11423 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11424 acrtc = to_amdgpu_crtc(crtc); 11425 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 11426 if (connector) 11427 aconnector = to_amdgpu_dm_connector(connector); 11428 11429 /* TODO This hack should go away */ 11430 if (connector && enable) { 11431 /* Make sure fake sink is created in plug-in scenario */ 11432 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 11433 connector); 11434 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 11435 connector); 11436 11437 if (WARN_ON(!drm_new_conn_state)) { 11438 ret = -EINVAL; 11439 goto fail; 11440 } 11441 11442 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 11443 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 11444 11445 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 11446 goto skip_modeset; 11447 11448 new_stream = create_validate_stream_for_sink(connector, 11449 &new_crtc_state->mode, 11450 dm_new_conn_state, 11451 dm_old_crtc_state->stream); 11452 11453 /* 11454 * we can have no stream on ACTION_SET if a display 11455 * was disconnected during S3, in this case it is not an 11456 * error, the OS will be updated after detection, and 11457 * will do the right thing on next atomic commit 11458 */ 11459 11460 if (!new_stream) { 11461 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 11462 __func__, acrtc->base.base.id); 11463 ret = -ENOMEM; 11464 goto fail; 11465 } 11466 11467 /* 11468 * TODO: Check VSDB bits to decide whether this should 11469 * be enabled or not. 11470 */ 11471 new_stream->triggered_crtc_reset.enabled = 11472 dm->force_timing_sync; 11473 11474 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 11475 11476 ret = fill_hdr_info_packet(drm_new_conn_state, 11477 &new_stream->hdr_static_metadata); 11478 if (ret) 11479 goto fail; 11480 11481 /* 11482 * If we already removed the old stream from the context 11483 * (and set the new stream to NULL) then we can't reuse 11484 * the old stream even if the stream and scaling are unchanged. 11485 * We'll hit the BUG_ON and black screen. 11486 * 11487 * TODO: Refactor this function to allow this check to work 11488 * in all conditions. 11489 */ 11490 if (amdgpu_freesync_vid_mode && 11491 dm_new_crtc_state->stream && 11492 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 11493 goto skip_modeset; 11494 11495 if (dm_new_crtc_state->stream && 11496 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 11497 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 11498 new_crtc_state->mode_changed = false; 11499 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 11500 new_crtc_state->mode_changed); 11501 } 11502 } 11503 11504 /* mode_changed flag may get updated above, need to check again */ 11505 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 11506 goto skip_modeset; 11507 11508 drm_dbg_state(state->dev, 11509 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 11510 acrtc->crtc_id, 11511 new_crtc_state->enable, 11512 new_crtc_state->active, 11513 new_crtc_state->planes_changed, 11514 new_crtc_state->mode_changed, 11515 new_crtc_state->active_changed, 11516 new_crtc_state->connectors_changed); 11517 11518 /* Remove stream for any changed/disabled CRTC */ 11519 if (!enable) { 11520 11521 if (!dm_old_crtc_state->stream) 11522 goto skip_modeset; 11523 11524 /* Unset freesync video if it was active before */ 11525 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 11526 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 11527 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 11528 } 11529 11530 /* Now check if we should set freesync video mode */ 11531 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 11532 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 11533 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 11534 is_timing_unchanged_for_freesync(new_crtc_state, 11535 old_crtc_state)) { 11536 new_crtc_state->mode_changed = false; 11537 drm_dbg_driver(adev_to_drm(adev), 11538 "Mode change not required for front porch change, setting mode_changed to %d", 11539 new_crtc_state->mode_changed); 11540 11541 set_freesync_fixed_config(dm_new_crtc_state); 11542 11543 goto skip_modeset; 11544 } else if (amdgpu_freesync_vid_mode && aconnector && 11545 is_freesync_video_mode(&new_crtc_state->mode, 11546 aconnector)) { 11547 struct drm_display_mode *high_mode; 11548 11549 high_mode = get_highest_refresh_rate_mode(aconnector, false); 11550 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 11551 set_freesync_fixed_config(dm_new_crtc_state); 11552 } 11553 11554 ret = dm_atomic_get_state(state, &dm_state); 11555 if (ret) 11556 goto fail; 11557 11558 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 11559 crtc->base.id); 11560 11561 /* i.e. reset mode */ 11562 if (dc_state_remove_stream( 11563 dm->dc, 11564 dm_state->context, 11565 dm_old_crtc_state->stream) != DC_OK) { 11566 ret = -EINVAL; 11567 goto fail; 11568 } 11569 11570 dc_stream_release(dm_old_crtc_state->stream); 11571 dm_new_crtc_state->stream = NULL; 11572 11573 reset_freesync_config_for_crtc(dm_new_crtc_state); 11574 11575 *lock_and_validation_needed = true; 11576 11577 } else {/* Add stream for any updated/enabled CRTC */ 11578 /* 11579 * Quick fix to prevent NULL pointer on new_stream when 11580 * added MST connectors not found in existing crtc_state in the chained mode 11581 * TODO: need to dig out the root cause of that 11582 */ 11583 if (!connector) 11584 goto skip_modeset; 11585 11586 if (modereset_required(new_crtc_state)) 11587 goto skip_modeset; 11588 11589 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 11590 dm_old_crtc_state->stream)) { 11591 11592 WARN_ON(dm_new_crtc_state->stream); 11593 11594 ret = dm_atomic_get_state(state, &dm_state); 11595 if (ret) 11596 goto fail; 11597 11598 dm_new_crtc_state->stream = new_stream; 11599 11600 dc_stream_retain(new_stream); 11601 11602 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 11603 crtc->base.id); 11604 11605 if (dc_state_add_stream( 11606 dm->dc, 11607 dm_state->context, 11608 dm_new_crtc_state->stream) != DC_OK) { 11609 ret = -EINVAL; 11610 goto fail; 11611 } 11612 11613 *lock_and_validation_needed = true; 11614 } 11615 } 11616 11617skip_modeset: 11618 /* Release extra reference */ 11619 if (new_stream) 11620 dc_stream_release(new_stream); 11621 11622 /* 11623 * We want to do dc stream updates that do not require a 11624 * full modeset below. 11625 */ 11626 if (!(enable && connector && new_crtc_state->active)) 11627 return 0; 11628 /* 11629 * Given above conditions, the dc state cannot be NULL because: 11630 * 1. We're in the process of enabling CRTCs (just been added 11631 * to the dc context, or already is on the context) 11632 * 2. Has a valid connector attached, and 11633 * 3. Is currently active and enabled. 11634 * => The dc stream state currently exists. 11635 */ 11636 BUG_ON(dm_new_crtc_state->stream == NULL); 11637 11638 /* Scaling or underscan settings */ 11639 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 11640 drm_atomic_crtc_needs_modeset(new_crtc_state)) 11641 update_stream_scaling_settings( 11642 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 11643 11644 /* ABM settings */ 11645 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 11646 11647 /* 11648 * Color management settings. We also update color properties 11649 * when a modeset is needed, to ensure it gets reprogrammed. 11650 */ 11651 if (dm_new_crtc_state->base.color_mgmt_changed || 11652 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 11653 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 11654 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 11655 if (ret) 11656 goto fail; 11657 } 11658 11659 /* Update Freesync settings. */ 11660 get_freesync_config_for_crtc(dm_new_crtc_state, 11661 dm_new_conn_state); 11662 11663 return ret; 11664 11665fail: 11666 if (new_stream) 11667 dc_stream_release(new_stream); 11668 return ret; 11669} 11670 11671static bool should_reset_plane(struct drm_atomic_state *state, 11672 struct drm_plane *plane, 11673 struct drm_plane_state *old_plane_state, 11674 struct drm_plane_state *new_plane_state) 11675{ 11676 struct drm_plane *other; 11677 struct drm_plane_state *old_other_state, *new_other_state; 11678 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11679 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 11680 struct amdgpu_device *adev = drm_to_adev(plane->dev); 11681 struct drm_connector_state *new_con_state; 11682 struct drm_connector *connector; 11683 int i; 11684 11685 /* 11686 * TODO: Remove this hack for all asics once it proves that the 11687 * fast updates works fine on DCN3.2+. 11688 */ 11689 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 11690 state->allow_modeset) 11691 return true; 11692 11693 /* Check for writeback commit */ 11694 for_each_new_connector_in_state(state, connector, new_con_state, i) { 11695 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 11696 continue; 11697 11698 if (new_con_state->writeback_job) 11699 return true; 11700 } 11701 11702 if (amdgpu_in_reset(adev) && state->allow_modeset) 11703 return true; 11704 11705 /* Exit early if we know that we're adding or removing the plane. */ 11706 if (old_plane_state->crtc != new_plane_state->crtc) 11707 return true; 11708 11709 /* old crtc == new_crtc == NULL, plane not in context. */ 11710 if (!new_plane_state->crtc) 11711 return false; 11712 11713 new_crtc_state = 11714 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 11715 old_crtc_state = 11716 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 11717 11718 if (!new_crtc_state) 11719 return true; 11720 11721 /* 11722 * A change in cursor mode means a new dc pipe needs to be acquired or 11723 * released from the state 11724 */ 11725 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 11726 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 11727 if (plane->type == DRM_PLANE_TYPE_CURSOR && 11728 old_dm_crtc_state != NULL && 11729 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 11730 return true; 11731 } 11732 11733 /* CRTC Degamma changes currently require us to recreate planes. */ 11734 if (new_crtc_state->color_mgmt_changed) 11735 return true; 11736 11737 /* 11738 * On zpos change, planes need to be reordered by removing and re-adding 11739 * them one by one to the dc state, in order of descending zpos. 11740 * 11741 * TODO: We can likely skip bandwidth validation if the only thing that 11742 * changed about the plane was it'z z-ordering. 11743 */ 11744 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 11745 return true; 11746 11747 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 11748 return true; 11749 11750 /* 11751 * If there are any new primary or overlay planes being added or 11752 * removed then the z-order can potentially change. To ensure 11753 * correct z-order and pipe acquisition the current DC architecture 11754 * requires us to remove and recreate all existing planes. 11755 * 11756 * TODO: Come up with a more elegant solution for this. 11757 */ 11758 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 11759 struct amdgpu_framebuffer *old_afb, *new_afb; 11760 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 11761 11762 dm_new_other_state = to_dm_plane_state(new_other_state); 11763 dm_old_other_state = to_dm_plane_state(old_other_state); 11764 11765 if (other->type == DRM_PLANE_TYPE_CURSOR) 11766 continue; 11767 11768 if (old_other_state->crtc != new_plane_state->crtc && 11769 new_other_state->crtc != new_plane_state->crtc) 11770 continue; 11771 11772 if (old_other_state->crtc != new_other_state->crtc) 11773 return true; 11774 11775 /* Src/dst size and scaling updates. */ 11776 if (old_other_state->src_w != new_other_state->src_w || 11777 old_other_state->src_h != new_other_state->src_h || 11778 old_other_state->crtc_w != new_other_state->crtc_w || 11779 old_other_state->crtc_h != new_other_state->crtc_h) 11780 return true; 11781 11782 /* Rotation / mirroring updates. */ 11783 if (old_other_state->rotation != new_other_state->rotation) 11784 return true; 11785 11786 /* Blending updates. */ 11787 if (old_other_state->pixel_blend_mode != 11788 new_other_state->pixel_blend_mode) 11789 return true; 11790 11791 /* Alpha updates. */ 11792 if (old_other_state->alpha != new_other_state->alpha) 11793 return true; 11794 11795 /* Colorspace changes. */ 11796 if (old_other_state->color_range != new_other_state->color_range || 11797 old_other_state->color_encoding != new_other_state->color_encoding) 11798 return true; 11799 11800 /* HDR/Transfer Function changes. */ 11801 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 11802 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 11803 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 11804 dm_old_other_state->ctm != dm_new_other_state->ctm || 11805 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 11806 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 11807 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 11808 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 11809 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 11810 return true; 11811 11812 /* Framebuffer checks fall at the end. */ 11813 if (!old_other_state->fb || !new_other_state->fb) 11814 continue; 11815 11816 /* Pixel format changes can require bandwidth updates. */ 11817 if (old_other_state->fb->format != new_other_state->fb->format) 11818 return true; 11819 11820 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 11821 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 11822 11823 /* Tiling and DCC changes also require bandwidth updates. */ 11824 if (old_afb->tiling_flags != new_afb->tiling_flags || 11825 old_afb->base.modifier != new_afb->base.modifier) 11826 return true; 11827 } 11828 11829 return false; 11830} 11831 11832static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 11833 struct drm_plane_state *new_plane_state, 11834 struct drm_framebuffer *fb) 11835{ 11836 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 11837 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 11838 unsigned int pitch; 11839 bool linear; 11840 11841 if (fb->width > new_acrtc->max_cursor_width || 11842 fb->height > new_acrtc->max_cursor_height) { 11843 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 11844 new_plane_state->fb->width, 11845 new_plane_state->fb->height); 11846 return -EINVAL; 11847 } 11848 if (new_plane_state->src_w != fb->width << 16 || 11849 new_plane_state->src_h != fb->height << 16) { 11850 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 11851 return -EINVAL; 11852 } 11853 11854 /* Pitch in pixels */ 11855 pitch = fb->pitches[0] / fb->format->cpp[0]; 11856 11857 if (fb->width != pitch) { 11858 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 11859 fb->width, pitch); 11860 return -EINVAL; 11861 } 11862 11863 switch (pitch) { 11864 case 64: 11865 case 128: 11866 case 256: 11867 /* FB pitch is supported by cursor plane */ 11868 break; 11869 default: 11870 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 11871 return -EINVAL; 11872 } 11873 11874 /* Core DRM takes care of checking FB modifiers, so we only need to 11875 * check tiling flags when the FB doesn't have a modifier. 11876 */ 11877 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 11878 if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 11879 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 11880 } else if (adev->family >= AMDGPU_FAMILY_AI) { 11881 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 11882 } else { 11883 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 11884 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 11885 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 11886 } 11887 if (!linear) { 11888 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 11889 return -EINVAL; 11890 } 11891 } 11892 11893 return 0; 11894} 11895 11896/* 11897 * Helper function for checking the cursor in native mode 11898 */ 11899static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 11900 struct drm_plane *plane, 11901 struct drm_plane_state *new_plane_state, 11902 bool enable) 11903{ 11904 11905 struct amdgpu_crtc *new_acrtc; 11906 int ret; 11907 11908 if (!enable || !new_plane_crtc || 11909 drm_atomic_plane_disabling(plane->state, new_plane_state)) 11910 return 0; 11911 11912 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 11913 11914 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 11915 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 11916 return -EINVAL; 11917 } 11918 11919 if (new_plane_state->fb) { 11920 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 11921 new_plane_state->fb); 11922 if (ret) 11923 return ret; 11924 } 11925 11926 return 0; 11927} 11928 11929static bool dm_should_update_native_cursor(struct drm_atomic_state *state, 11930 struct drm_crtc *old_plane_crtc, 11931 struct drm_crtc *new_plane_crtc, 11932 bool enable) 11933{ 11934 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11935 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 11936 11937 if (!enable) { 11938 if (old_plane_crtc == NULL) 11939 return true; 11940 11941 old_crtc_state = drm_atomic_get_old_crtc_state( 11942 state, old_plane_crtc); 11943 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 11944 11945 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 11946 } else { 11947 if (new_plane_crtc == NULL) 11948 return true; 11949 11950 new_crtc_state = drm_atomic_get_new_crtc_state( 11951 state, new_plane_crtc); 11952 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11953 11954 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 11955 } 11956} 11957 11958static int dm_update_plane_state(struct dc *dc, 11959 struct drm_atomic_state *state, 11960 struct drm_plane *plane, 11961 struct drm_plane_state *old_plane_state, 11962 struct drm_plane_state *new_plane_state, 11963 bool enable, 11964 bool *lock_and_validation_needed, 11965 bool *is_top_most_overlay) 11966{ 11967 11968 struct dm_atomic_state *dm_state = NULL; 11969 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 11970 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11971 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 11972 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 11973 bool needs_reset, update_native_cursor; 11974 int ret = 0; 11975 11976 11977 new_plane_crtc = new_plane_state->crtc; 11978 old_plane_crtc = old_plane_state->crtc; 11979 dm_new_plane_state = to_dm_plane_state(new_plane_state); 11980 dm_old_plane_state = to_dm_plane_state(old_plane_state); 11981 11982 update_native_cursor = dm_should_update_native_cursor(state, 11983 old_plane_crtc, 11984 new_plane_crtc, 11985 enable); 11986 11987 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 11988 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 11989 new_plane_state, enable); 11990 if (ret) 11991 return ret; 11992 11993 return 0; 11994 } 11995 11996 needs_reset = should_reset_plane(state, plane, old_plane_state, 11997 new_plane_state); 11998 11999 /* Remove any changed/removed planes */ 12000 if (!enable) { 12001 if (!needs_reset) 12002 return 0; 12003 12004 if (!old_plane_crtc) 12005 return 0; 12006 12007 old_crtc_state = drm_atomic_get_old_crtc_state( 12008 state, old_plane_crtc); 12009 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 12010 12011 if (!dm_old_crtc_state->stream) 12012 return 0; 12013 12014 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 12015 plane->base.id, old_plane_crtc->base.id); 12016 12017 ret = dm_atomic_get_state(state, &dm_state); 12018 if (ret) 12019 return ret; 12020 12021 if (!dc_state_remove_plane( 12022 dc, 12023 dm_old_crtc_state->stream, 12024 dm_old_plane_state->dc_state, 12025 dm_state->context)) { 12026 12027 return -EINVAL; 12028 } 12029 12030 if (dm_old_plane_state->dc_state) 12031 dc_plane_state_release(dm_old_plane_state->dc_state); 12032 12033 dm_new_plane_state->dc_state = NULL; 12034 12035 *lock_and_validation_needed = true; 12036 12037 } else { /* Add new planes */ 12038 struct dc_plane_state *dc_new_plane_state; 12039 12040 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 12041 return 0; 12042 12043 if (!new_plane_crtc) 12044 return 0; 12045 12046 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 12047 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12048 12049 if (!dm_new_crtc_state->stream) 12050 return 0; 12051 12052 if (!needs_reset) 12053 return 0; 12054 12055 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 12056 if (ret) 12057 goto out; 12058 12059 WARN_ON(dm_new_plane_state->dc_state); 12060 12061 dc_new_plane_state = dc_create_plane_state(dc); 12062 if (!dc_new_plane_state) { 12063 ret = -ENOMEM; 12064 goto out; 12065 } 12066 12067 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 12068 plane->base.id, new_plane_crtc->base.id); 12069 12070 ret = fill_dc_plane_attributes( 12071 drm_to_adev(new_plane_crtc->dev), 12072 dc_new_plane_state, 12073 new_plane_state, 12074 new_crtc_state); 12075 if (ret) { 12076 dc_plane_state_release(dc_new_plane_state); 12077 goto out; 12078 } 12079 12080 ret = dm_atomic_get_state(state, &dm_state); 12081 if (ret) { 12082 dc_plane_state_release(dc_new_plane_state); 12083 goto out; 12084 } 12085 12086 /* 12087 * Any atomic check errors that occur after this will 12088 * not need a release. The plane state will be attached 12089 * to the stream, and therefore part of the atomic 12090 * state. It'll be released when the atomic state is 12091 * cleaned. 12092 */ 12093 if (!dc_state_add_plane( 12094 dc, 12095 dm_new_crtc_state->stream, 12096 dc_new_plane_state, 12097 dm_state->context)) { 12098 12099 dc_plane_state_release(dc_new_plane_state); 12100 ret = -EINVAL; 12101 goto out; 12102 } 12103 12104 dm_new_plane_state->dc_state = dc_new_plane_state; 12105 12106 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 12107 12108 /* Tell DC to do a full surface update every time there 12109 * is a plane change. Inefficient, but works for now. 12110 */ 12111 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 12112 12113 *lock_and_validation_needed = true; 12114 } 12115 12116out: 12117 /* If enabling cursor overlay failed, attempt fallback to native mode */ 12118 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 12119 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 12120 new_plane_state, enable); 12121 if (ret) 12122 return ret; 12123 12124 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 12125 } 12126 12127 return ret; 12128} 12129 12130static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 12131 int *src_w, int *src_h) 12132{ 12133 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 12134 case DRM_MODE_ROTATE_90: 12135 case DRM_MODE_ROTATE_270: 12136 *src_w = plane_state->src_h >> 16; 12137 *src_h = plane_state->src_w >> 16; 12138 break; 12139 case DRM_MODE_ROTATE_0: 12140 case DRM_MODE_ROTATE_180: 12141 default: 12142 *src_w = plane_state->src_w >> 16; 12143 *src_h = plane_state->src_h >> 16; 12144 break; 12145 } 12146} 12147 12148static void 12149dm_get_plane_scale(struct drm_plane_state *plane_state, 12150 int *out_plane_scale_w, int *out_plane_scale_h) 12151{ 12152 int plane_src_w, plane_src_h; 12153 12154 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 12155 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0; 12156 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0; 12157} 12158 12159/* 12160 * The normalized_zpos value cannot be used by this iterator directly. It's only 12161 * calculated for enabled planes, potentially causing normalized_zpos collisions 12162 * between enabled/disabled planes in the atomic state. We need a unique value 12163 * so that the iterator will not generate the same object twice, or loop 12164 * indefinitely. 12165 */ 12166static inline struct __drm_planes_state *__get_next_zpos( 12167 struct drm_atomic_state *state, 12168 struct __drm_planes_state *prev) 12169{ 12170 unsigned int highest_zpos = 0, prev_zpos = 256; 12171 uint32_t highest_id = 0, prev_id = UINT_MAX; 12172 struct drm_plane_state *new_plane_state; 12173 struct drm_plane *plane; 12174 int i, highest_i = -1; 12175 12176 if (prev != NULL) { 12177 prev_zpos = prev->new_state->zpos; 12178 prev_id = prev->ptr->base.id; 12179 } 12180 12181 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 12182 /* Skip planes with higher zpos than the previously returned */ 12183 if (new_plane_state->zpos > prev_zpos || 12184 (new_plane_state->zpos == prev_zpos && 12185 plane->base.id >= prev_id)) 12186 continue; 12187 12188 /* Save the index of the plane with highest zpos */ 12189 if (new_plane_state->zpos > highest_zpos || 12190 (new_plane_state->zpos == highest_zpos && 12191 plane->base.id > highest_id)) { 12192 highest_zpos = new_plane_state->zpos; 12193 highest_id = plane->base.id; 12194 highest_i = i; 12195 } 12196 } 12197 12198 if (highest_i < 0) 12199 return NULL; 12200 12201 return &state->planes[highest_i]; 12202} 12203 12204/* 12205 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 12206 * by descending zpos, as read from the new plane state. This is the same 12207 * ordering as defined by drm_atomic_normalize_zpos(). 12208 */ 12209#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 12210 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 12211 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 12212 for_each_if(((plane) = __i->ptr, \ 12213 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 12214 (old_plane_state) = __i->old_state, \ 12215 (new_plane_state) = __i->new_state, 1)) 12216 12217static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 12218{ 12219 struct drm_connector *connector; 12220 struct drm_connector_state *conn_state, *old_conn_state; 12221 struct amdgpu_dm_connector *aconnector = NULL; 12222 int i; 12223 12224 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 12225 if (!conn_state->crtc) 12226 conn_state = old_conn_state; 12227 12228 if (conn_state->crtc != crtc) 12229 continue; 12230 12231 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 12232 continue; 12233 12234 aconnector = to_amdgpu_dm_connector(connector); 12235 if (!aconnector->mst_output_port || !aconnector->mst_root) 12236 aconnector = NULL; 12237 else 12238 break; 12239 } 12240 12241 if (!aconnector) 12242 return 0; 12243 12244 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 12245} 12246 12247/** 12248 * DOC: Cursor Modes - Native vs Overlay 12249 * 12250 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 12251 * plane. It does not require a dedicated hw plane to enable, but it is 12252 * subjected to the same z-order and scaling as the hw plane. It also has format 12253 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 12254 * hw plane. 12255 * 12256 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 12257 * own scaling and z-pos. It also has no blending restrictions. It lends to a 12258 * cursor behavior more akin to a DRM client's expectations. However, it does 12259 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 12260 * available. 12261 */ 12262 12263/** 12264 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 12265 * @adev: amdgpu device 12266 * @state: DRM atomic state 12267 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 12268 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 12269 * 12270 * Get whether the cursor should be enabled in native mode, or overlay mode, on 12271 * the dm_crtc_state. 12272 * 12273 * The cursor should be enabled in overlay mode if there exists an underlying 12274 * plane - on which the cursor may be blended - that is either YUV formatted, or 12275 * scaled differently from the cursor. 12276 * 12277 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 12278 * calling this function. 12279 * 12280 * Return: 0 on success, or an error code if getting the cursor plane state 12281 * failed. 12282 */ 12283static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 12284 struct drm_atomic_state *state, 12285 struct dm_crtc_state *dm_crtc_state, 12286 enum amdgpu_dm_cursor_mode *cursor_mode) 12287{ 12288 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 12289 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 12290 struct drm_plane *plane; 12291 bool consider_mode_change = false; 12292 bool entire_crtc_covered = false; 12293 bool cursor_changed = false; 12294 int underlying_scale_w, underlying_scale_h; 12295 int cursor_scale_w, cursor_scale_h; 12296 int i; 12297 12298 /* Overlay cursor not supported on HW before DCN 12299 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 12300 * as previous DCN generations, so enable native mode on DCN401 12301 */ 12302 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 12303 *cursor_mode = DM_CURSOR_NATIVE_MODE; 12304 return 0; 12305 } 12306 12307 /* Init cursor_mode to be the same as current */ 12308 *cursor_mode = dm_crtc_state->cursor_mode; 12309 12310 /* 12311 * Cursor mode can change if a plane's format changes, scale changes, is 12312 * enabled/disabled, or z-order changes. 12313 */ 12314 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 12315 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 12316 12317 /* Only care about planes on this CRTC */ 12318 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 12319 continue; 12320 12321 if (plane->type == DRM_PLANE_TYPE_CURSOR) 12322 cursor_changed = true; 12323 12324 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 12325 drm_atomic_plane_disabling(old_plane_state, plane_state) || 12326 old_plane_state->fb->format != plane_state->fb->format) { 12327 consider_mode_change = true; 12328 break; 12329 } 12330 12331 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 12332 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 12333 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 12334 consider_mode_change = true; 12335 break; 12336 } 12337 } 12338 12339 if (!consider_mode_change && !crtc_state->zpos_changed) 12340 return 0; 12341 12342 /* 12343 * If no cursor change on this CRTC, and not enabled on this CRTC, then 12344 * no need to set cursor mode. This avoids needlessly locking the cursor 12345 * state. 12346 */ 12347 if (!cursor_changed && 12348 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 12349 return 0; 12350 } 12351 12352 cursor_state = drm_atomic_get_plane_state(state, 12353 crtc_state->crtc->cursor); 12354 if (IS_ERR(cursor_state)) 12355 return PTR_ERR(cursor_state); 12356 12357 /* Cursor is disabled */ 12358 if (!cursor_state->fb) 12359 return 0; 12360 12361 /* For all planes in descending z-order (all of which are below cursor 12362 * as per zpos definitions), check their scaling and format 12363 */ 12364 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 12365 12366 /* Only care about non-cursor planes on this CRTC */ 12367 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 12368 plane->type == DRM_PLANE_TYPE_CURSOR) 12369 continue; 12370 12371 /* Underlying plane is YUV format - use overlay cursor */ 12372 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 12373 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 12374 return 0; 12375 } 12376 12377 dm_get_plane_scale(plane_state, 12378 &underlying_scale_w, &underlying_scale_h); 12379 dm_get_plane_scale(cursor_state, 12380 &cursor_scale_w, &cursor_scale_h); 12381 12382 /* Underlying plane has different scale - use overlay cursor */ 12383 if (cursor_scale_w != underlying_scale_w && 12384 cursor_scale_h != underlying_scale_h) { 12385 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 12386 return 0; 12387 } 12388 12389 /* If this plane covers the whole CRTC, no need to check planes underneath */ 12390 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 12391 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 12392 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 12393 entire_crtc_covered = true; 12394 break; 12395 } 12396 } 12397 12398 /* If planes do not cover the entire CRTC, use overlay mode to enable 12399 * cursor over holes 12400 */ 12401 if (entire_crtc_covered) 12402 *cursor_mode = DM_CURSOR_NATIVE_MODE; 12403 else 12404 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 12405 12406 return 0; 12407} 12408 12409static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 12410 struct drm_atomic_state *state, 12411 struct drm_crtc_state *crtc_state) 12412{ 12413 struct drm_plane *plane; 12414 struct drm_plane_state *new_plane_state, *old_plane_state; 12415 12416 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 12417 new_plane_state = drm_atomic_get_plane_state(state, plane); 12418 old_plane_state = drm_atomic_get_plane_state(state, plane); 12419 12420 if (IS_ERR(new_plane_state) || IS_ERR(old_plane_state)) { 12421 drm_err(dev, "Failed to get plane state for plane %s\n", plane->name); 12422 return false; 12423 } 12424 12425 if (old_plane_state->fb && new_plane_state->fb && 12426 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 12427 return true; 12428 } 12429 12430 return false; 12431} 12432 12433/** 12434 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 12435 * 12436 * @dev: The DRM device 12437 * @state: The atomic state to commit 12438 * 12439 * Validate that the given atomic state is programmable by DC into hardware. 12440 * This involves constructing a &struct dc_state reflecting the new hardware 12441 * state we wish to commit, then querying DC to see if it is programmable. It's 12442 * important not to modify the existing DC state. Otherwise, atomic_check 12443 * may unexpectedly commit hardware changes. 12444 * 12445 * When validating the DC state, it's important that the right locks are 12446 * acquired. For full updates case which removes/adds/updates streams on one 12447 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 12448 * that any such full update commit will wait for completion of any outstanding 12449 * flip using DRMs synchronization events. 12450 * 12451 * Note that DM adds the affected connectors for all CRTCs in state, when that 12452 * might not seem necessary. This is because DC stream creation requires the 12453 * DC sink, which is tied to the DRM connector state. Cleaning this up should 12454 * be possible but non-trivial - a possible TODO item. 12455 * 12456 * Return: -Error code if validation failed. 12457 */ 12458static int amdgpu_dm_atomic_check(struct drm_device *dev, 12459 struct drm_atomic_state *state) 12460{ 12461 struct amdgpu_device *adev = drm_to_adev(dev); 12462 struct dm_atomic_state *dm_state = NULL; 12463 struct dc *dc = adev->dm.dc; 12464 struct drm_connector *connector; 12465 struct drm_connector_state *old_con_state, *new_con_state; 12466 struct drm_crtc *crtc; 12467 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 12468 struct drm_plane *plane; 12469 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 12470 enum dc_status status; 12471 int ret, i; 12472 bool lock_and_validation_needed = false; 12473 bool is_top_most_overlay = true; 12474 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 12475 struct drm_dp_mst_topology_mgr *mgr; 12476 struct drm_dp_mst_topology_state *mst_state; 12477 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 12478 12479 trace_amdgpu_dm_atomic_check_begin(state); 12480 12481 ret = drm_atomic_helper_check_modeset(dev, state); 12482 if (ret) { 12483 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); 12484 goto fail; 12485 } 12486 12487 /* Check connector changes */ 12488 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 12489 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 12490 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 12491 12492 /* Skip connectors that are disabled or part of modeset already. */ 12493 if (!new_con_state->crtc) 12494 continue; 12495 12496 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 12497 if (IS_ERR(new_crtc_state)) { 12498 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); 12499 ret = PTR_ERR(new_crtc_state); 12500 goto fail; 12501 } 12502 12503 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 12504 dm_old_con_state->scaling != dm_new_con_state->scaling) 12505 new_crtc_state->connectors_changed = true; 12506 } 12507 12508 if (dc_resource_is_dsc_encoding_supported(dc)) { 12509 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12510 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12511 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 12512 } 12513 12514 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12515 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 12516 ret = add_affected_mst_dsc_crtcs(state, crtc); 12517 if (ret) { 12518 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); 12519 goto fail; 12520 } 12521 } 12522 } 12523 } 12524 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12525 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 12526 12527 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 12528 !new_crtc_state->color_mgmt_changed && 12529 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 12530 dm_old_crtc_state->dsc_force_changed == false) 12531 continue; 12532 12533 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 12534 if (ret) { 12535 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); 12536 goto fail; 12537 } 12538 12539 if (!new_crtc_state->enable) 12540 continue; 12541 12542 ret = drm_atomic_add_affected_connectors(state, crtc); 12543 if (ret) { 12544 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); 12545 goto fail; 12546 } 12547 12548 ret = drm_atomic_add_affected_planes(state, crtc); 12549 if (ret) { 12550 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); 12551 goto fail; 12552 } 12553 12554 if (dm_old_crtc_state->dsc_force_changed) 12555 new_crtc_state->mode_changed = true; 12556 } 12557 12558 /* 12559 * Add all primary and overlay planes on the CRTC to the state 12560 * whenever a plane is enabled to maintain correct z-ordering 12561 * and to enable fast surface updates. 12562 */ 12563 drm_for_each_crtc(crtc, dev) { 12564 bool modified = false; 12565 12566 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 12567 if (plane->type == DRM_PLANE_TYPE_CURSOR) 12568 continue; 12569 12570 if (new_plane_state->crtc == crtc || 12571 old_plane_state->crtc == crtc) { 12572 modified = true; 12573 break; 12574 } 12575 } 12576 12577 if (!modified) 12578 continue; 12579 12580 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 12581 if (plane->type == DRM_PLANE_TYPE_CURSOR) 12582 continue; 12583 12584 new_plane_state = 12585 drm_atomic_get_plane_state(state, plane); 12586 12587 if (IS_ERR(new_plane_state)) { 12588 ret = PTR_ERR(new_plane_state); 12589 drm_dbg_atomic(dev, "new_plane_state is BAD\n"); 12590 goto fail; 12591 } 12592 } 12593 } 12594 12595 /* 12596 * DC consults the zpos (layer_index in DC terminology) to determine the 12597 * hw plane on which to enable the hw cursor (see 12598 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 12599 * atomic state, so call drm helper to normalize zpos. 12600 */ 12601 ret = drm_atomic_normalize_zpos(dev, state); 12602 if (ret) { 12603 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 12604 goto fail; 12605 } 12606 12607 /* 12608 * Determine whether cursors on each CRTC should be enabled in native or 12609 * overlay mode. 12610 */ 12611 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 12612 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12613 12614 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 12615 &dm_new_crtc_state->cursor_mode); 12616 if (ret) { 12617 drm_dbg(dev, "Failed to determine cursor mode\n"); 12618 goto fail; 12619 } 12620 12621 /* 12622 * If overlay cursor is needed, DC cannot go through the 12623 * native cursor update path. All enabled planes on the CRTC 12624 * need to be added for DC to not disable a plane by mistake 12625 */ 12626 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 12627 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 12628 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 12629 ret = -EINVAL; 12630 goto fail; 12631 } 12632 12633 ret = drm_atomic_add_affected_planes(state, crtc); 12634 if (ret) 12635 goto fail; 12636 } 12637 } 12638 12639 /* Remove exiting planes if they are modified */ 12640 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 12641 12642 ret = dm_update_plane_state(dc, state, plane, 12643 old_plane_state, 12644 new_plane_state, 12645 false, 12646 &lock_and_validation_needed, 12647 &is_top_most_overlay); 12648 if (ret) { 12649 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 12650 goto fail; 12651 } 12652 } 12653 12654 /* Disable all crtcs which require disable */ 12655 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12656 ret = dm_update_crtc_state(&adev->dm, state, crtc, 12657 old_crtc_state, 12658 new_crtc_state, 12659 false, 12660 &lock_and_validation_needed); 12661 if (ret) { 12662 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); 12663 goto fail; 12664 } 12665 } 12666 12667 /* Enable all crtcs which require enable */ 12668 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12669 ret = dm_update_crtc_state(&adev->dm, state, crtc, 12670 old_crtc_state, 12671 new_crtc_state, 12672 true, 12673 &lock_and_validation_needed); 12674 if (ret) { 12675 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); 12676 goto fail; 12677 } 12678 } 12679 12680 /* Add new/modified planes */ 12681 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 12682 ret = dm_update_plane_state(dc, state, plane, 12683 old_plane_state, 12684 new_plane_state, 12685 true, 12686 &lock_and_validation_needed, 12687 &is_top_most_overlay); 12688 if (ret) { 12689 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 12690 goto fail; 12691 } 12692 } 12693 12694#if defined(CONFIG_DRM_AMD_DC_FP) 12695 if (dc_resource_is_dsc_encoding_supported(dc)) { 12696 ret = pre_validate_dsc(state, &dm_state, vars); 12697 if (ret != 0) 12698 goto fail; 12699 } 12700#endif 12701 12702 /* Run this here since we want to validate the streams we created */ 12703 ret = drm_atomic_helper_check_planes(dev, state); 12704 if (ret) { 12705 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); 12706 goto fail; 12707 } 12708 12709 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 12710 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12711 if (dm_new_crtc_state->mpo_requested) 12712 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 12713 } 12714 12715 /* Check cursor restrictions */ 12716 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 12717 enum amdgpu_dm_cursor_mode required_cursor_mode; 12718 int is_rotated, is_scaled; 12719 12720 /* Overlay cusor not subject to native cursor restrictions */ 12721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12722 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 12723 continue; 12724 12725 /* Check if rotation or scaling is enabled on DCN401 */ 12726 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 12727 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 12728 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 12729 12730 is_rotated = new_cursor_state && 12731 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 12732 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 12733 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 12734 12735 if (is_rotated || is_scaled) { 12736 drm_dbg_driver( 12737 crtc->dev, 12738 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 12739 crtc->base.id, crtc->name); 12740 ret = -EINVAL; 12741 goto fail; 12742 } 12743 } 12744 12745 /* If HW can only do native cursor, check restrictions again */ 12746 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 12747 &required_cursor_mode); 12748 if (ret) { 12749 drm_dbg_driver(crtc->dev, 12750 "[CRTC:%d:%s] Checking cursor mode failed\n", 12751 crtc->base.id, crtc->name); 12752 goto fail; 12753 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 12754 drm_dbg_driver(crtc->dev, 12755 "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n", 12756 crtc->base.id, crtc->name); 12757 ret = -EINVAL; 12758 goto fail; 12759 } 12760 } 12761 12762 if (state->legacy_cursor_update) { 12763 /* 12764 * This is a fast cursor update coming from the plane update 12765 * helper, check if it can be done asynchronously for better 12766 * performance. 12767 */ 12768 state->async_update = 12769 !drm_atomic_helper_async_check(dev, state); 12770 12771 /* 12772 * Skip the remaining global validation if this is an async 12773 * update. Cursor updates can be done without affecting 12774 * state or bandwidth calcs and this avoids the performance 12775 * penalty of locking the private state object and 12776 * allocating a new dc_state. 12777 */ 12778 if (state->async_update) 12779 return 0; 12780 } 12781 12782 /* Check scaling and underscan changes*/ 12783 /* TODO Removed scaling changes validation due to inability to commit 12784 * new stream into context w\o causing full reset. Need to 12785 * decide how to handle. 12786 */ 12787 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 12788 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 12789 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 12790 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 12791 12792 /* Skip any modesets/resets */ 12793 if (!acrtc || drm_atomic_crtc_needs_modeset( 12794 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 12795 continue; 12796 12797 /* Skip any thing not scale or underscan changes */ 12798 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 12799 continue; 12800 12801 lock_and_validation_needed = true; 12802 } 12803 12804 /* set the slot info for each mst_state based on the link encoding format */ 12805 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 12806 struct amdgpu_dm_connector *aconnector; 12807 struct drm_connector *connector; 12808 struct drm_connector_list_iter iter; 12809 u8 link_coding_cap; 12810 12811 drm_connector_list_iter_begin(dev, &iter); 12812 drm_for_each_connector_iter(connector, &iter) { 12813 if (connector->index == mst_state->mgr->conn_base_id) { 12814 aconnector = to_amdgpu_dm_connector(connector); 12815 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 12816 drm_dp_mst_update_slots(mst_state, link_coding_cap); 12817 12818 break; 12819 } 12820 } 12821 drm_connector_list_iter_end(&iter); 12822 } 12823 12824 /** 12825 * Streams and planes are reset when there are changes that affect 12826 * bandwidth. Anything that affects bandwidth needs to go through 12827 * DC global validation to ensure that the configuration can be applied 12828 * to hardware. 12829 * 12830 * We have to currently stall out here in atomic_check for outstanding 12831 * commits to finish in this case because our IRQ handlers reference 12832 * DRM state directly - we can end up disabling interrupts too early 12833 * if we don't. 12834 * 12835 * TODO: Remove this stall and drop DM state private objects. 12836 */ 12837 if (lock_and_validation_needed) { 12838 ret = dm_atomic_get_state(state, &dm_state); 12839 if (ret) { 12840 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); 12841 goto fail; 12842 } 12843 12844 ret = do_aquire_global_lock(dev, state); 12845 if (ret) { 12846 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); 12847 goto fail; 12848 } 12849 12850#if defined(CONFIG_DRM_AMD_DC_FP) 12851 if (dc_resource_is_dsc_encoding_supported(dc)) { 12852 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 12853 if (ret) { 12854 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n"); 12855 ret = -EINVAL; 12856 goto fail; 12857 } 12858 } 12859#endif 12860 12861 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 12862 if (ret) { 12863 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); 12864 goto fail; 12865 } 12866 12867 /* 12868 * Perform validation of MST topology in the state: 12869 * We need to perform MST atomic check before calling 12870 * dc_validate_global_state(), or there is a chance 12871 * to get stuck in an infinite loop and hang eventually. 12872 */ 12873 ret = drm_dp_mst_atomic_check(state); 12874 if (ret) { 12875 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); 12876 goto fail; 12877 } 12878 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 12879 if (status != DC_OK) { 12880 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 12881 dc_status_to_str(status), status); 12882 ret = -EINVAL; 12883 goto fail; 12884 } 12885 } else { 12886 /* 12887 * The commit is a fast update. Fast updates shouldn't change 12888 * the DC context, affect global validation, and can have their 12889 * commit work done in parallel with other commits not touching 12890 * the same resource. If we have a new DC context as part of 12891 * the DM atomic state from validation we need to free it and 12892 * retain the existing one instead. 12893 * 12894 * Furthermore, since the DM atomic state only contains the DC 12895 * context and can safely be annulled, we can free the state 12896 * and clear the associated private object now to free 12897 * some memory and avoid a possible use-after-free later. 12898 */ 12899 12900 for (i = 0; i < state->num_private_objs; i++) { 12901 struct drm_private_obj *obj = state->private_objs[i].ptr; 12902 12903 if (obj->funcs == adev->dm.atomic_obj.funcs) { 12904 int j = state->num_private_objs-1; 12905 12906 dm_atomic_destroy_state(obj, 12907 state->private_objs[i].state_to_destroy); 12908 12909 /* If i is not at the end of the array then the 12910 * last element needs to be moved to where i was 12911 * before the array can safely be truncated. 12912 */ 12913 if (i != j) 12914 state->private_objs[i] = 12915 state->private_objs[j]; 12916 12917 state->private_objs[j].ptr = NULL; 12918 state->private_objs[j].state_to_destroy = NULL; 12919 state->private_objs[j].old_state = NULL; 12920 state->private_objs[j].new_state = NULL; 12921 12922 state->num_private_objs = j; 12923 break; 12924 } 12925 } 12926 } 12927 12928 /* Store the overall update type for use later in atomic check. */ 12929 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 12930 struct dm_crtc_state *dm_new_crtc_state = 12931 to_dm_crtc_state(new_crtc_state); 12932 12933 /* 12934 * Only allow async flips for fast updates that don't change 12935 * the FB pitch, the DCC state, rotation, mem_type, etc. 12936 */ 12937 if (new_crtc_state->async_flip && 12938 (lock_and_validation_needed || 12939 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 12940 drm_dbg_atomic(crtc->dev, 12941 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 12942 crtc->base.id, crtc->name); 12943 ret = -EINVAL; 12944 goto fail; 12945 } 12946 12947 dm_new_crtc_state->update_type = lock_and_validation_needed ? 12948 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 12949 } 12950 12951 /* Must be success */ 12952 WARN_ON(ret); 12953 12954 trace_amdgpu_dm_atomic_check_finish(state, ret); 12955 12956 return ret; 12957 12958fail: 12959 if (ret == -EDEADLK) 12960 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 12961 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 12962 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 12963 else 12964 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); 12965 12966 trace_amdgpu_dm_atomic_check_finish(state, ret); 12967 12968 return ret; 12969} 12970 12971static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 12972 unsigned int offset, 12973 unsigned int total_length, 12974 u8 *data, 12975 unsigned int length, 12976 struct amdgpu_hdmi_vsdb_info *vsdb) 12977{ 12978 bool res; 12979 union dmub_rb_cmd cmd; 12980 struct dmub_cmd_send_edid_cea *input; 12981 struct dmub_cmd_edid_cea_output *output; 12982 12983 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 12984 return false; 12985 12986 memset(&cmd, 0, sizeof(cmd)); 12987 12988 input = &cmd.edid_cea.data.input; 12989 12990 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 12991 cmd.edid_cea.header.sub_type = 0; 12992 cmd.edid_cea.header.payload_bytes = 12993 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 12994 input->offset = offset; 12995 input->length = length; 12996 input->cea_total_length = total_length; 12997 memcpy(input->payload, data, length); 12998 12999 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 13000 if (!res) { 13001 drm_err(adev_to_drm(dm->adev), "EDID CEA parser failed\n"); 13002 return false; 13003 } 13004 13005 output = &cmd.edid_cea.data.output; 13006 13007 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 13008 if (!output->ack.success) { 13009 drm_err(adev_to_drm(dm->adev), "EDID CEA ack failed at offset %d\n", 13010 output->ack.offset); 13011 } 13012 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 13013 if (!output->amd_vsdb.vsdb_found) 13014 return false; 13015 13016 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 13017 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 13018 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 13019 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 13020 } else { 13021 drm_warn(adev_to_drm(dm->adev), "Unknown EDID CEA parser results\n"); 13022 return false; 13023 } 13024 13025 return true; 13026} 13027 13028static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 13029 u8 *edid_ext, int len, 13030 struct amdgpu_hdmi_vsdb_info *vsdb_info) 13031{ 13032 int i; 13033 13034 /* send extension block to DMCU for parsing */ 13035 for (i = 0; i < len; i += 8) { 13036 bool res; 13037 int offset; 13038 13039 /* send 8 bytes a time */ 13040 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 13041 return false; 13042 13043 if (i+8 == len) { 13044 /* EDID block sent completed, expect result */ 13045 int version, min_rate, max_rate; 13046 13047 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 13048 if (res) { 13049 /* amd vsdb found */ 13050 vsdb_info->freesync_supported = 1; 13051 vsdb_info->amd_vsdb_version = version; 13052 vsdb_info->min_refresh_rate_hz = min_rate; 13053 vsdb_info->max_refresh_rate_hz = max_rate; 13054 return true; 13055 } 13056 /* not amd vsdb */ 13057 return false; 13058 } 13059 13060 /* check for ack*/ 13061 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 13062 if (!res) 13063 return false; 13064 } 13065 13066 return false; 13067} 13068 13069static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 13070 u8 *edid_ext, int len, 13071 struct amdgpu_hdmi_vsdb_info *vsdb_info) 13072{ 13073 int i; 13074 13075 /* send extension block to DMCU for parsing */ 13076 for (i = 0; i < len; i += 8) { 13077 /* send 8 bytes a time */ 13078 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 13079 return false; 13080 } 13081 13082 return vsdb_info->freesync_supported; 13083} 13084 13085static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 13086 u8 *edid_ext, int len, 13087 struct amdgpu_hdmi_vsdb_info *vsdb_info) 13088{ 13089 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 13090 bool ret; 13091 13092 mutex_lock(&adev->dm.dc_lock); 13093 if (adev->dm.dmub_srv) 13094 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 13095 else 13096 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 13097 mutex_unlock(&adev->dm.dc_lock); 13098 return ret; 13099} 13100 13101static void parse_edid_displayid_vrr(struct drm_connector *connector, 13102 const struct edid *edid) 13103{ 13104 u8 *edid_ext = NULL; 13105 int i; 13106 int j = 0; 13107 u16 min_vfreq; 13108 u16 max_vfreq; 13109 13110 if (!edid || !edid->extensions) 13111 return; 13112 13113 /* Find DisplayID extension */ 13114 for (i = 0; i < edid->extensions; i++) { 13115 edid_ext = (void *)(edid + (i + 1)); 13116 if (edid_ext[0] == DISPLAYID_EXT) 13117 break; 13118 } 13119 13120 if (i == edid->extensions) 13121 return; 13122 13123 while (j < EDID_LENGTH) { 13124 /* Get dynamic video timing range from DisplayID if available */ 13125 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && 13126 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { 13127 min_vfreq = edid_ext[j+9]; 13128 if (edid_ext[j+1] & 7) 13129 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); 13130 else 13131 max_vfreq = edid_ext[j+10]; 13132 13133 if (max_vfreq && min_vfreq) { 13134 connector->display_info.monitor_range.max_vfreq = max_vfreq; 13135 connector->display_info.monitor_range.min_vfreq = min_vfreq; 13136 13137 return; 13138 } 13139 } 13140 j++; 13141 } 13142} 13143 13144static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 13145 const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 13146{ 13147 u8 *edid_ext = NULL; 13148 int i; 13149 int j = 0; 13150 13151 if (edid == NULL || edid->extensions == 0) 13152 return -ENODEV; 13153 13154 /* Find DisplayID extension */ 13155 for (i = 0; i < edid->extensions; i++) { 13156 edid_ext = (void *)(edid + (i + 1)); 13157 if (edid_ext[0] == DISPLAYID_EXT) 13158 break; 13159 } 13160 13161 while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) { 13162 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 13163 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 13164 13165 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 13166 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 13167 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 13168 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 13169 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 13170 13171 return true; 13172 } 13173 j++; 13174 } 13175 13176 return false; 13177} 13178 13179static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 13180 const struct edid *edid, 13181 struct amdgpu_hdmi_vsdb_info *vsdb_info) 13182{ 13183 u8 *edid_ext = NULL; 13184 int i; 13185 bool valid_vsdb_found = false; 13186 13187 /*----- drm_find_cea_extension() -----*/ 13188 /* No EDID or EDID extensions */ 13189 if (edid == NULL || edid->extensions == 0) 13190 return -ENODEV; 13191 13192 /* Find CEA extension */ 13193 for (i = 0; i < edid->extensions; i++) { 13194 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 13195 if (edid_ext[0] == CEA_EXT) 13196 break; 13197 } 13198 13199 if (i == edid->extensions) 13200 return -ENODEV; 13201 13202 /*----- cea_db_offsets() -----*/ 13203 if (edid_ext[0] != CEA_EXT) 13204 return -ENODEV; 13205 13206 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 13207 13208 return valid_vsdb_found ? i : -ENODEV; 13209} 13210 13211/** 13212 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 13213 * 13214 * @connector: Connector to query. 13215 * @drm_edid: DRM EDID from monitor 13216 * 13217 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 13218 * track of some of the display information in the internal data struct used by 13219 * amdgpu_dm. This function checks which type of connector we need to set the 13220 * FreeSync parameters. 13221 */ 13222void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 13223 const struct drm_edid *drm_edid) 13224{ 13225 int i = 0; 13226 struct amdgpu_dm_connector *amdgpu_dm_connector = 13227 to_amdgpu_dm_connector(connector); 13228 struct dm_connector_state *dm_con_state = NULL; 13229 struct dc_sink *sink; 13230 struct amdgpu_device *adev = drm_to_adev(connector->dev); 13231 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 13232 const struct edid *edid; 13233 bool freesync_capable = false; 13234 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 13235 13236 if (!connector->state) { 13237 drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__); 13238 goto update; 13239 } 13240 13241 sink = amdgpu_dm_connector->dc_sink ? 13242 amdgpu_dm_connector->dc_sink : 13243 amdgpu_dm_connector->dc_em_sink; 13244 13245 drm_edid_connector_update(connector, drm_edid); 13246 13247 if (!drm_edid || !sink) { 13248 dm_con_state = to_dm_connector_state(connector->state); 13249 13250 amdgpu_dm_connector->min_vfreq = 0; 13251 amdgpu_dm_connector->max_vfreq = 0; 13252 freesync_capable = false; 13253 13254 goto update; 13255 } 13256 13257 dm_con_state = to_dm_connector_state(connector->state); 13258 13259 if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) 13260 goto update; 13261 13262 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() 13263 13264 /* Some eDP panels only have the refresh rate range info in DisplayID */ 13265 if ((connector->display_info.monitor_range.min_vfreq == 0 || 13266 connector->display_info.monitor_range.max_vfreq == 0)) 13267 parse_edid_displayid_vrr(connector, edid); 13268 13269 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 13270 sink->sink_signal == SIGNAL_TYPE_EDP)) { 13271 if (amdgpu_dm_connector->dc_link && 13272 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { 13273 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 13274 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 13275 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 13276 freesync_capable = true; 13277 } 13278 13279 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 13280 13281 if (vsdb_info.replay_mode) { 13282 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 13283 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 13284 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 13285 } 13286 13287 } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 13288 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 13289 if (i >= 0 && vsdb_info.freesync_supported) { 13290 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 13291 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 13292 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 13293 freesync_capable = true; 13294 13295 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 13296 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 13297 } 13298 } 13299 13300 if (amdgpu_dm_connector->dc_link) 13301 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 13302 13303 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 13304 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 13305 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 13306 13307 amdgpu_dm_connector->pack_sdp_v1_3 = true; 13308 amdgpu_dm_connector->as_type = as_type; 13309 amdgpu_dm_connector->vsdb_info = vsdb_info; 13310 13311 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 13312 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 13313 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 13314 freesync_capable = true; 13315 13316 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 13317 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 13318 } 13319 } 13320 13321update: 13322 if (dm_con_state) 13323 dm_con_state->freesync_capable = freesync_capable; 13324 13325 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && 13326 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { 13327 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false; 13328 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false; 13329 } 13330 13331 if (connector->vrr_capable_property) 13332 drm_connector_set_vrr_capable_property(connector, 13333 freesync_capable); 13334} 13335 13336void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 13337{ 13338 struct amdgpu_device *adev = drm_to_adev(dev); 13339 struct dc *dc = adev->dm.dc; 13340 int i; 13341 13342 mutex_lock(&adev->dm.dc_lock); 13343 if (dc->current_state) { 13344 for (i = 0; i < dc->current_state->stream_count; ++i) 13345 dc->current_state->streams[i] 13346 ->triggered_crtc_reset.enabled = 13347 adev->dm.force_timing_sync; 13348 13349 dm_enable_per_frame_crtc_master_sync(dc->current_state); 13350 dc_trigger_sync(dc, dc->current_state); 13351 } 13352 mutex_unlock(&adev->dm.dc_lock); 13353} 13354 13355static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 13356{ 13357 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 13358 dc_exit_ips_for_hw_access(dc); 13359} 13360 13361void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 13362 u32 value, const char *func_name) 13363{ 13364#ifdef DM_CHECK_ADDR_0 13365 if (address == 0) { 13366 drm_err(adev_to_drm(ctx->driver_context), 13367 "invalid register write. address = 0"); 13368 return; 13369 } 13370#endif 13371 13372 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 13373 cgs_write_register(ctx->cgs_device, address, value); 13374 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 13375} 13376 13377uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 13378 const char *func_name) 13379{ 13380 u32 value; 13381#ifdef DM_CHECK_ADDR_0 13382 if (address == 0) { 13383 drm_err(adev_to_drm(ctx->driver_context), 13384 "invalid register read; address = 0\n"); 13385 return 0; 13386 } 13387#endif 13388 13389 if (ctx->dmub_srv && 13390 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 13391 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 13392 ASSERT(false); 13393 return 0; 13394 } 13395 13396 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 13397 13398 value = cgs_read_register(ctx->cgs_device, address); 13399 13400 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 13401 13402 return value; 13403} 13404 13405int amdgpu_dm_process_dmub_aux_transfer_sync( 13406 struct dc_context *ctx, 13407 unsigned int link_index, 13408 struct aux_payload *payload, 13409 enum aux_return_code_type *operation_result) 13410{ 13411 struct amdgpu_device *adev = ctx->driver_context; 13412 struct dmub_notification *p_notify = adev->dm.dmub_notify; 13413 int ret = -1; 13414 13415 mutex_lock(&adev->dm.dpia_aux_lock); 13416 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 13417 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 13418 goto out; 13419 } 13420 13421 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 13422 drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!"); 13423 *operation_result = AUX_RET_ERROR_TIMEOUT; 13424 goto out; 13425 } 13426 13427 if (p_notify->result != AUX_RET_SUCCESS) { 13428 /* 13429 * Transient states before tunneling is enabled could 13430 * lead to this error. We can ignore this for now. 13431 */ 13432 if (p_notify->result == AUX_RET_ERROR_PROTOCOL_ERROR) { 13433 drm_warn(adev_to_drm(adev), "DPIA AUX failed on 0x%x(%d), error %d\n", 13434 payload->address, payload->length, 13435 p_notify->result); 13436 } 13437 *operation_result = p_notify->result; 13438 goto out; 13439 } 13440 13441 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command & 0xF; 13442 if (adev->dm.dmub_notify->aux_reply.command & 0xF0) 13443 /* The reply is stored in the top nibble of the command. */ 13444 payload->reply[0] = (adev->dm.dmub_notify->aux_reply.command >> 4) & 0xF; 13445 13446 /*write req may receive a byte indicating partially written number as well*/ 13447 if (p_notify->aux_reply.length) 13448 memcpy(payload->data, p_notify->aux_reply.data, 13449 p_notify->aux_reply.length); 13450 13451 /* success */ 13452 ret = p_notify->aux_reply.length; 13453 *operation_result = p_notify->result; 13454out: 13455 reinit_completion(&adev->dm.dmub_aux_transfer_done); 13456 mutex_unlock(&adev->dm.dpia_aux_lock); 13457 return ret; 13458} 13459 13460static void abort_fused_io( 13461 struct dc_context *ctx, 13462 const struct dmub_cmd_fused_request *request 13463) 13464{ 13465 union dmub_rb_cmd command = { 0 }; 13466 struct dmub_rb_cmd_fused_io *io = &command.fused_io; 13467 13468 io->header.type = DMUB_CMD__FUSED_IO; 13469 io->header.sub_type = DMUB_CMD__FUSED_IO_ABORT; 13470 io->header.payload_bytes = sizeof(*io) - sizeof(io->header); 13471 io->request = *request; 13472 dm_execute_dmub_cmd(ctx, &command, DM_DMUB_WAIT_TYPE_NO_WAIT); 13473} 13474 13475static bool execute_fused_io( 13476 struct amdgpu_device *dev, 13477 struct dc_context *ctx, 13478 union dmub_rb_cmd *commands, 13479 uint8_t count, 13480 uint32_t timeout_us 13481) 13482{ 13483 const uint8_t ddc_line = commands[0].fused_io.request.u.aux.ddc_line; 13484 13485 if (ddc_line >= ARRAY_SIZE(dev->dm.fused_io)) 13486 return false; 13487 13488 struct fused_io_sync *sync = &dev->dm.fused_io[ddc_line]; 13489 struct dmub_rb_cmd_fused_io *first = &commands[0].fused_io; 13490 const bool result = dm_execute_dmub_cmd_list(ctx, count, commands, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 13491 && first->header.ret_status 13492 && first->request.status == FUSED_REQUEST_STATUS_SUCCESS; 13493 13494 if (!result) 13495 return false; 13496 13497 while (wait_for_completion_timeout(&sync->replied, usecs_to_jiffies(timeout_us))) { 13498 reinit_completion(&sync->replied); 13499 13500 struct dmub_cmd_fused_request *reply = (struct dmub_cmd_fused_request *) sync->reply_data; 13501 13502 static_assert(sizeof(*reply) <= sizeof(sync->reply_data), "Size mismatch"); 13503 13504 if (reply->identifier == first->request.identifier) { 13505 first->request = *reply; 13506 return true; 13507 } 13508 } 13509 13510 reinit_completion(&sync->replied); 13511 first->request.status = FUSED_REQUEST_STATUS_TIMEOUT; 13512 abort_fused_io(ctx, &first->request); 13513 return false; 13514} 13515 13516bool amdgpu_dm_execute_fused_io( 13517 struct amdgpu_device *dev, 13518 struct dc_link *link, 13519 union dmub_rb_cmd *commands, 13520 uint8_t count, 13521 uint32_t timeout_us) 13522{ 13523 struct amdgpu_display_manager *dm = &dev->dm; 13524 13525 mutex_lock(&dm->dpia_aux_lock); 13526 13527 const bool result = execute_fused_io(dev, link->ctx, commands, count, timeout_us); 13528 13529 mutex_unlock(&dm->dpia_aux_lock); 13530 return result; 13531} 13532 13533int amdgpu_dm_process_dmub_set_config_sync( 13534 struct dc_context *ctx, 13535 unsigned int link_index, 13536 struct set_config_cmd_payload *payload, 13537 enum set_config_status *operation_result) 13538{ 13539 struct amdgpu_device *adev = ctx->driver_context; 13540 bool is_cmd_complete; 13541 int ret; 13542 13543 mutex_lock(&adev->dm.dpia_aux_lock); 13544 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 13545 link_index, payload, adev->dm.dmub_notify); 13546 13547 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 13548 ret = 0; 13549 *operation_result = adev->dm.dmub_notify->sc_status; 13550 } else { 13551 drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!"); 13552 ret = -1; 13553 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 13554 } 13555 13556 if (!is_cmd_complete) 13557 reinit_completion(&adev->dm.dmub_aux_transfer_done); 13558 mutex_unlock(&adev->dm.dpia_aux_lock); 13559 return ret; 13560} 13561 13562bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 13563{ 13564 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 13565} 13566 13567bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 13568{ 13569 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 13570} 13571 13572void dm_acpi_process_phy_transition_interlock( 13573 const struct dc_context *ctx, 13574 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 13575{ 13576 // Not yet implemented 13577}
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