kfd_process_queue_manager.c

   1// SPDX-License-Identifier: GPL-2.0 OR MIT
   2/*
   3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 */
  24
  25#include <linux/slab.h>
  26#include <linux/list.h>
  27#include "kfd_device_queue_manager.h"
  28#include "kfd_priv.h"
  29#include "kfd_kernel_queue.h"
  30#include "amdgpu_amdkfd.h"
  31#include "amdgpu_reset.h"
  32
  33static inline struct process_queue_node *get_queue_by_qid(
  34			struct process_queue_manager *pqm, unsigned int qid)
  35{
  36	struct process_queue_node *pqn;
  37
  38	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
  39		if ((pqn->q && pqn->q->properties.queue_id == qid) ||
  40		    (pqn->kq && pqn->kq->queue->properties.queue_id == qid))
  41			return pqn;
  42	}
  43
  44	return NULL;
  45}
  46
  47static int assign_queue_slot_by_qid(struct process_queue_manager *pqm,
  48				    unsigned int qid)
  49{
  50	if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
  51		return -EINVAL;
  52
  53	if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) {
  54		pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid);
  55		return -ENOSPC;
  56	}
  57
  58	return 0;
  59}
  60
  61static int find_available_queue_slot(struct process_queue_manager *pqm,
  62					unsigned int *qid)
  63{
  64	unsigned long found;
  65
  66	found = find_first_zero_bit(pqm->queue_slot_bitmap,
  67			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
  68
  69	pr_debug("The new slot id %lu\n", found);
  70
  71	if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
  72		pr_info("Cannot open more queues for process with pid %d\n",
  73			pqm->process->lead_thread->pid);
  74		return -ENOMEM;
  75	}
  76
  77	set_bit(found, pqm->queue_slot_bitmap);
  78	*qid = found;
  79
  80	return 0;
  81}
  82
  83void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
  84{
  85	struct kfd_node *dev = pdd->dev;
  86
  87	if (pdd->already_dequeued)
  88		return;
  89	/* The MES context flush needs to filter out the case which the
  90	 * KFD process is created without setting up the MES context and
  91	 * queue for creating a compute queue.
  92	 */
  93	dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
  94	if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr &&
  95	    down_read_trylock(&dev->adev->reset_domain->sem)) {
  96		amdgpu_mes_flush_shader_debugger(dev->adev,
  97						 pdd->proc_ctx_gpu_addr);
  98		up_read(&dev->adev->reset_domain->sem);
  99	}
 100	pdd->already_dequeued = true;
 101}
 102
 103int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
 104			void *gws)
 105{
 106	struct mqd_update_info minfo = {0};
 107	struct kfd_node *dev = NULL;
 108	struct process_queue_node *pqn;
 109	struct kfd_process_device *pdd;
 110	struct kgd_mem *mem = NULL;
 111	int ret;
 112
 113	pqn = get_queue_by_qid(pqm, qid);
 114	if (!pqn) {
 115		pr_err("Queue id does not match any known queue\n");
 116		return -EINVAL;
 117	}
 118
 119	if (pqn->q)
 120		dev = pqn->q->device;
 121	if (WARN_ON(!dev))
 122		return -ENODEV;
 123
 124	pdd = kfd_get_process_device_data(dev, pqm->process);
 125	if (!pdd) {
 126		pr_err("Process device data doesn't exist\n");
 127		return -EINVAL;
 128	}
 129
 130	/* Only allow one queue per process can have GWS assigned */
 131	if (gws && pdd->qpd.num_gws)
 132		return -EBUSY;
 133
 134	if (!gws && pdd->qpd.num_gws == 0)
 135		return -EINVAL;
 136
 137	if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &&
 138	     KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &&
 139	     KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) &&
 140	    !dev->kfd->shared_resources.enable_mes) {
 141		if (gws)
 142			ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info,
 143				gws, &mem);
 144		else
 145			ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info,
 146				pqn->q->gws);
 147		if (unlikely(ret))
 148			return ret;
 149		pqn->q->gws = mem;
 150	} else {
 151		/*
 152		 * Intentionally set GWS to a non-NULL value
 153		 * for devices that do not use GWS for global wave
 154		 * synchronization but require the formality
 155		 * of setting GWS for cooperative groups.
 156		 */
 157		pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL;
 158	}
 159
 160	pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0;
 161	minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0;
 162
 163	return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
 164							pqn->q, &minfo);
 165}
 166
 167void kfd_process_dequeue_from_all_devices(struct kfd_process *p)
 168{
 169	int i;
 170
 171	for (i = 0; i < p->n_pdds; i++)
 172		kfd_process_dequeue_from_device(p->pdds[i]);
 173}
 174
 175int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
 176{
 177	INIT_LIST_HEAD(&pqm->queues);
 178	pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
 179					       GFP_KERNEL);
 180	if (!pqm->queue_slot_bitmap)
 181		return -ENOMEM;
 182	pqm->process = p;
 183
 184	return 0;
 185}
 186
 187static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
 188				     struct process_queue_node *pqn)
 189{
 190	struct kfd_node *dev;
 191	struct kfd_process_device *pdd;
 192
 193	dev = pqn->q->device;
 194
 195	pdd = kfd_get_process_device_data(dev, pqm->process);
 196	if (!pdd) {
 197		pr_err("Process device data doesn't exist\n");
 198		return;
 199	}
 200
 201	if (pqn->q->gws) {
 202		if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
 203		    KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) &&
 204		    KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) &&
 205		    !dev->kfd->shared_resources.enable_mes)
 206			amdgpu_amdkfd_remove_gws_from_process(
 207				pqm->process->kgd_process_info, pqn->q->gws);
 208		pdd->qpd.num_gws = 0;
 209	}
 210
 211	if (dev->kfd->shared_resources.enable_mes) {
 212		amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo);
 213		amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart);
 214	}
 215}
 216
 217void pqm_uninit(struct process_queue_manager *pqm)
 218{
 219	struct process_queue_node *pqn, *next;
 220
 221	list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
 222		if (pqn->q) {
 223			struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device,
 224										     pqm->process);
 225			if (pdd) {
 226				kfd_queue_unref_bo_vas(pdd, &pqn->q->properties);
 227				kfd_queue_release_buffers(pdd, &pqn->q->properties);
 228			} else {
 229				WARN_ON(!pdd);
 230			}
 231			pqm_clean_queue_resource(pqm, pqn);
 232		}
 233
 234		kfd_procfs_del_queue(pqn->q);
 235		uninit_queue(pqn->q);
 236		list_del(&pqn->process_queue_list);
 237		kfree(pqn);
 238	}
 239
 240	bitmap_free(pqm->queue_slot_bitmap);
 241	pqm->queue_slot_bitmap = NULL;
 242}
 243
 244static int init_user_queue(struct process_queue_manager *pqm,
 245				struct kfd_node *dev, struct queue **q,
 246				struct queue_properties *q_properties,
 247				unsigned int qid)
 248{
 249	int retval;
 250
 251	/* Doorbell initialized in user space*/
 252	q_properties->doorbell_ptr = NULL;
 253	q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW);
 254
 255	/* let DQM handle it*/
 256	q_properties->vmid = 0;
 257	q_properties->queue_id = qid;
 258
 259	retval = init_queue(q, q_properties);
 260	if (retval != 0)
 261		return retval;
 262
 263	(*q)->device = dev;
 264	(*q)->process = pqm->process;
 265
 266	if (dev->kfd->shared_resources.enable_mes) {
 267		retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
 268						AMDGPU_MES_GANG_CTX_SIZE,
 269						&(*q)->gang_ctx_bo,
 270						&(*q)->gang_ctx_gpu_addr,
 271						&(*q)->gang_ctx_cpu_ptr,
 272						false);
 273		if (retval) {
 274			pr_err("failed to allocate gang context bo\n");
 275			goto cleanup;
 276		}
 277		memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);
 278
 279		/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
 280		 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
 281		 */
 282		if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) {
 283			pr_err("Queue memory allocated to wrong device\n");
 284			retval = -EINVAL;
 285			goto free_gang_ctx_bo;
 286		}
 287
 288		retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo,
 289							  &(*q)->wptr_bo_gart);
 290		if (retval) {
 291			pr_err("Failed to map wptr bo to GART\n");
 292			goto free_gang_ctx_bo;
 293		}
 294	}
 295
 296	pr_debug("PQM After init queue");
 297	return 0;
 298
 299free_gang_ctx_bo:
 300	amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo);
 301cleanup:
 302	uninit_queue(*q);
 303	*q = NULL;
 304	return retval;
 305}
 306
 307int pqm_create_queue(struct process_queue_manager *pqm,
 308			    struct kfd_node *dev,
 309			    struct queue_properties *properties,
 310			    unsigned int *qid,
 311			    const struct kfd_criu_queue_priv_data *q_data,
 312			    const void *restore_mqd,
 313			    const void *restore_ctl_stack,
 314			    uint32_t *p_doorbell_offset_in_process)
 315{
 316	int retval;
 317	struct kfd_process_device *pdd;
 318	struct queue *q;
 319	struct process_queue_node *pqn;
 320	struct kernel_queue *kq;
 321	enum kfd_queue_type type = properties->type;
 322	unsigned int max_queues = 127; /* HWS limit */
 323
 324	/*
 325	 * On GFX 9.4.3/9.5.0, increase the number of queues that
 326	 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0.
 327	 */
 328	if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||
 329	    KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||
 330	    KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))
 331		max_queues = 255;
 332
 333	q = NULL;
 334	kq = NULL;
 335
 336	pdd = kfd_get_process_device_data(dev, pqm->process);
 337	if (!pdd) {
 338		pr_err("Process device data doesn't exist\n");
 339		return -1;
 340	}
 341
 342	/*
 343	 * for debug process, verify that it is within the static queues limit
 344	 * currently limit is set to half of the total avail HQD slots
 345	 * If we are just about to create DIQ, the is_debug flag is not set yet
 346	 * Hence we also check the type as well
 347	 */
 348	if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ))
 349		max_queues = dev->kfd->device_info.max_no_of_hqd/2;
 350
 351	if (pdd->qpd.queue_count >= max_queues)
 352		return -ENOSPC;
 353
 354	if (q_data) {
 355		retval = assign_queue_slot_by_qid(pqm, q_data->q_id);
 356		*qid = q_data->q_id;
 357	} else
 358		retval = find_available_queue_slot(pqm, qid);
 359
 360	if (retval != 0)
 361		return retval;
 362
 363	/* Register process if this is the first queue */
 364	if (list_empty(&pdd->qpd.queues_list) &&
 365	    list_empty(&pdd->qpd.priv_queue_list))
 366		dev->dqm->ops.register_process(dev->dqm, &pdd->qpd);
 367
 368	/* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */
 369	if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
 370		retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
 371						     AMDGPU_MES_PROC_CTX_SIZE,
 372						     &pdd->proc_ctx_bo,
 373						     &pdd->proc_ctx_gpu_addr,
 374						     &pdd->proc_ctx_cpu_ptr,
 375						     false);
 376		if (retval) {
 377			dev_err(dev->adev->dev, "failed to allocate process context bo\n");
 378			return retval;
 379		}
 380		memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
 381	}
 382
 383	pqn = kzalloc(sizeof(*pqn), GFP_KERNEL);
 384	if (!pqn) {
 385		retval = -ENOMEM;
 386		goto err_allocate_pqn;
 387	}
 388
 389	switch (type) {
 390	case KFD_QUEUE_TYPE_SDMA:
 391	case KFD_QUEUE_TYPE_SDMA_XGMI:
 392	case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID:
 393		/* SDMA queues are always allocated statically no matter
 394		 * which scheduler mode is used. We also do not need to
 395		 * check whether a SDMA queue can be allocated here, because
 396		 * allocate_sdma_queue() in create_queue() has the
 397		 * corresponding check logic.
 398		 */
 399		retval = init_user_queue(pqm, dev, &q, properties, *qid);
 400		if (retval != 0)
 401			goto err_create_queue;
 402		pqn->q = q;
 403		pqn->kq = NULL;
 404		retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
 405						    restore_mqd, restore_ctl_stack);
 406		print_queue(q);
 407		break;
 408
 409	case KFD_QUEUE_TYPE_COMPUTE:
 410		/* check if there is over subscription */
 411		if ((dev->dqm->sched_policy ==
 412		     KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
 413		((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
 414		(dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) {
 415			pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n");
 416			retval = -EPERM;
 417			goto err_create_queue;
 418		}
 419
 420		retval = init_user_queue(pqm, dev, &q, properties, *qid);
 421		if (retval != 0)
 422			goto err_create_queue;
 423		pqn->q = q;
 424		pqn->kq = NULL;
 425		retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
 426						    restore_mqd, restore_ctl_stack);
 427		print_queue(q);
 428		break;
 429	case KFD_QUEUE_TYPE_DIQ:
 430		kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ);
 431		if (!kq) {
 432			retval = -ENOMEM;
 433			goto err_create_queue;
 434		}
 435		kq->queue->properties.queue_id = *qid;
 436		pqn->kq = kq;
 437		pqn->q = NULL;
 438		retval = kfd_process_drain_interrupts(pdd);
 439		if (retval)
 440			break;
 441
 442		retval = dev->dqm->ops.create_kernel_queue(dev->dqm,
 443							kq, &pdd->qpd);
 444		break;
 445	default:
 446		WARN(1, "Invalid queue type %d", type);
 447		retval = -EINVAL;
 448	}
 449
 450	if (retval != 0) {
 451		if ((type == KFD_QUEUE_TYPE_SDMA ||
 452		    type == KFD_QUEUE_TYPE_SDMA_XGMI ||
 453		    type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) &&
 454		    retval == -ENOMEM)
 455			pr_warn("process pid %d DQM create queue type %d failed. ret %d\n",
 456				pqm->process->lead_thread->pid, type, retval);
 457		else
 458			pr_err("process pid %d DQM create queue type %d failed. ret %d\n",
 459				pqm->process->lead_thread->pid, type, retval);
 460		goto err_create_queue;
 461	}
 462
 463	if (q && p_doorbell_offset_in_process) {
 464		/* Return the doorbell offset within the doorbell page
 465		 * to the caller so it can be passed up to user mode
 466		 * (in bytes).
 467		 * relative doorbell index = Absolute doorbell index -
 468		 * absolute index of first doorbell in the page.
 469		 */
 470		uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev,
 471								       pdd->qpd.proc_doorbells,
 472								       0,
 473								       pdd->dev->kfd->device_info.doorbell_size);
 474
 475		*p_doorbell_offset_in_process = (q->properties.doorbell_off
 476						- first_db_index) * sizeof(uint32_t);
 477	}
 478
 479	pr_debug("PQM After DQM create queue\n");
 480
 481	list_add(&pqn->process_queue_list, &pqm->queues);
 482
 483	if (q) {
 484		pr_debug("PQM done creating queue\n");
 485		kfd_procfs_add_queue(q);
 486		print_queue_properties(&q->properties);
 487	}
 488
 489	return retval;
 490
 491err_create_queue:
 492	uninit_queue(q);
 493	if (kq)
 494		kernel_queue_uninit(kq);
 495	kfree(pqn);
 496err_allocate_pqn:
 497	/* check if queues list is empty unregister process from device */
 498	clear_bit(*qid, pqm->queue_slot_bitmap);
 499	if (list_empty(&pdd->qpd.queues_list) &&
 500	    list_empty(&pdd->qpd.priv_queue_list))
 501		dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd);
 502	return retval;
 503}
 504
 505int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 506{
 507	struct process_queue_node *pqn;
 508	struct kfd_process_device *pdd;
 509	struct device_queue_manager *dqm;
 510	struct kfd_node *dev;
 511	int retval;
 512
 513	dqm = NULL;
 514
 515	retval = 0;
 516
 517	pqn = get_queue_by_qid(pqm, qid);
 518	if (!pqn) {
 519		pr_err("Queue id does not match any known queue\n");
 520		return -EINVAL;
 521	}
 522
 523	dev = NULL;
 524	if (pqn->kq)
 525		dev = pqn->kq->dev;
 526	if (pqn->q)
 527		dev = pqn->q->device;
 528	if (WARN_ON(!dev))
 529		return -ENODEV;
 530
 531	pdd = kfd_get_process_device_data(dev, pqm->process);
 532	if (!pdd) {
 533		pr_err("Process device data doesn't exist\n");
 534		return -1;
 535	}
 536
 537	if (pqn->kq) {
 538		/* destroy kernel queue (DIQ) */
 539		dqm = pqn->kq->dev->dqm;
 540		dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd);
 541		kernel_queue_uninit(pqn->kq);
 542	}
 543
 544	if (pqn->q) {
 545		retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties);
 546		if (retval)
 547			goto err_destroy_queue;
 548
 549		dqm = pqn->q->device->dqm;
 550		retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
 551		if (retval) {
 552			pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n",
 553				pdd->pasid,
 554				pqn->q->properties.queue_id, retval);
 555			if (retval != -ETIME && retval != -EIO)
 556				goto err_destroy_queue;
 557		}
 558		kfd_procfs_del_queue(pqn->q);
 559		kfd_queue_release_buffers(pdd, &pqn->q->properties);
 560		pqm_clean_queue_resource(pqm, pqn);
 561		uninit_queue(pqn->q);
 562	}
 563
 564	list_del(&pqn->process_queue_list);
 565	kfree(pqn);
 566	clear_bit(qid, pqm->queue_slot_bitmap);
 567
 568	if (list_empty(&pdd->qpd.queues_list) &&
 569	    list_empty(&pdd->qpd.priv_queue_list))
 570		dqm->ops.unregister_process(dqm, &pdd->qpd);
 571
 572err_destroy_queue:
 573	return retval;
 574}
 575
 576int pqm_update_queue_properties(struct process_queue_manager *pqm,
 577				unsigned int qid, struct queue_properties *p)
 578{
 579	int retval;
 580	struct process_queue_node *pqn;
 581
 582	pqn = get_queue_by_qid(pqm, qid);
 583	if (!pqn || !pqn->q) {
 584		pr_debug("No queue %d exists for update operation\n", qid);
 585		return -EFAULT;
 586	}
 587
 588	/*
 589	 * Update with NULL ring address is used to disable the queue
 590	 */
 591	if (p->queue_address && p->queue_size) {
 592		struct kfd_process_device *pdd;
 593		struct amdgpu_vm *vm;
 594		struct queue *q = pqn->q;
 595		int err;
 596
 597		pdd = kfd_get_process_device_data(q->device, q->process);
 598		if (!pdd)
 599			return -ENODEV;
 600		vm = drm_priv_to_vm(pdd->drm_priv);
 601		err = amdgpu_bo_reserve(vm->root.bo, false);
 602		if (err)
 603			return err;
 604
 605		if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo,
 606					 p->queue_size)) {
 607			pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n",
 608				 p->queue_address, p->queue_size);
 609			amdgpu_bo_unreserve(vm->root.bo);
 610			return -EFAULT;
 611		}
 612
 613		kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo);
 614		kfd_queue_buffer_put(&pqn->q->properties.ring_bo);
 615		amdgpu_bo_unreserve(vm->root.bo);
 616
 617		pqn->q->properties.ring_bo = p->ring_bo;
 618	}
 619
 620	pqn->q->properties.queue_address = p->queue_address;
 621	pqn->q->properties.queue_size = p->queue_size;
 622	pqn->q->properties.queue_percent = p->queue_percent;
 623	pqn->q->properties.priority = p->priority;
 624	pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc;
 625
 626	retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
 627							pqn->q, NULL);
 628	if (retval != 0)
 629		return retval;
 630
 631	return 0;
 632}
 633
 634int pqm_update_mqd(struct process_queue_manager *pqm,
 635				unsigned int qid, struct mqd_update_info *minfo)
 636{
 637	int retval;
 638	struct process_queue_node *pqn;
 639
 640	pqn = get_queue_by_qid(pqm, qid);
 641	if (!pqn) {
 642		pr_debug("No queue %d exists for update operation\n", qid);
 643		return -EFAULT;
 644	}
 645
 646	/* CUs are masked for debugger requirements so deny user mask  */
 647	if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr)
 648		return -EBUSY;
 649
 650	/* ASICs that have WGPs must enforce pairwise enabled mask checks. */
 651	if (minfo && minfo->cu_mask.ptr &&
 652			KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
 653		int i;
 654
 655		for (i = 0; i < minfo->cu_mask.count; i += 2) {
 656			uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
 657
 658			if (cu_pair && cu_pair != 0x3) {
 659				pr_debug("CUs must be adjacent pairwise enabled.\n");
 660				return -EINVAL;
 661			}
 662		}
 663	}
 664
 665	retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
 666							pqn->q, minfo);
 667	if (retval != 0)
 668		return retval;
 669
 670	if (minfo && minfo->cu_mask.ptr)
 671		pqn->q->properties.is_user_cu_masked = true;
 672
 673	return 0;
 674}
 675
 676struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
 677					unsigned int qid)
 678{
 679	struct process_queue_node *pqn;
 680
 681	pqn = get_queue_by_qid(pqm, qid);
 682	return pqn ? pqn->q : NULL;
 683}
 684
 685int pqm_get_wave_state(struct process_queue_manager *pqm,
 686		       unsigned int qid,
 687		       void __user *ctl_stack,
 688		       u32 *ctl_stack_used_size,
 689		       u32 *save_area_used_size)
 690{
 691	struct process_queue_node *pqn;
 692
 693	pqn = get_queue_by_qid(pqm, qid);
 694	if (!pqn) {
 695		pr_debug("amdkfd: No queue %d exists for operation\n",
 696			 qid);
 697		return -EFAULT;
 698	}
 699
 700	return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm,
 701						       pqn->q,
 702						       ctl_stack,
 703						       ctl_stack_used_size,
 704						       save_area_used_size);
 705}
 706
 707int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
 708			   uint64_t exception_clear_mask,
 709			   void __user *buf,
 710			   int *num_qss_entries,
 711			   uint32_t *entry_size)
 712{
 713	struct process_queue_node *pqn;
 714	struct kfd_queue_snapshot_entry src;
 715	uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries;
 716	int r = 0;
 717
 718	*num_qss_entries = 0;
 719	if (!(*entry_size))
 720		return -EINVAL;
 721
 722	*entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry));
 723	mutex_lock(&pqm->process->event_mutex);
 724
 725	memset(&src, 0, sizeof(src));
 726
 727	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
 728		if (!pqn->q)
 729			continue;
 730
 731		if (*num_qss_entries < tmp_qss_entries) {
 732			set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src);
 733
 734			if (copy_to_user(buf, &src, *entry_size)) {
 735				r = -EFAULT;
 736				break;
 737			}
 738			buf += tmp_entry_size;
 739		}
 740		*num_qss_entries += 1;
 741	}
 742
 743	mutex_unlock(&pqm->process->event_mutex);
 744	return r;
 745}
 746
 747static int get_queue_data_sizes(struct kfd_process_device *pdd,
 748				struct queue *q,
 749				uint32_t *mqd_size,
 750				uint32_t *ctl_stack_size)
 751{
 752	int ret;
 753
 754	ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm,
 755					    q->properties.queue_id,
 756					    mqd_size,
 757					    ctl_stack_size);
 758	if (ret)
 759		pr_err("Failed to get queue dump info (%d)\n", ret);
 760
 761	return ret;
 762}
 763
 764int kfd_process_get_queue_info(struct kfd_process *p,
 765			       uint32_t *num_queues,
 766			       uint64_t *priv_data_sizes)
 767{
 768	uint32_t extra_data_sizes = 0;
 769	struct queue *q;
 770	int i;
 771	int ret;
 772
 773	*num_queues = 0;
 774
 775	/* Run over all PDDs of the process */
 776	for (i = 0; i < p->n_pdds; i++) {
 777		struct kfd_process_device *pdd = p->pdds[i];
 778
 779		list_for_each_entry(q, &pdd->qpd.queues_list, list) {
 780			if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
 781				q->properties.type == KFD_QUEUE_TYPE_SDMA ||
 782				q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
 783				uint32_t mqd_size, ctl_stack_size;
 784
 785				*num_queues = *num_queues + 1;
 786
 787				ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
 788				if (ret)
 789					return ret;
 790
 791				extra_data_sizes += mqd_size + ctl_stack_size;
 792			} else {
 793				pr_err("Unsupported queue type (%d)\n", q->properties.type);
 794				return -EOPNOTSUPP;
 795			}
 796		}
 797	}
 798	*priv_data_sizes = extra_data_sizes +
 799				(*num_queues * sizeof(struct kfd_criu_queue_priv_data));
 800
 801	return 0;
 802}
 803
 804static int pqm_checkpoint_mqd(struct process_queue_manager *pqm,
 805			      unsigned int qid,
 806			      void *mqd,
 807			      void *ctl_stack)
 808{
 809	struct process_queue_node *pqn;
 810
 811	pqn = get_queue_by_qid(pqm, qid);
 812	if (!pqn) {
 813		pr_debug("amdkfd: No queue %d exists for operation\n", qid);
 814		return -EFAULT;
 815	}
 816
 817	if (!pqn->q->device->dqm->ops.checkpoint_mqd) {
 818		pr_err("amdkfd: queue dumping not supported on this device\n");
 819		return -EOPNOTSUPP;
 820	}
 821
 822	return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm,
 823						       pqn->q, mqd, ctl_stack);
 824}
 825
 826static int criu_checkpoint_queue(struct kfd_process_device *pdd,
 827			   struct queue *q,
 828			   struct kfd_criu_queue_priv_data *q_data)
 829{
 830	uint8_t *mqd, *ctl_stack;
 831	int ret;
 832
 833	mqd = (void *)(q_data + 1);
 834	ctl_stack = mqd + q_data->mqd_size;
 835
 836	q_data->gpu_id = pdd->user_gpu_id;
 837	q_data->type = q->properties.type;
 838	q_data->format = q->properties.format;
 839	q_data->q_id =  q->properties.queue_id;
 840	q_data->q_address = q->properties.queue_address;
 841	q_data->q_size = q->properties.queue_size;
 842	q_data->priority = q->properties.priority;
 843	q_data->q_percent = q->properties.queue_percent;
 844	q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr;
 845	q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr;
 846	q_data->doorbell_id = q->doorbell_id;
 847
 848	q_data->sdma_id = q->sdma_id;
 849
 850	q_data->eop_ring_buffer_address =
 851		q->properties.eop_ring_buffer_address;
 852
 853	q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size;
 854
 855	q_data->ctx_save_restore_area_address =
 856		q->properties.ctx_save_restore_area_address;
 857
 858	q_data->ctx_save_restore_area_size =
 859		q->properties.ctx_save_restore_area_size;
 860
 861	q_data->gws = !!q->gws;
 862
 863	ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack);
 864	if (ret) {
 865		pr_err("Failed checkpoint queue_mqd (%d)\n", ret);
 866		return ret;
 867	}
 868
 869	pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id);
 870	return ret;
 871}
 872
 873static int criu_checkpoint_queues_device(struct kfd_process_device *pdd,
 874				   uint8_t __user *user_priv,
 875				   unsigned int *q_index,
 876				   uint64_t *queues_priv_data_offset)
 877{
 878	unsigned int q_private_data_size = 0;
 879	uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */
 880	struct queue *q;
 881	int ret = 0;
 882
 883	list_for_each_entry(q, &pdd->qpd.queues_list, list) {
 884		struct kfd_criu_queue_priv_data *q_data;
 885		uint64_t q_data_size;
 886		uint32_t mqd_size;
 887		uint32_t ctl_stack_size;
 888
 889		if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE &&
 890			q->properties.type != KFD_QUEUE_TYPE_SDMA &&
 891			q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) {
 892
 893			pr_err("Unsupported queue type (%d)\n", q->properties.type);
 894			ret = -EOPNOTSUPP;
 895			break;
 896		}
 897
 898		ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
 899		if (ret)
 900			break;
 901
 902		q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size;
 903
 904		/* Increase local buffer space if needed */
 905		if (q_private_data_size < q_data_size) {
 906			kfree(q_private_data);
 907
 908			q_private_data = kzalloc(q_data_size, GFP_KERNEL);
 909			if (!q_private_data) {
 910				ret = -ENOMEM;
 911				break;
 912			}
 913			q_private_data_size = q_data_size;
 914		}
 915
 916		q_data = (struct kfd_criu_queue_priv_data *)q_private_data;
 917
 918		/*
 919		 * data stored in this order:
 920		 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
 921		 */
 922		q_data->mqd_size = mqd_size;
 923		q_data->ctl_stack_size = ctl_stack_size;
 924
 925		ret = criu_checkpoint_queue(pdd, q, q_data);
 926		if (ret)
 927			break;
 928
 929		q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE;
 930
 931		ret = copy_to_user(user_priv + *queues_priv_data_offset,
 932				q_data, q_data_size);
 933		if (ret) {
 934			ret = -EFAULT;
 935			break;
 936		}
 937		*queues_priv_data_offset += q_data_size;
 938		*q_index = *q_index + 1;
 939	}
 940
 941	kfree(q_private_data);
 942
 943	return ret;
 944}
 945
 946int kfd_criu_checkpoint_queues(struct kfd_process *p,
 947			 uint8_t __user *user_priv_data,
 948			 uint64_t *priv_data_offset)
 949{
 950	int ret = 0, pdd_index, q_index = 0;
 951
 952	for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
 953		struct kfd_process_device *pdd = p->pdds[pdd_index];
 954
 955		/*
 956		 * criu_checkpoint_queues_device will copy data to user and update q_index and
 957		 * queues_priv_data_offset
 958		 */
 959		ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index,
 960					      priv_data_offset);
 961
 962		if (ret)
 963			break;
 964	}
 965
 966	return ret;
 967}
 968
 969static void set_queue_properties_from_criu(struct queue_properties *qp,
 970					  struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc)
 971{
 972	qp->is_interop = false;
 973	qp->queue_percent = q_data->q_percent;
 974	qp->priority = q_data->priority;
 975	qp->queue_address = q_data->q_address;
 976	qp->queue_size = q_data->q_size;
 977	qp->read_ptr = (uint32_t *) q_data->read_ptr_addr;
 978	qp->write_ptr = (uint32_t *) q_data->write_ptr_addr;
 979	qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address;
 980	qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size;
 981	qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address;
 982	qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size;
 983	if (q_data->type == KFD_QUEUE_TYPE_COMPUTE)
 984		qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc;
 985	else
 986		qp->ctl_stack_size = q_data->ctl_stack_size;
 987
 988	qp->type = q_data->type;
 989	qp->format = q_data->format;
 990}
 991
 992int kfd_criu_restore_queue(struct kfd_process *p,
 993			   uint8_t __user *user_priv_ptr,
 994			   uint64_t *priv_data_offset,
 995			   uint64_t max_priv_data_size)
 996{
 997	uint8_t *mqd, *ctl_stack, *q_extra_data = NULL;
 998	struct kfd_criu_queue_priv_data *q_data;
 999	struct kfd_process_device *pdd;
1000	uint64_t q_extra_data_size;
1001	struct queue_properties qp;
1002	unsigned int queue_id;
1003	int ret = 0;
1004
1005	if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size)
1006		return -EINVAL;
1007
1008	q_data = kmalloc(sizeof(*q_data), GFP_KERNEL);
1009	if (!q_data)
1010		return -ENOMEM;
1011
1012	ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data));
1013	if (ret) {
1014		ret = -EFAULT;
1015		goto exit;
1016	}
1017
1018	*priv_data_offset += sizeof(*q_data);
1019	q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size;
1020
1021	if (*priv_data_offset + q_extra_data_size > max_priv_data_size) {
1022		ret = -EINVAL;
1023		goto exit;
1024	}
1025
1026	q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL);
1027	if (!q_extra_data) {
1028		ret = -ENOMEM;
1029		goto exit;
1030	}
1031
1032	ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size);
1033	if (ret) {
1034		ret = -EFAULT;
1035		goto exit;
1036	}
1037
1038	*priv_data_offset += q_extra_data_size;
1039
1040	pdd = kfd_process_device_data_by_id(p, q_data->gpu_id);
1041	if (!pdd) {
1042		pr_err("Failed to get pdd\n");
1043		ret = -EINVAL;
1044		goto exit;
1045	}
1046
1047	/*
1048	 * data stored in this order:
1049	 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
1050	 */
1051	mqd = q_extra_data;
1052	ctl_stack = mqd + q_data->mqd_size;
1053
1054	memset(&qp, 0, sizeof(qp));
1055	set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask));
1056
1057	print_queue_properties(&qp);
1058
1059	ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL);
1060	if (ret) {
1061		pr_err("Failed to create new queue err:%d\n", ret);
1062		goto exit;
1063	}
1064
1065	if (q_data->gws)
1066		ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws);
1067
1068exit:
1069	if (ret)
1070		pr_err("Failed to restore queue (%d)\n", ret);
1071	else
1072		pr_debug("Queue id %d was restored successfully\n", queue_id);
1073
1074	kfree(q_data);
1075	kfree(q_extra_data);
1076
1077	return ret;
1078}
1079
1080int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1081				  unsigned int qid,
1082				  uint32_t *mqd_size,
1083				  uint32_t *ctl_stack_size)
1084{
1085	struct process_queue_node *pqn;
1086
1087	pqn = get_queue_by_qid(pqm, qid);
1088	if (!pqn) {
1089		pr_debug("amdkfd: No queue %d exists for operation\n", qid);
1090		return -EFAULT;
1091	}
1092
1093	if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) {
1094		pr_err("amdkfd: queue dumping not supported on this device\n");
1095		return -EOPNOTSUPP;
1096	}
1097
1098	pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm,
1099						       pqn->q, mqd_size,
1100						       ctl_stack_size);
1101	return 0;
1102}
1103
1104#if defined(CONFIG_DEBUG_FS)
1105
1106int pqm_debugfs_mqds(struct seq_file *m, void *data)
1107{
1108	struct process_queue_manager *pqm = data;
1109	struct process_queue_node *pqn;
1110	struct queue *q;
1111	enum KFD_MQD_TYPE mqd_type;
1112	struct mqd_manager *mqd_mgr;
1113	int r = 0, xcc, num_xccs = 1;
1114	void *mqd;
1115	uint64_t size = 0;
1116
1117	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
1118		if (pqn->q) {
1119			q = pqn->q;
1120			switch (q->properties.type) {
1121			case KFD_QUEUE_TYPE_SDMA:
1122			case KFD_QUEUE_TYPE_SDMA_XGMI:
1123				seq_printf(m, "  SDMA queue on device %x\n",
1124					   q->device->id);
1125				mqd_type = KFD_MQD_TYPE_SDMA;
1126				break;
1127			case KFD_QUEUE_TYPE_COMPUTE:
1128				seq_printf(m, "  Compute queue on device %x\n",
1129					   q->device->id);
1130				mqd_type = KFD_MQD_TYPE_CP;
1131				num_xccs = NUM_XCC(q->device->xcc_mask);
1132				break;
1133			default:
1134				seq_printf(m,
1135				"  Bad user queue type %d on device %x\n",
1136					   q->properties.type, q->device->id);
1137				continue;
1138			}
1139			mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type];
1140			size = mqd_mgr->mqd_stride(mqd_mgr,
1141							&q->properties);
1142		} else if (pqn->kq) {
1143			q = pqn->kq->queue;
1144			mqd_mgr = pqn->kq->mqd_mgr;
1145			switch (q->properties.type) {
1146			case KFD_QUEUE_TYPE_DIQ:
1147				seq_printf(m, "  DIQ on device %x\n",
1148					   pqn->kq->dev->id);
1149				break;
1150			default:
1151				seq_printf(m,
1152				"  Bad kernel queue type %d on device %x\n",
1153					   q->properties.type,
1154					   pqn->kq->dev->id);
1155				continue;
1156			}
1157		} else {
1158			seq_printf(m,
1159		"  Weird: Queue node with neither kernel nor user queue\n");
1160			continue;
1161		}
1162
1163		for (xcc = 0; xcc < num_xccs; xcc++) {
1164			mqd = q->mqd + size * xcc;
1165			r = mqd_mgr->debugfs_show_mqd(m, mqd);
1166			if (r != 0)
1167				break;
1168		}
1169	}
1170
1171	return r;
1172}
1173
1174#endif