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kfd_pm4_headers_ai.h
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linux-6.19.14/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
1/* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2/* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25#ifndef F32_MES_PM4_PACKETS_H 26#define F32_MES_PM4_PACKETS_H 27 28#ifndef PM4_MES_HEADER_DEFINED 29#define PM4_MES_HEADER_DEFINED 30union PM4_MES_TYPE_3_HEADER { 31 struct { 32 uint32_t reserved1 : 8; /* < reserved */ 33 uint32_t opcode : 8; /* < IT opcode */ 34 uint32_t count : 14;/* < number of DWORDs - 1 in the 35 * information body. 36 */ 37 uint32_t type : 2; /* < packet identifier. 38 * It should be 3 for type 3 packets 39 */ 40 }; 41 uint32_t u32All; 42}; 43#endif /* PM4_MES_HEADER_DEFINED */ 44 45/*--------------------MES_SET_RESOURCES--------------------*/ 46 47#ifndef PM4_MES_SET_RESOURCES_DEFINED 48#define PM4_MES_SET_RESOURCES_DEFINED 49enum mes_set_resources_queue_type_enum { 50 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 51 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 52 queue_type__mes_set_resources__hsa_debug_interface_queue = 4 53}; 54 55 56struct pm4_mes_set_resources { 57 union { 58 union PM4_MES_TYPE_3_HEADER header; /* header */ 59 uint32_t ordinal1; 60 }; 61 62 union { 63 struct { 64 uint32_t vmid_mask:16; 65 uint32_t unmap_latency:8; 66 uint32_t reserved1:4; 67 uint32_t enb_xnack_retry_disable_check:1; 68 enum mes_set_resources_queue_type_enum queue_type:3; 69 } bitfields2; 70 uint32_t ordinal2; 71 }; 72 73 uint32_t queue_mask_lo; 74 uint32_t queue_mask_hi; 75 uint32_t gws_mask_lo; 76 uint32_t gws_mask_hi; 77 78 union { 79 struct { 80 uint32_t oac_mask:16; 81 uint32_t reserved2:16; 82 } bitfields7; 83 uint32_t ordinal7; 84 }; 85 86 union { 87 struct { 88 uint32_t gds_heap_base:10; 89 uint32_t reserved3:1; 90 uint32_t gds_heap_size:10; 91 uint32_t reserved4:11; 92 } bitfields8; 93 uint32_t ordinal8; 94 }; 95 96}; 97#endif 98 99/*--------------------MES_RUN_LIST--------------------*/ 100 101#ifndef PM4_MES_RUN_LIST_DEFINED 102#define PM4_MES_RUN_LIST_DEFINED 103 104struct pm4_mes_runlist { 105 union { 106 union PM4_MES_TYPE_3_HEADER header; /* header */ 107 uint32_t ordinal1; 108 }; 109 110 union { 111 struct { 112 uint32_t reserved1:2; 113 uint32_t ib_base_lo:30; 114 } bitfields2; 115 uint32_t ordinal2; 116 }; 117 118 uint32_t ib_base_hi; 119 120 union { 121 struct { 122 uint32_t ib_size:20; 123 uint32_t chain:1; 124 uint32_t offload_polling:1; 125 uint32_t chained_runlist_idle_disable:1; 126 uint32_t valid:1; 127 uint32_t process_cnt:4; 128 uint32_t reserved3:4; 129 } bitfields4; 130 uint32_t ordinal4; 131 }; 132 133}; 134#endif 135 136/*--------------------MES_MAP_PROCESS--------------------*/ 137 138#ifndef PM4_MES_MAP_PROCESS_DEFINED 139#define PM4_MES_MAP_PROCESS_DEFINED 140 141struct pm4_mes_map_process { 142 union { 143 union PM4_MES_TYPE_3_HEADER header; /* header */ 144 uint32_t ordinal1; 145 }; 146 147 union { 148 struct { 149 uint32_t pasid:16; /* 0 - 15 */ 150 uint32_t reserved1:1; /* 16 */ 151 uint32_t exec_cleaner_shader:1; /* 17 */ 152 uint32_t debug_vmid:4; 153 uint32_t new_debug:1; 154 uint32_t reserved2:1; 155 uint32_t diq_enable:1; 156 uint32_t process_quantum:7; 157 } bitfields2; 158 uint32_t ordinal2; 159 }; 160 161 uint32_t vm_context_page_table_base_addr_lo32; 162 163 uint32_t vm_context_page_table_base_addr_hi32; 164 165 uint32_t sh_mem_bases; 166 167 uint32_t sh_mem_config; 168 169 uint32_t sq_shader_tba_lo; 170 171 uint32_t sq_shader_tba_hi; 172 173 uint32_t sq_shader_tma_lo; 174 175 uint32_t sq_shader_tma_hi; 176 177 uint32_t reserved6; 178 179 uint32_t gds_addr_lo; 180 181 uint32_t gds_addr_hi; 182 183 union { 184 struct { 185 uint32_t num_gws:7; 186 uint32_t sdma_enable:1; 187 uint32_t num_oac:4; 188 uint32_t gds_size_hi:4; 189 uint32_t gds_size:6; 190 uint32_t num_queues:10; 191 } bitfields14; 192 uint32_t ordinal14; 193 }; 194 195 uint32_t completion_signal_lo; 196 197 uint32_t completion_signal_hi; 198 199}; 200 201#endif 202 203/*--------------------MES_MAP_PROCESS_VM--------------------*/ 204 205#ifndef PM4_MES_MAP_PROCESS_VM_DEFINED 206#define PM4_MES_MAP_PROCESS_VM_DEFINED 207 208struct PM4_MES_MAP_PROCESS_VM { 209 union { 210 union PM4_MES_TYPE_3_HEADER header; /* header */ 211 uint32_t ordinal1; 212 }; 213 214 uint32_t reserved1; 215 216 uint32_t vm_context_cntl; 217 218 uint32_t reserved2; 219 220 uint32_t vm_context_page_table_end_addr_lo32; 221 222 uint32_t vm_context_page_table_end_addr_hi32; 223 224 uint32_t vm_context_page_table_start_addr_lo32; 225 226 uint32_t vm_context_page_table_start_addr_hi32; 227 228 uint32_t reserved3; 229 230 uint32_t reserved4; 231 232 uint32_t reserved5; 233 234 uint32_t reserved6; 235 236 uint32_t reserved7; 237 238 uint32_t reserved8; 239 240 uint32_t completion_signal_lo32; 241 242 uint32_t completion_signal_hi32; 243 244}; 245#endif 246 247/*--------------------MES_MAP_QUEUES--------------------*/ 248 249#ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 250#define PM4_MES_MAP_QUEUES_VI_DEFINED 251enum mes_map_queues_queue_sel_enum { 252 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 253queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 254}; 255 256enum mes_map_queues_queue_type_enum { 257 queue_type__mes_map_queues__normal_compute_vi = 0, 258 queue_type__mes_map_queues__debug_interface_queue_vi = 1, 259 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 260queue_type__mes_map_queues__low_latency_static_queue_vi = 3 261}; 262 263enum mes_map_queues_engine_sel_enum { 264 engine_sel__mes_map_queues__compute_vi = 0, 265 engine_sel__mes_map_queues__sdma0_vi = 2, 266 engine_sel__mes_map_queues__sdma1_vi = 3 267}; 268 269enum mes_map_queues_extended_engine_sel_enum { 270 extended_engine_sel__mes_map_queues__legacy_engine_sel = 0, 271 extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1, 272 extended_engine_sel__mes_map_queues__sdma8_to_15_sel = 2 273}; 274 275struct pm4_mes_map_queues { 276 union { 277 union PM4_MES_TYPE_3_HEADER header; /* header */ 278 uint32_t ordinal1; 279 }; 280 281 union { 282 struct { 283 uint32_t reserved1:2; 284 enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2; 285 enum mes_map_queues_queue_sel_enum queue_sel:2; 286 uint32_t reserved5:6; 287 uint32_t gws_control_queue:1; 288 uint32_t reserved2:8; 289 enum mes_map_queues_queue_type_enum queue_type:3; 290 uint32_t reserved3:2; 291 enum mes_map_queues_engine_sel_enum engine_sel:3; 292 uint32_t num_queues:3; 293 } bitfields2; 294 uint32_t ordinal2; 295 }; 296 297 union { 298 struct { 299 uint32_t reserved3:1; 300 uint32_t check_disable:1; 301 uint32_t doorbell_offset:26; 302 uint32_t reserved4:4; 303 } bitfields3; 304 uint32_t ordinal3; 305 }; 306 307 uint32_t mqd_addr_lo; 308 uint32_t mqd_addr_hi; 309 uint32_t wptr_addr_lo; 310 uint32_t wptr_addr_hi; 311}; 312#endif 313 314/*--------------------MES_QUERY_STATUS--------------------*/ 315 316#ifndef PM4_MES_QUERY_STATUS_DEFINED 317#define PM4_MES_QUERY_STATUS_DEFINED 318enum mes_query_status_interrupt_sel_enum { 319 interrupt_sel__mes_query_status__completion_status = 0, 320 interrupt_sel__mes_query_status__process_status = 1, 321 interrupt_sel__mes_query_status__queue_status = 2 322}; 323 324enum mes_query_status_command_enum { 325 command__mes_query_status__interrupt_only = 0, 326 command__mes_query_status__fence_only_immediate = 1, 327 command__mes_query_status__fence_only_after_write_ack = 2, 328 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 329}; 330 331enum mes_query_status_engine_sel_enum { 332 engine_sel__mes_query_status__compute = 0, 333 engine_sel__mes_query_status__sdma0_queue = 2, 334 engine_sel__mes_query_status__sdma1_queue = 3 335}; 336 337struct pm4_mes_query_status { 338 union { 339 union PM4_MES_TYPE_3_HEADER header; /* header */ 340 uint32_t ordinal1; 341 }; 342 343 union { 344 struct { 345 uint32_t context_id:28; 346 enum mes_query_status_interrupt_sel_enum interrupt_sel:2; 347 enum mes_query_status_command_enum command:2; 348 } bitfields2; 349 uint32_t ordinal2; 350 }; 351 352 union { 353 struct { 354 uint32_t pasid:16; 355 uint32_t reserved1:16; 356 } bitfields3a; 357 struct { 358 uint32_t reserved2:2; 359 uint32_t doorbell_offset:26; 360 enum mes_query_status_engine_sel_enum engine_sel:3; 361 uint32_t reserved3:1; 362 } bitfields3b; 363 uint32_t ordinal3; 364 }; 365 366 uint32_t addr_lo; 367 uint32_t addr_hi; 368 uint32_t data_lo; 369 uint32_t data_hi; 370}; 371#endif 372 373/*--------------------MES_UNMAP_QUEUES--------------------*/ 374 375#ifndef PM4_MES_UNMAP_QUEUES_DEFINED 376#define PM4_MES_UNMAP_QUEUES_DEFINED 377enum mes_unmap_queues_action_enum { 378 action__mes_unmap_queues__preempt_queues = 0, 379 action__mes_unmap_queues__reset_queues = 1, 380 action__mes_unmap_queues__disable_process_queues = 2, 381 action__mes_unmap_queues__reserved = 3 382}; 383 384enum mes_unmap_queues_queue_sel_enum { 385 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 386 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 387 queue_sel__mes_unmap_queues__unmap_all_queues = 2, 388 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 389}; 390 391enum mes_unmap_queues_engine_sel_enum { 392 engine_sel__mes_unmap_queues__compute = 0, 393 engine_sel__mes_unmap_queues__sdma0 = 2, 394 engine_sel__mes_unmap_queues__sdmal = 3 395}; 396 397enum mes_unmap_queues_extended_engine_sel_enum { 398 extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0, 399 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1 400}; 401 402struct pm4_mes_unmap_queues { 403 union { 404 union PM4_MES_TYPE_3_HEADER header; /* header */ 405 uint32_t ordinal1; 406 }; 407 408 union { 409 struct { 410 enum mes_unmap_queues_action_enum action:2; 411 enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2; 412 enum mes_unmap_queues_queue_sel_enum queue_sel:2; 413 uint32_t reserved2:20; 414 enum mes_unmap_queues_engine_sel_enum engine_sel:3; 415 uint32_t num_queues:3; 416 } bitfields2; 417 uint32_t ordinal2; 418 }; 419 420 union { 421 struct { 422 uint32_t pasid:16; 423 uint32_t reserved3:16; 424 } bitfields3a; 425 struct { 426 uint32_t reserved4:2; 427 uint32_t doorbell_offset0:26; 428 int32_t reserved5:4; 429 } bitfields3b; 430 uint32_t ordinal3; 431 }; 432 433 union { 434 struct { 435 uint32_t reserved6:2; 436 uint32_t doorbell_offset1:26; 437 uint32_t reserved7:4; 438 } bitfields4; 439 uint32_t ordinal4; 440 }; 441 442 union { 443 struct { 444 uint32_t reserved8:2; 445 uint32_t doorbell_offset2:26; 446 uint32_t reserved9:4; 447 } bitfields5; 448 uint32_t ordinal5; 449 }; 450 451 union { 452 struct { 453 uint32_t reserved10:2; 454 uint32_t doorbell_offset3:26; 455 uint32_t reserved11:4; 456 } bitfields6; 457 uint32_t ordinal6; 458 }; 459}; 460#endif 461 462#ifndef PM4_MEC_RELEASE_MEM_DEFINED 463#define PM4_MEC_RELEASE_MEM_DEFINED 464 465enum mec_release_mem_event_index_enum { 466 event_index__mec_release_mem__end_of_pipe = 5, 467 event_index__mec_release_mem__shader_done = 6 468}; 469 470enum mec_release_mem_cache_policy_enum { 471 cache_policy__mec_release_mem__lru = 0, 472 cache_policy__mec_release_mem__stream = 1 473}; 474 475enum mec_release_mem_pq_exe_status_enum { 476 pq_exe_status__mec_release_mem__default = 0, 477 pq_exe_status__mec_release_mem__phase_update = 1 478}; 479 480enum mec_release_mem_dst_sel_enum { 481 dst_sel__mec_release_mem__memory_controller = 0, 482 dst_sel__mec_release_mem__tc_l2 = 1, 483 dst_sel__mec_release_mem__queue_write_pointer_register = 2, 484 dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 485}; 486 487enum mec_release_mem_int_sel_enum { 488 int_sel__mec_release_mem__none = 0, 489 int_sel__mec_release_mem__send_interrupt_only = 1, 490 int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, 491 int_sel__mec_release_mem__send_data_after_write_confirm = 3, 492 int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, 493 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, 494 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 495}; 496 497enum mec_release_mem_data_sel_enum { 498 data_sel__mec_release_mem__none = 0, 499 data_sel__mec_release_mem__send_32_bit_low = 1, 500 data_sel__mec_release_mem__send_64_bit_data = 2, 501 data_sel__mec_release_mem__send_gpu_clock_counter = 3, 502 data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, 503 data_sel__mec_release_mem__store_gds_data_to_memory = 5 504}; 505 506struct pm4_mec_release_mem { 507 union { 508 union PM4_MES_TYPE_3_HEADER header; /*header */ 509 unsigned int ordinal1; 510 }; 511 512 union { 513 struct { 514 unsigned int event_type:6; 515 unsigned int reserved1:2; 516 enum mec_release_mem_event_index_enum event_index:4; 517 unsigned int tcl1_vol_action_ena:1; 518 unsigned int tc_vol_action_ena:1; 519 unsigned int reserved2:1; 520 unsigned int tc_wb_action_ena:1; 521 unsigned int tcl1_action_ena:1; 522 unsigned int tc_action_ena:1; 523 uint32_t reserved3:1; 524 uint32_t tc_nc_action_ena:1; 525 uint32_t tc_wc_action_ena:1; 526 uint32_t tc_md_action_ena:1; 527 uint32_t reserved4:3; 528 enum mec_release_mem_cache_policy_enum cache_policy:2; 529 uint32_t reserved5:2; 530 enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; 531 uint32_t reserved6:2; 532 } bitfields2; 533 unsigned int ordinal2; 534 }; 535 536 union { 537 struct { 538 uint32_t reserved7:16; 539 enum mec_release_mem_dst_sel_enum dst_sel:2; 540 uint32_t reserved8:6; 541 enum mec_release_mem_int_sel_enum int_sel:3; 542 uint32_t reserved9:2; 543 enum mec_release_mem_data_sel_enum data_sel:3; 544 } bitfields3; 545 unsigned int ordinal3; 546 }; 547 548 union { 549 struct { 550 uint32_t reserved10:2; 551 unsigned int address_lo_32b:30; 552 } bitfields4; 553 struct { 554 uint32_t reserved11:3; 555 uint32_t address_lo_64b:29; 556 } bitfields4b; 557 uint32_t reserved12; 558 unsigned int ordinal4; 559 }; 560 561 union { 562 uint32_t address_hi; 563 uint32_t reserved13; 564 uint32_t ordinal5; 565 }; 566 567 union { 568 uint32_t data_lo; 569 uint32_t cmp_data_lo; 570 struct { 571 uint32_t dw_offset:16; 572 uint32_t num_dwords:16; 573 } bitfields6c; 574 uint32_t reserved14; 575 uint32_t ordinal6; 576 }; 577 578 union { 579 uint32_t data_hi; 580 uint32_t cmp_data_hi; 581 uint32_t reserved15; 582 uint32_t reserved16; 583 uint32_t ordinal7; 584 }; 585 586 uint32_t int_ctxid; 587 588}; 589 590#endif 591 592#ifndef PM4_MEC_WRITE_DATA_DEFINED 593#define PM4_MEC_WRITE_DATA_DEFINED 594 595enum WRITE_DATA_dst_sel_enum { 596 dst_sel___write_data__mem_mapped_register = 0, 597 dst_sel___write_data__tc_l2 = 2, 598 dst_sel___write_data__gds = 3, 599 dst_sel___write_data__memory = 5, 600 dst_sel___write_data__memory_mapped_adc_persistent_state = 6, 601}; 602 603enum WRITE_DATA_addr_incr_enum { 604 addr_incr___write_data__increment_address = 0, 605 addr_incr___write_data__do_not_increment_address = 1 606}; 607 608enum WRITE_DATA_wr_confirm_enum { 609 wr_confirm___write_data__do_not_wait_for_write_confirmation = 0, 610 wr_confirm___write_data__wait_for_write_confirmation = 1 611}; 612 613enum WRITE_DATA_cache_policy_enum { 614 cache_policy___write_data__lru = 0, 615 cache_policy___write_data__stream = 1 616}; 617 618 619struct pm4_mec_write_data_mmio { 620 union { 621 union PM4_MES_TYPE_3_HEADER header; /*header */ 622 unsigned int ordinal1; 623 }; 624 625 union { 626 struct { 627 unsigned int reserved1:8; 628 unsigned int dst_sel:4; 629 unsigned int reserved2:4; 630 unsigned int addr_incr:1; 631 unsigned int reserved3:2; 632 unsigned int resume_vf:1; 633 unsigned int wr_confirm:1; 634 unsigned int reserved4:4; 635 unsigned int cache_policy:2; 636 unsigned int reserved5:5; 637 } bitfields2; 638 unsigned int ordinal2; 639 }; 640 641 union { 642 struct { 643 unsigned int dst_mmreg_addr:18; 644 unsigned int reserved6:14; 645 } bitfields3; 646 unsigned int ordinal3; 647 }; 648 649 uint32_t reserved7; 650 651 uint32_t data; 652 653}; 654 655#endif 656 657enum { 658 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 659}; 660#endif 661
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