kfd_device_queue_manager_cik.c

  1// SPDX-License-Identifier: GPL-2.0 OR MIT
  2/*
  3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include "kfd_device_queue_manager.h"
 26#include "cik_regs.h"
 27#include "oss/oss_2_4_sh_mask.h"
 28#include "gca/gfx_7_2_sh_mask.h"
 29
 30/*
 31 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
 32 * stay in user mode.
 33 */
 34#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
 35/* APE1 limit is inclusive and 64K aligned. */
 36#define APE1_LIMIT_ALIGNMENT 0xFFFF
 37
 38static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 39				   struct qcm_process_device *qpd,
 40				   enum cache_policy default_policy,
 41				   enum cache_policy alternate_policy,
 42				   void __user *alternate_aperture_base,
 43				   uint64_t alternate_aperture_size,
 44				   u32 misc_process_properties);
 45static int update_qpd_cik(struct device_queue_manager *dqm,
 46			  struct qcm_process_device *qpd);
 47static void init_sdma_vm(struct device_queue_manager *dqm,
 48			 struct queue *q,
 49			 struct qcm_process_device *qpd);
 50
 51void device_queue_manager_init_cik(
 52	struct device_queue_manager_asic_ops *asic_ops)
 53{
 54	asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik;
 55	asic_ops->update_qpd = update_qpd_cik;
 56	asic_ops->init_sdma_vm = init_sdma_vm;
 57	asic_ops->mqd_manager_init = mqd_manager_init_cik;
 58}
 59
 60static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
 61{
 62	/* In 64-bit mode, we can only control the top 3 bits of the LDS,
 63	 * scratch and GPUVM apertures.
 64	 * The hardware fills in the remaining 59 bits according to the
 65	 * following pattern:
 66	 * LDS:		X0000000'00000000 - X0000001'00000000 (4GB)
 67	 * Scratch:	X0000001'00000000 - X0000002'00000000 (4GB)
 68	 * GPUVM:	Y0010000'00000000 - Y0020000'00000000 (1TB)
 69	 *
 70	 * (where X/Y is the configurable nybble with the low-bit 0)
 71	 *
 72	 * LDS and scratch will have the same top nybble programmed in the
 73	 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
 74	 * GPUVM can have a different top nybble programmed in the
 75	 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
 76	 * We don't bother to support different top nybbles
 77	 * for LDS/Scratch and GPUVM.
 78	 */
 79
 80	WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
 81		top_address_nybble == 0);
 82
 83	return PRIVATE_BASE(top_address_nybble << 12) |
 84			SHARED_BASE(top_address_nybble << 12);
 85}
 86
 87static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 88				   struct qcm_process_device *qpd,
 89				   enum cache_policy default_policy,
 90				   enum cache_policy alternate_policy,
 91				   void __user *alternate_aperture_base,
 92				   uint64_t alternate_aperture_size,
 93				   u32 misc_process_properties)
 94{
 95	uint32_t default_mtype;
 96	uint32_t ape1_mtype;
 97	unsigned int temp;
 98	bool retval = true;
 99
100	if (alternate_aperture_size == 0) {
101		/* base > limit disables APE1 */
102		qpd->sh_mem_ape1_base = 1;
103		qpd->sh_mem_ape1_limit = 0;
104	} else {
105		/*
106		 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
107		 *			SH_MEM_APE1_BASE[31:0], 0x0000 }
108		 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
109		 *			SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
110		 * Verify that the base and size parameters can be
111		 * represented in this format and convert them.
112		 * Additionally restrict APE1 to user-mode addresses.
113		 */
114
115		uint64_t base = (uintptr_t)alternate_aperture_base;
116		uint64_t limit = base + alternate_aperture_size - 1;
117
118		if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
119		   (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
120			retval = false;
121			goto out;
122		}
123
124		qpd->sh_mem_ape1_base = base >> 16;
125		qpd->sh_mem_ape1_limit = limit >> 16;
126	}
127
128	default_mtype = (default_policy == cache_policy_coherent) ?
129			MTYPE_NONCACHED :
130			MTYPE_CACHED;
131
132	ape1_mtype = (alternate_policy == cache_policy_coherent) ?
133			MTYPE_NONCACHED :
134			MTYPE_CACHED;
135
136	qpd->sh_mem_config = (qpd->sh_mem_config & PTR32)
137			| ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
138			| DEFAULT_MTYPE(default_mtype)
139			| APE1_MTYPE(ape1_mtype);
140	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
141	 * aperture addresses.
142	 */
143	temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd));
144	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
145
146	pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
147		qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
148
149out:
150	return retval;
151}
152
153static int update_qpd_cik(struct device_queue_manager *dqm,
154			  struct qcm_process_device *qpd)
155{
156	return 0;
157}
158
159static void init_sdma_vm(struct device_queue_manager *dqm,
160			 struct queue *q,
161			 struct qcm_process_device *qpd)
162{
163	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
164	 * aperture addresses.
165	 */
166	q->properties.sdma_vm_addr =
167		((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
168		 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
169		SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
170}