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cwsr_trap_handler_gfx9.asm
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linux-6.19.14/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * gfx9: 26 * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3 27 * sp3 gfx9.sp3 -hex gfx9.hex 28 * 29 * arcturus: 30 * cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3 31 * sp3 arcturus.sp3 -hex arcturus.hex 32 * 33 * aldebaran: 34 * cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3 35 * sp3 aldebaran.sp3 -hex aldebaran.hex 36 * 37 * gc_9_4_3: 38 * cpp -DASIC_FAMILY=GC_9_4_3 cwsr_trap_handler_gfx9.asm -P -o gc_9_4_3.sp3 39 * sp3 gc_9_4_3.sp3 -hex gc_9_4_3.hex 40 * 41 * gc_9_5_0: 42 * cpp -DASIC_FAMILY=GC_9_5_0 cwsr_trap_handler_gfx9.asm -P -o gc_9_5_0.sp3 43 * sp3 gc_9_5_0.sp3 -hex gc_9_5_0.hex 44 */ 45 46#define CHIP_VEGAM 18 47#define CHIP_ARCTURUS 23 48#define CHIP_ALDEBARAN 25 49#define CHIP_GC_9_4_3 26 50#define CHIP_GC_9_5_0 27 51 52var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 53var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger 54var SINGLE_STEP_MISSED_WORKAROUND = (ASIC_FAMILY <= CHIP_ALDEBARAN) //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 55 56#if ASIC_FAMILY < CHIP_GC_9_4_3 57#define VMEM_MODIFIERS slc:1 glc:1 58#else 59#define VMEM_MODIFIERS sc0:1 nt:1 60#endif 61 62/**************************************************************************/ 63/* variables */ 64/**************************************************************************/ 65var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 66var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 67var SQ_WAVE_STATUS_HALT_MASK = 0x2000 68var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 69var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 70var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 71var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 72var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 73var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 74 75var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 76#if ASIC_FAMILY >= CHIP_GC_9_5_0 77var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 11 78var LDS_RESTORE_GRANULARITY_BYTES = 1280 79#else 80var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 81var LDS_RESTORE_GRANULARITY_BYTES = 512 82#endif 83var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 84var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 85var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 86 87#if ASIC_FAMILY >= CHIP_ALDEBARAN 88var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 6 89var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT = 12 90var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE = 6 91#else 92var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 93#endif 94 95var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 96var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 97var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 98var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 99var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 100var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 101var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 102var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 103var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 104var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 105var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 106var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 107var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 108var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 109var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 110var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 111var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 112var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 113var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 114var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 115 116var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 117var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 118 119var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 120var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 121 122var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 123 124var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 125var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 126var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 127var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 128 129/* Save */ 130var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 131var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 132var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 133var S_SAVE_PC_HI_HT_MASK = 0x01000000 134var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 135var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 136 137var s_save_spi_init_lo = exec_lo 138var s_save_spi_init_hi = exec_hi 139 140var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 141var s_save_pc_hi = ttmp1 142var s_save_exec_lo = ttmp2 143var s_save_exec_hi = ttmp3 144var s_save_tmp = ttmp14 145var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine 146var s_save_xnack_mask_lo = ttmp6 147var s_save_xnack_mask_hi = ttmp7 148var s_save_buf_rsrc0 = ttmp8 149var s_save_buf_rsrc1 = ttmp9 150var s_save_buf_rsrc2 = ttmp10 151var s_save_buf_rsrc3 = ttmp11 152var s_save_status = ttmp12 153var s_save_mem_offset = ttmp4 154var s_save_alloc_size = s_save_trapsts //conflict 155var s_save_m0 = ttmp5 156var s_save_ttmps_lo = s_save_tmp //no conflict 157var s_save_ttmps_hi = s_save_trapsts //no conflict 158#if ASIC_FAMILY >= CHIP_GC_9_4_3 159var s_save_ib_sts = ttmp13 160#else 161var s_save_ib_sts = ttmp11 162#endif 163 164/* Restore */ 165var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 166var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 167 168var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 169var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 170 171var s_restore_spi_init_lo = exec_lo 172var s_restore_spi_init_hi = exec_hi 173 174var s_restore_mem_offset = ttmp12 175var s_restore_tmp2 = ttmp13 176var s_restore_alloc_size = ttmp3 177var s_restore_tmp = ttmp2 178var s_restore_mem_offset_save = s_restore_tmp //no conflict 179var s_restore_accvgpr_offset_save = ttmp7 180 181var s_restore_m0 = s_restore_alloc_size //no conflict 182 183var s_restore_mode = s_restore_accvgpr_offset_save 184 185var s_restore_pc_lo = ttmp0 186var s_restore_pc_hi = ttmp1 187var s_restore_exec_lo = ttmp4 188var s_restore_exec_hi = ttmp5 189var s_restore_status = ttmp14 190var s_restore_trapsts = ttmp15 191var s_restore_xnack_mask_lo = xnack_mask_lo 192var s_restore_xnack_mask_hi = xnack_mask_hi 193var s_restore_buf_rsrc0 = ttmp8 194var s_restore_buf_rsrc1 = ttmp9 195var s_restore_buf_rsrc2 = ttmp10 196var s_restore_buf_rsrc3 = ttmp11 197var s_restore_ttmps_lo = s_restore_tmp //no conflict 198var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 199 200/**************************************************************************/ 201/* trap handler entry points */ 202/**************************************************************************/ 203/* Shader Main*/ 204 205shader main 206 asic(DEFAULT) 207 type(CS) 208 209 210 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 211 212L_JUMP_TO_RESTORE: 213 s_branch L_RESTORE //restore 214 215L_SKIP_RESTORE: 216 217 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 218 219 // Clear SPI_PRIO: do not save with elevated priority. 220 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 221 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 222 223 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 224 225 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 226 s_cbranch_scc0 L_NOT_HALTED 227 228L_HALTED: 229 // Host trap may occur while wave is halted. 230 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 231 s_cbranch_scc1 L_FETCH_2ND_TRAP 232 233L_CHECK_SAVE: 234 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 235 s_cbranch_scc1 L_SAVE //this is the operation for save 236 237 // Wave is halted but neither host trap nor SAVECTX is raised. 238 // Caused by instruction fetch memory violation. 239 // Spin wait until context saved to prevent interrupt storm. 240 s_sleep 0x10 241 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 242 s_branch L_CHECK_SAVE 243 244L_NOT_HALTED: 245 // Let second-level handle non-SAVECTX exception or trap. 246 // Any concurrent SAVECTX will be handled upon re-entry once halted. 247 248 // Check non-maskable exceptions. memory_violation, illegal_instruction 249 // and debugger (host trap, wave start/end, trap after instruction) 250 // exceptions always cause the wave to enter the trap handler. 251 s_and_b32 ttmp2, s_save_trapsts, \ 252 SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ 253 SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ 254 SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ 255 SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ 256 SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ 257 SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK 258 s_cbranch_scc1 L_FETCH_2ND_TRAP 259 260 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 261 // Maskable exceptions only cause the wave to enter the trap handler if 262 // their respective bit in mode.excp_en is set. 263 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 264 s_cbranch_scc0 L_CHECK_TRAP_ID 265 266 s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 267 s_cbranch_scc0 L_NOT_ADDR_WATCH 268 s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 269 270L_NOT_ADDR_WATCH: 271 s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 272 s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 273 s_and_b32 ttmp2, ttmp2, ttmp3 274 s_cbranch_scc1 L_FETCH_2ND_TRAP 275 276L_CHECK_TRAP_ID: 277 // Check trap_id != 0 278 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 279 s_cbranch_scc1 L_FETCH_2ND_TRAP 280 281if SINGLE_STEP_MISSED_WORKAROUND 282 // Prioritize single step exception over context save. 283 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 284 s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 285 s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 286 s_cbranch_scc1 L_FETCH_2ND_TRAP 287end 288 289 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 290 s_cbranch_scc1 L_SAVE 291 292L_FETCH_2ND_TRAP: 293 // Preserve and clear scalar XNACK state before issuing scalar reads. 294 save_and_clear_ib_sts(ttmp14) 295 296 // Read second-level TBA/TMA from first-level TMA and jump if available. 297 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 298 // ttmp12 holds SQ_WAVE_STATUS 299 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 300 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 301 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 302 303 s_bitcmp1_b32 ttmp15, 0xF 304 s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA 305 s_or_b32 ttmp15, ttmp15, 0xFFFF0000 306L_NO_SIGN_EXTEND_TMA: 307 308 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 309 s_waitcnt lgkmcnt(0) 310 s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT 311 s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK 312 s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 313 314 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 315 s_waitcnt lgkmcnt(0) 316 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 317 s_waitcnt lgkmcnt(0) 318 319 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 320 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 321 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 322 323L_NO_NEXT_TRAP: 324 // If not caused by trap then halt wave to prevent re-entry. 325 s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 326 s_cbranch_scc1 L_TRAP_CASE 327 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 328 329 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 330 // Rewind the PC to prevent this from occurring. 331 s_sub_u32 ttmp0, ttmp0, 0x8 332 s_subb_u32 ttmp1, ttmp1, 0x0 333 334 s_branch L_EXIT_TRAP 335 336L_TRAP_CASE: 337 // Host trap will not cause trap re-entry. 338 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 339 s_cbranch_scc1 L_EXIT_TRAP 340 341 // Advance past trap instruction to prevent re-entry. 342 s_add_u32 ttmp0, ttmp0, 0x4 343 s_addc_u32 ttmp1, ttmp1, 0x0 344 345L_EXIT_TRAP: 346 s_and_b32 ttmp1, ttmp1, 0xFFFF 347 348 restore_ib_sts(ttmp14) 349 350 // Restore SQ_WAVE_STATUS. 351 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 352 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 353 set_status_without_spi_prio(s_save_status, ttmp2) 354 355 s_rfe_b64 [ttmp0, ttmp1] 356 357 // ********* End handling of non-CWSR traps ******************* 358 359/**************************************************************************/ 360/* save routine */ 361/**************************************************************************/ 362 363L_SAVE: 364 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 365 366 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 367 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 368 369 save_and_clear_ib_sts(s_save_tmp) 370 371 /* inform SPI the readiness and wait for SPI's go signal */ 372 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 373 s_mov_b32 s_save_exec_hi, exec_hi 374 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 375 376 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 377 378 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 379 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 380 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 381 382 L_SLEEP: 383 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 384 385 s_cbranch_execz L_SLEEP 386 387 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 388 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 389 get_vgpr_size_bytes(s_save_ttmps_lo) 390 get_sgpr_size_bytes(s_save_ttmps_hi) 391 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 392 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 393 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 394 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 395 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 396 ack_sqc_store_workaround() 397 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 398 ack_sqc_store_workaround() 399 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 400 ack_sqc_store_workaround() 401 402 /* setup Resource Contants */ 403 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 404 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 405 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 406 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 407 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 408 409 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 410 s_mov_b32 s_save_m0, m0 //save M0 411 412 /* global mem offset */ 413 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 414 415 416 417 418 /* save HW registers */ 419 ////////////////////////////// 420 421 L_SAVE_HWREG: 422 // HWREG SR memory offset : size(VGPR)+size(SGPR) 423 get_vgpr_size_bytes(s_save_mem_offset) 424 get_sgpr_size_bytes(s_save_tmp) 425 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 426 427 428 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 429 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 430 431 432 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 433 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 434 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 435 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 436 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 437 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 438 439 //s_save_trapsts conflicts with s_save_alloc_size 440 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 441 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 442 443 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 444 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 445 446 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 447 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 448 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 449 450 // Clear VSKIP state now that MODE.VSKIP has been saved. 451 // If user shader set it then vector instructions would be skipped. 452 s_setvskip 0,0 453 454 /* the first wave in the threadgroup */ 455 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 456 s_mov_b32 s_save_exec_hi, 0x0 457 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 458 459 460 /* save SGPRs */ 461 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 462 ////////////////////////////// 463 464 // SGPR SR memory offset : size(VGPR) 465 get_vgpr_size_bytes(s_save_mem_offset) 466 // TODO, change RSRC word to rearrange memory layout for SGPRS 467 468 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 469 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 470 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 471 472 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 473 474 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 475 476 477 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 478 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 479 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 480 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 481 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 482 483 s_mov_b32 m0, 0x0 //SGPR initial index value =0 484 s_nop 0x0 //Manually inserted wait states 485 L_SAVE_SGPR_LOOP: 486 // SGPR is allocated in 16 SGPR granularity 487 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 488 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 489 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 490 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 491 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 492 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 493 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 494 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 495 496 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 497 s_add_u32 m0, m0, 16 //next sgpr index 498 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 499 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 500 // restore s_save_buf_rsrc0,1 501 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 502 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 503 504 505 506 507 /* save first 4 VGPR, then LDS save could use */ 508 // each wave will alloc 4 vgprs at least... 509 ///////////////////////////////////////////////////////////////////////////////////// 510 511 s_mov_b32 s_save_mem_offset, 0 512 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 513 s_mov_b32 exec_hi, 0xFFFFFFFF 514 s_mov_b32 xnack_mask_lo, 0x0 515 s_mov_b32 xnack_mask_hi, 0x0 516 517 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 518 519 520 // VGPR Allocated in 4-GPR granularity 521 522if SAVE_AFTER_XNACK_ERROR 523 check_if_tcp_store_ok() 524 s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP 525 526 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 527 s_branch L_SAVE_LDS 528 529L_SAVE_FIRST_VGPRS_WITH_TCP: 530end 531 532 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 533 534 /* save LDS */ 535 ////////////////////////////// 536 537 L_SAVE_LDS: 538 539 // Change EXEC to all threads... 540 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 541 s_mov_b32 exec_hi, 0xFFFFFFFF 542 543 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 544 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 545 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 546 547 s_barrier //LDS is used? wait for other waves in the same TG 548 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 549 s_cbranch_scc0 L_SAVE_LDS_DONE 550 551 // first wave do LDS save; 552 553 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 554 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 555 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 556 557 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 558 // 559 get_vgpr_size_bytes(s_save_mem_offset) 560 get_sgpr_size_bytes(s_save_tmp) 561 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 562 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 563 564 565 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 566 567 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 568 569 570 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 571 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 572 573if SAVE_AFTER_XNACK_ERROR 574 check_if_tcp_store_ok() 575 s_cbranch_scc1 L_SAVE_LDS_WITH_TCP 576 577 v_lshlrev_b32 v2, 2, v3 578L_SAVE_LDS_LOOP_SQC: 579#if ASIC_FAMILY < CHIP_GC_9_5_0 580 ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40 581 s_waitcnt lgkmcnt(0) 582 write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset) 583 584 v_add_u32 v2, 0x200, v2 585#else 586 // gfx950 needs to save in multiple of 256 bytes. 587 ds_read_b32 v0, v2 588 s_waitcnt lgkmcnt(0) 589 write_vgprs_to_mem_with_sqc(v0, 1, s_save_buf_rsrc0, s_save_mem_offset) 590 591 v_add_u32 v2, 0x100, v2 592#endif 593 594 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 595 s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC 596 597 s_branch L_SAVE_LDS_DONE 598 599L_SAVE_LDS_WITH_TCP: 600end 601 602 v_mul_i32_i24 v2, v3, 8 // tid*8 603 v_mov_b32 v3, 256*2 604 s_mov_b32 m0, 0x10000 605 s_mov_b32 s0, s_save_buf_rsrc3 606 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 607 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 608 609L_SAVE_LDS_LOOP_VECTOR: 610 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 611 s_waitcnt lgkmcnt(0) 612 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset VMEM_MODIFIERS offen:1 613// s_waitcnt vmcnt(0) 614// v_add_u32 v2, vcc[0:1], v2, v3 615 v_add_u32 v2, v2, v3 616 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 617#if ASIC_FAMILY >= CHIP_GC_9_5_0 618 s_mov_b64 exec, vcc 619#endif 620 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 621 622 // restore rsrc3 623 s_mov_b32 s_save_buf_rsrc3, s0 624 625L_SAVE_LDS_DONE: 626 627 628 /* save VGPRs - set the Rest VGPRs */ 629 ////////////////////////////////////////////////////////////////////////////////////// 630 L_SAVE_VGPR: 631 // VGPR SR memory offset: 0 632 // TODO rearrange the RSRC words to use swizzle for VGPR save... 633 634 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 635 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 636 s_mov_b32 exec_hi, 0xFFFFFFFF 637 638 get_num_arch_vgprs(s_save_alloc_size) 639 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 640 641 642 // VGPR store using dw burst 643 s_mov_b32 m0, 0x4 //VGPR initial index value =0 644 s_cmp_lt_u32 m0, s_save_alloc_size 645 s_cbranch_scc0 L_SAVE_VGPR_END 646 647 648 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 649 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 650 651if SAVE_AFTER_XNACK_ERROR 652 check_if_tcp_store_ok() 653 s_cbranch_scc1 L_SAVE_VGPR_LOOP 654 655L_SAVE_VGPR_LOOP_SQC: 656 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 657 658 s_add_u32 m0, m0, 4 659 s_cmp_lt_u32 m0, s_save_alloc_size 660 s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC 661 662 s_set_gpr_idx_off 663 s_branch L_SAVE_VGPR_END 664end 665 666 L_SAVE_VGPR_LOOP: 667 v_mov_b32 v0, v0 //v0 = v[0+m0] 668 v_mov_b32 v1, v1 //v0 = v[0+m0] 669 v_mov_b32 v2, v2 //v0 = v[0+m0] 670 v_mov_b32 v3, v3 //v0 = v[0+m0] 671 672 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 673 674 s_add_u32 m0, m0, 4 //next vgpr index 675 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 676 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 677 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 678 s_set_gpr_idx_off 679 680L_SAVE_VGPR_END: 681 682#if ASIC_FAMILY >= CHIP_ARCTURUS 683 // Save ACC VGPRs 684 685#if ASIC_FAMILY >= CHIP_ALDEBARAN 686 // ACC VGPR count may differ from ARCH VGPR count. 687 get_num_acc_vgprs(s_save_alloc_size, s_save_tmp) 688 s_and_b32 s_save_alloc_size, s_save_alloc_size, s_save_alloc_size 689 s_cbranch_scc0 L_SAVE_ACCVGPR_END 690 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 691#endif 692 693 s_mov_b32 m0, 0x0 //VGPR initial index value =0 694 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 695 696if SAVE_AFTER_XNACK_ERROR 697 check_if_tcp_store_ok() 698 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 699 700L_SAVE_ACCVGPR_LOOP_SQC: 701 for var vgpr = 0; vgpr < 4; ++ vgpr 702 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 703 end 704 705 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 706 707 s_add_u32 m0, m0, 4 708 s_cmp_lt_u32 m0, s_save_alloc_size 709 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC 710 711 s_set_gpr_idx_off 712 s_branch L_SAVE_ACCVGPR_END 713end 714 715L_SAVE_ACCVGPR_LOOP: 716 for var vgpr = 0; vgpr < 4; ++ vgpr 717 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 718 end 719 720 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 721 722 s_add_u32 m0, m0, 4 723 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 724 s_cmp_lt_u32 m0, s_save_alloc_size 725 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 726 s_set_gpr_idx_off 727 728L_SAVE_ACCVGPR_END: 729#endif 730 731 s_branch L_END_PGM 732 733 734 735/**************************************************************************/ 736/* restore routine */ 737/**************************************************************************/ 738 739L_RESTORE: 740 /* Setup Resource Contants */ 741 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 742 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 743 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 744 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 745 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 746 747 /* global mem offset */ 748// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 749 750 /* the first wave in the threadgroup */ 751 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 752 s_cbranch_scc0 L_RESTORE_VGPR 753 754 /* restore LDS */ 755 ////////////////////////////// 756 L_RESTORE_LDS: 757 758 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 759 s_mov_b32 exec_hi, 0xFFFFFFFF 760 761 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 762 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 763 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 764 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 765 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 766 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 767 768 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 769 // 770 get_vgpr_size_bytes(s_restore_mem_offset) 771 get_sgpr_size_bytes(s_restore_tmp) 772 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 773 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 774 775 776 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 777 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 778 779 L_RESTORE_LDS_LOOP: 780 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 781 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 782#if ASIC_FAMILY >= CHIP_GC_9_5_0 783 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:512 // third 64DW 784 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:768 // forth 64DW 785 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:1024 // fifth 64DW 786#endif 787 s_add_u32 m0, m0, LDS_RESTORE_GRANULARITY_BYTES // 128/320 DW 788 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, LDS_RESTORE_GRANULARITY_BYTES //mem offset increased by 128/320 DW 789 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 790 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 791 792 793 /* restore VGPRs */ 794 ////////////////////////////// 795 L_RESTORE_VGPR: 796 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 797 s_mov_b32 exec_hi, 0xFFFFFFFF 798 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 799 800 // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3. 801 get_num_arch_vgprs(s_restore_alloc_size) 802 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 803 804 // ARCH VGPRs at offset: 0 805 s_mov_b32 s_restore_mem_offset, 0x0 806 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 807 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 808 s_mov_b32 m0, 4 //VGPR initial index value = 1 809 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 810 811 L_RESTORE_VGPR_LOOP: 812 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 813 v_mov_b32 v0, v0 //v[0+m0] = v0 814 v_mov_b32 v1, v1 815 v_mov_b32 v2, v2 816 v_mov_b32 v3, v3 817 s_add_u32 m0, m0, 4 //next vgpr index 818 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 819 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 820 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 821 822#if ASIC_FAMILY >= CHIP_ALDEBARAN 823 // ACC VGPR count may differ from ARCH VGPR count. 824 get_num_acc_vgprs(s_restore_alloc_size, s_restore_tmp2) 825 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, s_restore_alloc_size 826 s_cbranch_scc0 L_RESTORE_ACCVGPR_END 827 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 828#endif 829 830#if ASIC_FAMILY >= CHIP_ARCTURUS 831 // ACC VGPRs at offset: size(ARCH VGPRs) 832 s_mov_b32 m0, 0 833 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 834 835 L_RESTORE_ACCVGPR_LOOP: 836 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 837 838 for var vgpr = 0; vgpr < 4; ++ vgpr 839 v_accvgpr_write acc[vgpr], v[vgpr] 840 end 841 842 s_add_u32 m0, m0, 4 //next vgpr index 843 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 844 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 845 s_cbranch_scc1 L_RESTORE_ACCVGPR_LOOP //VGPR restore (except v0) is complete? 846 L_RESTORE_ACCVGPR_END: 847#endif 848 849 s_set_gpr_idx_off 850 851 // Restore VGPRs 0-3 last, no longer needed. 852 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset_save) 853 854 /* restore SGPRs */ 855 ////////////////////////////// 856 857 // SGPR SR memory offset : size(VGPR) 858 get_vgpr_size_bytes(s_restore_mem_offset) 859 get_sgpr_size_bytes(s_restore_tmp) 860 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 861 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 862 // TODO, change RSRC word to rearrange memory layout for SGPRS 863 864 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 865 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 866 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 867 868 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 869 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 870 871 s_mov_b32 m0, s_restore_alloc_size 872 873 L_RESTORE_SGPR_LOOP: 874 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 875 s_waitcnt lgkmcnt(0) //ensure data ready 876 877 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 878 s_nop 0 // hazard SALU M0=> S_MOVREL 879 880 s_movreld_b64 s0, s0 //s[0+m0] = s0 881 s_movreld_b64 s2, s2 882 s_movreld_b64 s4, s4 883 s_movreld_b64 s6, s6 884 s_movreld_b64 s8, s8 885 s_movreld_b64 s10, s10 886 s_movreld_b64 s12, s12 887 s_movreld_b64 s14, s14 888 889 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 890 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 891 892 /* restore HW registers */ 893 ////////////////////////////// 894 L_RESTORE_HWREG: 895 896 897 // HWREG SR memory offset : size(VGPR)+size(SGPR) 898 get_vgpr_size_bytes(s_restore_mem_offset) 899 get_sgpr_size_bytes(s_restore_tmp) 900 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 901 902 903 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 904 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 905 906 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 907 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 908 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 909 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 910 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 911 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 912 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 913 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 914 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 915 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 916 917 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 918 919 s_mov_b32 m0, s_restore_m0 920 s_mov_b32 exec_lo, s_restore_exec_lo 921 s_mov_b32 exec_hi, s_restore_exec_hi 922 923 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 924 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 925 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 926 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 927 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 928 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 929 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 930 931 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 932 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 933 get_vgpr_size_bytes(s_restore_ttmps_lo) 934 get_sgpr_size_bytes(s_restore_ttmps_hi) 935 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 936 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 937 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 938 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 939 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 940 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 941 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 942 s_waitcnt lgkmcnt(0) 943 944 restore_ib_sts(s_restore_tmp) 945 946 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 947 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 948 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 949 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 950 951 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 952 953 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 954 955 956/**************************************************************************/ 957/* the END */ 958/**************************************************************************/ 959L_END_PGM: 960 s_endpgm_saved 961 962end 963 964 965/**************************************************************************/ 966/* the helper functions */ 967/**************************************************************************/ 968 969//Only for save hwreg to mem 970function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 971 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 972 s_mov_b32 m0, s_mem_offset 973 s_buffer_store_dword s, s_rsrc, m0 glc:1 974 ack_sqc_store_workaround() 975 s_add_u32 s_mem_offset, s_mem_offset, 4 976 s_mov_b32 m0, exec_lo 977end 978 979 980// HWREG are saved before SGPRs, so all HWREG could be use. 981function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 982 983 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 984 ack_sqc_store_workaround() 985 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 986 ack_sqc_store_workaround() 987 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 988 ack_sqc_store_workaround() 989 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 990 ack_sqc_store_workaround() 991 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 992 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 993end 994 995 996function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 997 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 998 s_add_u32 s_mem_offset, s_mem_offset, 4 999end 1000 1001function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1002 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1003 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1004end 1005 1006function check_if_tcp_store_ok 1007 // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail. 1008 s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK 1009 s_cbranch_scc1 L_TCP_STORE_CHECK_DONE 1010 1011 s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) 1012 s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp 1013 1014L_TCP_STORE_CHECK_DONE: 1015end 1016 1017function write_4vgprs_to_mem(s_rsrc, s_mem_offset) 1018 buffer_store_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 1019 buffer_store_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256 1020 buffer_store_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2 1021 buffer_store_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3 1022end 1023 1024function read_4vgprs_from_mem(s_rsrc, s_mem_offset) 1025 buffer_load_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 1026 buffer_load_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256 1027 buffer_load_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2 1028 buffer_load_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3 1029 s_waitcnt vmcnt(0) 1030end 1031 1032function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset) 1033 s_mov_b32 s4, 0 1034 1035L_WRITE_VGPR_LANE_LOOP: 1036 for var lane = 0; lane < 4; ++ lane 1037 v_readlane_b32 s[lane], v, s4 1038 s_add_u32 s4, s4, 1 1039 end 1040 1041 s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1 1042 ack_sqc_store_workaround() 1043 1044 s_add_u32 s_mem_offset, s_mem_offset, 0x10 1045 s_cmp_eq_u32 s4, 0x40 1046 s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP 1047end 1048 1049function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset) 1050 for var vgpr = 0; vgpr < n_vgprs; ++ vgpr 1051 write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset) 1052 end 1053end 1054 1055function get_lds_size_bytes(s_lds_size_byte) 1056 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1057 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1058 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1059end 1060 1061function get_vgpr_size_bytes(s_vgpr_size_byte) 1062 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1063 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1064 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1065 1066#if ASIC_FAMILY >= CHIP_ARCTURUS 1067 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs 1068#endif 1069end 1070 1071function get_sgpr_size_bytes(s_sgpr_size_byte) 1072 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1073 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1074 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1075end 1076 1077function get_hwreg_size_bytes 1078 return 128 //HWREG size 128 bytes 1079end 1080 1081function get_num_arch_vgprs(s_num_arch_vgprs) 1082#if ASIC_FAMILY >= CHIP_ALDEBARAN 1083 // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count. 1084 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE) 1085#else 1086 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1087#endif 1088 1089 // Number of VGPRs = (vgpr_size + 1) * 4 1090 s_add_u32 s_num_arch_vgprs, s_num_arch_vgprs, 1 1091 s_lshl_b32 s_num_arch_vgprs, s_num_arch_vgprs, 2 1092end 1093 1094#if ASIC_FAMILY >= CHIP_ALDEBARAN 1095function get_num_acc_vgprs(s_num_acc_vgprs, s_tmp) 1096 // VGPR count = (GPR_ALLOC.VGPR_SIZE + 1) * 8 1097 s_getreg_b32 s_num_acc_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1098 s_add_u32 s_num_acc_vgprs, s_num_acc_vgprs, 1 1099 s_lshl_b32 s_num_acc_vgprs, s_num_acc_vgprs, 3 1100 1101 // ACC VGPR count = VGPR count - ARCH VGPR count. 1102 get_num_arch_vgprs(s_tmp) 1103 s_sub_u32 s_num_acc_vgprs, s_num_acc_vgprs, s_tmp 1104end 1105#endif 1106 1107function ack_sqc_store_workaround 1108 if ACK_SQC_STORE 1109 s_waitcnt lgkmcnt(0) 1110 end 1111end 1112 1113function set_status_without_spi_prio(status, tmp) 1114 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1115 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1116 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1117 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1118 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1119end 1120 1121function save_and_clear_ib_sts(tmp) 1122 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space s_save_ib_sts[31:26]. 1123 s_getreg_b32 tmp, hwreg(HW_REG_IB_STS) 1124 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1125 s_lshl_b32 tmp, tmp, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1126 s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_SAVE_RCNT_FIRST_REPLAY_MASK 1127 s_or_b32 s_save_ib_sts, s_save_ib_sts, tmp 1128 s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0x0 1129end 1130 1131function restore_ib_sts(tmp) 1132 s_lshr_b32 tmp, s_save_ib_sts, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1133 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1134 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp 1135end
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