vega20_ih.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include <linux/pci.h>
 25
 26#include "amdgpu.h"
 27#include "amdgpu_ih.h"
 28#include "soc15.h"
 29
 30#include "oss/osssys_4_2_0_offset.h"
 31#include "oss/osssys_4_2_0_sh_mask.h"
 32
 33#include "soc15_common.h"
 34#include "vega20_ih.h"
 35
 36#define MAX_REARM_RETRY 10
 37
 38#define mmIH_CHICKEN_ALDEBARAN			0x18d
 39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX		0
 40
 41#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN		0x00ea
 42#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX	0
 43#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT	0x10
 44#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK	0x00010000L
 45
 46static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
 47
 48/**
 49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
 50 *
 51 * @adev: amdgpu_device pointer
 52 *
 53 * Initialize register offset ih rings (VEGA20).
 54 */
 55static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
 56{
 57	struct amdgpu_ih_regs *ih_regs;
 58
 59	if (adev->irq.ih.ring_size) {
 60		ih_regs = &adev->irq.ih.ih_regs;
 61		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
 62		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
 63		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
 64		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
 65		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
 66		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
 67		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
 68		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
 69		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
 70	}
 71
 72	if (adev->irq.ih1.ring_size) {
 73		ih_regs = &adev->irq.ih1.ih_regs;
 74		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
 75		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
 76		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
 77		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
 78		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
 79		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
 80		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
 81	}
 82
 83	if (adev->irq.ih2.ring_size) {
 84		ih_regs = &adev->irq.ih2.ih_regs;
 85		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
 86		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
 87		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
 88		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
 89		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
 90		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
 91		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
 92	}
 93}
 94
 95/**
 96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
 97 *
 98 * @adev: amdgpu_device pointer
 99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
104static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105					    struct amdgpu_ih_ring *ih,
106					    bool enable)
107{
108	struct amdgpu_ih_regs *ih_regs;
109	uint32_t tmp;
110
111	ih_regs = &ih->ih_regs;
112
113	tmp = RREG32(ih_regs->ih_rb_cntl);
114	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117	if (enable) {
118		/* Unset the CLEAR_OVERFLOW bit to make sure the next step
119		 * is switching the bit from 0 to 1
120		 */
121		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
122		if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
123			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
124				return -ETIMEDOUT;
125		} else {
126			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
127		}
128
129		/* Clear RB_OVERFLOW bit */
130		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
131		if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
132			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
133				return -ETIMEDOUT;
134		} else {
135			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
136		}
137
138		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
139		 * can be detected.
140		 */
141		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
142	}
143
144	/* enable_intr field is only valid in ring0 */
145	if (ih == &adev->irq.ih)
146		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
147	if (amdgpu_sriov_vf(adev)) {
148		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
149			dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
150			return -ETIMEDOUT;
151		}
152	} else {
153		WREG32(ih_regs->ih_rb_cntl, tmp);
154	}
155
156	if (enable) {
157		ih->enabled = true;
158	} else {
159		/* set rptr, wptr to 0 */
160		WREG32(ih_regs->ih_rb_rptr, 0);
161		WREG32(ih_regs->ih_rb_wptr, 0);
162		ih->enabled = false;
163		ih->rptr = 0;
164	}
165
166	return 0;
167}
168
169/**
170 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
171 *
172 * @adev: amdgpu_device pointer
173 * @enable: enable or disable interrupt ring buffers
174 *
175 * Toggle all the available interrupt ring buffers (VEGA20).
176 */
177static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
178{
179	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
180	int i;
181	int r;
182
183	for (i = 0; i < ARRAY_SIZE(ih); i++) {
184		if (ih[i]->ring_size) {
185			r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
186			if (r)
187				return r;
188		}
189	}
190
191	return 0;
192}
193
194static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
195{
196	int rb_bufsz = order_base_2(ih->ring_size / 4);
197
198	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
199				   MC_SPACE, ih->use_bus_addr ? 1 : 4);
200	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
201				   WPTR_OVERFLOW_CLEAR, 1);
202	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
203				   WPTR_OVERFLOW_ENABLE, 1);
204	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
205	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
206	 * value is written to memory
207	 */
208	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
209				   WPTR_WRITEBACK_ENABLE, 1);
210	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
211	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
212	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
213
214	return ih_rb_cntl;
215}
216
217static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
218{
219	u32 ih_doorbell_rtpr = 0;
220
221	if (ih->use_doorbell) {
222		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223						 IH_DOORBELL_RPTR, OFFSET,
224						 ih->doorbell_index);
225		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
226						 IH_DOORBELL_RPTR,
227						 ENABLE, 1);
228	} else {
229		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
230						 IH_DOORBELL_RPTR,
231						 ENABLE, 0);
232	}
233	return ih_doorbell_rtpr;
234}
235
236/**
237 * vega20_ih_enable_ring - enable an ih ring buffer
238 *
239 * @adev: amdgpu_device pointer
240 * @ih: amdgpu_ih_ring pointer
241 *
242 * Enable an ih ring buffer (VEGA20)
243 */
244static int vega20_ih_enable_ring(struct amdgpu_device *adev,
245				 struct amdgpu_ih_ring *ih)
246{
247	struct amdgpu_ih_regs *ih_regs;
248	uint32_t tmp;
249
250	ih_regs = &ih->ih_regs;
251
252	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
253	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
254	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
255
256	tmp = RREG32(ih_regs->ih_rb_cntl);
257	tmp = vega20_ih_rb_cntl(ih, tmp);
258	if (ih == &adev->irq.ih)
259		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
260	if (ih == &adev->irq.ih1)
261		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
262	if (amdgpu_sriov_vf(adev)) {
263		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
264			dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
265			return -ETIMEDOUT;
266		}
267	} else {
268		WREG32(ih_regs->ih_rb_cntl, tmp);
269	}
270
271	if (ih == &adev->irq.ih) {
272		/* set the ih ring 0 writeback address whether it's enabled or not */
273		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
274		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
275	}
276
277	/* set rptr, wptr to 0 */
278	WREG32(ih_regs->ih_rb_wptr, 0);
279	WREG32(ih_regs->ih_rb_rptr, 0);
280
281	WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
282
283	return 0;
284}
285
286static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
287{
288	u32 val = 0;
289
290	val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
291	val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
292
293	return val;
294}
295
296/**
297 * vega20_ih_irq_init - init and enable the interrupt ring
298 *
299 * @adev: amdgpu_device pointer
300 *
301 * Allocate a ring buffer for the interrupt controller,
302 * enable the RLC, disable interrupts, enable the IH
303 * ring buffer and enable it (VI).
304 * Called at device load and reume.
305 * Returns 0 for success, errors for failure.
306 */
307static int vega20_ih_irq_init(struct amdgpu_device *adev)
308{
309	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
310	u32 ih_chicken;
311	int ret;
312	int i;
313
314	/* disable irqs */
315	ret = vega20_ih_toggle_interrupts(adev, false);
316	if (ret)
317		return ret;
318
319	adev->nbio.funcs->ih_control(adev);
320
321	if (!amdgpu_sriov_vf(adev)) {
322		if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) &&
323		    adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
324			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
325			if (adev->irq.ih.use_bus_addr) {
326				ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
327							   MC_SPACE_GPA_ENABLE, 1);
328			}
329			WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
330		}
331
332		/* psp firmware won't program IH_CHICKEN for aldebaran
333		 * driver needs to program it properly according to
334		 * MC_SPACE type in IH_RB_CNTL */
335		if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||
336		    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) ||
337		    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) {
338			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
339			if (adev->irq.ih.use_bus_addr) {
340				ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
341							   MC_SPACE_GPA_ENABLE, 1);
342			}
343			WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
344		}
345	}
346
347	for (i = 0; i < ARRAY_SIZE(ih); i++) {
348		if (ih[i]->ring_size) {
349			ret = vega20_ih_enable_ring(adev, ih[i]);
350			if (ret)
351				return ret;
352		}
353		ih[i]->overflow = false;
354	}
355
356	if (!amdgpu_sriov_vf(adev))
357		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
358						    adev->irq.ih.doorbell_index);
359
360	pci_set_master(adev->pdev);
361
362	/* Allocate the doorbell for IH Retry CAM */
363	adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
364	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
365		vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
366
367	/* Enable IH Retry CAM */
368	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||
369	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) ||
370	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 4) ||
371	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))
372		WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
373			       ENABLE, 1);
374	else
375		WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
376
377	adev->irq.retry_cam_enabled = true;
378
379	/* enable interrupts */
380	ret = vega20_ih_toggle_interrupts(adev, true);
381	if (ret)
382		return ret;
383
384	if (adev->irq.ih_soft.ring_size)
385		adev->irq.ih_soft.enabled = true;
386
387	return 0;
388}
389
390/**
391 * vega20_ih_irq_disable - disable interrupts
392 *
393 * @adev: amdgpu_device pointer
394 *
395 * Disable interrupts on the hw (VEGA20).
396 */
397static void vega20_ih_irq_disable(struct amdgpu_device *adev)
398{
399	vega20_ih_toggle_interrupts(adev, false);
400
401	/* Wait and acknowledge irq */
402	mdelay(1);
403}
404
405/**
406 * vega20_ih_get_wptr - get the IH ring buffer wptr
407 *
408 * @adev: amdgpu_device pointer
409 * @ih: amdgpu_ih_ring pointer
410 *
411 * Get the IH ring buffer wptr from either the register
412 * or the writeback memory buffer (VEGA20).  Also check for
413 * ring buffer overflow and deal with it.
414 * Returns the value of the wptr.
415 */
416static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
417			      struct amdgpu_ih_ring *ih)
418{
419	u32 wptr, tmp;
420	struct amdgpu_ih_regs *ih_regs;
421
422	if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
423		/* Only ring0 supports writeback. On other rings fall back
424		 * to register-based code with overflow checking below.
425		 * ih_soft ring doesn't have any backing hardware registers,
426		 * update wptr and return.
427		 */
428		wptr = le32_to_cpu(*ih->wptr_cpu);
429
430		if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
431			goto out;
432	}
433
434	ih_regs = &ih->ih_regs;
435
436	/* Double check that the overflow wasn't already cleared. */
437	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
438	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
439		goto out;
440
441	if (!amdgpu_sriov_vf(adev))
442		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
443	else
444		ih->overflow = true;
445
446	/* When a ring buffer overflow happen start parsing interrupt
447	 * from the last not overwritten vector (wptr + 32). Hopefully
448	 * this should allow us to catchup.
449	 */
450	tmp = (wptr + 32) & ih->ptr_mask;
451	dev_warn_ratelimited(adev->dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
452			     amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
453	ih->rptr = tmp;
454
455	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
456	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
457	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
458
459	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
460	 * can be detected.
461	 */
462	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
463	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
464
465out:
466	return (wptr & ih->ptr_mask);
467}
468
469/**
470 * vega20_ih_irq_rearm - rearm IRQ if lost
471 *
472 * @adev: amdgpu_device pointer
473 * @ih: amdgpu_ih_ring pointer
474 *
475 */
476static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
477			       struct amdgpu_ih_ring *ih)
478{
479	uint32_t v = 0;
480	uint32_t i = 0;
481	struct amdgpu_ih_regs *ih_regs;
482
483	ih_regs = &ih->ih_regs;
484
485	/* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
486	for (i = 0; i < MAX_REARM_RETRY; i++) {
487		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
488		if ((v < ih->ring_size) && (v != ih->rptr))
489			WDOORBELL32(ih->doorbell_index, ih->rptr);
490		else
491			break;
492	}
493}
494
495/**
496 * vega20_ih_set_rptr - set the IH ring buffer rptr
497 *
498 * @adev: amdgpu_device pointer
499 * @ih: amdgpu_ih_ring pointer
500 *
501 * Set the IH ring buffer rptr.
502 */
503static void vega20_ih_set_rptr(struct amdgpu_device *adev,
504			       struct amdgpu_ih_ring *ih)
505{
506	struct amdgpu_ih_regs *ih_regs;
507
508	if (ih == &adev->irq.ih_soft)
509		return;
510
511	if (ih->use_doorbell) {
512		/* XXX check if swapping is necessary on BE */
513		*ih->rptr_cpu = ih->rptr;
514		WDOORBELL32(ih->doorbell_index, ih->rptr);
515
516		if (amdgpu_sriov_vf(adev))
517			vega20_ih_irq_rearm(adev, ih);
518	} else {
519		ih_regs = &ih->ih_regs;
520		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
521	}
522}
523
524/**
525 * vega20_ih_self_irq - dispatch work for ring 1 and 2
526 *
527 * @adev: amdgpu_device pointer
528 * @source: irq source
529 * @entry: IV with WPTR update
530 *
531 * Update the WPTR from the IV and schedule work to handle the entries.
532 */
533static int vega20_ih_self_irq(struct amdgpu_device *adev,
534			      struct amdgpu_irq_src *source,
535			      struct amdgpu_iv_entry *entry)
536{
537	switch (entry->ring_id) {
538	case 1:
539		schedule_work(&adev->irq.ih1_work);
540		break;
541	case 2:
542		schedule_work(&adev->irq.ih2_work);
543		break;
544	default:
545		break;
546	}
547	return 0;
548}
549
550static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
551	.process = vega20_ih_self_irq,
552};
553
554static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
555{
556	adev->irq.self_irq.num_types = 0;
557	adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
558}
559
560static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block)
561{
562	struct amdgpu_device *adev = ip_block->adev;
563
564	vega20_ih_set_interrupt_funcs(adev);
565	vega20_ih_set_self_irq_funcs(adev);
566	return 0;
567}
568
569static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block)
570{
571	struct amdgpu_device *adev = ip_block->adev;
572	bool use_bus_addr = true;
573	int r;
574
575	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
576			      &adev->irq.self_irq);
577	if (r)
578		return r;
579
580	if ((adev->flags & AMD_IS_APU) &&
581	    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)))
582		use_bus_addr = false;
583
584	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
585	if (r)
586		return r;
587
588	adev->irq.ih.use_doorbell = true;
589	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
590
591	r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
592	if (r)
593		return r;
594
595	adev->irq.ih1.use_doorbell = true;
596	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
597
598	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) &&
599	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) {
600		r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
601		if (r)
602			return r;
603
604		adev->irq.ih2.use_doorbell = true;
605		adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
606	}
607
608	/* initialize ih control registers offset */
609	vega20_ih_init_register_offset(adev);
610
611	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
612	if (r)
613		return r;
614
615	r = amdgpu_irq_init(adev);
616
617	return r;
618}
619
620static int vega20_ih_sw_fini(struct amdgpu_ip_block *ip_block)
621{
622	struct amdgpu_device *adev = ip_block->adev;
623
624	amdgpu_irq_fini_sw(adev);
625
626	return 0;
627}
628
629static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block)
630{
631	int r;
632	struct amdgpu_device *adev = ip_block->adev;
633
634	r = vega20_ih_irq_init(adev);
635	if (r)
636		return r;
637
638	return 0;
639}
640
641static int vega20_ih_hw_fini(struct amdgpu_ip_block *ip_block)
642{
643	vega20_ih_irq_disable(ip_block->adev);
644
645	return 0;
646}
647
648static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block)
649{
650	return vega20_ih_hw_fini(ip_block);
651}
652
653static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)
654{
655	return vega20_ih_hw_init(ip_block);
656}
657
658static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)
659{
660	/* todo */
661	return true;
662}
663
664static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
665{
666	/* todo */
667	return -ETIMEDOUT;
668}
669
670static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)
671{
672	/* todo */
673
674	return 0;
675}
676
677static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
678					       bool enable)
679{
680	uint32_t data, def, field_val;
681
682	if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
683		def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
684		field_val = enable ? 0 : 1;
685		data = REG_SET_FIELD(data, IH_CLK_CTRL,
686				     IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
687		data = REG_SET_FIELD(data, IH_CLK_CTRL,
688				     IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
689		data = REG_SET_FIELD(data, IH_CLK_CTRL,
690				     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
691		data = REG_SET_FIELD(data, IH_CLK_CTRL,
692				     OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
693		data = REG_SET_FIELD(data, IH_CLK_CTRL,
694				     LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
695		data = REG_SET_FIELD(data, IH_CLK_CTRL,
696				     DYN_CLK_SOFT_OVERRIDE, field_val);
697		data = REG_SET_FIELD(data, IH_CLK_CTRL,
698				     REG_CLK_SOFT_OVERRIDE, field_val);
699		if (def != data)
700			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
701	}
702}
703
704static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
705					  enum amd_clockgating_state state)
706{
707	struct amdgpu_device *adev = ip_block->adev;
708
709	vega20_ih_update_clockgating_state(adev,
710				state == AMD_CG_STATE_GATE);
711	return 0;
712
713}
714
715static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
716					  enum amd_powergating_state state)
717{
718	return 0;
719}
720
721const struct amd_ip_funcs vega20_ih_ip_funcs = {
722	.name = "vega20_ih",
723	.early_init = vega20_ih_early_init,
724	.sw_init = vega20_ih_sw_init,
725	.sw_fini = vega20_ih_sw_fini,
726	.hw_init = vega20_ih_hw_init,
727	.hw_fini = vega20_ih_hw_fini,
728	.suspend = vega20_ih_suspend,
729	.resume = vega20_ih_resume,
730	.is_idle = vega20_ih_is_idle,
731	.wait_for_idle = vega20_ih_wait_for_idle,
732	.soft_reset = vega20_ih_soft_reset,
733	.set_clockgating_state = vega20_ih_set_clockgating_state,
734	.set_powergating_state = vega20_ih_set_powergating_state,
735};
736
737static const struct amdgpu_ih_funcs vega20_ih_funcs = {
738	.get_wptr = vega20_ih_get_wptr,
739	.decode_iv = amdgpu_ih_decode_iv_helper,
740	.decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
741	.set_rptr = vega20_ih_set_rptr
742};
743
744static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
745{
746	adev->irq.ih_funcs = &vega20_ih_funcs;
747}
748
749const struct amdgpu_ip_block_version vega20_ih_ip_block = {
750	.type = AMD_IP_BLOCK_TYPE_IH,
751	.major = 4,
752	.minor = 2,
753	.rev = 0,
754	.funcs = &vega20_ih_ip_funcs,
755};