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uvd_v7_0.c
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/firmware.h> 25 26#include "amdgpu.h" 27#include "amdgpu_uvd.h" 28#include "amdgpu_cs.h" 29#include "soc15.h" 30#include "soc15d.h" 31#include "soc15_common.h" 32#include "mmsch_v1_0.h" 33 34#include "uvd/uvd_7_0_offset.h" 35#include "uvd/uvd_7_0_sh_mask.h" 36#include "vce/vce_4_0_offset.h" 37#include "vce/vce_4_0_default.h" 38#include "vce/vce_4_0_sh_mask.h" 39#include "nbif/nbif_6_1_offset.h" 40#include "mmhub/mmhub_1_0_offset.h" 41#include "mmhub/mmhub_1_0_sh_mask.h" 42#include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44#define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45#define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46//UVD_PG0_CC_UVD_HARVESTING 47#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50#define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55static int uvd_v7_0_start(struct amdgpu_device *adev); 56static void uvd_v7_0_stop(struct amdgpu_device *adev); 57static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62}; 63 64/** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72{ 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76} 77 78/** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86{ 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93} 94 95/** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103{ 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107} 108 109/** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117{ 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return *ring->wptr_cpu_addr; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127} 128 129/** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137{ 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141} 142 143/** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151{ 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167} 168 169/** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176{ 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr; 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) 187 return r; 188 189 rptr = amdgpu_ring_get_rptr(ring); 190 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 192 amdgpu_ring_commit(ring); 193 194 for (i = 0; i < adev->usec_timeout; i++) { 195 if (amdgpu_ring_get_rptr(ring) != rptr) 196 break; 197 udelay(1); 198 } 199 200 if (i >= adev->usec_timeout) 201 r = -ETIMEDOUT; 202 203 return r; 204} 205 206/** 207 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 208 * 209 * @ring: ring we should submit the msg to 210 * @handle: session handle to use 211 * @bo: amdgpu object for which we query the offset 212 * @fence: optional fence to return 213 * 214 * Open up a stream for HW test 215 */ 216static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, 217 struct amdgpu_bo *bo, 218 struct dma_fence **fence) 219{ 220 const unsigned ib_size_dw = 16; 221 struct amdgpu_job *job; 222 struct amdgpu_ib *ib; 223 struct dma_fence *f = NULL; 224 uint64_t addr; 225 int i, r; 226 227 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 228 AMDGPU_IB_POOL_DIRECT, &job, 229 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 230 if (r) 231 return r; 232 233 ib = &job->ibs[0]; 234 addr = amdgpu_bo_gpu_offset(bo); 235 236 ib->length_dw = 0; 237 ib->ptr[ib->length_dw++] = 0x00000018; 238 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 239 ib->ptr[ib->length_dw++] = handle; 240 ib->ptr[ib->length_dw++] = 0x00000000; 241 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 242 ib->ptr[ib->length_dw++] = addr; 243 244 ib->ptr[ib->length_dw++] = 0x00000014; 245 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 246 ib->ptr[ib->length_dw++] = 0x0000001c; 247 ib->ptr[ib->length_dw++] = 0x00000000; 248 ib->ptr[ib->length_dw++] = 0x00000000; 249 250 ib->ptr[ib->length_dw++] = 0x00000008; 251 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 252 253 for (i = ib->length_dw; i < ib_size_dw; ++i) 254 ib->ptr[i] = 0x0; 255 256 r = amdgpu_job_submit_direct(job, ring, &f); 257 if (r) 258 goto err; 259 260 if (fence) 261 *fence = dma_fence_get(f); 262 dma_fence_put(f); 263 return 0; 264 265err: 266 amdgpu_job_free(job); 267 return r; 268} 269 270/** 271 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 272 * 273 * @ring: ring we should submit the msg to 274 * @handle: session handle to use 275 * @bo: amdgpu object for which we query the offset 276 * @fence: optional fence to return 277 * 278 * Close up a stream for HW test or if userspace failed to do so 279 */ 280static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, 281 struct amdgpu_bo *bo, 282 struct dma_fence **fence) 283{ 284 const unsigned ib_size_dw = 16; 285 struct amdgpu_job *job; 286 struct amdgpu_ib *ib; 287 struct dma_fence *f = NULL; 288 uint64_t addr; 289 int i, r; 290 291 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 292 AMDGPU_IB_POOL_DIRECT, &job, 293 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 294 if (r) 295 return r; 296 297 ib = &job->ibs[0]; 298 addr = amdgpu_bo_gpu_offset(bo); 299 300 ib->length_dw = 0; 301 ib->ptr[ib->length_dw++] = 0x00000018; 302 ib->ptr[ib->length_dw++] = 0x00000001; 303 ib->ptr[ib->length_dw++] = handle; 304 ib->ptr[ib->length_dw++] = 0x00000000; 305 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 306 ib->ptr[ib->length_dw++] = addr; 307 308 ib->ptr[ib->length_dw++] = 0x00000014; 309 ib->ptr[ib->length_dw++] = 0x00000002; 310 ib->ptr[ib->length_dw++] = 0x0000001c; 311 ib->ptr[ib->length_dw++] = 0x00000000; 312 ib->ptr[ib->length_dw++] = 0x00000000; 313 314 ib->ptr[ib->length_dw++] = 0x00000008; 315 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 316 317 for (i = ib->length_dw; i < ib_size_dw; ++i) 318 ib->ptr[i] = 0x0; 319 320 r = amdgpu_job_submit_direct(job, ring, &f); 321 if (r) 322 goto err; 323 324 if (fence) 325 *fence = dma_fence_get(f); 326 dma_fence_put(f); 327 return 0; 328 329err: 330 amdgpu_job_free(job); 331 return r; 332} 333 334/** 335 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 336 * 337 * @ring: the engine to test on 338 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 339 * 340 */ 341static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 342{ 343 struct dma_fence *fence = NULL; 344 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo; 345 long r; 346 347 r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL); 348 if (r) 349 goto error; 350 351 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence); 352 if (r) 353 goto error; 354 355 r = dma_fence_wait_timeout(fence, false, timeout); 356 if (r == 0) 357 r = -ETIMEDOUT; 358 else if (r > 0) 359 r = 0; 360 361error: 362 dma_fence_put(fence); 363 return r; 364} 365 366static int uvd_v7_0_early_init(struct amdgpu_ip_block *ip_block) 367{ 368 struct amdgpu_device *adev = ip_block->adev; 369 370 if (adev->asic_type == CHIP_VEGA20) { 371 u32 harvest; 372 int i; 373 374 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 375 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 376 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 377 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 378 adev->uvd.harvest_config |= 1 << i; 379 } 380 } 381 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 382 AMDGPU_UVD_HARVEST_UVD1)) 383 /* both instances are harvested, disable the block */ 384 return -ENOENT; 385 } else { 386 adev->uvd.num_uvd_inst = 1; 387 } 388 389 if (amdgpu_sriov_vf(adev)) 390 adev->uvd.num_enc_rings = 1; 391 else 392 adev->uvd.num_enc_rings = 2; 393 uvd_v7_0_set_ring_funcs(adev); 394 uvd_v7_0_set_enc_ring_funcs(adev); 395 uvd_v7_0_set_irq_funcs(adev); 396 397 return 0; 398} 399 400static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 401{ 402 struct amdgpu_ring *ring; 403 404 int i, j, r; 405 struct amdgpu_device *adev = ip_block->adev; 406 407 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 408 if (adev->uvd.harvest_config & (1 << j)) 409 continue; 410 /* UVD TRAP */ 411 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 412 if (r) 413 return r; 414 415 /* UVD ENC TRAP */ 416 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 417 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 418 if (r) 419 return r; 420 } 421 } 422 423 r = amdgpu_uvd_sw_init(adev); 424 if (r) 425 return r; 426 427 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 428 const struct common_firmware_header *hdr; 429 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 430 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 431 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 432 adev->firmware.fw_size += 433 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 434 435 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 436 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 437 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 438 adev->firmware.fw_size += 439 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 440 } 441 DRM_INFO("PSP loading UVD firmware\n"); 442 } 443 444 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 445 if (adev->uvd.harvest_config & (1 << j)) 446 continue; 447 if (!amdgpu_sriov_vf(adev)) { 448 ring = &adev->uvd.inst[j].ring; 449 ring->vm_hub = AMDGPU_MMHUB0(0); 450 sprintf(ring->name, "uvd_%d", ring->me); 451 r = amdgpu_ring_init(adev, ring, 512, 452 &adev->uvd.inst[j].irq, 0, 453 AMDGPU_RING_PRIO_DEFAULT, NULL); 454 if (r) 455 return r; 456 } 457 458 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 459 ring = &adev->uvd.inst[j].ring_enc[i]; 460 ring->vm_hub = AMDGPU_MMHUB0(0); 461 sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i); 462 if (amdgpu_sriov_vf(adev)) { 463 ring->use_doorbell = true; 464 465 /* currently only use the first enconding ring for 466 * sriov, so set unused location for other unused rings. 467 */ 468 if (i == 0) 469 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2; 470 else 471 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1; 472 } 473 r = amdgpu_ring_init(adev, ring, 512, 474 &adev->uvd.inst[j].irq, 0, 475 AMDGPU_RING_PRIO_DEFAULT, NULL); 476 if (r) 477 return r; 478 } 479 } 480 481 r = amdgpu_uvd_resume(adev); 482 if (r) 483 return r; 484 485 r = amdgpu_virt_alloc_mm_table(adev); 486 if (r) 487 return r; 488 489 return r; 490} 491 492static int uvd_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 493{ 494 int i, j, r; 495 struct amdgpu_device *adev = ip_block->adev; 496 497 amdgpu_virt_free_mm_table(adev); 498 499 r = amdgpu_uvd_suspend(adev); 500 if (r) 501 return r; 502 503 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 504 if (adev->uvd.harvest_config & (1 << j)) 505 continue; 506 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 507 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 508 } 509 return amdgpu_uvd_sw_fini(adev); 510} 511 512/** 513 * uvd_v7_0_hw_init - start and test UVD block 514 * 515 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 516 * 517 * Initialize the hardware, boot up the VCPU and do some testing 518 */ 519static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 520{ 521 struct amdgpu_device *adev = ip_block->adev; 522 struct amdgpu_ring *ring; 523 uint32_t tmp; 524 int i, j, r; 525 526 if (amdgpu_sriov_vf(adev)) 527 r = uvd_v7_0_sriov_start(adev); 528 else 529 r = uvd_v7_0_start(adev); 530 if (r) 531 goto done; 532 533 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 534 if (adev->uvd.harvest_config & (1 << j)) 535 continue; 536 ring = &adev->uvd.inst[j].ring; 537 538 if (!amdgpu_sriov_vf(adev)) { 539 r = amdgpu_ring_test_helper(ring); 540 if (r) 541 goto done; 542 543 r = amdgpu_ring_alloc(ring, 10); 544 if (r) { 545 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 546 goto done; 547 } 548 549 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 550 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 551 amdgpu_ring_write(ring, tmp); 552 amdgpu_ring_write(ring, 0xFFFFF); 553 554 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 555 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 556 amdgpu_ring_write(ring, tmp); 557 amdgpu_ring_write(ring, 0xFFFFF); 558 559 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 560 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 561 amdgpu_ring_write(ring, tmp); 562 amdgpu_ring_write(ring, 0xFFFFF); 563 564 /* Clear timeout status bits */ 565 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 566 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 567 amdgpu_ring_write(ring, 0x8); 568 569 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 570 mmUVD_SEMA_CNTL), 0)); 571 amdgpu_ring_write(ring, 3); 572 573 amdgpu_ring_commit(ring); 574 } 575 576 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 577 ring = &adev->uvd.inst[j].ring_enc[i]; 578 r = amdgpu_ring_test_helper(ring); 579 if (r) 580 goto done; 581 } 582 } 583done: 584 if (!r) 585 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 586 587 return r; 588} 589 590/** 591 * uvd_v7_0_hw_fini - stop the hardware block 592 * 593 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 594 * 595 * Stop the UVD block, mark ring as not ready any more 596 */ 597static int uvd_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 598{ 599 struct amdgpu_device *adev = ip_block->adev; 600 601 cancel_delayed_work_sync(&adev->uvd.idle_work); 602 603 if (!amdgpu_sriov_vf(adev)) 604 uvd_v7_0_stop(adev); 605 else { 606 /* full access mode, so don't touch any UVD register */ 607 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 608 } 609 610 return 0; 611} 612 613static int uvd_v7_0_prepare_suspend(struct amdgpu_ip_block *ip_block) 614{ 615 struct amdgpu_device *adev = ip_block->adev; 616 617 return amdgpu_uvd_prepare_suspend(adev); 618} 619 620static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) 621{ 622 int r; 623 struct amdgpu_device *adev = ip_block->adev; 624 625 /* 626 * Proper cleanups before halting the HW engine: 627 * - cancel the delayed idle work 628 * - enable powergating 629 * - enable clockgating 630 * - disable dpm 631 * 632 * TODO: to align with the VCN implementation, move the 633 * jobs for clockgating/powergating/dpm setting to 634 * ->set_powergating_state(). 635 */ 636 cancel_delayed_work_sync(&adev->uvd.idle_work); 637 638 if (adev->pm.dpm_enabled) { 639 amdgpu_dpm_enable_uvd(adev, false); 640 } else { 641 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 642 /* shutdown the UVD block */ 643 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 644 AMD_PG_STATE_GATE); 645 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 646 AMD_CG_STATE_GATE); 647 } 648 649 r = uvd_v7_0_hw_fini(ip_block); 650 if (r) 651 return r; 652 653 return amdgpu_uvd_suspend(adev); 654} 655 656static int uvd_v7_0_resume(struct amdgpu_ip_block *ip_block) 657{ 658 int r; 659 660 r = amdgpu_uvd_resume(ip_block->adev); 661 if (r) 662 return r; 663 664 return uvd_v7_0_hw_init(ip_block); 665} 666 667/** 668 * uvd_v7_0_mc_resume - memory controller programming 669 * 670 * @adev: amdgpu_device pointer 671 * 672 * Let the UVD memory controller know it's offsets 673 */ 674static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 675{ 676 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 677 uint32_t offset; 678 int i; 679 680 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 681 if (adev->uvd.harvest_config & (1 << i)) 682 continue; 683 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 684 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 685 i == 0 ? 686 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo : 687 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 688 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 689 i == 0 ? 690 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi : 691 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 692 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 693 offset = 0; 694 } else { 695 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 696 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 697 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 698 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 699 offset = size; 700 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 701 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 702 } 703 704 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 705 706 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 707 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 708 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 709 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 710 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 711 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 712 713 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 714 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 715 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 716 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 717 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 718 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 719 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 720 721 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 722 adev->gfx.config.gb_addr_config); 723 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 724 adev->gfx.config.gb_addr_config); 725 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 726 adev->gfx.config.gb_addr_config); 727 728 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 729 } 730} 731 732static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 733 struct amdgpu_mm_table *table) 734{ 735 uint32_t data = 0, loop; 736 uint64_t addr = table->gpu_addr; 737 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 738 uint32_t size; 739 int i; 740 741 size = header->header_size + header->vce_table_size + header->uvd_table_size; 742 743 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 744 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 745 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 746 747 /* 2, update vmid of descriptor */ 748 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 749 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 750 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 751 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 752 753 /* 3, notify mmsch about the size of this descriptor */ 754 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 755 756 /* 4, set resp to zero */ 757 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 758 759 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 760 if (adev->uvd.harvest_config & (1 << i)) 761 continue; 762 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 763 *adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0; 764 adev->uvd.inst[i].ring_enc[0].wptr = 0; 765 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 766 } 767 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 768 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 769 770 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 771 loop = 1000; 772 while ((data & 0x10000002) != 0x10000002) { 773 udelay(10); 774 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 775 loop--; 776 if (!loop) 777 break; 778 } 779 780 if (!loop) { 781 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 782 return -EBUSY; 783 } 784 785 return 0; 786} 787 788static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 789{ 790 struct amdgpu_ring *ring; 791 uint32_t offset, size, tmp; 792 uint32_t table_size = 0; 793 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 794 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 795 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 796 struct mmsch_v1_0_cmd_end end = { {0} }; 797 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 798 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 799 uint8_t i = 0; 800 801 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 802 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 803 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 804 end.cmd_header.command_type = MMSCH_COMMAND__END; 805 806 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 807 header->version = MMSCH_VERSION; 808 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 809 810 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 811 header->uvd_table_offset = header->header_size; 812 else 813 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 814 815 init_table += header->uvd_table_offset; 816 817 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 818 if (adev->uvd.harvest_config & (1 << i)) 819 continue; 820 ring = &adev->uvd.inst[i].ring; 821 ring->wptr = 0; 822 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 823 824 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 825 0xFFFFFFFF, 0x00000004); 826 /* mc resume*/ 827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 828 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 829 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 830 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 832 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 833 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 835 offset = 0; 836 } else { 837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 838 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 840 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 841 offset = size; 842 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 843 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 844 845 } 846 847 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 848 849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 850 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 851 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 852 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 853 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 855 856 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 857 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 858 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 859 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 860 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 861 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 862 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 863 864 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 865 /* mc resume end*/ 866 867 /* disable clock gating */ 868 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 869 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 870 871 /* disable interupt */ 872 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 873 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 874 875 /* stall UMC and register bus before resetting VCPU */ 876 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 877 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 878 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 879 880 /* put LMI, VCPU, RBC etc... into reset */ 881 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 882 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 883 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 884 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 885 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 886 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 887 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 888 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 889 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 890 891 /* initialize UVD memory controller */ 892 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 893 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 894 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 895 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 896 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 897 UVD_LMI_CTRL__REQ_MODE_MASK | 898 0x00100000L)); 899 900 /* take all subblocks out of reset, except VCPU */ 901 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 902 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 903 904 /* enable VCPU clock */ 905 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 906 UVD_VCPU_CNTL__CLK_EN_MASK); 907 908 /* enable master interrupt */ 909 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 910 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 911 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 912 913 /* clear the bit 4 of UVD_STATUS */ 914 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 915 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 916 917 /* force RBC into idle state */ 918 size = order_base_2(ring->ring_size); 919 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 920 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 921 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 922 923 ring = &adev->uvd.inst[i].ring_enc[0]; 924 ring->wptr = 0; 925 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 926 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 927 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 928 929 /* boot up the VCPU */ 930 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 931 932 /* enable UMC */ 933 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 934 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 935 936 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 937 } 938 /* add end packet */ 939 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 940 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 941 header->uvd_table_size = table_size; 942 943 } 944 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 945} 946 947/** 948 * uvd_v7_0_start - start UVD block 949 * 950 * @adev: amdgpu_device pointer 951 * 952 * Setup and start the UVD block 953 */ 954static int uvd_v7_0_start(struct amdgpu_device *adev) 955{ 956 struct amdgpu_ring *ring; 957 uint32_t rb_bufsz, tmp; 958 uint32_t lmi_swap_cntl; 959 uint32_t mp_swap_cntl; 960 int i, j, k, r; 961 962 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 963 if (adev->uvd.harvest_config & (1 << k)) 964 continue; 965 /* disable DPG */ 966 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 967 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 968 } 969 970 /* disable byte swapping */ 971 lmi_swap_cntl = 0; 972 mp_swap_cntl = 0; 973 974 uvd_v7_0_mc_resume(adev); 975 976 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 977 if (adev->uvd.harvest_config & (1 << k)) 978 continue; 979 ring = &adev->uvd.inst[k].ring; 980 /* disable clock gating */ 981 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 982 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 983 984 /* disable interupt */ 985 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 986 ~UVD_MASTINT_EN__VCPU_EN_MASK); 987 988 /* stall UMC and register bus before resetting VCPU */ 989 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 990 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 991 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 992 mdelay(1); 993 994 /* put LMI, VCPU, RBC etc... into reset */ 995 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 996 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 997 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 998 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 999 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 1000 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 1001 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 1002 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 1003 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1004 mdelay(5); 1005 1006 /* initialize UVD memory controller */ 1007 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 1008 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1009 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1010 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1011 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1012 UVD_LMI_CTRL__REQ_MODE_MASK | 1013 0x00100000L); 1014 1015#ifdef __BIG_ENDIAN 1016 /* swap (8 in 32) RB and IB */ 1017 lmi_swap_cntl = 0xa; 1018 mp_swap_cntl = 0; 1019#endif 1020 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1021 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 1022 1023 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 1024 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 1025 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 1026 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1027 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1028 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1029 1030 /* take all subblocks out of reset, except VCPU */ 1031 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1032 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1033 mdelay(5); 1034 1035 /* enable VCPU clock */ 1036 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1037 UVD_VCPU_CNTL__CLK_EN_MASK); 1038 1039 /* enable UMC */ 1040 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1041 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1042 1043 /* boot up the VCPU */ 1044 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1045 mdelay(10); 1046 1047 for (i = 0; i < 10; ++i) { 1048 uint32_t status; 1049 1050 for (j = 0; j < 100; ++j) { 1051 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1052 if (status & 2) 1053 break; 1054 mdelay(10); 1055 } 1056 r = 0; 1057 if (status & 2) 1058 break; 1059 1060 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1061 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1062 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1063 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1064 mdelay(10); 1065 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1066 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1067 mdelay(10); 1068 r = -1; 1069 } 1070 1071 if (r) { 1072 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1073 return r; 1074 } 1075 /* enable master interrupt */ 1076 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1077 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1078 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1079 1080 /* clear the bit 4 of UVD_STATUS */ 1081 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1082 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1083 1084 /* force RBC into idle state */ 1085 rb_bufsz = order_base_2(ring->ring_size); 1086 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1087 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1088 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1089 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1090 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1091 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1092 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1093 1094 /* set the write pointer delay */ 1095 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1096 1097 /* set the wb address */ 1098 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1099 (upper_32_bits(ring->gpu_addr) >> 2)); 1100 1101 /* program the RB_BASE for ring buffer */ 1102 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1103 lower_32_bits(ring->gpu_addr)); 1104 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1105 upper_32_bits(ring->gpu_addr)); 1106 1107 /* Initialize the ring buffer's read and write pointers */ 1108 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1109 1110 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1111 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1112 lower_32_bits(ring->wptr)); 1113 1114 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1115 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1116 1117 ring = &adev->uvd.inst[k].ring_enc[0]; 1118 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1119 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1120 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1121 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1122 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1123 1124 ring = &adev->uvd.inst[k].ring_enc[1]; 1125 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1126 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1127 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1128 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1129 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1130 } 1131 return 0; 1132} 1133 1134/** 1135 * uvd_v7_0_stop - stop UVD block 1136 * 1137 * @adev: amdgpu_device pointer 1138 * 1139 * stop the UVD block 1140 */ 1141static void uvd_v7_0_stop(struct amdgpu_device *adev) 1142{ 1143 uint8_t i = 0; 1144 1145 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1146 if (adev->uvd.harvest_config & (1 << i)) 1147 continue; 1148 /* force RBC into idle state */ 1149 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1150 1151 /* Stall UMC and register bus before resetting VCPU */ 1152 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1153 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1154 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1155 mdelay(1); 1156 1157 /* put VCPU into reset */ 1158 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1159 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1160 mdelay(5); 1161 1162 /* disable VCPU clock */ 1163 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1164 1165 /* Unstall UMC and register bus */ 1166 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1167 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1168 } 1169} 1170 1171/** 1172 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1173 * 1174 * @ring: amdgpu_ring pointer 1175 * @addr: address 1176 * @seq: sequence number 1177 * @flags: fence related flags 1178 * 1179 * Write a fence and a trap command to the ring. 1180 */ 1181static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1182 unsigned flags) 1183{ 1184 struct amdgpu_device *adev = ring->adev; 1185 1186 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1187 1188 amdgpu_ring_write(ring, 1189 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1190 amdgpu_ring_write(ring, seq); 1191 amdgpu_ring_write(ring, 1192 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1193 amdgpu_ring_write(ring, addr & 0xffffffff); 1194 amdgpu_ring_write(ring, 1195 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1196 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1197 amdgpu_ring_write(ring, 1198 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1199 amdgpu_ring_write(ring, 0); 1200 1201 amdgpu_ring_write(ring, 1202 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1203 amdgpu_ring_write(ring, 0); 1204 amdgpu_ring_write(ring, 1205 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1206 amdgpu_ring_write(ring, 0); 1207 amdgpu_ring_write(ring, 1208 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1209 amdgpu_ring_write(ring, 2); 1210} 1211 1212/** 1213 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1214 * 1215 * @ring: amdgpu_ring pointer 1216 * @addr: address 1217 * @seq: sequence number 1218 * @flags: fence related flags 1219 * 1220 * Write enc a fence and a trap command to the ring. 1221 */ 1222static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1223 u64 seq, unsigned flags) 1224{ 1225 1226 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1227 1228 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1229 amdgpu_ring_write(ring, addr); 1230 amdgpu_ring_write(ring, upper_32_bits(addr)); 1231 amdgpu_ring_write(ring, seq); 1232 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1233} 1234 1235/** 1236 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1237 * 1238 * @ring: amdgpu_ring pointer 1239 */ 1240static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1241{ 1242 /* The firmware doesn't seem to like touching registers at this point. */ 1243} 1244 1245/** 1246 * uvd_v7_0_ring_test_ring - register write test 1247 * 1248 * @ring: amdgpu_ring pointer 1249 * 1250 * Test if we can successfully write to the context register 1251 */ 1252static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1253{ 1254 struct amdgpu_device *adev = ring->adev; 1255 uint32_t tmp = 0; 1256 unsigned i; 1257 int r; 1258 1259 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1260 r = amdgpu_ring_alloc(ring, 3); 1261 if (r) 1262 return r; 1263 1264 amdgpu_ring_write(ring, 1265 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1266 amdgpu_ring_write(ring, 0xDEADBEEF); 1267 amdgpu_ring_commit(ring); 1268 for (i = 0; i < adev->usec_timeout; i++) { 1269 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1270 if (tmp == 0xDEADBEEF) 1271 break; 1272 udelay(1); 1273 } 1274 1275 if (i >= adev->usec_timeout) 1276 r = -ETIMEDOUT; 1277 1278 return r; 1279} 1280 1281/** 1282 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1283 * 1284 * @p: the CS parser with the IBs 1285 * @job: which job this ib is in 1286 * @ib: which IB to patch 1287 * 1288 */ 1289static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1290 struct amdgpu_job *job, 1291 struct amdgpu_ib *ib) 1292{ 1293 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1294 unsigned i; 1295 1296 /* No patching necessary for the first instance */ 1297 if (!ring->me) 1298 return 0; 1299 1300 for (i = 0; i < ib->length_dw; i += 2) { 1301 uint32_t reg = amdgpu_ib_get_value(ib, i); 1302 1303 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1304 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1305 1306 amdgpu_ib_set_value(ib, i, reg); 1307 } 1308 return 0; 1309} 1310 1311/** 1312 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1313 * 1314 * @ring: amdgpu_ring pointer 1315 * @job: job to retrieve vmid from 1316 * @ib: indirect buffer to execute 1317 * @flags: unused 1318 * 1319 * Write ring commands to execute the indirect buffer 1320 */ 1321static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1322 struct amdgpu_job *job, 1323 struct amdgpu_ib *ib, 1324 uint32_t flags) 1325{ 1326 struct amdgpu_device *adev = ring->adev; 1327 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1328 1329 amdgpu_ring_write(ring, 1330 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1331 amdgpu_ring_write(ring, vmid); 1332 1333 amdgpu_ring_write(ring, 1334 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1335 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1336 amdgpu_ring_write(ring, 1337 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1338 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1339 amdgpu_ring_write(ring, 1340 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1341 amdgpu_ring_write(ring, ib->length_dw); 1342} 1343 1344/** 1345 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1346 * 1347 * @ring: amdgpu_ring pointer 1348 * @job: job to retrive vmid from 1349 * @ib: indirect buffer to execute 1350 * @flags: unused 1351 * 1352 * Write enc ring commands to execute the indirect buffer 1353 */ 1354static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1355 struct amdgpu_job *job, 1356 struct amdgpu_ib *ib, 1357 uint32_t flags) 1358{ 1359 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1360 1361 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1362 amdgpu_ring_write(ring, vmid); 1363 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1364 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1365 amdgpu_ring_write(ring, ib->length_dw); 1366} 1367 1368static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1369 uint32_t reg, uint32_t val) 1370{ 1371 struct amdgpu_device *adev = ring->adev; 1372 1373 amdgpu_ring_write(ring, 1374 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1375 amdgpu_ring_write(ring, reg << 2); 1376 amdgpu_ring_write(ring, 1377 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1378 amdgpu_ring_write(ring, val); 1379 amdgpu_ring_write(ring, 1380 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1381 amdgpu_ring_write(ring, 8); 1382} 1383 1384static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1385 uint32_t val, uint32_t mask) 1386{ 1387 struct amdgpu_device *adev = ring->adev; 1388 1389 amdgpu_ring_write(ring, 1390 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1391 amdgpu_ring_write(ring, reg << 2); 1392 amdgpu_ring_write(ring, 1393 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1394 amdgpu_ring_write(ring, val); 1395 amdgpu_ring_write(ring, 1396 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1397 amdgpu_ring_write(ring, mask); 1398 amdgpu_ring_write(ring, 1399 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1400 amdgpu_ring_write(ring, 12); 1401} 1402 1403static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1404 unsigned vmid, uint64_t pd_addr) 1405{ 1406 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1407 uint32_t data0, data1, mask; 1408 1409 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1410 1411 /* wait for reg writes */ 1412 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1413 data1 = lower_32_bits(pd_addr); 1414 mask = 0xffffffff; 1415 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1416} 1417 1418static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1419{ 1420 struct amdgpu_device *adev = ring->adev; 1421 int i; 1422 1423 WARN_ON(ring->wptr % 2 || count % 2); 1424 1425 for (i = 0; i < count / 2; i++) { 1426 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1427 amdgpu_ring_write(ring, 0); 1428 } 1429} 1430 1431static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1432{ 1433 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1434} 1435 1436static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1437 uint32_t reg, uint32_t val, 1438 uint32_t mask) 1439{ 1440 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1441 amdgpu_ring_write(ring, reg << 2); 1442 amdgpu_ring_write(ring, mask); 1443 amdgpu_ring_write(ring, val); 1444} 1445 1446static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1447 unsigned int vmid, uint64_t pd_addr) 1448{ 1449 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1450 1451 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1452 1453 /* wait for reg writes */ 1454 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1455 vmid * hub->ctx_addr_distance, 1456 lower_32_bits(pd_addr), 0xffffffff); 1457} 1458 1459static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1460 uint32_t reg, uint32_t val) 1461{ 1462 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1463 amdgpu_ring_write(ring, reg << 2); 1464 amdgpu_ring_write(ring, val); 1465} 1466 1467static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 unsigned type, 1470 enum amdgpu_interrupt_state state) 1471{ 1472 // TODO 1473 return 0; 1474} 1475 1476static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1477 struct amdgpu_irq_src *source, 1478 struct amdgpu_iv_entry *entry) 1479{ 1480 uint32_t ip_instance; 1481 1482 switch (entry->client_id) { 1483 case SOC15_IH_CLIENTID_UVD: 1484 ip_instance = 0; 1485 break; 1486 case SOC15_IH_CLIENTID_UVD1: 1487 ip_instance = 1; 1488 break; 1489 default: 1490 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1491 return 0; 1492 } 1493 1494 DRM_DEBUG("IH: UVD TRAP\n"); 1495 1496 switch (entry->src_id) { 1497 case 124: 1498 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1499 break; 1500 case 119: 1501 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1502 break; 1503 case 120: 1504 if (!amdgpu_sriov_vf(adev)) 1505 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1506 break; 1507 default: 1508 DRM_ERROR("Unhandled interrupt: %d %d\n", 1509 entry->src_id, entry->src_data[0]); 1510 break; 1511 } 1512 1513 return 0; 1514} 1515 1516static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1517 enum amd_clockgating_state state) 1518{ 1519 /* needed for driver unload*/ 1520 return 0; 1521} 1522 1523const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1524 .name = "uvd_v7_0", 1525 .early_init = uvd_v7_0_early_init, 1526 .sw_init = uvd_v7_0_sw_init, 1527 .sw_fini = uvd_v7_0_sw_fini, 1528 .hw_init = uvd_v7_0_hw_init, 1529 .hw_fini = uvd_v7_0_hw_fini, 1530 .prepare_suspend = uvd_v7_0_prepare_suspend, 1531 .suspend = uvd_v7_0_suspend, 1532 .resume = uvd_v7_0_resume, 1533 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1534 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1535}; 1536 1537static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1538 .type = AMDGPU_RING_TYPE_UVD, 1539 .align_mask = 0xf, 1540 .support_64bit_ptrs = false, 1541 .no_user_fence = true, 1542 .get_rptr = uvd_v7_0_ring_get_rptr, 1543 .get_wptr = uvd_v7_0_ring_get_wptr, 1544 .set_wptr = uvd_v7_0_ring_set_wptr, 1545 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1546 .emit_frame_size = 1547 6 + /* hdp invalidate */ 1548 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1549 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1550 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1551 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1552 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1553 .emit_ib = uvd_v7_0_ring_emit_ib, 1554 .emit_fence = uvd_v7_0_ring_emit_fence, 1555 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1556 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1557 .test_ring = uvd_v7_0_ring_test_ring, 1558 .test_ib = amdgpu_uvd_ring_test_ib, 1559 .insert_nop = uvd_v7_0_ring_insert_nop, 1560 .pad_ib = amdgpu_ring_generic_pad_ib, 1561 .begin_use = amdgpu_uvd_ring_begin_use, 1562 .end_use = amdgpu_uvd_ring_end_use, 1563 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1564 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1565 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1566}; 1567 1568static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1569 .type = AMDGPU_RING_TYPE_UVD_ENC, 1570 .align_mask = 0x3f, 1571 .nop = HEVC_ENC_CMD_NO_OP, 1572 .support_64bit_ptrs = false, 1573 .no_user_fence = true, 1574 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1575 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1576 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1577 .emit_frame_size = 1578 3 + 3 + /* hdp flush / invalidate */ 1579 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1580 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1581 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1582 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1583 1, /* uvd_v7_0_enc_ring_insert_end */ 1584 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1585 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1586 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1587 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1588 .test_ring = uvd_v7_0_enc_ring_test_ring, 1589 .test_ib = uvd_v7_0_enc_ring_test_ib, 1590 .insert_nop = amdgpu_ring_insert_nop, 1591 .insert_end = uvd_v7_0_enc_ring_insert_end, 1592 .pad_ib = amdgpu_ring_generic_pad_ib, 1593 .begin_use = amdgpu_uvd_ring_begin_use, 1594 .end_use = amdgpu_uvd_ring_end_use, 1595 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1596 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1597 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1598}; 1599 1600static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1601{ 1602 int i; 1603 1604 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1605 if (adev->uvd.harvest_config & (1 << i)) 1606 continue; 1607 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1608 adev->uvd.inst[i].ring.me = i; 1609 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1610 } 1611} 1612 1613static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1614{ 1615 int i, j; 1616 1617 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1618 if (adev->uvd.harvest_config & (1 << j)) 1619 continue; 1620 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1621 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1622 adev->uvd.inst[j].ring_enc[i].me = j; 1623 } 1624 1625 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1626 } 1627} 1628 1629static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1630 .set = uvd_v7_0_set_interrupt_state, 1631 .process = uvd_v7_0_process_interrupt, 1632}; 1633 1634static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1635{ 1636 int i; 1637 1638 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1639 if (adev->uvd.harvest_config & (1 << i)) 1640 continue; 1641 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1642 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1643 } 1644} 1645 1646const struct amdgpu_ip_block_version uvd_v7_0_ip_block = { 1647 .type = AMD_IP_BLOCK_TYPE_UVD, 1648 .major = 7, 1649 .minor = 0, 1650 .rev = 0, 1651 .funcs = &uvd_v7_0_ip_funcs, 1652};
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