soc24.c

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#include <linux/firmware.h>
 24#include <linux/slab.h>
 25#include <linux/module.h>
 26#include <linux/pci.h>
 27
 28#include "amdgpu.h"
 29#include "amdgpu_ih.h"
 30#include "amdgpu_uvd.h"
 31#include "amdgpu_vce.h"
 32#include "amdgpu_ucode.h"
 33#include "amdgpu_psp.h"
 34#include "amdgpu_smu.h"
 35#include "atom.h"
 36#include "amd_pcie.h"
 37
 38#include "gc/gc_12_0_0_offset.h"
 39#include "gc/gc_12_0_0_sh_mask.h"
 40#include "mp/mp_14_0_2_offset.h"
 41
 42#include "soc15.h"
 43#include "soc15_common.h"
 44#include "soc24.h"
 45#include "mxgpu_nv.h"
 46
 47static const struct amd_ip_funcs soc24_common_ip_funcs;
 48
 49static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {
 50	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 51	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
 52	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 53};
 54
 55static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_encode_vcn0 = {
 56	.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0),
 57	.codec_array = vcn_5_0_0_video_codecs_encode_array_vcn0,
 58};
 59
 60static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_decode_array_vcn0[] = {
 61	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 62	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 63	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 64	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 65	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 66};
 67
 68static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_decode_vcn0 = {
 69	.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0),
 70	.codec_array = vcn_5_0_0_video_codecs_decode_array_vcn0,
 71};
 72
 73static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode,
 74				 const struct amdgpu_video_codecs **codecs)
 75{
 76	if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 77		return -EINVAL;
 78
 79	switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
 80	case IP_VERSION(5, 0, 0):
 81		if (encode)
 82			*codecs = &vcn_5_0_0_video_codecs_encode_vcn0;
 83		else
 84			*codecs = &vcn_5_0_0_video_codecs_decode_vcn0;
 85		return 0;
 86	default:
 87		return -EINVAL;
 88	}
 89}
 90
 91static u32 soc24_get_config_memsize(struct amdgpu_device *adev)
 92{
 93	return adev->nbio.funcs->get_memsize(adev);
 94}
 95
 96static u32 soc24_get_xclk(struct amdgpu_device *adev)
 97{
 98	return adev->clock.spll.reference_freq;
 99}
100
101void soc24_grbm_select(struct amdgpu_device *adev,
102		       u32 me, u32 pipe, u32 queue, u32 vmid)
103{
104	u32 grbm_gfx_cntl = 0;
105	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
106	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
107	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
108	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
109
110	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
111}
112
113static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {
114	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
115	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
116	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
117	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
118	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
119	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
120	{ SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
121	{ SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
122	{ SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
123	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
124	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
125	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
126	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
127	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
128	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
129	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
130	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
131	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
132	{ SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
133};
134
135static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,
136					    u32 se_num,
137					    u32 sh_num,
138					    u32 reg_offset)
139{
140	uint32_t val;
141
142	mutex_lock(&adev->grbm_idx_mutex);
143	if (se_num != 0xffffffff || sh_num != 0xffffffff)
144		amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
145
146	val = RREG32(reg_offset);
147
148	if (se_num != 0xffffffff || sh_num != 0xffffffff)
149		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
150	mutex_unlock(&adev->grbm_idx_mutex);
151	return val;
152}
153
154static uint32_t soc24_get_register_value(struct amdgpu_device *adev,
155					 bool indexed, u32 se_num,
156					 u32 sh_num, u32 reg_offset)
157{
158	if (indexed) {
159		return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);
160	} else {
161		if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&
162		    adev->gfx.config.gb_addr_config)
163			return adev->gfx.config.gb_addr_config;
164		return RREG32(reg_offset);
165	}
166}
167
168static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,
169			       u32 sh_num, u32 reg_offset, u32 *value)
170{
171	uint32_t i;
172	struct soc15_allowed_register_entry  *en;
173
174	*value = 0;
175	for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) {
176		en = &soc24_allowed_read_registers[i];
177		if (!adev->reg_offset[en->hwip][en->inst])
178			continue;
179		else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
180					+ en->reg_offset))
181			continue;
182
183		*value = soc24_get_register_value(adev,
184				soc24_allowed_read_registers[i].grbm_indexed,
185				se_num, sh_num, reg_offset);
186		return 0;
187	}
188	return -EINVAL;
189}
190
191static enum amd_reset_method
192soc24_asic_reset_method(struct amdgpu_device *adev)
193{
194	if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
195	    amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
196	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)
197		return amdgpu_reset_method;
198
199	if (amdgpu_reset_method != -1)
200		dev_warn(adev->dev,
201			 "Specified reset method:%d isn't supported, using AUTO instead.\n",
202			 amdgpu_reset_method);
203
204	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
205	case IP_VERSION(14, 0, 2):
206	case IP_VERSION(14, 0, 3):
207		return AMD_RESET_METHOD_MODE1;
208	default:
209		if (amdgpu_dpm_is_baco_supported(adev))
210			return AMD_RESET_METHOD_BACO;
211		else
212			return AMD_RESET_METHOD_MODE1;
213	}
214}
215
216static int soc24_asic_reset(struct amdgpu_device *adev)
217{
218	int ret = 0;
219
220	switch (soc24_asic_reset_method(adev)) {
221	case AMD_RESET_METHOD_PCI:
222		dev_info(adev->dev, "PCI reset\n");
223		ret = amdgpu_device_pci_reset(adev);
224		break;
225	case AMD_RESET_METHOD_BACO:
226		dev_info(adev->dev, "BACO reset\n");
227		ret = amdgpu_dpm_baco_reset(adev);
228		break;
229	case AMD_RESET_METHOD_MODE2:
230		dev_info(adev->dev, "MODE2 reset\n");
231		ret = amdgpu_dpm_mode2_reset(adev);
232		break;
233	default:
234		dev_info(adev->dev, "MODE1 reset\n");
235		ret = amdgpu_device_mode1_reset(adev);
236		break;
237	}
238
239	return ret;
240}
241
242static void soc24_program_aspm(struct amdgpu_device *adev)
243{
244	if (!amdgpu_device_should_use_aspm(adev))
245		return;
246
247	if (!(adev->flags & AMD_IS_APU) &&
248	    (adev->nbio.funcs->program_aspm))
249		adev->nbio.funcs->program_aspm(adev);
250}
251
252const struct amdgpu_ip_block_version soc24_common_ip_block = {
253	.type = AMD_IP_BLOCK_TYPE_COMMON,
254	.major = 1,
255	.minor = 0,
256	.rev = 0,
257	.funcs = &soc24_common_ip_funcs,
258};
259
260static bool soc24_need_full_reset(struct amdgpu_device *adev)
261{
262	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
263	case IP_VERSION(12, 0, 0):
264	case IP_VERSION(12, 0, 1):
265	default:
266		return true;
267	}
268}
269
270static bool soc24_need_reset_on_init(struct amdgpu_device *adev)
271{
272	u32 sol_reg;
273
274	if (adev->flags & AMD_IS_APU)
275		return false;
276
277	/* Check sOS sign of life register to confirm sys driver and sOS
278	 * are already been loaded.
279	 */
280	sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
281	if (sol_reg)
282		return true;
283
284	return false;
285}
286
287static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev)
288{
289	/* TODO
290	 * dummy implement for pcie_replay_count sysfs interface
291	 * */
292	return 0;
293}
294
295static void soc24_init_doorbell_index(struct amdgpu_device *adev)
296{
297	adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
298	adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
299	adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
300	adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
301	adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
302	adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
303	adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
304	adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
305	adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
306	adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
307	adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
308	adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
309	adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
310	adev->doorbell_index.gfx_userqueue_start =
311		AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
312	adev->doorbell_index.gfx_userqueue_end =
313		AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
314	adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
315	adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
316	adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
317	adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
318	adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
319	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
320	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
321	adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
322	adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
323	adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
324	adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
325
326	adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
327	adev->doorbell_index.sdma_doorbell_range = 20;
328}
329
330static void soc24_pre_asic_init(struct amdgpu_device *adev)
331{
332}
333
334static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,
335					  bool enter)
336{
337	if (enter)
338		amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
339	else
340		amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
341
342	if (adev->gfx.funcs->update_perfmon_mgcg)
343		adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
344
345	return 0;
346}
347
348static const struct amdgpu_asic_funcs soc24_asic_funcs = {
349	.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
350	.read_register = &soc24_read_register,
351	.reset = &soc24_asic_reset,
352	.reset_method = &soc24_asic_reset_method,
353	.get_xclk = &soc24_get_xclk,
354	.get_config_memsize = &soc24_get_config_memsize,
355	.init_doorbell_index = &soc24_init_doorbell_index,
356	.need_full_reset = &soc24_need_full_reset,
357	.need_reset_on_init = &soc24_need_reset_on_init,
358	.get_pcie_replay_count = &soc24_get_pcie_replay_count,
359	.supports_baco = &amdgpu_dpm_is_baco_supported,
360	.pre_asic_init = &soc24_pre_asic_init,
361	.query_video_codecs = &soc24_query_video_codecs,
362	.update_umd_stable_pstate = &soc24_update_umd_stable_pstate,
363};
364
365static int soc24_common_early_init(struct amdgpu_ip_block *ip_block)
366{
367	struct amdgpu_device *adev = ip_block->adev;
368
369	adev->nbio.funcs->set_reg_remap(adev);
370	adev->smc_rreg = NULL;
371	adev->smc_wreg = NULL;
372	adev->pcie_rreg = &amdgpu_device_indirect_rreg;
373	adev->pcie_wreg = &amdgpu_device_indirect_wreg;
374	adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
375	adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
376	adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
377	adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
378	adev->uvd_ctx_rreg = NULL;
379	adev->uvd_ctx_wreg = NULL;
380	adev->didt_rreg = NULL;
381	adev->didt_wreg = NULL;
382
383	adev->asic_funcs = &soc24_asic_funcs;
384
385	adev->rev_id = amdgpu_device_get_rev_id(adev);
386	adev->external_rev_id = 0xff;
387
388	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
389	case IP_VERSION(12, 0, 0):
390		adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
391			AMD_CG_SUPPORT_GFX_CGLS |
392			AMD_CG_SUPPORT_GFX_MGCG |
393			AMD_CG_SUPPORT_GFX_3D_CGCG |
394			AMD_CG_SUPPORT_GFX_3D_CGLS |
395			AMD_CG_SUPPORT_REPEATER_FGCG |
396			AMD_CG_SUPPORT_GFX_FGCG |
397			AMD_CG_SUPPORT_GFX_PERF_CLK |
398			AMD_CG_SUPPORT_ATHUB_MGCG |
399			AMD_CG_SUPPORT_ATHUB_LS |
400			AMD_CG_SUPPORT_MC_MGCG |
401			AMD_CG_SUPPORT_HDP_SD |
402			AMD_CG_SUPPORT_MC_LS;
403		adev->pg_flags = AMD_PG_SUPPORT_VCN |
404			AMD_PG_SUPPORT_JPEG |
405			AMD_PG_SUPPORT_VCN_DPG;
406		adev->external_rev_id = adev->rev_id + 0x40;
407		break;
408	case IP_VERSION(12, 0, 1):
409		adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
410			AMD_CG_SUPPORT_GFX_CGLS |
411			AMD_CG_SUPPORT_GFX_MGCG |
412			AMD_CG_SUPPORT_GFX_3D_CGCG |
413			AMD_CG_SUPPORT_GFX_3D_CGLS |
414			AMD_CG_SUPPORT_REPEATER_FGCG |
415			AMD_CG_SUPPORT_GFX_FGCG |
416			AMD_CG_SUPPORT_GFX_PERF_CLK |
417			AMD_CG_SUPPORT_ATHUB_MGCG |
418			AMD_CG_SUPPORT_ATHUB_LS |
419			AMD_CG_SUPPORT_MC_MGCG |
420			AMD_CG_SUPPORT_HDP_SD |
421			AMD_CG_SUPPORT_MC_LS;
422
423		adev->pg_flags = AMD_PG_SUPPORT_VCN |
424			AMD_PG_SUPPORT_JPEG |
425			AMD_PG_SUPPORT_JPEG_DPG |
426			AMD_PG_SUPPORT_VCN_DPG;
427		adev->external_rev_id = adev->rev_id + 0x50;
428		break;
429	default:
430		/* FIXME: not supported yet */
431		return -EINVAL;
432	}
433
434	if (amdgpu_sriov_vf(adev)) {
435		amdgpu_virt_init_setting(adev);
436		xgpu_nv_mailbox_set_irq_funcs(adev);
437	}
438
439	return 0;
440}
441
442static int soc24_common_late_init(struct amdgpu_ip_block *ip_block)
443{
444	struct amdgpu_device *adev = ip_block->adev;
445
446	if (amdgpu_sriov_vf(adev)) {
447		xgpu_nv_mailbox_get_irq(adev);
448	} else {
449		if (adev->nbio.ras &&
450		    adev->nbio.ras_err_event_athub_irq.funcs)
451			/* don't need to fail gpu late init
452			 * if enabling athub_err_event interrupt failed
453			 * nbif v6_3_1 only support fatal error hanlding
454			 * just enable the interrupt directly
455			 */
456			amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
457	}
458
459	/* Enable selfring doorbell aperture late because doorbell BAR
460	 * aperture will change if resize BAR successfully in gmc sw_init.
461	 */
462	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
463
464	return 0;
465}
466
467static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block)
468{
469	struct amdgpu_device *adev = ip_block->adev;
470
471	if (amdgpu_sriov_vf(adev))
472		xgpu_nv_mailbox_add_irq_id(adev);
473
474	return 0;
475}
476
477static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block)
478{
479	struct amdgpu_device *adev = ip_block->adev;
480
481	/* enable aspm */
482	soc24_program_aspm(adev);
483	/* setup nbio registers */
484	adev->nbio.funcs->init_registers(adev);
485	/* remap HDP registers to a hole in mmio space,
486	 * for the purpose of expose those registers
487	 * to process space
488	 */
489	if (adev->nbio.funcs->remap_hdp_registers)
490		adev->nbio.funcs->remap_hdp_registers(adev);
491
492	if (adev->df.funcs->hw_init)
493		adev->df.funcs->hw_init(adev);
494
495	/* enable the doorbell aperture */
496	adev->nbio.funcs->enable_doorbell_aperture(adev, true);
497
498	return 0;
499}
500
501static int soc24_common_hw_fini(struct amdgpu_ip_block *ip_block)
502{
503	struct amdgpu_device *adev = ip_block->adev;
504
505	/* Disable the doorbell aperture and selfring doorbell aperture
506	 * separately in hw_fini because soc21_enable_doorbell_aperture
507	 * has been removed and there is no need to delay disabling
508	 * selfring doorbell.
509	 */
510	adev->nbio.funcs->enable_doorbell_aperture(adev, false);
511	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
512
513	if (amdgpu_sriov_vf(adev)) {
514		xgpu_nv_mailbox_put_irq(adev);
515	} else {
516		if (adev->nbio.ras &&
517		    adev->nbio.ras_err_event_athub_irq.funcs)
518			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
519	}
520
521	return 0;
522}
523
524static int soc24_common_suspend(struct amdgpu_ip_block *ip_block)
525{
526	return soc24_common_hw_fini(ip_block);
527}
528
529static int soc24_common_resume(struct amdgpu_ip_block *ip_block)
530{
531	return soc24_common_hw_init(ip_block);
532}
533
534static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
535{
536	return true;
537}
538
539static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
540					      enum amd_clockgating_state state)
541{
542	struct amdgpu_device *adev = ip_block->adev;
543
544	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
545	case IP_VERSION(6, 3, 1):
546		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
547				state == AMD_CG_STATE_GATE);
548		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
549				state == AMD_CG_STATE_GATE);
550		adev->hdp.funcs->update_clock_gating(adev,
551				state == AMD_CG_STATE_GATE);
552		break;
553	default:
554		break;
555	}
556	return 0;
557}
558
559static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
560					      enum amd_powergating_state state)
561{
562	struct amdgpu_device *adev = ip_block->adev;
563
564	switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
565	case IP_VERSION(7, 0, 0):
566	case IP_VERSION(7, 0, 1):
567		adev->lsdma.funcs->update_memory_power_gating(adev,
568				state == AMD_PG_STATE_GATE);
569		break;
570	default:
571		break;
572	}
573
574	return 0;
575}
576
577static void soc24_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
578{
579	struct amdgpu_device *adev = ip_block->adev;
580
581	adev->nbio.funcs->get_clockgating_state(adev, flags);
582
583	adev->hdp.funcs->get_clock_gating_state(adev, flags);
584
585	return;
586}
587
588static const struct amd_ip_funcs soc24_common_ip_funcs = {
589	.name = "soc24_common",
590	.early_init = soc24_common_early_init,
591	.late_init = soc24_common_late_init,
592	.sw_init = soc24_common_sw_init,
593	.hw_init = soc24_common_hw_init,
594	.hw_fini = soc24_common_hw_fini,
595	.suspend = soc24_common_suspend,
596	.resume = soc24_common_resume,
597	.is_idle = soc24_common_is_idle,
598	.set_clockgating_state = soc24_common_set_clockgating_state,
599	.set_powergating_state = soc24_common_set_powergating_state,
600	.get_clockgating_state = soc24_common_get_clockgating_state,
601};