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sdma_v6_0_0_pkt_open.h

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root linux-6.19.14 drivers gpu drm amd amdgpu sdma_v6_0_0_pkt_open.h
linux-6.19.14/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h C
   1/*
   2 * Copyright 2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __SDMA_V6_0_0_PKT_OPEN_H_
  24#define __SDMA_V6_0_0_PKT_OPEN_H_
  25
  26#define SDMA_OP_NOP  0
  27#define SDMA_OP_COPY  1
  28#define SDMA_OP_WRITE  2
  29#define SDMA_OP_INDIRECT  4
  30#define SDMA_OP_FENCE  5
  31#define SDMA_OP_TRAP  6
  32#define SDMA_OP_SEM  7
  33#define SDMA_OP_POLL_REGMEM  8
  34#define SDMA_OP_COND_EXE  9
  35#define SDMA_OP_ATOMIC  10
  36#define SDMA_OP_CONST_FILL  11
  37#define SDMA_OP_PTEPDE  12
  38#define SDMA_OP_TIMESTAMP  13
  39#define SDMA_OP_SRBM_WRITE  14
  40#define SDMA_OP_PRE_EXE  15
  41#define SDMA_OP_GPUVM_INV  16
  42#define SDMA_OP_GCR_REQ  17
  43#define SDMA_OP_DUMMY_TRAP  32
  44#define SDMA_SUBOP_TIMESTAMP_SET  0
  45#define SDMA_SUBOP_TIMESTAMP_GET  1
  46#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL  2
  47#define SDMA_SUBOP_COPY_LINEAR  0
  48#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND  4
  49#define SDMA_SUBOP_COPY_TILED  1
  50#define SDMA_SUBOP_COPY_TILED_SUB_WIND  5
  51#define SDMA_SUBOP_COPY_T2T_SUB_WIND  6
  52#define SDMA_SUBOP_COPY_SOA  3
  53#define SDMA_SUBOP_COPY_DIRTY_PAGE  7
  54#define SDMA_SUBOP_COPY_LINEAR_PHY  8
  55#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE  36
  56#define SDMA_SUBOP_COPY_LINEAR_BC  16
  57#define SDMA_SUBOP_COPY_TILED_BC  17
  58#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC  20
  59#define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC  21
  60#define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC  22
  61#define SDMA_SUBOP_WRITE_LINEAR  0
  62#define SDMA_SUBOP_WRITE_TILED  1
  63#define SDMA_SUBOP_WRITE_TILED_BC  17
  64#define SDMA_SUBOP_PTEPDE_GEN  0
  65#define SDMA_SUBOP_PTEPDE_COPY  1
  66#define SDMA_SUBOP_PTEPDE_RMW  2
  67#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS  3
  68#define SDMA_SUBOP_MEM_INCR  1
  69#define SDMA_SUBOP_DATA_FILL_MULTI  1
  70#define SDMA_SUBOP_POLL_REG_WRITE_MEM  1
  71#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM  2
  72#define SDMA_SUBOP_POLL_MEM_VERIFY  3
  73#define SDMA_SUBOP_VM_INVALIDATION  4
  74#define HEADER_AGENT_DISPATCH  4
  75#define HEADER_BARRIER  5
  76#define SDMA_OP_AQL_COPY  0
  77#define SDMA_OP_AQL_BARRIER_OR  0
  78
  79#define SDMA_GCR_RANGE_IS_PA		(1 << 18)
  80#define SDMA_GCR_SEQ(x)			(((x) & 0x3) << 16)
  81#define SDMA_GCR_GL2_WB			(1 << 15)
  82#define SDMA_GCR_GL2_INV		(1 << 14)
  83#define SDMA_GCR_GL2_DISCARD		(1 << 13)
  84#define SDMA_GCR_GL2_RANGE(x)		(((x) & 0x3) << 11)
  85#define SDMA_GCR_GL2_US			(1 << 10)
  86#define SDMA_GCR_GL1_INV		(1 << 9)
  87#define SDMA_GCR_GLV_INV		(1 << 8)
  88#define SDMA_GCR_GLK_INV		(1 << 7)
  89#define SDMA_GCR_GLK_WB			(1 << 6)
  90#define SDMA_GCR_GLM_INV		(1 << 5)
  91#define SDMA_GCR_GLM_WB			(1 << 4)
  92#define SDMA_GCR_GL1_RANGE(x)		(((x) & 0x3) << 2)
  93#define SDMA_GCR_GLI_INV(x)		(((x) & 0x3) << 0)
  94
  95#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f)
  96#define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9)
  97#define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16)
  98#define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18)
  99#define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24)
 100#define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26)
 101
 102/*
 103** Definitions for SDMA_PKT_COPY_LINEAR packet
 104*/
 105
 106/*define for HEADER word*/
 107/*define for op field*/
 108#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
 109#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask   0x000000FF
 110#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift  0
 111#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)
 112
 113/*define for sub_op field*/
 114#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
 115#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask   0x000000FF
 116#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift  8
 117#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)
 118
 119/*define for encrypt field*/
 120#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0
 121#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask   0x00000001
 122#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift  16
 123#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift)
 124
 125/*define for tmz field*/
 126#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0
 127#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask   0x00000001
 128#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift  18
 129#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift)
 130
 131/*define for cpv field*/
 132#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset 0
 133#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask   0x00000001
 134#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift  19
 135#define SDMA_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift)
 136
 137/*define for backwards field*/
 138#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0
 139#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask   0x00000001
 140#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift  25
 141#define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift)
 142
 143/*define for broadcast field*/
 144#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
 145#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask   0x00000001
 146#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift  27
 147#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)
 148
 149/*define for COUNT word*/
 150/*define for count field*/
 151#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1
 152#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask   0x3FFFFFFF
 153#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift  0
 154#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)
 155
 156/*define for PARAMETER word*/
 157/*define for dst_sw field*/
 158#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2
 159#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
 160#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift  16
 161#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
 162
 163/*define for dst_cache_policy field*/
 164#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 2
 165#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask   0x00000007
 166#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift  18
 167#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift)
 168
 169/*define for src_sw field*/
 170#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2
 171#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
 172#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift  24
 173#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
 174
 175/*define for src_cache_policy field*/
 176#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 2
 177#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask   0x00000007
 178#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift  26
 179#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift)
 180
 181/*define for SRC_ADDR_LO word*/
 182/*define for src_addr_31_0 field*/
 183#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
 184#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 185#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
 186#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
 187
 188/*define for SRC_ADDR_HI word*/
 189/*define for src_addr_63_32 field*/
 190#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
 191#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 192#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
 193#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
 194
 195/*define for DST_ADDR_LO word*/
 196/*define for dst_addr_31_0 field*/
 197#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
 198#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
 199#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
 200#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
 201
 202/*define for DST_ADDR_HI word*/
 203/*define for dst_addr_63_32 field*/
 204#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
 205#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
 206#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
 207#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
 208
 209
 210/*
 211** Definitions for SDMA_PKT_COPY_LINEAR_BC packet
 212*/
 213
 214/*define for HEADER word*/
 215/*define for op field*/
 216#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0
 217#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask   0x000000FF
 218#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift  0
 219#define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift)
 220
 221/*define for sub_op field*/
 222#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0
 223#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask   0x000000FF
 224#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift  8
 225#define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift)
 226
 227/*define for COUNT word*/
 228/*define for count field*/
 229#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1
 230#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask   0x003FFFFF
 231#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift  0
 232#define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift)
 233
 234/*define for PARAMETER word*/
 235/*define for dst_sw field*/
 236#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2
 237#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask   0x00000003
 238#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift  16
 239#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift)
 240
 241/*define for dst_ha field*/
 242#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2
 243#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask   0x00000001
 244#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift  19
 245#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift)
 246
 247/*define for src_sw field*/
 248#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2
 249#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask   0x00000003
 250#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift  24
 251#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift)
 252
 253/*define for src_ha field*/
 254#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2
 255#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask   0x00000001
 256#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift  27
 257#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift)
 258
 259/*define for SRC_ADDR_LO word*/
 260/*define for src_addr_31_0 field*/
 261#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3
 262#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 263#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
 264#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift)
 265
 266/*define for SRC_ADDR_HI word*/
 267/*define for src_addr_63_32 field*/
 268#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4
 269#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 270#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
 271#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift)
 272
 273/*define for DST_ADDR_LO word*/
 274/*define for dst_addr_31_0 field*/
 275#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5
 276#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
 277#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
 278#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift)
 279
 280/*define for DST_ADDR_HI word*/
 281/*define for dst_addr_63_32 field*/
 282#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6
 283#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
 284#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
 285#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift)
 286
 287
 288/*
 289** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet
 290*/
 291
 292/*define for HEADER word*/
 293/*define for op field*/
 294#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0
 295#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask   0x000000FF
 296#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift  0
 297#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift)
 298
 299/*define for sub_op field*/
 300#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0
 301#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask   0x000000FF
 302#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift  8
 303#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift)
 304
 305/*define for tmz field*/
 306#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0
 307#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask   0x00000001
 308#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift  18
 309#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift)
 310
 311/*define for cpv field*/
 312#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset 0
 313#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask   0x00000001
 314#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift  19
 315#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift)
 316
 317/*define for all field*/
 318#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0
 319#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask   0x00000001
 320#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift  31
 321#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift)
 322
 323/*define for COUNT word*/
 324/*define for count field*/
 325#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1
 326#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask   0x003FFFFF
 327#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift  0
 328#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift)
 329
 330/*define for PARAMETER word*/
 331/*define for dst_mtype field*/
 332#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2
 333#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask   0x00000007
 334#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift  3
 335#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift)
 336
 337/*define for dst_l2_policy field*/
 338#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2
 339#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask   0x00000003
 340#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift  6
 341#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift)
 342
 343/*define for dst_llc field*/
 344#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset 2
 345#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask   0x00000001
 346#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift  8
 347#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift)
 348
 349/*define for src_mtype field*/
 350#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2
 351#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask   0x00000007
 352#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift  11
 353#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift)
 354
 355/*define for src_l2_policy field*/
 356#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2
 357#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask   0x00000003
 358#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift  14
 359#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift)
 360
 361/*define for src_llc field*/
 362#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset 2
 363#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask   0x00000001
 364#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift  16
 365#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift)
 366
 367/*define for dst_sw field*/
 368#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2
 369#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask   0x00000003
 370#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift  17
 371#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift)
 372
 373/*define for dst_gcc field*/
 374#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2
 375#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask   0x00000001
 376#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift  19
 377#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift)
 378
 379/*define for dst_sys field*/
 380#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2
 381#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask   0x00000001
 382#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift  20
 383#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift)
 384
 385/*define for dst_snoop field*/
 386#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2
 387#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask   0x00000001
 388#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift  22
 389#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift)
 390
 391/*define for dst_gpa field*/
 392#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2
 393#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask   0x00000001
 394#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift  23
 395#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift)
 396
 397/*define for src_sw field*/
 398#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2
 399#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask   0x00000003
 400#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift  24
 401#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift)
 402
 403/*define for src_sys field*/
 404#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2
 405#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask   0x00000001
 406#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift  28
 407#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift)
 408
 409/*define for src_snoop field*/
 410#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2
 411#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask   0x00000001
 412#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift  30
 413#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift)
 414
 415/*define for src_gpa field*/
 416#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2
 417#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask   0x00000001
 418#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift  31
 419#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift)
 420
 421/*define for SRC_ADDR_LO word*/
 422/*define for src_addr_31_0 field*/
 423#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3
 424#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 425#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift  0
 426#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift)
 427
 428/*define for SRC_ADDR_HI word*/
 429/*define for src_addr_63_32 field*/
 430#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4
 431#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 432#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift  0
 433#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift)
 434
 435/*define for DST_ADDR_LO word*/
 436/*define for dst_addr_31_0 field*/
 437#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5
 438#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
 439#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift  0
 440#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift)
 441
 442/*define for DST_ADDR_HI word*/
 443/*define for dst_addr_63_32 field*/
 444#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6
 445#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
 446#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift  0
 447#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift)
 448
 449
 450/*
 451** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet
 452*/
 453
 454/*define for HEADER word*/
 455/*define for op field*/
 456#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0
 457#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask   0x000000FF
 458#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift  0
 459#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift)
 460
 461/*define for sub_op field*/
 462#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0
 463#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask   0x000000FF
 464#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift  8
 465#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift)
 466
 467/*define for tmz field*/
 468#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0
 469#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask   0x00000001
 470#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift  18
 471#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift)
 472
 473/*define for cpv field*/
 474#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset 0
 475#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask   0x00000001
 476#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift  19
 477#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift)
 478
 479/*define for COUNT word*/
 480/*define for count field*/
 481#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1
 482#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask   0x003FFFFF
 483#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift  0
 484#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift)
 485
 486/*define for addr_pair_num field*/
 487#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset 1
 488#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask   0x000000FF
 489#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift  24
 490#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift)
 491
 492/*define for PARAMETER word*/
 493/*define for dst_mtype field*/
 494#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2
 495#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask   0x00000007
 496#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift  3
 497#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift)
 498
 499/*define for dst_l2_policy field*/
 500#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2
 501#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask   0x00000003
 502#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift  6
 503#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift)
 504
 505/*define for dst_llc field*/
 506#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset 2
 507#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask   0x00000001
 508#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift  8
 509#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift)
 510
 511/*define for src_mtype field*/
 512#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2
 513#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask   0x00000007
 514#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift  11
 515#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift)
 516
 517/*define for src_l2_policy field*/
 518#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2
 519#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask   0x00000003
 520#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift  14
 521#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift)
 522
 523/*define for src_llc field*/
 524#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset 2
 525#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask   0x00000001
 526#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift  16
 527#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift)
 528
 529/*define for dst_sw field*/
 530#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2
 531#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask   0x00000003
 532#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift  17
 533#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift)
 534
 535/*define for dst_gcc field*/
 536#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2
 537#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask   0x00000001
 538#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift  19
 539#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift)
 540
 541/*define for dst_sys field*/
 542#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2
 543#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask   0x00000001
 544#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift  20
 545#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift)
 546
 547/*define for dst_log field*/
 548#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2
 549#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask   0x00000001
 550#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift  21
 551#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift)
 552
 553/*define for dst_snoop field*/
 554#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2
 555#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask   0x00000001
 556#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift  22
 557#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift)
 558
 559/*define for dst_gpa field*/
 560#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2
 561#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask   0x00000001
 562#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift  23
 563#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift)
 564
 565/*define for src_sw field*/
 566#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2
 567#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask   0x00000003
 568#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift  24
 569#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift)
 570
 571/*define for src_gcc field*/
 572#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2
 573#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask   0x00000001
 574#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift  27
 575#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift)
 576
 577/*define for src_sys field*/
 578#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2
 579#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask   0x00000001
 580#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift  28
 581#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift)
 582
 583/*define for src_snoop field*/
 584#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2
 585#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask   0x00000001
 586#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift  30
 587#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift)
 588
 589/*define for src_gpa field*/
 590#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2
 591#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask   0x00000001
 592#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift  31
 593#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift)
 594
 595/*define for SRC_ADDR_LO word*/
 596/*define for src_addr_31_0 field*/
 597#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
 598#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 599#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
 600#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
 601
 602/*define for SRC_ADDR_HI word*/
 603/*define for src_addr_63_32 field*/
 604#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
 605#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 606#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
 607#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
 608
 609/*define for DST_ADDR_LO word*/
 610/*define for dst_addr_31_0 field*/
 611#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
 612#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
 613#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
 614#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
 615
 616/*define for DST_ADDR_HI word*/
 617/*define for dst_addr_63_32 field*/
 618#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
 619#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
 620#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
 621#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
 622
 623
 624/*
 625** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet
 626*/
 627
 628/*define for HEADER word*/
 629/*define for op field*/
 630#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
 631#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask   0x000000FF
 632#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift  0
 633#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)
 634
 635/*define for sub_op field*/
 636#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
 637#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask   0x000000FF
 638#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift  8
 639#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)
 640
 641/*define for encrypt field*/
 642#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0
 643#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask   0x00000001
 644#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift  16
 645#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift)
 646
 647/*define for tmz field*/
 648#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0
 649#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask   0x00000001
 650#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift  18
 651#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift)
 652
 653/*define for cpv field*/
 654#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset 0
 655#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask   0x00000001
 656#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift  19
 657#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift)
 658
 659/*define for broadcast field*/
 660#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
 661#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask   0x00000001
 662#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift  27
 663#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)
 664
 665/*define for COUNT word*/
 666/*define for count field*/
 667#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1
 668#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask   0x3FFFFFFF
 669#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift  0
 670#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)
 671
 672/*define for PARAMETER word*/
 673/*define for dst2_sw field*/
 674#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2
 675#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask   0x00000003
 676#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift  8
 677#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)
 678
 679/*define for dst2_cache_policy field*/
 680#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset 2
 681#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask   0x00000007
 682#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift  10
 683#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift)
 684
 685/*define for dst1_sw field*/
 686#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2
 687#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask   0x00000003
 688#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift  16
 689#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)
 690
 691/*define for dst1_cache_policy field*/
 692#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset 2
 693#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask   0x00000007
 694#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift  18
 695#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift)
 696
 697/*define for src_sw field*/
 698#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2
 699#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask   0x00000003
 700#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift  24
 701#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)
 702
 703/*define for src_cache_policy field*/
 704#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset 2
 705#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask   0x00000007
 706#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift  26
 707#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift)
 708
 709/*define for SRC_ADDR_LO word*/
 710/*define for src_addr_31_0 field*/
 711#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
 712#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 713#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
 714#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
 715
 716/*define for SRC_ADDR_HI word*/
 717/*define for src_addr_63_32 field*/
 718#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
 719#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 720#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
 721#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
 722
 723/*define for DST1_ADDR_LO word*/
 724/*define for dst1_addr_31_0 field*/
 725#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5
 726#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask   0xFFFFFFFF
 727#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift  0
 728#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)
 729
 730/*define for DST1_ADDR_HI word*/
 731/*define for dst1_addr_63_32 field*/
 732#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6
 733#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask   0xFFFFFFFF
 734#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift  0
 735#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)
 736
 737/*define for DST2_ADDR_LO word*/
 738/*define for dst2_addr_31_0 field*/
 739#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7
 740#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask   0xFFFFFFFF
 741#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift  0
 742#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)
 743
 744/*define for DST2_ADDR_HI word*/
 745/*define for dst2_addr_63_32 field*/
 746#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8
 747#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask   0xFFFFFFFF
 748#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift  0
 749#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)
 750
 751
 752/*
 753** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet
 754*/
 755
 756/*define for HEADER word*/
 757/*define for op field*/
 758#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
 759#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask   0x000000FF
 760#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift  0
 761#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)
 762
 763/*define for sub_op field*/
 764#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
 765#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask   0x000000FF
 766#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift  8
 767#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)
 768
 769/*define for tmz field*/
 770#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0
 771#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask   0x00000001
 772#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift  18
 773#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift)
 774
 775/*define for cpv field*/
 776#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset 0
 777#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask   0x00000001
 778#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift  19
 779#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift)
 780
 781/*define for elementsize field*/
 782#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
 783#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask   0x00000007
 784#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift  29
 785#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)
 786
 787/*define for SRC_ADDR_LO word*/
 788/*define for src_addr_31_0 field*/
 789#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1
 790#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 791#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift  0
 792#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)
 793
 794/*define for SRC_ADDR_HI word*/
 795/*define for src_addr_63_32 field*/
 796#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2
 797#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 798#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift  0
 799#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)
 800
 801/*define for DW_3 word*/
 802/*define for src_x field*/
 803#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3
 804#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask   0x00003FFF
 805#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift  0
 806#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)
 807
 808/*define for src_y field*/
 809#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3
 810#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask   0x00003FFF
 811#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift  16
 812#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)
 813
 814/*define for DW_4 word*/
 815/*define for src_z field*/
 816#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4
 817#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask   0x00001FFF
 818#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift  0
 819#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)
 820
 821/*define for src_pitch field*/
 822#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4
 823#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask   0x0007FFFF
 824#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift  13
 825#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)
 826
 827/*define for DW_5 word*/
 828/*define for src_slice_pitch field*/
 829#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5
 830#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask   0x0FFFFFFF
 831#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift  0
 832#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)
 833
 834/*define for DST_ADDR_LO word*/
 835/*define for dst_addr_31_0 field*/
 836#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6
 837#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
 838#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift  0
 839#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)
 840
 841/*define for DST_ADDR_HI word*/
 842/*define for dst_addr_63_32 field*/
 843#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7
 844#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
 845#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift  0
 846#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)
 847
 848/*define for DW_8 word*/
 849/*define for dst_x field*/
 850#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8
 851#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask   0x00003FFF
 852#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift  0
 853#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)
 854
 855/*define for dst_y field*/
 856#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8
 857#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask   0x00003FFF
 858#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift  16
 859#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)
 860
 861/*define for DW_9 word*/
 862/*define for dst_z field*/
 863#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9
 864#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask   0x00001FFF
 865#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift  0
 866#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)
 867
 868/*define for dst_pitch field*/
 869#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9
 870#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask   0x0007FFFF
 871#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift  13
 872#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)
 873
 874/*define for DW_10 word*/
 875/*define for dst_slice_pitch field*/
 876#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10
 877#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
 878#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift  0
 879#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)
 880
 881/*define for DW_11 word*/
 882/*define for rect_x field*/
 883#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11
 884#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask   0x00003FFF
 885#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift  0
 886#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)
 887
 888/*define for rect_y field*/
 889#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11
 890#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask   0x00003FFF
 891#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift  16
 892#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)
 893
 894/*define for DW_12 word*/
 895/*define for rect_z field*/
 896#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12
 897#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask   0x00001FFF
 898#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift  0
 899#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)
 900
 901/*define for dst_sw field*/
 902#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12
 903#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask   0x00000003
 904#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift  16
 905#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)
 906
 907/*define for dst_cache_policy field*/
 908#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset 12
 909#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask   0x00000007
 910#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift  18
 911#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift)
 912
 913/*define for src_sw field*/
 914#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12
 915#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask   0x00000003
 916#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift  24
 917#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)
 918
 919/*define for src_cache_policy field*/
 920#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset 12
 921#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask   0x00000007
 922#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift  26
 923#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift)
 924
 925
 926/*
 927** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE packet
 928*/
 929
 930/*define for HEADER word*/
 931/*define for op field*/
 932#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset 0
 933#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask   0x000000FF
 934#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift  0
 935#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift)
 936
 937/*define for sub_op field*/
 938#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset 0
 939#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask   0x000000FF
 940#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift  8
 941#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift)
 942
 943/*define for tmz field*/
 944#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset 0
 945#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask   0x00000001
 946#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift  18
 947#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift)
 948
 949/*define for cpv field*/
 950#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset 0
 951#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask   0x00000001
 952#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift  19
 953#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift)
 954
 955/*define for SRC_ADDR_LO word*/
 956/*define for src_addr_31_0 field*/
 957#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset 1
 958#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
 959#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift  0
 960#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift)
 961
 962/*define for SRC_ADDR_HI word*/
 963/*define for src_addr_63_32 field*/
 964#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset 2
 965#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
 966#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift  0
 967#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift)
 968
 969/*define for DW_3 word*/
 970/*define for src_x field*/
 971#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset 3
 972#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask   0xFFFFFFFF
 973#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift  0
 974#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift)
 975
 976/*define for DW_4 word*/
 977/*define for src_y field*/
 978#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset 4
 979#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask   0xFFFFFFFF
 980#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift  0
 981#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift)
 982
 983/*define for DW_5 word*/
 984/*define for src_z field*/
 985#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset 5
 986#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask   0xFFFFFFFF
 987#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift  0
 988#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift)
 989
 990/*define for DW_6 word*/
 991/*define for src_pitch field*/
 992#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset 6
 993#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask   0xFFFFFFFF
 994#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift  0
 995#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift)
 996
 997/*define for DW_7 word*/
 998/*define for src_slice_pitch_31_0 field*/
 999#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset 7
1000#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask   0xFFFFFFFF
1001#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift  0
1002#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift)
1003
1004/*define for DW_8 word*/
1005/*define for src_slice_pitch_47_32 field*/
1006#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset 8
1007#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask   0x0000FFFF
1008#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift  0
1009#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift)
1010
1011/*define for DST_ADDR_LO word*/
1012/*define for dst_addr_31_0 field*/
1013#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset 9
1014#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
1015#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift  0
1016#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift)
1017
1018/*define for DST_ADDR_HI word*/
1019/*define for dst_addr_63_32 field*/
1020#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset 10
1021#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
1022#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift  0
1023#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift)
1024
1025/*define for DW_11 word*/
1026/*define for dst_x field*/
1027#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset 11
1028#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask   0xFFFFFFFF
1029#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift  0
1030#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift)
1031
1032/*define for DW_12 word*/
1033/*define for dst_y field*/
1034#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset 12
1035#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask   0xFFFFFFFF
1036#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift  0
1037#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift)
1038
1039/*define for DW_13 word*/
1040/*define for dst_z field*/
1041#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset 13
1042#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask   0xFFFFFFFF
1043#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift  0
1044#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift)
1045
1046/*define for DW_14 word*/
1047/*define for dst_pitch field*/
1048#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset 14
1049#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask   0xFFFFFFFF
1050#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift  0
1051#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift)
1052
1053/*define for DW_15 word*/
1054/*define for dst_slice_pitch_31_0 field*/
1055#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset 15
1056#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask   0xFFFFFFFF
1057#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift  0
1058#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift)
1059
1060/*define for DW_16 word*/
1061/*define for dst_slice_pitch_47_32 field*/
1062#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset 16
1063#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask   0x0000FFFF
1064#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift  0
1065#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift)
1066
1067/*define for dst_sw field*/
1068#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset 16
1069#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask   0x00000003
1070#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift  16
1071#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift)
1072
1073/*define for dst_policy field*/
1074#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset 16
1075#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask   0x00000007
1076#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift  18
1077#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift)
1078
1079/*define for src_sw field*/
1080#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset 16
1081#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask   0x00000003
1082#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift  24
1083#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift)
1084
1085/*define for src_policy field*/
1086#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset 16
1087#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask   0x00000007
1088#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift  26
1089#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift)
1090
1091/*define for DW_17 word*/
1092/*define for rect_x field*/
1093#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset 17
1094#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask   0xFFFFFFFF
1095#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift  0
1096#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift)
1097
1098/*define for DW_18 word*/
1099/*define for rect_y field*/
1100#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset 18
1101#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask   0xFFFFFFFF
1102#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift  0
1103#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift)
1104
1105/*define for DW_19 word*/
1106/*define for rect_z field*/
1107#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset 19
1108#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask   0xFFFFFFFF
1109#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift  0
1110#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift)
1111
1112
1113/*
1114** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet
1115*/
1116
1117/*define for HEADER word*/
1118/*define for op field*/
1119#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0
1120#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask   0x000000FF
1121#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift  0
1122#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift)
1123
1124/*define for sub_op field*/
1125#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0
1126#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask   0x000000FF
1127#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift  8
1128#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift)
1129
1130/*define for elementsize field*/
1131#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0
1132#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask   0x00000007
1133#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift  29
1134#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift)
1135
1136/*define for SRC_ADDR_LO word*/
1137/*define for src_addr_31_0 field*/
1138#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1
1139#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
1140#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
1141#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift)
1142
1143/*define for SRC_ADDR_HI word*/
1144/*define for src_addr_63_32 field*/
1145#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2
1146#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
1147#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
1148#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift)
1149
1150/*define for DW_3 word*/
1151/*define for src_x field*/
1152#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3
1153#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask   0x00003FFF
1154#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift  0
1155#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift)
1156
1157/*define for src_y field*/
1158#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3
1159#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask   0x00003FFF
1160#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift  16
1161#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift)
1162
1163/*define for DW_4 word*/
1164/*define for src_z field*/
1165#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4
1166#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask   0x000007FF
1167#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift  0
1168#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift)
1169
1170/*define for src_pitch field*/
1171#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4
1172#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask   0x00003FFF
1173#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift  13
1174#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift)
1175
1176/*define for DW_5 word*/
1177/*define for src_slice_pitch field*/
1178#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5
1179#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask   0x0FFFFFFF
1180#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift  0
1181#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift)
1182
1183/*define for DST_ADDR_LO word*/
1184/*define for dst_addr_31_0 field*/
1185#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6
1186#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
1187#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
1188#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift)
1189
1190/*define for DST_ADDR_HI word*/
1191/*define for dst_addr_63_32 field*/
1192#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7
1193#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
1194#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
1195#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift)
1196
1197/*define for DW_8 word*/
1198/*define for dst_x field*/
1199#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8
1200#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask   0x00003FFF
1201#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift  0
1202#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift)
1203
1204/*define for dst_y field*/
1205#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8
1206#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask   0x00003FFF
1207#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift  16
1208#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift)
1209
1210/*define for DW_9 word*/
1211/*define for dst_z field*/
1212#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9
1213#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask   0x000007FF
1214#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift  0
1215#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift)
1216
1217/*define for dst_pitch field*/
1218#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9
1219#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask   0x00003FFF
1220#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift  13
1221#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift)
1222
1223/*define for DW_10 word*/
1224/*define for dst_slice_pitch field*/
1225#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10
1226#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
1227#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift  0
1228#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift)
1229
1230/*define for DW_11 word*/
1231/*define for rect_x field*/
1232#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11
1233#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask   0x00003FFF
1234#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift  0
1235#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift)
1236
1237/*define for rect_y field*/
1238#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11
1239#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask   0x00003FFF
1240#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift  16
1241#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift)
1242
1243/*define for DW_12 word*/
1244/*define for rect_z field*/
1245#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12
1246#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask   0x000007FF
1247#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift  0
1248#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift)
1249
1250/*define for dst_sw field*/
1251#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12
1252#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask   0x00000003
1253#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift  16
1254#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift)
1255
1256/*define for dst_ha field*/
1257#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12
1258#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask   0x00000001
1259#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift  19
1260#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift)
1261
1262/*define for src_sw field*/
1263#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12
1264#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask   0x00000003
1265#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift  24
1266#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift)
1267
1268/*define for src_ha field*/
1269#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12
1270#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask   0x00000001
1271#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift  27
1272#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift)
1273
1274
1275/*
1276** Definitions for SDMA_PKT_COPY_TILED packet
1277*/
1278
1279/*define for HEADER word*/
1280/*define for op field*/
1281#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
1282#define SDMA_PKT_COPY_TILED_HEADER_op_mask   0x000000FF
1283#define SDMA_PKT_COPY_TILED_HEADER_op_shift  0
1284#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)
1285
1286/*define for sub_op field*/
1287#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
1288#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask   0x000000FF
1289#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift  8
1290#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)
1291
1292/*define for encrypt field*/
1293#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0
1294#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask   0x00000001
1295#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift  16
1296#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift)
1297
1298/*define for tmz field*/
1299#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0
1300#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask   0x00000001
1301#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift  18
1302#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift)
1303
1304/*define for cpv field*/
1305#define SDMA_PKT_COPY_TILED_HEADER_cpv_offset 0
1306#define SDMA_PKT_COPY_TILED_HEADER_cpv_mask   0x00000001
1307#define SDMA_PKT_COPY_TILED_HEADER_cpv_shift  19
1308#define SDMA_PKT_COPY_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift)
1309
1310/*define for detile field*/
1311#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
1312#define SDMA_PKT_COPY_TILED_HEADER_detile_mask   0x00000001
1313#define SDMA_PKT_COPY_TILED_HEADER_detile_shift  31
1314#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)
1315
1316/*define for TILED_ADDR_LO word*/
1317/*define for tiled_addr_31_0 field*/
1318#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1
1319#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
1320#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift  0
1321#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)
1322
1323/*define for TILED_ADDR_HI word*/
1324/*define for tiled_addr_63_32 field*/
1325#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2
1326#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
1327#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift  0
1328#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)
1329
1330/*define for DW_3 word*/
1331/*define for width field*/
1332#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3
1333#define SDMA_PKT_COPY_TILED_DW_3_width_mask   0x00003FFF
1334#define SDMA_PKT_COPY_TILED_DW_3_width_shift  0
1335#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift)
1336
1337/*define for DW_4 word*/
1338/*define for height field*/
1339#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4
1340#define SDMA_PKT_COPY_TILED_DW_4_height_mask   0x00003FFF
1341#define SDMA_PKT_COPY_TILED_DW_4_height_shift  0
1342#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift)
1343
1344/*define for depth field*/
1345#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4
1346#define SDMA_PKT_COPY_TILED_DW_4_depth_mask   0x00001FFF
1347#define SDMA_PKT_COPY_TILED_DW_4_depth_shift  16
1348#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift)
1349
1350/*define for DW_5 word*/
1351/*define for element_size field*/
1352#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5
1353#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask   0x00000007
1354#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift  0
1355#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)
1356
1357/*define for swizzle_mode field*/
1358#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5
1359#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask   0x0000001F
1360#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift  3
1361#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift)
1362
1363/*define for dimension field*/
1364#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5
1365#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask   0x00000003
1366#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift  9
1367#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift)
1368
1369/*define for mip_max field*/
1370#define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5
1371#define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask   0x0000000F
1372#define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift  16
1373#define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift)
1374
1375/*define for DW_6 word*/
1376/*define for x field*/
1377#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6
1378#define SDMA_PKT_COPY_TILED_DW_6_x_mask   0x00003FFF
1379#define SDMA_PKT_COPY_TILED_DW_6_x_shift  0
1380#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)
1381
1382/*define for y field*/
1383#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6
1384#define SDMA_PKT_COPY_TILED_DW_6_y_mask   0x00003FFF
1385#define SDMA_PKT_COPY_TILED_DW_6_y_shift  16
1386#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)
1387
1388/*define for DW_7 word*/
1389/*define for z field*/
1390#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7
1391#define SDMA_PKT_COPY_TILED_DW_7_z_mask   0x00001FFF
1392#define SDMA_PKT_COPY_TILED_DW_7_z_shift  0
1393#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)
1394
1395/*define for linear_sw field*/
1396#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7
1397#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask   0x00000003
1398#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift  16
1399#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)
1400
1401/*define for linear_cache_policy field*/
1402#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset 7
1403#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask   0x00000007
1404#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift  18
1405#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift)
1406
1407/*define for tile_sw field*/
1408#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7
1409#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask   0x00000003
1410#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift  24
1411#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)
1412
1413/*define for tile_cache_policy field*/
1414#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset 7
1415#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask   0x00000007
1416#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift  26
1417#define SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift)
1418
1419/*define for LINEAR_ADDR_LO word*/
1420/*define for linear_addr_31_0 field*/
1421#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8
1422#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1423#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1424#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1425
1426/*define for LINEAR_ADDR_HI word*/
1427/*define for linear_addr_63_32 field*/
1428#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9
1429#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1430#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1431#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1432
1433/*define for LINEAR_PITCH word*/
1434/*define for linear_pitch field*/
1435#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10
1436#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1437#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift  0
1438#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)
1439
1440/*define for LINEAR_SLICE_PITCH word*/
1441/*define for linear_slice_pitch field*/
1442#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11
1443#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask   0xFFFFFFFF
1444#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift  0
1445#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)
1446
1447/*define for COUNT word*/
1448/*define for count field*/
1449#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12
1450#define SDMA_PKT_COPY_TILED_COUNT_count_mask   0x3FFFFFFF
1451#define SDMA_PKT_COPY_TILED_COUNT_count_shift  0
1452#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)
1453
1454
1455/*
1456** Definitions for SDMA_PKT_COPY_TILED_BC packet
1457*/
1458
1459/*define for HEADER word*/
1460/*define for op field*/
1461#define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0
1462#define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask   0x000000FF
1463#define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift  0
1464#define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift)
1465
1466/*define for sub_op field*/
1467#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0
1468#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask   0x000000FF
1469#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift  8
1470#define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift)
1471
1472/*define for detile field*/
1473#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0
1474#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask   0x00000001
1475#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift  31
1476#define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift)
1477
1478/*define for TILED_ADDR_LO word*/
1479/*define for tiled_addr_31_0 field*/
1480#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1
1481#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
1482#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift  0
1483#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift)
1484
1485/*define for TILED_ADDR_HI word*/
1486/*define for tiled_addr_63_32 field*/
1487#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2
1488#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
1489#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift  0
1490#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift)
1491
1492/*define for DW_3 word*/
1493/*define for width field*/
1494#define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3
1495#define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask   0x00003FFF
1496#define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift  0
1497#define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift)
1498
1499/*define for DW_4 word*/
1500/*define for height field*/
1501#define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4
1502#define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask   0x00003FFF
1503#define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift  0
1504#define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift)
1505
1506/*define for depth field*/
1507#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4
1508#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask   0x000007FF
1509#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift  16
1510#define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift)
1511
1512/*define for DW_5 word*/
1513/*define for element_size field*/
1514#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5
1515#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask   0x00000007
1516#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift  0
1517#define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift)
1518
1519/*define for array_mode field*/
1520#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5
1521#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask   0x0000000F
1522#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift  3
1523#define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift)
1524
1525/*define for mit_mode field*/
1526#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5
1527#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask   0x00000007
1528#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift  8
1529#define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift)
1530
1531/*define for tilesplit_size field*/
1532#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5
1533#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask   0x00000007
1534#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift  11
1535#define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift)
1536
1537/*define for bank_w field*/
1538#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5
1539#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask   0x00000003
1540#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift  15
1541#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift)
1542
1543/*define for bank_h field*/
1544#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5
1545#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask   0x00000003
1546#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift  18
1547#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift)
1548
1549/*define for num_bank field*/
1550#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5
1551#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask   0x00000003
1552#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift  21
1553#define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift)
1554
1555/*define for mat_aspt field*/
1556#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5
1557#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask   0x00000003
1558#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift  24
1559#define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift)
1560
1561/*define for pipe_config field*/
1562#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5
1563#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask   0x0000001F
1564#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift  26
1565#define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift)
1566
1567/*define for DW_6 word*/
1568/*define for x field*/
1569#define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6
1570#define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask   0x00003FFF
1571#define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift  0
1572#define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift)
1573
1574/*define for y field*/
1575#define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6
1576#define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask   0x00003FFF
1577#define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift  16
1578#define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift)
1579
1580/*define for DW_7 word*/
1581/*define for z field*/
1582#define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7
1583#define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask   0x000007FF
1584#define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift  0
1585#define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift)
1586
1587/*define for linear_sw field*/
1588#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7
1589#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask   0x00000003
1590#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift  16
1591#define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift)
1592
1593/*define for tile_sw field*/
1594#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7
1595#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask   0x00000003
1596#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift  24
1597#define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift)
1598
1599/*define for LINEAR_ADDR_LO word*/
1600/*define for linear_addr_31_0 field*/
1601#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8
1602#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1603#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1604#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1605
1606/*define for LINEAR_ADDR_HI word*/
1607/*define for linear_addr_63_32 field*/
1608#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9
1609#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1610#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1611#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1612
1613/*define for LINEAR_PITCH word*/
1614/*define for linear_pitch field*/
1615#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10
1616#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1617#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift  0
1618#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift)
1619
1620/*define for LINEAR_SLICE_PITCH word*/
1621/*define for linear_slice_pitch field*/
1622#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11
1623#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask   0xFFFFFFFF
1624#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift  0
1625#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)
1626
1627/*define for COUNT word*/
1628/*define for count field*/
1629#define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 12
1630#define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask   0x000FFFFF
1631#define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift  2
1632#define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift)
1633
1634
1635/*
1636** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet
1637*/
1638
1639/*define for HEADER word*/
1640/*define for op field*/
1641#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
1642#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask   0x000000FF
1643#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift  0
1644#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)
1645
1646/*define for sub_op field*/
1647#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
1648#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask   0x000000FF
1649#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift  8
1650#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)
1651
1652/*define for encrypt field*/
1653#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0
1654#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask   0x00000001
1655#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift  16
1656#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift)
1657
1658/*define for tmz field*/
1659#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0
1660#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask   0x00000001
1661#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift  18
1662#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift)
1663
1664/*define for cpv field*/
1665#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset 0
1666#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask   0x00000001
1667#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift  19
1668#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift)
1669
1670/*define for videocopy field*/
1671#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
1672#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask   0x00000001
1673#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift  26
1674#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)
1675
1676/*define for broadcast field*/
1677#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
1678#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask   0x00000001
1679#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift  27
1680#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)
1681
1682/*define for TILED_ADDR_LO_0 word*/
1683/*define for tiled_addr0_31_0 field*/
1684#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1
1685#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask   0xFFFFFFFF
1686#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift  0
1687#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)
1688
1689/*define for TILED_ADDR_HI_0 word*/
1690/*define for tiled_addr0_63_32 field*/
1691#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2
1692#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask   0xFFFFFFFF
1693#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift  0
1694#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)
1695
1696/*define for TILED_ADDR_LO_1 word*/
1697/*define for tiled_addr1_31_0 field*/
1698#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3
1699#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask   0xFFFFFFFF
1700#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift  0
1701#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)
1702
1703/*define for TILED_ADDR_HI_1 word*/
1704/*define for tiled_addr1_63_32 field*/
1705#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4
1706#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask   0xFFFFFFFF
1707#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift  0
1708#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)
1709
1710/*define for DW_5 word*/
1711/*define for width field*/
1712#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5
1713#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask   0x00003FFF
1714#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift  0
1715#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift)
1716
1717/*define for DW_6 word*/
1718/*define for height field*/
1719#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6
1720#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask   0x00003FFF
1721#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift  0
1722#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift)
1723
1724/*define for depth field*/
1725#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6
1726#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask   0x00001FFF
1727#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift  16
1728#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift)
1729
1730/*define for DW_7 word*/
1731/*define for element_size field*/
1732#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7
1733#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask   0x00000007
1734#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift  0
1735#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)
1736
1737/*define for swizzle_mode field*/
1738#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7
1739#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask   0x0000001F
1740#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift  3
1741#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift)
1742
1743/*define for dimension field*/
1744#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7
1745#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask   0x00000003
1746#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift  9
1747#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift)
1748
1749/*define for mip_max field*/
1750#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7
1751#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask   0x0000000F
1752#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift  16
1753#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift)
1754
1755/*define for DW_8 word*/
1756/*define for x field*/
1757#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8
1758#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask   0x00003FFF
1759#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift  0
1760#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)
1761
1762/*define for y field*/
1763#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8
1764#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask   0x00003FFF
1765#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift  16
1766#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)
1767
1768/*define for DW_9 word*/
1769/*define for z field*/
1770#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9
1771#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask   0x00001FFF
1772#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift  0
1773#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)
1774
1775/*define for DW_10 word*/
1776/*define for dst2_sw field*/
1777#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10
1778#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask   0x00000003
1779#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift  8
1780#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)
1781
1782/*define for dst2_cache_policy field*/
1783#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset 10
1784#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask   0x00000007
1785#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift  10
1786#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift)
1787
1788/*define for linear_sw field*/
1789#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10
1790#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask   0x00000003
1791#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift  16
1792#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)
1793
1794/*define for linear_cache_policy field*/
1795#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset 10
1796#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask   0x00000007
1797#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift  18
1798#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift)
1799
1800/*define for tile_sw field*/
1801#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10
1802#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask   0x00000003
1803#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift  24
1804#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)
1805
1806/*define for tile_cache_policy field*/
1807#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset 10
1808#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask   0x00000007
1809#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift  26
1810#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift)
1811
1812/*define for LINEAR_ADDR_LO word*/
1813/*define for linear_addr_31_0 field*/
1814#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11
1815#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1816#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1817#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)
1818
1819/*define for LINEAR_ADDR_HI word*/
1820/*define for linear_addr_63_32 field*/
1821#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12
1822#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1823#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1824#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)
1825
1826/*define for LINEAR_PITCH word*/
1827/*define for linear_pitch field*/
1828#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13
1829#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1830#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift  0
1831#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)
1832
1833/*define for LINEAR_SLICE_PITCH word*/
1834/*define for linear_slice_pitch field*/
1835#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14
1836#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask   0xFFFFFFFF
1837#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift  0
1838#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)
1839
1840/*define for COUNT word*/
1841/*define for count field*/
1842#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15
1843#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask   0x3FFFFFFF
1844#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift  0
1845#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)
1846
1847
1848/*
1849** Definitions for SDMA_PKT_COPY_T2T packet
1850*/
1851
1852/*define for HEADER word*/
1853/*define for op field*/
1854#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
1855#define SDMA_PKT_COPY_T2T_HEADER_op_mask   0x000000FF
1856#define SDMA_PKT_COPY_T2T_HEADER_op_shift  0
1857#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)
1858
1859/*define for sub_op field*/
1860#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
1861#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask   0x000000FF
1862#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift  8
1863#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)
1864
1865/*define for tmz field*/
1866#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0
1867#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask   0x00000001
1868#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift  18
1869#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift)
1870
1871/*define for dcc field*/
1872#define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0
1873#define SDMA_PKT_COPY_T2T_HEADER_dcc_mask   0x00000001
1874#define SDMA_PKT_COPY_T2T_HEADER_dcc_shift  19
1875#define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift)
1876
1877/*define for cpv field*/
1878#define SDMA_PKT_COPY_T2T_HEADER_cpv_offset 0
1879#define SDMA_PKT_COPY_T2T_HEADER_cpv_mask   0x00000001
1880#define SDMA_PKT_COPY_T2T_HEADER_cpv_shift  28
1881#define SDMA_PKT_COPY_T2T_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift)
1882
1883/*define for dcc_dir field*/
1884#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0
1885#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask   0x00000001
1886#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift  31
1887#define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift)
1888
1889/*define for SRC_ADDR_LO word*/
1890/*define for src_addr_31_0 field*/
1891#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1
1892#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
1893#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift  0
1894#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)
1895
1896/*define for SRC_ADDR_HI word*/
1897/*define for src_addr_63_32 field*/
1898#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2
1899#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
1900#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift  0
1901#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)
1902
1903/*define for DW_3 word*/
1904/*define for src_x field*/
1905#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3
1906#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask   0x00003FFF
1907#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift  0
1908#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)
1909
1910/*define for src_y field*/
1911#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3
1912#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask   0x00003FFF
1913#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift  16
1914#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)
1915
1916/*define for DW_4 word*/
1917/*define for src_z field*/
1918#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4
1919#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask   0x00001FFF
1920#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift  0
1921#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)
1922
1923/*define for src_width field*/
1924#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4
1925#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask   0x00003FFF
1926#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift  16
1927#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift)
1928
1929/*define for DW_5 word*/
1930/*define for src_height field*/
1931#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5
1932#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask   0x00003FFF
1933#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift  0
1934#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift)
1935
1936/*define for src_depth field*/
1937#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5
1938#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask   0x00001FFF
1939#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift  16
1940#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift)
1941
1942/*define for DW_6 word*/
1943/*define for src_element_size field*/
1944#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6
1945#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask   0x00000007
1946#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift  0
1947#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)
1948
1949/*define for src_swizzle_mode field*/
1950#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6
1951#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask   0x0000001F
1952#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift  3
1953#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift)
1954
1955/*define for src_dimension field*/
1956#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6
1957#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask   0x00000003
1958#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift  9
1959#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift)
1960
1961/*define for src_mip_max field*/
1962#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6
1963#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask   0x0000000F
1964#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift  16
1965#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift)
1966
1967/*define for src_mip_id field*/
1968#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6
1969#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask   0x0000000F
1970#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift  20
1971#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift)
1972
1973/*define for DST_ADDR_LO word*/
1974/*define for dst_addr_31_0 field*/
1975#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7
1976#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
1977#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift  0
1978#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)
1979
1980/*define for DST_ADDR_HI word*/
1981/*define for dst_addr_63_32 field*/
1982#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8
1983#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
1984#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift  0
1985#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)
1986
1987/*define for DW_9 word*/
1988/*define for dst_x field*/
1989#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9
1990#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask   0x00003FFF
1991#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift  0
1992#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)
1993
1994/*define for dst_y field*/
1995#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9
1996#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask   0x00003FFF
1997#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift  16
1998#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)
1999
2000/*define for DW_10 word*/
2001/*define for dst_z field*/
2002#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10
2003#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask   0x00001FFF
2004#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift  0
2005#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)
2006
2007/*define for dst_width field*/
2008#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10
2009#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask   0x00003FFF
2010#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift  16
2011#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift)
2012
2013/*define for DW_11 word*/
2014/*define for dst_height field*/
2015#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11
2016#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask   0x00003FFF
2017#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift  0
2018#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift)
2019
2020/*define for dst_depth field*/
2021#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11
2022#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask   0x00001FFF
2023#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift  16
2024#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift)
2025
2026/*define for DW_12 word*/
2027/*define for dst_element_size field*/
2028#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12
2029#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask   0x00000007
2030#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift  0
2031#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift)
2032
2033/*define for dst_swizzle_mode field*/
2034#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12
2035#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask   0x0000001F
2036#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift  3
2037#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift)
2038
2039/*define for dst_dimension field*/
2040#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12
2041#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask   0x00000003
2042#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift  9
2043#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift)
2044
2045/*define for dst_mip_max field*/
2046#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12
2047#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask   0x0000000F
2048#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift  16
2049#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift)
2050
2051/*define for dst_mip_id field*/
2052#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12
2053#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask   0x0000000F
2054#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift  20
2055#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift)
2056
2057/*define for DW_13 word*/
2058/*define for rect_x field*/
2059#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13
2060#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask   0x00003FFF
2061#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift  0
2062#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)
2063
2064/*define for rect_y field*/
2065#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13
2066#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask   0x00003FFF
2067#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift  16
2068#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)
2069
2070/*define for DW_14 word*/
2071/*define for rect_z field*/
2072#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14
2073#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask   0x00001FFF
2074#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift  0
2075#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)
2076
2077/*define for dst_sw field*/
2078#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14
2079#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask   0x00000003
2080#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift  16
2081#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)
2082
2083/*define for dst_cache_policy field*/
2084#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset 14
2085#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask   0x00000007
2086#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift  18
2087#define SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift)
2088
2089/*define for src_sw field*/
2090#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14
2091#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask   0x00000003
2092#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift  24
2093#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)
2094
2095/*define for src_cache_policy field*/
2096#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset 14
2097#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask   0x00000007
2098#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift  26
2099#define SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift)
2100
2101/*define for META_ADDR_LO word*/
2102/*define for meta_addr_31_0 field*/
2103#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15
2104#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask   0xFFFFFFFF
2105#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift  0
2106#define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift)
2107
2108/*define for META_ADDR_HI word*/
2109/*define for meta_addr_63_32 field*/
2110#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16
2111#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask   0xFFFFFFFF
2112#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift  0
2113#define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift)
2114
2115/*define for META_CONFIG word*/
2116/*define for data_format field*/
2117#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17
2118#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask   0x0000007F
2119#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift  0
2120#define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift)
2121
2122/*define for color_transform_disable field*/
2123#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17
2124#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask   0x00000001
2125#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift  7
2126#define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift)
2127
2128/*define for alpha_is_on_msb field*/
2129#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17
2130#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask   0x00000001
2131#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift  8
2132#define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift)
2133
2134/*define for number_type field*/
2135#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17
2136#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask   0x00000007
2137#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift  9
2138#define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift)
2139
2140/*define for surface_type field*/
2141#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17
2142#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask   0x00000003
2143#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift  12
2144#define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift)
2145
2146/*define for meta_llc field*/
2147#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset 17
2148#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask   0x00000001
2149#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift  14
2150#define SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift)
2151
2152/*define for max_comp_block_size field*/
2153#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17
2154#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask   0x00000003
2155#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift  24
2156#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift)
2157
2158/*define for max_uncomp_block_size field*/
2159#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17
2160#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask   0x00000003
2161#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift  26
2162#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift)
2163
2164/*define for write_compress_enable field*/
2165#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17
2166#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask   0x00000001
2167#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift  28
2168#define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift)
2169
2170/*define for meta_tmz field*/
2171#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17
2172#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask   0x00000001
2173#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift  29
2174#define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift)
2175
2176/*define for pipe_aligned field*/
2177#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset 17
2178#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask   0x00000001
2179#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift  31
2180#define SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift)
2181
2182
2183/*
2184** Definitions for SDMA_PKT_COPY_T2T_BC packet
2185*/
2186
2187/*define for HEADER word*/
2188/*define for op field*/
2189#define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0
2190#define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask   0x000000FF
2191#define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift  0
2192#define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift)
2193
2194/*define for sub_op field*/
2195#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0
2196#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask   0x000000FF
2197#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift  8
2198#define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift)
2199
2200/*define for SRC_ADDR_LO word*/
2201/*define for src_addr_31_0 field*/
2202#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1
2203#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
2204#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
2205#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift)
2206
2207/*define for SRC_ADDR_HI word*/
2208/*define for src_addr_63_32 field*/
2209#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2
2210#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
2211#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
2212#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift)
2213
2214/*define for DW_3 word*/
2215/*define for src_x field*/
2216#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3
2217#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask   0x00003FFF
2218#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift  0
2219#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift)
2220
2221/*define for src_y field*/
2222#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3
2223#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask   0x00003FFF
2224#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift  16
2225#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift)
2226
2227/*define for DW_4 word*/
2228/*define for src_z field*/
2229#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4
2230#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask   0x000007FF
2231#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift  0
2232#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift)
2233
2234/*define for src_width field*/
2235#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4
2236#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask   0x00003FFF
2237#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift  16
2238#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift)
2239
2240/*define for DW_5 word*/
2241/*define for src_height field*/
2242#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5
2243#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask   0x00003FFF
2244#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift  0
2245#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift)
2246
2247/*define for src_depth field*/
2248#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5
2249#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask   0x000007FF
2250#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift  16
2251#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift)
2252
2253/*define for DW_6 word*/
2254/*define for src_element_size field*/
2255#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6
2256#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask   0x00000007
2257#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift  0
2258#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift)
2259
2260/*define for src_array_mode field*/
2261#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6
2262#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask   0x0000000F
2263#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift  3
2264#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift)
2265
2266/*define for src_mit_mode field*/
2267#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6
2268#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask   0x00000007
2269#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift  8
2270#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift)
2271
2272/*define for src_tilesplit_size field*/
2273#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6
2274#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask   0x00000007
2275#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift  11
2276#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift)
2277
2278/*define for src_bank_w field*/
2279#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6
2280#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask   0x00000003
2281#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift  15
2282#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift)
2283
2284/*define for src_bank_h field*/
2285#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6
2286#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask   0x00000003
2287#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift  18
2288#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift)
2289
2290/*define for src_num_bank field*/
2291#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6
2292#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask   0x00000003
2293#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift  21
2294#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift)
2295
2296/*define for src_mat_aspt field*/
2297#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6
2298#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask   0x00000003
2299#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift  24
2300#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift)
2301
2302/*define for src_pipe_config field*/
2303#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6
2304#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask   0x0000001F
2305#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift  26
2306#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift)
2307
2308/*define for DST_ADDR_LO word*/
2309/*define for dst_addr_31_0 field*/
2310#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7
2311#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
2312#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
2313#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift)
2314
2315/*define for DST_ADDR_HI word*/
2316/*define for dst_addr_63_32 field*/
2317#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8
2318#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
2319#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
2320#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift)
2321
2322/*define for DW_9 word*/
2323/*define for dst_x field*/
2324#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9
2325#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask   0x00003FFF
2326#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift  0
2327#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift)
2328
2329/*define for dst_y field*/
2330#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9
2331#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask   0x00003FFF
2332#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift  16
2333#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift)
2334
2335/*define for DW_10 word*/
2336/*define for dst_z field*/
2337#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10
2338#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask   0x000007FF
2339#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift  0
2340#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift)
2341
2342/*define for dst_width field*/
2343#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10
2344#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask   0x00003FFF
2345#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift  16
2346#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift)
2347
2348/*define for DW_11 word*/
2349/*define for dst_height field*/
2350#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11
2351#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask   0x00003FFF
2352#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift  0
2353#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift)
2354
2355/*define for dst_depth field*/
2356#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11
2357#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask   0x00000FFF
2358#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift  16
2359#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift)
2360
2361/*define for DW_12 word*/
2362/*define for dst_element_size field*/
2363#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12
2364#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask   0x00000007
2365#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift  0
2366#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift)
2367
2368/*define for dst_array_mode field*/
2369#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12
2370#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask   0x0000000F
2371#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift  3
2372#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift)
2373
2374/*define for dst_mit_mode field*/
2375#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12
2376#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask   0x00000007
2377#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift  8
2378#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift)
2379
2380/*define for dst_tilesplit_size field*/
2381#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12
2382#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask   0x00000007
2383#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift  11
2384#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift)
2385
2386/*define for dst_bank_w field*/
2387#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12
2388#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask   0x00000003
2389#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift  15
2390#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift)
2391
2392/*define for dst_bank_h field*/
2393#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12
2394#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask   0x00000003
2395#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift  18
2396#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift)
2397
2398/*define for dst_num_bank field*/
2399#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12
2400#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask   0x00000003
2401#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift  21
2402#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift)
2403
2404/*define for dst_mat_aspt field*/
2405#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12
2406#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask   0x00000003
2407#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift  24
2408#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift)
2409
2410/*define for dst_pipe_config field*/
2411#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12
2412#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask   0x0000001F
2413#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift  26
2414#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift)
2415
2416/*define for DW_13 word*/
2417/*define for rect_x field*/
2418#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13
2419#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask   0x00003FFF
2420#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift  0
2421#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift)
2422
2423/*define for rect_y field*/
2424#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13
2425#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask   0x00003FFF
2426#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift  16
2427#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift)
2428
2429/*define for DW_14 word*/
2430/*define for rect_z field*/
2431#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14
2432#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask   0x000007FF
2433#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift  0
2434#define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift)
2435
2436/*define for dst_sw field*/
2437#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14
2438#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask   0x00000003
2439#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift  16
2440#define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift)
2441
2442/*define for src_sw field*/
2443#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14
2444#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask   0x00000003
2445#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift  24
2446#define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift)
2447
2448
2449/*
2450** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet
2451*/
2452
2453/*define for HEADER word*/
2454/*define for op field*/
2455#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
2456#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask   0x000000FF
2457#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift  0
2458#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)
2459
2460/*define for sub_op field*/
2461#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
2462#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask   0x000000FF
2463#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift  8
2464#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)
2465
2466/*define for tmz field*/
2467#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0
2468#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask   0x00000001
2469#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift  18
2470#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift)
2471
2472/*define for dcc field*/
2473#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0
2474#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask   0x00000001
2475#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift  19
2476#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift)
2477
2478/*define for cpv field*/
2479#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset 0
2480#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask   0x00000001
2481#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift  28
2482#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift)
2483
2484/*define for detile field*/
2485#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
2486#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask   0x00000001
2487#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift  31
2488#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)
2489
2490/*define for TILED_ADDR_LO word*/
2491/*define for tiled_addr_31_0 field*/
2492#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1
2493#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
2494#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift  0
2495#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)
2496
2497/*define for TILED_ADDR_HI word*/
2498/*define for tiled_addr_63_32 field*/
2499#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2
2500#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
2501#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift  0
2502#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)
2503
2504/*define for DW_3 word*/
2505/*define for tiled_x field*/
2506#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3
2507#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask   0x00003FFF
2508#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift  0
2509#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)
2510
2511/*define for tiled_y field*/
2512#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3
2513#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask   0x00003FFF
2514#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift  16
2515#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)
2516
2517/*define for DW_4 word*/
2518/*define for tiled_z field*/
2519#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4
2520#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask   0x00001FFF
2521#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift  0
2522#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)
2523
2524/*define for width field*/
2525#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4
2526#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask   0x00003FFF
2527#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift  16
2528#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift)
2529
2530/*define for DW_5 word*/
2531/*define for height field*/
2532#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5
2533#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask   0x00003FFF
2534#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift  0
2535#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift)
2536
2537/*define for depth field*/
2538#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5
2539#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask   0x00001FFF
2540#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift  16
2541#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift)
2542
2543/*define for DW_6 word*/
2544/*define for element_size field*/
2545#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6
2546#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask   0x00000007
2547#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift  0
2548#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)
2549
2550/*define for swizzle_mode field*/
2551#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6
2552#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask   0x0000001F
2553#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift  3
2554#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift)
2555
2556/*define for dimension field*/
2557#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6
2558#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask   0x00000003
2559#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift  9
2560#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift)
2561
2562/*define for mip_max field*/
2563#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6
2564#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask   0x0000000F
2565#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift  16
2566#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift)
2567
2568/*define for mip_id field*/
2569#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6
2570#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask   0x0000000F
2571#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift  20
2572#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift)
2573
2574/*define for LINEAR_ADDR_LO word*/
2575/*define for linear_addr_31_0 field*/
2576#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7
2577#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
2578#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
2579#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)
2580
2581/*define for LINEAR_ADDR_HI word*/
2582/*define for linear_addr_63_32 field*/
2583#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8
2584#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
2585#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
2586#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)
2587
2588/*define for DW_9 word*/
2589/*define for linear_x field*/
2590#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9
2591#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask   0x00003FFF
2592#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift  0
2593#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)
2594
2595/*define for linear_y field*/
2596#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9
2597#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask   0x00003FFF
2598#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift  16
2599#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)
2600
2601/*define for DW_10 word*/
2602/*define for linear_z field*/
2603#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10
2604#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask   0x00001FFF
2605#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift  0
2606#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)
2607
2608/*define for linear_pitch field*/
2609#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10
2610#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask   0x00003FFF
2611#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift  16
2612#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)
2613
2614/*define for DW_11 word*/
2615/*define for linear_slice_pitch field*/
2616#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11
2617#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
2618#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift  0
2619#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)
2620
2621/*define for DW_12 word*/
2622/*define for rect_x field*/
2623#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12
2624#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask   0x00003FFF
2625#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift  0
2626#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)
2627
2628/*define for rect_y field*/
2629#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12
2630#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask   0x00003FFF
2631#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift  16
2632#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)
2633
2634/*define for DW_13 word*/
2635/*define for rect_z field*/
2636#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13
2637#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask   0x00001FFF
2638#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift  0
2639#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)
2640
2641/*define for linear_sw field*/
2642#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13
2643#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask   0x00000003
2644#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift  16
2645#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)
2646
2647/*define for linear_cache_policy field*/
2648#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset 13
2649#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask   0x00000007
2650#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift  18
2651#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift)
2652
2653/*define for tile_sw field*/
2654#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13
2655#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask   0x00000003
2656#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift  24
2657#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)
2658
2659/*define for tile_cache_policy field*/
2660#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset 13
2661#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask   0x00000007
2662#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift  26
2663#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift)
2664
2665/*define for META_ADDR_LO word*/
2666/*define for meta_addr_31_0 field*/
2667#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14
2668#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask   0xFFFFFFFF
2669#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift  0
2670#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift)
2671
2672/*define for META_ADDR_HI word*/
2673/*define for meta_addr_63_32 field*/
2674#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15
2675#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask   0xFFFFFFFF
2676#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift  0
2677#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift)
2678
2679/*define for META_CONFIG word*/
2680/*define for data_format field*/
2681#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16
2682#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask   0x0000007F
2683#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift  0
2684#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift)
2685
2686/*define for color_transform_disable field*/
2687#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16
2688#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask   0x00000001
2689#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift  7
2690#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift)
2691
2692/*define for alpha_is_on_msb field*/
2693#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16
2694#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask   0x00000001
2695#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift  8
2696#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift)
2697
2698/*define for number_type field*/
2699#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16
2700#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask   0x00000007
2701#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift  9
2702#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift)
2703
2704/*define for surface_type field*/
2705#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16
2706#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask   0x00000003
2707#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift  12
2708#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift)
2709
2710/*define for meta_llc field*/
2711#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset 16
2712#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask   0x00000001
2713#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift  14
2714#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift)
2715
2716/*define for max_comp_block_size field*/
2717#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16
2718#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask   0x00000003
2719#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift  24
2720#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift)
2721
2722/*define for max_uncomp_block_size field*/
2723#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16
2724#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask   0x00000003
2725#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift  26
2726#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift)
2727
2728/*define for write_compress_enable field*/
2729#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16
2730#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask   0x00000001
2731#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift  28
2732#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift)
2733
2734/*define for meta_tmz field*/
2735#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16
2736#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask   0x00000001
2737#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift  29
2738#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift)
2739
2740/*define for pipe_aligned field*/
2741#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset 16
2742#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask   0x00000001
2743#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift  31
2744#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift)
2745
2746
2747/*
2748** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet
2749*/
2750
2751/*define for HEADER word*/
2752/*define for op field*/
2753#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0
2754#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask   0x000000FF
2755#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift  0
2756#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift)
2757
2758/*define for sub_op field*/
2759#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0
2760#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask   0x000000FF
2761#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift  8
2762#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift)
2763
2764/*define for detile field*/
2765#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0
2766#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask   0x00000001
2767#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift  31
2768#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift)
2769
2770/*define for TILED_ADDR_LO word*/
2771/*define for tiled_addr_31_0 field*/
2772#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1
2773#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
2774#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift  0
2775#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift)
2776
2777/*define for TILED_ADDR_HI word*/
2778/*define for tiled_addr_63_32 field*/
2779#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2
2780#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
2781#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift  0
2782#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift)
2783
2784/*define for DW_3 word*/
2785/*define for tiled_x field*/
2786#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3
2787#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask   0x00003FFF
2788#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift  0
2789#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift)
2790
2791/*define for tiled_y field*/
2792#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3
2793#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask   0x00003FFF
2794#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift  16
2795#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift)
2796
2797/*define for DW_4 word*/
2798/*define for tiled_z field*/
2799#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4
2800#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask   0x000007FF
2801#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift  0
2802#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift)
2803
2804/*define for width field*/
2805#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4
2806#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask   0x00003FFF
2807#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift  16
2808#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift)
2809
2810/*define for DW_5 word*/
2811/*define for height field*/
2812#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5
2813#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask   0x00003FFF
2814#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift  0
2815#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift)
2816
2817/*define for depth field*/
2818#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5
2819#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask   0x000007FF
2820#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift  16
2821#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift)
2822
2823/*define for DW_6 word*/
2824/*define for element_size field*/
2825#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6
2826#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask   0x00000007
2827#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift  0
2828#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift)
2829
2830/*define for array_mode field*/
2831#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6
2832#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask   0x0000000F
2833#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift  3
2834#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift)
2835
2836/*define for mit_mode field*/
2837#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6
2838#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask   0x00000007
2839#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift  8
2840#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift)
2841
2842/*define for tilesplit_size field*/
2843#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6
2844#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask   0x00000007
2845#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift  11
2846#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift)
2847
2848/*define for bank_w field*/
2849#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6
2850#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask   0x00000003
2851#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift  15
2852#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift)
2853
2854/*define for bank_h field*/
2855#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6
2856#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask   0x00000003
2857#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift  18
2858#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift)
2859
2860/*define for num_bank field*/
2861#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6
2862#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask   0x00000003
2863#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift  21
2864#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift)
2865
2866/*define for mat_aspt field*/
2867#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6
2868#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask   0x00000003
2869#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift  24
2870#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift)
2871
2872/*define for pipe_config field*/
2873#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6
2874#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask   0x0000001F
2875#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift  26
2876#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift)
2877
2878/*define for LINEAR_ADDR_LO word*/
2879/*define for linear_addr_31_0 field*/
2880#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7
2881#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
2882#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
2883#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift)
2884
2885/*define for LINEAR_ADDR_HI word*/
2886/*define for linear_addr_63_32 field*/
2887#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8
2888#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
2889#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
2890#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift)
2891
2892/*define for DW_9 word*/
2893/*define for linear_x field*/
2894#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9
2895#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask   0x00003FFF
2896#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift  0
2897#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift)
2898
2899/*define for linear_y field*/
2900#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9
2901#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask   0x00003FFF
2902#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift  16
2903#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift)
2904
2905/*define for DW_10 word*/
2906/*define for linear_z field*/
2907#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10
2908#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask   0x000007FF
2909#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift  0
2910#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift)
2911
2912/*define for linear_pitch field*/
2913#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10
2914#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask   0x00003FFF
2915#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift  16
2916#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift)
2917
2918/*define for DW_11 word*/
2919/*define for linear_slice_pitch field*/
2920#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11
2921#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
2922#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift  0
2923#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift)
2924
2925/*define for DW_12 word*/
2926/*define for rect_x field*/
2927#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12
2928#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask   0x00003FFF
2929#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift  0
2930#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift)
2931
2932/*define for rect_y field*/
2933#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12
2934#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask   0x00003FFF
2935#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift  16
2936#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift)
2937
2938/*define for DW_13 word*/
2939/*define for rect_z field*/
2940#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13
2941#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask   0x000007FF
2942#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift  0
2943#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift)
2944
2945/*define for linear_sw field*/
2946#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13
2947#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask   0x00000003
2948#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift  16
2949#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift)
2950
2951/*define for tile_sw field*/
2952#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13
2953#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask   0x00000003
2954#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift  24
2955#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift)
2956
2957
2958/*
2959** Definitions for SDMA_PKT_COPY_STRUCT packet
2960*/
2961
2962/*define for HEADER word*/
2963/*define for op field*/
2964#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
2965#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask   0x000000FF
2966#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift  0
2967#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)
2968
2969/*define for sub_op field*/
2970#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
2971#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask   0x000000FF
2972#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift  8
2973#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)
2974
2975/*define for tmz field*/
2976#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0
2977#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask   0x00000001
2978#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift  18
2979#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift)
2980
2981/*define for cpv field*/
2982#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset 0
2983#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask   0x00000001
2984#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift  28
2985#define SDMA_PKT_COPY_STRUCT_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift)
2986
2987/*define for detile field*/
2988#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
2989#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask   0x00000001
2990#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift  31
2991#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)
2992
2993/*define for SB_ADDR_LO word*/
2994/*define for sb_addr_31_0 field*/
2995#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1
2996#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask   0xFFFFFFFF
2997#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift  0
2998#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)
2999
3000/*define for SB_ADDR_HI word*/
3001/*define for sb_addr_63_32 field*/
3002#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2
3003#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask   0xFFFFFFFF
3004#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift  0
3005#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)
3006
3007/*define for START_INDEX word*/
3008/*define for start_index field*/
3009#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3
3010#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask   0xFFFFFFFF
3011#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift  0
3012#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)
3013
3014/*define for COUNT word*/
3015/*define for count field*/
3016#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4
3017#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask   0xFFFFFFFF
3018#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift  0
3019#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)
3020
3021/*define for DW_5 word*/
3022/*define for stride field*/
3023#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5
3024#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask   0x000007FF
3025#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift  0
3026#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)
3027
3028/*define for linear_sw field*/
3029#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5
3030#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask   0x00000003
3031#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift  16
3032#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)
3033
3034/*define for linear_cache_policy field*/
3035#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset 5
3036#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask   0x00000007
3037#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift  18
3038#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift)
3039
3040/*define for struct_sw field*/
3041#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5
3042#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask   0x00000003
3043#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift  24
3044#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)
3045
3046/*define for struct_cache_policy field*/
3047#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset 5
3048#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask   0x00000007
3049#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift  26
3050#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift)
3051
3052/*define for LINEAR_ADDR_LO word*/
3053/*define for linear_addr_31_0 field*/
3054#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6
3055#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
3056#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
3057#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)
3058
3059/*define for LINEAR_ADDR_HI word*/
3060/*define for linear_addr_63_32 field*/
3061#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7
3062#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
3063#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
3064#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)
3065
3066
3067/*
3068** Definitions for SDMA_PKT_WRITE_UNTILED packet
3069*/
3070
3071/*define for HEADER word*/
3072/*define for op field*/
3073#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
3074#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask   0x000000FF
3075#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift  0
3076#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)
3077
3078/*define for sub_op field*/
3079#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
3080#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask   0x000000FF
3081#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift  8
3082#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)
3083
3084/*define for encrypt field*/
3085#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0
3086#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask   0x00000001
3087#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift  16
3088#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift)
3089
3090/*define for tmz field*/
3091#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0
3092#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask   0x00000001
3093#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift  18
3094#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift)
3095
3096/*define for cpv field*/
3097#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset 0
3098#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask   0x00000001
3099#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift  28
3100#define SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift)
3101
3102/*define for DST_ADDR_LO word*/
3103/*define for dst_addr_31_0 field*/
3104#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1
3105#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3106#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift  0
3107#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)
3108
3109/*define for DST_ADDR_HI word*/
3110/*define for dst_addr_63_32 field*/
3111#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2
3112#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3113#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift  0
3114#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)
3115
3116/*define for DW_3 word*/
3117/*define for count field*/
3118#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3
3119#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask   0x000FFFFF
3120#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift  0
3121#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)
3122
3123/*define for sw field*/
3124#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3
3125#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask   0x00000003
3126#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift  24
3127#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)
3128
3129/*define for cache_policy field*/
3130#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset 3
3131#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask   0x00000007
3132#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift  26
3133#define SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift)
3134
3135/*define for DATA0 word*/
3136/*define for data0 field*/
3137#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4
3138#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask   0xFFFFFFFF
3139#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift  0
3140#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)
3141
3142
3143/*
3144** Definitions for SDMA_PKT_WRITE_TILED packet
3145*/
3146
3147/*define for HEADER word*/
3148/*define for op field*/
3149#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
3150#define SDMA_PKT_WRITE_TILED_HEADER_op_mask   0x000000FF
3151#define SDMA_PKT_WRITE_TILED_HEADER_op_shift  0
3152#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)
3153
3154/*define for sub_op field*/
3155#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
3156#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask   0x000000FF
3157#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift  8
3158#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)
3159
3160/*define for encrypt field*/
3161#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0
3162#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask   0x00000001
3163#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift  16
3164#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift)
3165
3166/*define for tmz field*/
3167#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0
3168#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask   0x00000001
3169#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift  18
3170#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift)
3171
3172/*define for cpv field*/
3173#define SDMA_PKT_WRITE_TILED_HEADER_cpv_offset 0
3174#define SDMA_PKT_WRITE_TILED_HEADER_cpv_mask   0x00000001
3175#define SDMA_PKT_WRITE_TILED_HEADER_cpv_shift  28
3176#define SDMA_PKT_WRITE_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift)
3177
3178/*define for DST_ADDR_LO word*/
3179/*define for dst_addr_31_0 field*/
3180#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1
3181#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3182#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift  0
3183#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)
3184
3185/*define for DST_ADDR_HI word*/
3186/*define for dst_addr_63_32 field*/
3187#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2
3188#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3189#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift  0
3190#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)
3191
3192/*define for DW_3 word*/
3193/*define for width field*/
3194#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3
3195#define SDMA_PKT_WRITE_TILED_DW_3_width_mask   0x00003FFF
3196#define SDMA_PKT_WRITE_TILED_DW_3_width_shift  0
3197#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift)
3198
3199/*define for DW_4 word*/
3200/*define for height field*/
3201#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4
3202#define SDMA_PKT_WRITE_TILED_DW_4_height_mask   0x00003FFF
3203#define SDMA_PKT_WRITE_TILED_DW_4_height_shift  0
3204#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift)
3205
3206/*define for depth field*/
3207#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4
3208#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask   0x00001FFF
3209#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift  16
3210#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift)
3211
3212/*define for DW_5 word*/
3213/*define for element_size field*/
3214#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5
3215#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask   0x00000007
3216#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift  0
3217#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)
3218
3219/*define for swizzle_mode field*/
3220#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5
3221#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask   0x0000001F
3222#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift  3
3223#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift)
3224
3225/*define for dimension field*/
3226#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5
3227#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask   0x00000003
3228#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift  9
3229#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift)
3230
3231/*define for mip_max field*/
3232#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5
3233#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask   0x0000000F
3234#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift  16
3235#define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift)
3236
3237/*define for DW_6 word*/
3238/*define for x field*/
3239#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6
3240#define SDMA_PKT_WRITE_TILED_DW_6_x_mask   0x00003FFF
3241#define SDMA_PKT_WRITE_TILED_DW_6_x_shift  0
3242#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)
3243
3244/*define for y field*/
3245#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6
3246#define SDMA_PKT_WRITE_TILED_DW_6_y_mask   0x00003FFF
3247#define SDMA_PKT_WRITE_TILED_DW_6_y_shift  16
3248#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)
3249
3250/*define for DW_7 word*/
3251/*define for z field*/
3252#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7
3253#define SDMA_PKT_WRITE_TILED_DW_7_z_mask   0x00001FFF
3254#define SDMA_PKT_WRITE_TILED_DW_7_z_shift  0
3255#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)
3256
3257/*define for sw field*/
3258#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7
3259#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask   0x00000003
3260#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift  24
3261#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)
3262
3263/*define for cache_policy field*/
3264#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset 7
3265#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask   0x00000007
3266#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift  26
3267#define SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift)
3268
3269/*define for COUNT word*/
3270/*define for count field*/
3271#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8
3272#define SDMA_PKT_WRITE_TILED_COUNT_count_mask   0x000FFFFF
3273#define SDMA_PKT_WRITE_TILED_COUNT_count_shift  0
3274#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)
3275
3276/*define for DATA0 word*/
3277/*define for data0 field*/
3278#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9
3279#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask   0xFFFFFFFF
3280#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift  0
3281#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)
3282
3283
3284/*
3285** Definitions for SDMA_PKT_WRITE_TILED_BC packet
3286*/
3287
3288/*define for HEADER word*/
3289/*define for op field*/
3290#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0
3291#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask   0x000000FF
3292#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift  0
3293#define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift)
3294
3295/*define for sub_op field*/
3296#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0
3297#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask   0x000000FF
3298#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift  8
3299#define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift)
3300
3301/*define for DST_ADDR_LO word*/
3302/*define for dst_addr_31_0 field*/
3303#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1
3304#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3305#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
3306#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift)
3307
3308/*define for DST_ADDR_HI word*/
3309/*define for dst_addr_63_32 field*/
3310#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2
3311#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3312#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
3313#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift)
3314
3315/*define for DW_3 word*/
3316/*define for width field*/
3317#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3
3318#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask   0x00003FFF
3319#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift  0
3320#define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift)
3321
3322/*define for DW_4 word*/
3323/*define for height field*/
3324#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4
3325#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask   0x00003FFF
3326#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift  0
3327#define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift)
3328
3329/*define for depth field*/
3330#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4
3331#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask   0x000007FF
3332#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift  16
3333#define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift)
3334
3335/*define for DW_5 word*/
3336/*define for element_size field*/
3337#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5
3338#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask   0x00000007
3339#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift  0
3340#define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift)
3341
3342/*define for array_mode field*/
3343#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5
3344#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask   0x0000000F
3345#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift  3
3346#define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift)
3347
3348/*define for mit_mode field*/
3349#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5
3350#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask   0x00000007
3351#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift  8
3352#define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift)
3353
3354/*define for tilesplit_size field*/
3355#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5
3356#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask   0x00000007
3357#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift  11
3358#define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift)
3359
3360/*define for bank_w field*/
3361#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5
3362#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask   0x00000003
3363#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift  15
3364#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift)
3365
3366/*define for bank_h field*/
3367#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5
3368#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask   0x00000003
3369#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift  18
3370#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift)
3371
3372/*define for num_bank field*/
3373#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5
3374#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask   0x00000003
3375#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift  21
3376#define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift)
3377
3378/*define for mat_aspt field*/
3379#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5
3380#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask   0x00000003
3381#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift  24
3382#define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift)
3383
3384/*define for pipe_config field*/
3385#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5
3386#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask   0x0000001F
3387#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift  26
3388#define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift)
3389
3390/*define for DW_6 word*/
3391/*define for x field*/
3392#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6
3393#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask   0x00003FFF
3394#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift  0
3395#define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift)
3396
3397/*define for y field*/
3398#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6
3399#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask   0x00003FFF
3400#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift  16
3401#define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift)
3402
3403/*define for DW_7 word*/
3404/*define for z field*/
3405#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7
3406#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask   0x000007FF
3407#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift  0
3408#define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift)
3409
3410/*define for sw field*/
3411#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7
3412#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask   0x00000003
3413#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift  24
3414#define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift)
3415
3416/*define for COUNT word*/
3417/*define for count field*/
3418#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8
3419#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask   0x000FFFFF
3420#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift  2
3421#define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift)
3422
3423/*define for DATA0 word*/
3424/*define for data0 field*/
3425#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9
3426#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask   0xFFFFFFFF
3427#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift  0
3428#define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift)
3429
3430
3431/*
3432** Definitions for SDMA_PKT_PTEPDE_COPY packet
3433*/
3434
3435/*define for HEADER word*/
3436/*define for op field*/
3437#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0
3438#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask   0x000000FF
3439#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift  0
3440#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift)
3441
3442/*define for sub_op field*/
3443#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0
3444#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask   0x000000FF
3445#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift  8
3446#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift)
3447
3448/*define for tmz field*/
3449#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0
3450#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask   0x00000001
3451#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift  18
3452#define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift)
3453
3454/*define for cpv field*/
3455#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset 0
3456#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask   0x00000001
3457#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift  28
3458#define SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift)
3459
3460/*define for ptepde_op field*/
3461#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0
3462#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask   0x00000001
3463#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift  31
3464#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift)
3465
3466/*define for SRC_ADDR_LO word*/
3467/*define for src_addr_31_0 field*/
3468#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1
3469#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
3470#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift  0
3471#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift)
3472
3473/*define for SRC_ADDR_HI word*/
3474/*define for src_addr_63_32 field*/
3475#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2
3476#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
3477#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift  0
3478#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift)
3479
3480/*define for DST_ADDR_LO word*/
3481/*define for dst_addr_31_0 field*/
3482#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3
3483#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3484#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift  0
3485#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift)
3486
3487/*define for DST_ADDR_HI word*/
3488/*define for dst_addr_63_32 field*/
3489#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4
3490#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3491#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift  0
3492#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift)
3493
3494/*define for MASK_DW0 word*/
3495/*define for mask_dw0 field*/
3496#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5
3497#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
3498#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift  0
3499#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift)
3500
3501/*define for MASK_DW1 word*/
3502/*define for mask_dw1 field*/
3503#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6
3504#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
3505#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift  0
3506#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift)
3507
3508/*define for COUNT word*/
3509/*define for count field*/
3510#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7
3511#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask   0x0007FFFF
3512#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift  0
3513#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift)
3514
3515/*define for dst_cache_policy field*/
3516#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset 7
3517#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask   0x00000007
3518#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift  22
3519#define SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift)
3520
3521/*define for src_cache_policy field*/
3522#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset 7
3523#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask   0x00000007
3524#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift  29
3525#define SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift)
3526
3527
3528/*
3529** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet
3530*/
3531
3532/*define for HEADER word*/
3533/*define for op field*/
3534#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0
3535#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask   0x000000FF
3536#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift  0
3537#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift)
3538
3539/*define for sub_op field*/
3540#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0
3541#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask   0x000000FF
3542#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift  8
3543#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift)
3544
3545/*define for pte_size field*/
3546#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0
3547#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask   0x00000003
3548#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift  28
3549#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift)
3550
3551/*define for direction field*/
3552#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0
3553#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask   0x00000001
3554#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift  30
3555#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift)
3556
3557/*define for ptepde_op field*/
3558#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0
3559#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask   0x00000001
3560#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift  31
3561#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift)
3562
3563/*define for SRC_ADDR_LO word*/
3564/*define for src_addr_31_0 field*/
3565#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1
3566#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
3567#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift  0
3568#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift)
3569
3570/*define for SRC_ADDR_HI word*/
3571/*define for src_addr_63_32 field*/
3572#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2
3573#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
3574#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift  0
3575#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift)
3576
3577/*define for DST_ADDR_LO word*/
3578/*define for dst_addr_31_0 field*/
3579#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3
3580#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3581#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift  0
3582#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift)
3583
3584/*define for DST_ADDR_HI word*/
3585/*define for dst_addr_63_32 field*/
3586#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4
3587#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3588#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift  0
3589#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift)
3590
3591/*define for MASK_BIT_FOR_DW word*/
3592/*define for mask_first_xfer field*/
3593#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5
3594#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask   0x000000FF
3595#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift  0
3596#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift)
3597
3598/*define for mask_last_xfer field*/
3599#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5
3600#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask   0x000000FF
3601#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift  8
3602#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift)
3603
3604/*define for COUNT_IN_32B_XFER word*/
3605/*define for count field*/
3606#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6
3607#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask   0x0001FFFF
3608#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift  0
3609#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift)
3610
3611
3612/*
3613** Definitions for SDMA_PKT_PTEPDE_RMW packet
3614*/
3615
3616/*define for HEADER word*/
3617/*define for op field*/
3618#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0
3619#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask   0x000000FF
3620#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift  0
3621#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift)
3622
3623/*define for sub_op field*/
3624#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0
3625#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask   0x000000FF
3626#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift  8
3627#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift)
3628
3629/*define for mtype field*/
3630#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0
3631#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask   0x00000007
3632#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift  16
3633#define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift)
3634
3635/*define for gcc field*/
3636#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0
3637#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask   0x00000001
3638#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift  19
3639#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift)
3640
3641/*define for sys field*/
3642#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0
3643#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask   0x00000001
3644#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift  20
3645#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift)
3646
3647/*define for snp field*/
3648#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0
3649#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask   0x00000001
3650#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift  22
3651#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift)
3652
3653/*define for gpa field*/
3654#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0
3655#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask   0x00000001
3656#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift  23
3657#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift)
3658
3659/*define for l2_policy field*/
3660#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0
3661#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask   0x00000003
3662#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift  24
3663#define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift)
3664
3665/*define for llc_policy field*/
3666#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset 0
3667#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask   0x00000001
3668#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift  26
3669#define SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift)
3670
3671/*define for cpv field*/
3672#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset 0
3673#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask   0x00000001
3674#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift  28
3675#define SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift)
3676
3677/*define for ADDR_LO word*/
3678/*define for addr_31_0 field*/
3679#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1
3680#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3681#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift  0
3682#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift)
3683
3684/*define for ADDR_HI word*/
3685/*define for addr_63_32 field*/
3686#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2
3687#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3688#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift  0
3689#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift)
3690
3691/*define for MASK_LO word*/
3692/*define for mask_31_0 field*/
3693#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3
3694#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask   0xFFFFFFFF
3695#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift  0
3696#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift)
3697
3698/*define for MASK_HI word*/
3699/*define for mask_63_32 field*/
3700#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4
3701#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask   0xFFFFFFFF
3702#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift  0
3703#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift)
3704
3705/*define for VALUE_LO word*/
3706/*define for value_31_0 field*/
3707#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5
3708#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask   0xFFFFFFFF
3709#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift  0
3710#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift)
3711
3712/*define for VALUE_HI word*/
3713/*define for value_63_32 field*/
3714#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6
3715#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask   0xFFFFFFFF
3716#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift  0
3717#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift)
3718
3719/*define for COUNT word*/
3720/*define for num_of_pte field*/
3721#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset 7
3722#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask   0xFFFFFFFF
3723#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift  0
3724#define SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x) (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift)
3725
3726
3727/*
3728** Definitions for SDMA_PKT_REGISTER_RMW packet
3729*/
3730
3731/*define for HEADER word*/
3732/*define for op field*/
3733#define SDMA_PKT_REGISTER_RMW_HEADER_op_offset 0
3734#define SDMA_PKT_REGISTER_RMW_HEADER_op_mask   0x000000FF
3735#define SDMA_PKT_REGISTER_RMW_HEADER_op_shift  0
3736#define SDMA_PKT_REGISTER_RMW_HEADER_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift)
3737
3738/*define for sub_op field*/
3739#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset 0
3740#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask   0x000000FF
3741#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift  8
3742#define SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift)
3743
3744/*define for ADDR word*/
3745/*define for addr field*/
3746#define SDMA_PKT_REGISTER_RMW_ADDR_addr_offset 1
3747#define SDMA_PKT_REGISTER_RMW_ADDR_addr_mask   0x000FFFFF
3748#define SDMA_PKT_REGISTER_RMW_ADDR_addr_shift  0
3749#define SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift)
3750
3751/*define for aperture_id field*/
3752#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset 1
3753#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask   0x00000FFF
3754#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift  20
3755#define SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift)
3756
3757/*define for MASK word*/
3758/*define for mask field*/
3759#define SDMA_PKT_REGISTER_RMW_MASK_mask_offset 2
3760#define SDMA_PKT_REGISTER_RMW_MASK_mask_mask   0xFFFFFFFF
3761#define SDMA_PKT_REGISTER_RMW_MASK_mask_shift  0
3762#define SDMA_PKT_REGISTER_RMW_MASK_MASK(x) (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift)
3763
3764/*define for VALUE word*/
3765/*define for value field*/
3766#define SDMA_PKT_REGISTER_RMW_VALUE_value_offset 3
3767#define SDMA_PKT_REGISTER_RMW_VALUE_value_mask   0xFFFFFFFF
3768#define SDMA_PKT_REGISTER_RMW_VALUE_value_shift  0
3769#define SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x) (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift)
3770
3771/*define for MISC word*/
3772/*define for stride field*/
3773#define SDMA_PKT_REGISTER_RMW_MISC_stride_offset 4
3774#define SDMA_PKT_REGISTER_RMW_MISC_stride_mask   0x000FFFFF
3775#define SDMA_PKT_REGISTER_RMW_MISC_stride_shift  0
3776#define SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift)
3777
3778/*define for num_of_reg field*/
3779#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset 4
3780#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask   0x00000FFF
3781#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift  20
3782#define SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift)
3783
3784
3785/*
3786** Definitions for SDMA_PKT_WRITE_INCR packet
3787*/
3788
3789/*define for HEADER word*/
3790/*define for op field*/
3791#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
3792#define SDMA_PKT_WRITE_INCR_HEADER_op_mask   0x000000FF
3793#define SDMA_PKT_WRITE_INCR_HEADER_op_shift  0
3794#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)
3795
3796/*define for sub_op field*/
3797#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
3798#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask   0x000000FF
3799#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift  8
3800#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)
3801
3802/*define for cache_policy field*/
3803#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset 0
3804#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask   0x00000007
3805#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift  24
3806#define SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift)
3807
3808/*define for cpv field*/
3809#define SDMA_PKT_WRITE_INCR_HEADER_cpv_offset 0
3810#define SDMA_PKT_WRITE_INCR_HEADER_cpv_mask   0x00000001
3811#define SDMA_PKT_WRITE_INCR_HEADER_cpv_shift  28
3812#define SDMA_PKT_WRITE_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift)
3813
3814/*define for DST_ADDR_LO word*/
3815/*define for dst_addr_31_0 field*/
3816#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1
3817#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3818#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift  0
3819#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)
3820
3821/*define for DST_ADDR_HI word*/
3822/*define for dst_addr_63_32 field*/
3823#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2
3824#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3825#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift  0
3826#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)
3827
3828/*define for MASK_DW0 word*/
3829/*define for mask_dw0 field*/
3830#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3
3831#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
3832#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift  0
3833#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)
3834
3835/*define for MASK_DW1 word*/
3836/*define for mask_dw1 field*/
3837#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4
3838#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
3839#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift  0
3840#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)
3841
3842/*define for INIT_DW0 word*/
3843/*define for init_dw0 field*/
3844#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5
3845#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask   0xFFFFFFFF
3846#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift  0
3847#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)
3848
3849/*define for INIT_DW1 word*/
3850/*define for init_dw1 field*/
3851#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6
3852#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask   0xFFFFFFFF
3853#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift  0
3854#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)
3855
3856/*define for INCR_DW0 word*/
3857/*define for incr_dw0 field*/
3858#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7
3859#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask   0xFFFFFFFF
3860#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift  0
3861#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)
3862
3863/*define for INCR_DW1 word*/
3864/*define for incr_dw1 field*/
3865#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8
3866#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask   0xFFFFFFFF
3867#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift  0
3868#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)
3869
3870/*define for COUNT word*/
3871/*define for count field*/
3872#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9
3873#define SDMA_PKT_WRITE_INCR_COUNT_count_mask   0x0007FFFF
3874#define SDMA_PKT_WRITE_INCR_COUNT_count_shift  0
3875#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)
3876
3877
3878/*
3879** Definitions for SDMA_PKT_INDIRECT packet
3880*/
3881
3882/*define for HEADER word*/
3883/*define for op field*/
3884#define SDMA_PKT_INDIRECT_HEADER_op_offset 0
3885#define SDMA_PKT_INDIRECT_HEADER_op_mask   0x000000FF
3886#define SDMA_PKT_INDIRECT_HEADER_op_shift  0
3887#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)
3888
3889/*define for sub_op field*/
3890#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
3891#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask   0x000000FF
3892#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift  8
3893#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)
3894
3895/*define for vmid field*/
3896#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
3897#define SDMA_PKT_INDIRECT_HEADER_vmid_mask   0x0000000F
3898#define SDMA_PKT_INDIRECT_HEADER_vmid_shift  16
3899#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)
3900
3901/*define for priv field*/
3902#define SDMA_PKT_INDIRECT_HEADER_priv_offset 0
3903#define SDMA_PKT_INDIRECT_HEADER_priv_mask   0x00000001
3904#define SDMA_PKT_INDIRECT_HEADER_priv_shift  31
3905#define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift)
3906
3907/*define for BASE_LO word*/
3908/*define for ib_base_31_0 field*/
3909#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1
3910#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask   0xFFFFFFFF
3911#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift  0
3912#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)
3913
3914/*define for BASE_HI word*/
3915/*define for ib_base_63_32 field*/
3916#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2
3917#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask   0xFFFFFFFF
3918#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift  0
3919#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)
3920
3921/*define for IB_SIZE word*/
3922/*define for ib_size field*/
3923#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3
3924#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask   0x000FFFFF
3925#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift  0
3926#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)
3927
3928/*define for CSA_ADDR_LO word*/
3929/*define for csa_addr_31_0 field*/
3930#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4
3931#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask   0xFFFFFFFF
3932#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift  0
3933#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)
3934
3935/*define for CSA_ADDR_HI word*/
3936/*define for csa_addr_63_32 field*/
3937#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5
3938#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask   0xFFFFFFFF
3939#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift  0
3940#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)
3941
3942
3943/*
3944** Definitions for SDMA_PKT_SEMAPHORE packet
3945*/
3946
3947/*define for HEADER word*/
3948/*define for op field*/
3949#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
3950#define SDMA_PKT_SEMAPHORE_HEADER_op_mask   0x000000FF
3951#define SDMA_PKT_SEMAPHORE_HEADER_op_shift  0
3952#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)
3953
3954/*define for sub_op field*/
3955#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
3956#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask   0x000000FF
3957#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift  8
3958#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)
3959
3960/*define for write_one field*/
3961#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
3962#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask   0x00000001
3963#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift  29
3964#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)
3965
3966/*define for signal field*/
3967#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
3968#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask   0x00000001
3969#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift  30
3970#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)
3971
3972/*define for mailbox field*/
3973#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
3974#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask   0x00000001
3975#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift  31
3976#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)
3977
3978/*define for ADDR_LO word*/
3979/*define for addr_31_0 field*/
3980#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1
3981#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3982#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift  0
3983#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)
3984
3985/*define for ADDR_HI word*/
3986/*define for addr_63_32 field*/
3987#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2
3988#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3989#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift  0
3990#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)
3991
3992
3993/*
3994** Definitions for SDMA_PKT_MEM_INCR packet
3995*/
3996
3997/*define for HEADER word*/
3998/*define for op field*/
3999#define SDMA_PKT_MEM_INCR_HEADER_op_offset 0
4000#define SDMA_PKT_MEM_INCR_HEADER_op_mask   0x000000FF
4001#define SDMA_PKT_MEM_INCR_HEADER_op_shift  0
4002#define SDMA_PKT_MEM_INCR_HEADER_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift)
4003
4004/*define for sub_op field*/
4005#define SDMA_PKT_MEM_INCR_HEADER_sub_op_offset 0
4006#define SDMA_PKT_MEM_INCR_HEADER_sub_op_mask   0x000000FF
4007#define SDMA_PKT_MEM_INCR_HEADER_sub_op_shift  8
4008#define SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift)
4009
4010/*define for l2_policy field*/
4011#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset 0
4012#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask   0x00000003
4013#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift  24
4014#define SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift)
4015
4016/*define for llc_policy field*/
4017#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset 0
4018#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask   0x00000001
4019#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift  26
4020#define SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift)
4021
4022/*define for cpv field*/
4023#define SDMA_PKT_MEM_INCR_HEADER_cpv_offset 0
4024#define SDMA_PKT_MEM_INCR_HEADER_cpv_mask   0x00000001
4025#define SDMA_PKT_MEM_INCR_HEADER_cpv_shift  28
4026#define SDMA_PKT_MEM_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift)
4027
4028/*define for ADDR_LO word*/
4029/*define for addr_31_0 field*/
4030#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset 1
4031#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4032#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift  0
4033#define SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift)
4034
4035/*define for ADDR_HI word*/
4036/*define for addr_63_32 field*/
4037#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset 2
4038#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4039#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift  0
4040#define SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift)
4041
4042
4043/*
4044** Definitions for SDMA_PKT_VM_INVALIDATION packet
4045*/
4046
4047/*define for HEADER word*/
4048/*define for op field*/
4049#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0
4050#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask   0x000000FF
4051#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift  0
4052#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift)
4053
4054/*define for sub_op field*/
4055#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0
4056#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask   0x000000FF
4057#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift  8
4058#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift)
4059
4060/*define for gfx_eng_id field*/
4061#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0
4062#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask   0x0000001F
4063#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift  16
4064#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift)
4065
4066/*define for mm_eng_id field*/
4067#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0
4068#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask   0x0000001F
4069#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift  24
4070#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift)
4071
4072/*define for INVALIDATEREQ word*/
4073/*define for invalidatereq field*/
4074#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1
4075#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask   0xFFFFFFFF
4076#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift  0
4077#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift)
4078
4079/*define for ADDRESSRANGELO word*/
4080/*define for addressrangelo field*/
4081#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2
4082#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask   0xFFFFFFFF
4083#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift  0
4084#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift)
4085
4086/*define for ADDRESSRANGEHI word*/
4087/*define for invalidateack field*/
4088#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3
4089#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask   0x0000FFFF
4090#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift  0
4091#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift)
4092
4093/*define for addressrangehi field*/
4094#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3
4095#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask   0x0000001F
4096#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift  16
4097#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift)
4098
4099/*define for reserved field*/
4100#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3
4101#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask   0x000001FF
4102#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift  23
4103#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift)
4104
4105
4106/*
4107** Definitions for SDMA_PKT_FENCE packet
4108*/
4109
4110/*define for HEADER word*/
4111/*define for op field*/
4112#define SDMA_PKT_FENCE_HEADER_op_offset 0
4113#define SDMA_PKT_FENCE_HEADER_op_mask   0x000000FF
4114#define SDMA_PKT_FENCE_HEADER_op_shift  0
4115#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)
4116
4117/*define for sub_op field*/
4118#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
4119#define SDMA_PKT_FENCE_HEADER_sub_op_mask   0x000000FF
4120#define SDMA_PKT_FENCE_HEADER_sub_op_shift  8
4121#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)
4122
4123/*define for mtype field*/
4124#define SDMA_PKT_FENCE_HEADER_mtype_offset 0
4125#define SDMA_PKT_FENCE_HEADER_mtype_mask   0x00000007
4126#define SDMA_PKT_FENCE_HEADER_mtype_shift  16
4127#define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift)
4128
4129/*define for gcc field*/
4130#define SDMA_PKT_FENCE_HEADER_gcc_offset 0
4131#define SDMA_PKT_FENCE_HEADER_gcc_mask   0x00000001
4132#define SDMA_PKT_FENCE_HEADER_gcc_shift  19
4133#define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift)
4134
4135/*define for sys field*/
4136#define SDMA_PKT_FENCE_HEADER_sys_offset 0
4137#define SDMA_PKT_FENCE_HEADER_sys_mask   0x00000001
4138#define SDMA_PKT_FENCE_HEADER_sys_shift  20
4139#define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift)
4140
4141/*define for snp field*/
4142#define SDMA_PKT_FENCE_HEADER_snp_offset 0
4143#define SDMA_PKT_FENCE_HEADER_snp_mask   0x00000001
4144#define SDMA_PKT_FENCE_HEADER_snp_shift  22
4145#define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift)
4146
4147/*define for gpa field*/
4148#define SDMA_PKT_FENCE_HEADER_gpa_offset 0
4149#define SDMA_PKT_FENCE_HEADER_gpa_mask   0x00000001
4150#define SDMA_PKT_FENCE_HEADER_gpa_shift  23
4151#define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift)
4152
4153/*define for l2_policy field*/
4154#define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0
4155#define SDMA_PKT_FENCE_HEADER_l2_policy_mask   0x00000003
4156#define SDMA_PKT_FENCE_HEADER_l2_policy_shift  24
4157#define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift)
4158
4159/*define for llc_policy field*/
4160#define SDMA_PKT_FENCE_HEADER_llc_policy_offset 0
4161#define SDMA_PKT_FENCE_HEADER_llc_policy_mask   0x00000001
4162#define SDMA_PKT_FENCE_HEADER_llc_policy_shift  26
4163#define SDMA_PKT_FENCE_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift)
4164
4165/*define for cpv field*/
4166#define SDMA_PKT_FENCE_HEADER_cpv_offset 0
4167#define SDMA_PKT_FENCE_HEADER_cpv_mask   0x00000001
4168#define SDMA_PKT_FENCE_HEADER_cpv_shift  28
4169#define SDMA_PKT_FENCE_HEADER_CPV(x) (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift)
4170
4171/*define for ADDR_LO word*/
4172/*define for addr_31_0 field*/
4173#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1
4174#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4175#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift  0
4176#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)
4177
4178/*define for ADDR_HI word*/
4179/*define for addr_63_32 field*/
4180#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2
4181#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4182#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift  0
4183#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)
4184
4185/*define for DATA word*/
4186/*define for data field*/
4187#define SDMA_PKT_FENCE_DATA_data_offset 3
4188#define SDMA_PKT_FENCE_DATA_data_mask   0xFFFFFFFF
4189#define SDMA_PKT_FENCE_DATA_data_shift  0
4190#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)
4191
4192
4193/*
4194** Definitions for SDMA_PKT_SRBM_WRITE packet
4195*/
4196
4197/*define for HEADER word*/
4198/*define for op field*/
4199#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
4200#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask   0x000000FF
4201#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift  0
4202#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)
4203
4204/*define for sub_op field*/
4205#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
4206#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask   0x000000FF
4207#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift  8
4208#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)
4209
4210/*define for byte_en field*/
4211#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
4212#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask   0x0000000F
4213#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift  28
4214#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)
4215
4216/*define for ADDR word*/
4217/*define for addr field*/
4218#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1
4219#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask   0x0003FFFF
4220#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift  0
4221#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)
4222
4223/*define for apertureid field*/
4224#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1
4225#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask   0x00000FFF
4226#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift  20
4227#define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift)
4228
4229/*define for DATA word*/
4230/*define for data field*/
4231#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2
4232#define SDMA_PKT_SRBM_WRITE_DATA_data_mask   0xFFFFFFFF
4233#define SDMA_PKT_SRBM_WRITE_DATA_data_shift  0
4234#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)
4235
4236
4237/*
4238** Definitions for SDMA_PKT_PRE_EXE packet
4239*/
4240
4241/*define for HEADER word*/
4242/*define for op field*/
4243#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
4244#define SDMA_PKT_PRE_EXE_HEADER_op_mask   0x000000FF
4245#define SDMA_PKT_PRE_EXE_HEADER_op_shift  0
4246#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)
4247
4248/*define for sub_op field*/
4249#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
4250#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask   0x000000FF
4251#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift  8
4252#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)
4253
4254/*define for dev_sel field*/
4255#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
4256#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask   0x000000FF
4257#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift  16
4258#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)
4259
4260/*define for EXEC_COUNT word*/
4261/*define for exec_count field*/
4262#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1
4263#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
4264#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift  0
4265#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)
4266
4267
4268/*
4269** Definitions for SDMA_PKT_COND_EXE packet
4270*/
4271
4272/*define for HEADER word*/
4273/*define for op field*/
4274#define SDMA_PKT_COND_EXE_HEADER_op_offset 0
4275#define SDMA_PKT_COND_EXE_HEADER_op_mask   0x000000FF
4276#define SDMA_PKT_COND_EXE_HEADER_op_shift  0
4277#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)
4278
4279/*define for sub_op field*/
4280#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
4281#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask   0x000000FF
4282#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift  8
4283#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)
4284
4285/*define for cache_policy field*/
4286#define SDMA_PKT_COND_EXE_HEADER_cache_policy_offset 0
4287#define SDMA_PKT_COND_EXE_HEADER_cache_policy_mask   0x00000007
4288#define SDMA_PKT_COND_EXE_HEADER_cache_policy_shift  24
4289#define SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift)
4290
4291/*define for cpv field*/
4292#define SDMA_PKT_COND_EXE_HEADER_cpv_offset 0
4293#define SDMA_PKT_COND_EXE_HEADER_cpv_mask   0x00000001
4294#define SDMA_PKT_COND_EXE_HEADER_cpv_shift  28
4295#define SDMA_PKT_COND_EXE_HEADER_CPV(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift)
4296
4297/*define for ADDR_LO word*/
4298/*define for addr_31_0 field*/
4299#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1
4300#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4301#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift  0
4302#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)
4303
4304/*define for ADDR_HI word*/
4305/*define for addr_63_32 field*/
4306#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2
4307#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4308#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift  0
4309#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)
4310
4311/*define for REFERENCE word*/
4312/*define for reference field*/
4313#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3
4314#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask   0xFFFFFFFF
4315#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift  0
4316#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)
4317
4318/*define for EXEC_COUNT word*/
4319/*define for exec_count field*/
4320#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4
4321#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
4322#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift  0
4323#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)
4324
4325
4326/*
4327** Definitions for SDMA_PKT_CONSTANT_FILL packet
4328*/
4329
4330/*define for HEADER word*/
4331/*define for op field*/
4332#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
4333#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask   0x000000FF
4334#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift  0
4335#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)
4336
4337/*define for sub_op field*/
4338#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
4339#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask   0x000000FF
4340#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift  8
4341#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)
4342
4343/*define for sw field*/
4344#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
4345#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask   0x00000003
4346#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift  16
4347#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)
4348
4349/*define for cache_policy field*/
4350#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset 0
4351#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask   0x00000007
4352#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift  24
4353#define SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift)
4354
4355/*define for cpv field*/
4356#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset 0
4357#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask   0x00000001
4358#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift  28
4359#define SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift)
4360
4361/*define for fillsize field*/
4362#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
4363#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask   0x00000003
4364#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift  30
4365#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)
4366
4367/*define for DST_ADDR_LO word*/
4368/*define for dst_addr_31_0 field*/
4369#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1
4370#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
4371#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift  0
4372#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)
4373
4374/*define for DST_ADDR_HI word*/
4375/*define for dst_addr_63_32 field*/
4376#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2
4377#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
4378#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift  0
4379#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)
4380
4381/*define for DATA word*/
4382/*define for src_data_31_0 field*/
4383#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3
4384#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask   0xFFFFFFFF
4385#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift  0
4386#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)
4387
4388/*define for COUNT word*/
4389/*define for count field*/
4390#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4
4391#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask   0x3FFFFFFF
4392#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift  0
4393#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)
4394
4395
4396/*
4397** Definitions for SDMA_PKT_DATA_FILL_MULTI packet
4398*/
4399
4400/*define for HEADER word*/
4401/*define for op field*/
4402#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0
4403#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask   0x000000FF
4404#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift  0
4405#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift)
4406
4407/*define for sub_op field*/
4408#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0
4409#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask   0x000000FF
4410#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift  8
4411#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift)
4412
4413/*define for cache_policy field*/
4414#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset 0
4415#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask   0x00000007
4416#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift  24
4417#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift)
4418
4419/*define for cpv field*/
4420#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset 0
4421#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask   0x00000001
4422#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift  28
4423#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift)
4424
4425/*define for memlog_clr field*/
4426#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0
4427#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask   0x00000001
4428#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift  31
4429#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift)
4430
4431/*define for BYTE_STRIDE word*/
4432/*define for byte_stride field*/
4433#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1
4434#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask   0xFFFFFFFF
4435#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift  0
4436#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift)
4437
4438/*define for DMA_COUNT word*/
4439/*define for dma_count field*/
4440#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2
4441#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask   0xFFFFFFFF
4442#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift  0
4443#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift)
4444
4445/*define for DST_ADDR_LO word*/
4446/*define for dst_addr_31_0 field*/
4447#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3
4448#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
4449#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift  0
4450#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift)
4451
4452/*define for DST_ADDR_HI word*/
4453/*define for dst_addr_63_32 field*/
4454#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4
4455#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
4456#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift  0
4457#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift)
4458
4459/*define for BYTE_COUNT word*/
4460/*define for count field*/
4461#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5
4462#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask   0x03FFFFFF
4463#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift  0
4464#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift)
4465
4466
4467/*
4468** Definitions for SDMA_PKT_POLL_REGMEM packet
4469*/
4470
4471/*define for HEADER word*/
4472/*define for op field*/
4473#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
4474#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask   0x000000FF
4475#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift  0
4476#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)
4477
4478/*define for sub_op field*/
4479#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
4480#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask   0x000000FF
4481#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift  8
4482#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)
4483
4484/*define for cache_policy field*/
4485#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset 0
4486#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask   0x00000007
4487#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift  20
4488#define SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift)
4489
4490/*define for cpv field*/
4491#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset 0
4492#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask   0x00000001
4493#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift  24
4494#define SDMA_PKT_POLL_REGMEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift)
4495
4496/*define for hdp_flush field*/
4497#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
4498#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask   0x00000001
4499#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift  26
4500#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)
4501
4502/*define for func field*/
4503#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
4504#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask   0x00000007
4505#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift  28
4506#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)
4507
4508/*define for mem_poll field*/
4509#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
4510#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask   0x00000001
4511#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift  31
4512#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)
4513
4514/*define for ADDR_LO word*/
4515/*define for addr_31_0 field*/
4516#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1
4517#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4518#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift  0
4519#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)
4520
4521/*define for ADDR_HI word*/
4522/*define for addr_63_32 field*/
4523#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2
4524#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4525#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift  0
4526#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)
4527
4528/*define for VALUE word*/
4529/*define for value field*/
4530#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3
4531#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask   0xFFFFFFFF
4532#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift  0
4533#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)
4534
4535/*define for MASK word*/
4536/*define for mask field*/
4537#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4
4538#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask   0xFFFFFFFF
4539#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift  0
4540#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)
4541
4542/*define for DW5 word*/
4543/*define for interval field*/
4544#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5
4545#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask   0x0000FFFF
4546#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift  0
4547#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)
4548
4549/*define for retry_count field*/
4550#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5
4551#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask   0x00000FFF
4552#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift  16
4553#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)
4554
4555
4556/*
4557** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet
4558*/
4559
4560/*define for HEADER word*/
4561/*define for op field*/
4562#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0
4563#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask   0x000000FF
4564#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift  0
4565#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift)
4566
4567/*define for sub_op field*/
4568#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0
4569#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask   0x000000FF
4570#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift  8
4571#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift)
4572
4573/*define for cache_policy field*/
4574#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset 0
4575#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask   0x00000007
4576#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift  24
4577#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift)
4578
4579/*define for cpv field*/
4580#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset 0
4581#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask   0x00000001
4582#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift  28
4583#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift)
4584
4585/*define for SRC_ADDR word*/
4586/*define for addr_31_2 field*/
4587#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1
4588#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask   0x3FFFFFFF
4589#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift  2
4590#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift)
4591
4592/*define for DST_ADDR_LO word*/
4593/*define for addr_31_0 field*/
4594#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2
4595#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4596#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift  0
4597#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)
4598
4599/*define for DST_ADDR_HI word*/
4600/*define for addr_63_32 field*/
4601#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3
4602#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4603#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift  0
4604#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)
4605
4606
4607/*
4608** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet
4609*/
4610
4611/*define for HEADER word*/
4612/*define for op field*/
4613#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0
4614#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask   0x000000FF
4615#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift  0
4616#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift)
4617
4618/*define for sub_op field*/
4619#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0
4620#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask   0x000000FF
4621#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift  8
4622#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift)
4623
4624/*define for ea field*/
4625#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0
4626#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask   0x00000003
4627#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift  16
4628#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift)
4629
4630/*define for cache_policy field*/
4631#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset 0
4632#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask   0x00000007
4633#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift  24
4634#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift)
4635
4636/*define for cpv field*/
4637#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset 0
4638#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask   0x00000001
4639#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift  28
4640#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift)
4641
4642/*define for DST_ADDR_LO word*/
4643/*define for addr_31_0 field*/
4644#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1
4645#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4646#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift  0
4647#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)
4648
4649/*define for DST_ADDR_HI word*/
4650/*define for addr_63_32 field*/
4651#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2
4652#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4653#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift  0
4654#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)
4655
4656/*define for START_PAGE word*/
4657/*define for addr_31_4 field*/
4658#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3
4659#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask   0x0FFFFFFF
4660#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift  4
4661#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift)
4662
4663/*define for PAGE_NUM word*/
4664/*define for page_num_31_0 field*/
4665#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4
4666#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask   0xFFFFFFFF
4667#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift  0
4668#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift)
4669
4670
4671/*
4672** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet
4673*/
4674
4675/*define for HEADER word*/
4676/*define for op field*/
4677#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0
4678#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask   0x000000FF
4679#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift  0
4680#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift)
4681
4682/*define for sub_op field*/
4683#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0
4684#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask   0x000000FF
4685#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift  8
4686#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift)
4687
4688/*define for cache_policy field*/
4689#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset 0
4690#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask   0x00000007
4691#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift  24
4692#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift)
4693
4694/*define for cpv field*/
4695#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset 0
4696#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask   0x00000001
4697#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift  28
4698#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift)
4699
4700/*define for mode field*/
4701#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0
4702#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask   0x00000001
4703#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift  31
4704#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift)
4705
4706/*define for PATTERN word*/
4707/*define for pattern field*/
4708#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1
4709#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask   0xFFFFFFFF
4710#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift  0
4711#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift)
4712
4713/*define for CMP0_ADDR_START_LO word*/
4714/*define for cmp0_start_31_0 field*/
4715#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2
4716#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask   0xFFFFFFFF
4717#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift  0
4718#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift)
4719
4720/*define for CMP0_ADDR_START_HI word*/
4721/*define for cmp0_start_63_32 field*/
4722#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3
4723#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask   0xFFFFFFFF
4724#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift  0
4725#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift)
4726
4727/*define for CMP0_ADDR_END_LO word*/
4728/*define for cmp0_end_31_0 field*/
4729#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset 4
4730#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask   0xFFFFFFFF
4731#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift  0
4732#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift)
4733
4734/*define for CMP0_ADDR_END_HI word*/
4735/*define for cmp0_end_63_32 field*/
4736#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset 5
4737#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask   0xFFFFFFFF
4738#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift  0
4739#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift)
4740
4741/*define for CMP1_ADDR_START_LO word*/
4742/*define for cmp1_start_31_0 field*/
4743#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6
4744#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask   0xFFFFFFFF
4745#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift  0
4746#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift)
4747
4748/*define for CMP1_ADDR_START_HI word*/
4749/*define for cmp1_start_63_32 field*/
4750#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7
4751#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask   0xFFFFFFFF
4752#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift  0
4753#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift)
4754
4755/*define for CMP1_ADDR_END_LO word*/
4756/*define for cmp1_end_31_0 field*/
4757#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8
4758#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask   0xFFFFFFFF
4759#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift  0
4760#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift)
4761
4762/*define for CMP1_ADDR_END_HI word*/
4763/*define for cmp1_end_63_32 field*/
4764#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9
4765#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask   0xFFFFFFFF
4766#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift  0
4767#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift)
4768
4769/*define for REC_ADDR_LO word*/
4770/*define for rec_31_0 field*/
4771#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10
4772#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask   0xFFFFFFFF
4773#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift  0
4774#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift)
4775
4776/*define for REC_ADDR_HI word*/
4777/*define for rec_63_32 field*/
4778#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11
4779#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask   0xFFFFFFFF
4780#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift  0
4781#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift)
4782
4783/*define for RESERVED word*/
4784/*define for reserved field*/
4785#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12
4786#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask   0xFFFFFFFF
4787#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift  0
4788#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift)
4789
4790
4791/*
4792** Definitions for SDMA_PKT_ATOMIC packet
4793*/
4794
4795/*define for HEADER word*/
4796/*define for op field*/
4797#define SDMA_PKT_ATOMIC_HEADER_op_offset 0
4798#define SDMA_PKT_ATOMIC_HEADER_op_mask   0x000000FF
4799#define SDMA_PKT_ATOMIC_HEADER_op_shift  0
4800#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift)
4801
4802/*define for loop field*/
4803#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
4804#define SDMA_PKT_ATOMIC_HEADER_loop_mask   0x00000001
4805#define SDMA_PKT_ATOMIC_HEADER_loop_shift  16
4806#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift)
4807
4808/*define for tmz field*/
4809#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0
4810#define SDMA_PKT_ATOMIC_HEADER_tmz_mask   0x00000001
4811#define SDMA_PKT_ATOMIC_HEADER_tmz_shift  18
4812#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift)
4813
4814/*define for cache_policy field*/
4815#define SDMA_PKT_ATOMIC_HEADER_cache_policy_offset 0
4816#define SDMA_PKT_ATOMIC_HEADER_cache_policy_mask   0x00000007
4817#define SDMA_PKT_ATOMIC_HEADER_cache_policy_shift  20
4818#define SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift)
4819
4820/*define for cpv field*/
4821#define SDMA_PKT_ATOMIC_HEADER_cpv_offset 0
4822#define SDMA_PKT_ATOMIC_HEADER_cpv_mask   0x00000001
4823#define SDMA_PKT_ATOMIC_HEADER_cpv_shift  24
4824#define SDMA_PKT_ATOMIC_HEADER_CPV(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift)
4825
4826/*define for atomic_op field*/
4827#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
4828#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask   0x0000007F
4829#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift  25
4830#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift)
4831
4832/*define for ADDR_LO word*/
4833/*define for addr_31_0 field*/
4834#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1
4835#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4836#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift  0
4837#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift)
4838
4839/*define for ADDR_HI word*/
4840/*define for addr_63_32 field*/
4841#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2
4842#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4843#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift  0
4844#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift)
4845
4846/*define for SRC_DATA_LO word*/
4847/*define for src_data_31_0 field*/
4848#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3
4849#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask   0xFFFFFFFF
4850#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift  0
4851#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift)
4852
4853/*define for SRC_DATA_HI word*/
4854/*define for src_data_63_32 field*/
4855#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4
4856#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask   0xFFFFFFFF
4857#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift  0
4858#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift)
4859
4860/*define for CMP_DATA_LO word*/
4861/*define for cmp_data_31_0 field*/
4862#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5
4863#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask   0xFFFFFFFF
4864#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift  0
4865#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift)
4866
4867/*define for CMP_DATA_HI word*/
4868/*define for cmp_data_63_32 field*/
4869#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6
4870#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask   0xFFFFFFFF
4871#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift  0
4872#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift)
4873
4874/*define for LOOP_INTERVAL word*/
4875/*define for loop_interval field*/
4876#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7
4877#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask   0x00001FFF
4878#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift  0
4879#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift)
4880
4881
4882/*
4883** Definitions for SDMA_PKT_TIMESTAMP_SET packet
4884*/
4885
4886/*define for HEADER word*/
4887/*define for op field*/
4888#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
4889#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask   0x000000FF
4890#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift  0
4891#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)
4892
4893/*define for sub_op field*/
4894#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
4895#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask   0x000000FF
4896#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift  8
4897#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)
4898
4899/*define for INIT_DATA_LO word*/
4900/*define for init_data_31_0 field*/
4901#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1
4902#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask   0xFFFFFFFF
4903#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift  0
4904#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)
4905
4906/*define for INIT_DATA_HI word*/
4907/*define for init_data_63_32 field*/
4908#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2
4909#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask   0xFFFFFFFF
4910#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift  0
4911#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)
4912
4913
4914/*
4915** Definitions for SDMA_PKT_TIMESTAMP_GET packet
4916*/
4917
4918/*define for HEADER word*/
4919/*define for op field*/
4920#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
4921#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask   0x000000FF
4922#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift  0
4923#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)
4924
4925/*define for sub_op field*/
4926#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
4927#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask   0x000000FF
4928#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift  8
4929#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)
4930
4931/*define for l2_policy field*/
4932#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset 0
4933#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask   0x00000003
4934#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift  24
4935#define SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift)
4936
4937/*define for llc_policy field*/
4938#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset 0
4939#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask   0x00000001
4940#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift  26
4941#define SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift)
4942
4943/*define for cpv field*/
4944#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset 0
4945#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask   0x00000001
4946#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift  28
4947#define SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift)
4948
4949/*define for WRITE_ADDR_LO word*/
4950/*define for write_addr_31_3 field*/
4951#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1
4952#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
4953#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift  3
4954#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)
4955
4956/*define for WRITE_ADDR_HI word*/
4957/*define for write_addr_63_32 field*/
4958#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2
4959#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
4960#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift  0
4961#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)
4962
4963
4964/*
4965** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet
4966*/
4967
4968/*define for HEADER word*/
4969/*define for op field*/
4970#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
4971#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask   0x000000FF
4972#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift  0
4973#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)
4974
4975/*define for sub_op field*/
4976#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
4977#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask   0x000000FF
4978#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift  8
4979#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)
4980
4981/*define for l2_policy field*/
4982#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset 0
4983#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask   0x00000003
4984#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift  24
4985#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift)
4986
4987/*define for llc_policy field*/
4988#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset 0
4989#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask   0x00000001
4990#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift  26
4991#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift)
4992
4993/*define for cpv field*/
4994#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset 0
4995#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask   0x00000001
4996#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift  28
4997#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift)
4998
4999/*define for WRITE_ADDR_LO word*/
5000/*define for write_addr_31_3 field*/
5001#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1
5002#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
5003#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift  3
5004#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)
5005
5006/*define for WRITE_ADDR_HI word*/
5007/*define for write_addr_63_32 field*/
5008#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2
5009#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
5010#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift  0
5011#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)
5012
5013
5014/*
5015** Definitions for SDMA_PKT_TRAP packet
5016*/
5017
5018/*define for HEADER word*/
5019/*define for op field*/
5020#define SDMA_PKT_TRAP_HEADER_op_offset 0
5021#define SDMA_PKT_TRAP_HEADER_op_mask   0x000000FF
5022#define SDMA_PKT_TRAP_HEADER_op_shift  0
5023#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)
5024
5025/*define for sub_op field*/
5026#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
5027#define SDMA_PKT_TRAP_HEADER_sub_op_mask   0x000000FF
5028#define SDMA_PKT_TRAP_HEADER_sub_op_shift  8
5029#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)
5030
5031/*define for INT_CONTEXT word*/
5032/*define for int_context field*/
5033#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1
5034#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
5035#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift  0
5036#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)
5037
5038
5039/*
5040** Definitions for SDMA_PKT_DUMMY_TRAP packet
5041*/
5042
5043/*define for HEADER word*/
5044/*define for op field*/
5045#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0
5046#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask   0x000000FF
5047#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift  0
5048#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift)
5049
5050/*define for sub_op field*/
5051#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0
5052#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask   0x000000FF
5053#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift  8
5054#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift)
5055
5056/*define for INT_CONTEXT word*/
5057/*define for int_context field*/
5058#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1
5059#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
5060#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift  0
5061#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift)
5062
5063
5064/*
5065** Definitions for SDMA_PKT_GPUVM_INV packet
5066*/
5067
5068/*define for HEADER word*/
5069/*define for op field*/
5070#define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0
5071#define SDMA_PKT_GPUVM_INV_HEADER_op_mask   0x000000FF
5072#define SDMA_PKT_GPUVM_INV_HEADER_op_shift  0
5073#define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift)
5074
5075/*define for sub_op field*/
5076#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0
5077#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask   0x000000FF
5078#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift  8
5079#define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift)
5080
5081/*define for PAYLOAD1 word*/
5082/*define for per_vmid_inv_req field*/
5083#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1
5084#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask   0x0000FFFF
5085#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift  0
5086#define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift)
5087
5088/*define for flush_type field*/
5089#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1
5090#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask   0x00000007
5091#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift  16
5092#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift)
5093
5094/*define for l2_ptes field*/
5095#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1
5096#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask   0x00000001
5097#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift  19
5098#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift)
5099
5100/*define for l2_pde0 field*/
5101#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1
5102#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask   0x00000001
5103#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift  20
5104#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift)
5105
5106/*define for l2_pde1 field*/
5107#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1
5108#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask   0x00000001
5109#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift  21
5110#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift)
5111
5112/*define for l2_pde2 field*/
5113#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1
5114#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask   0x00000001
5115#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift  22
5116#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift)
5117
5118/*define for l1_ptes field*/
5119#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1
5120#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask   0x00000001
5121#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift  23
5122#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift)
5123
5124/*define for clr_protection_fault_status_addr field*/
5125#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1
5126#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask   0x00000001
5127#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift  24
5128#define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift)
5129
5130/*define for log_request field*/
5131#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1
5132#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask   0x00000001
5133#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift  25
5134#define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift)
5135
5136/*define for four_kilobytes field*/
5137#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1
5138#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask   0x00000001
5139#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift  26
5140#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift)
5141
5142/*define for PAYLOAD2 word*/
5143/*define for s field*/
5144#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2
5145#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask   0x00000001
5146#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift  0
5147#define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift)
5148
5149/*define for page_va_42_12 field*/
5150#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2
5151#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask   0x7FFFFFFF
5152#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift  1
5153#define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift)
5154
5155/*define for PAYLOAD3 word*/
5156/*define for page_va_47_43 field*/
5157#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3
5158#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask   0x0000003F
5159#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift  0
5160#define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift)
5161
5162
5163/*
5164** Definitions for SDMA_PKT_GCR_REQ packet
5165*/
5166
5167/*define for HEADER word*/
5168/*define for op field*/
5169#define SDMA_PKT_GCR_REQ_HEADER_op_offset 0
5170#define SDMA_PKT_GCR_REQ_HEADER_op_mask   0x000000FF
5171#define SDMA_PKT_GCR_REQ_HEADER_op_shift  0
5172#define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift)
5173
5174/*define for sub_op field*/
5175#define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0
5176#define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask   0x000000FF
5177#define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift  8
5178#define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift)
5179
5180/*define for PAYLOAD1 word*/
5181/*define for base_va_31_7 field*/
5182#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1
5183#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask   0x01FFFFFF
5184#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift  7
5185#define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift)
5186
5187/*define for PAYLOAD2 word*/
5188/*define for base_va_47_32 field*/
5189#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2
5190#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask   0x0000FFFF
5191#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift  0
5192#define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift)
5193
5194/*define for gcr_control_15_0 field*/
5195#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2
5196#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask   0x0000FFFF
5197#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift  16
5198#define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift)
5199
5200/*define for PAYLOAD3 word*/
5201/*define for gcr_control_18_16 field*/
5202#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3
5203#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask   0x00000007
5204#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift  0
5205#define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift)
5206
5207/*define for limit_va_31_7 field*/
5208#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3
5209#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask   0x01FFFFFF
5210#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift  7
5211#define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift)
5212
5213/*define for PAYLOAD4 word*/
5214/*define for limit_va_47_32 field*/
5215#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4
5216#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask   0x0000FFFF
5217#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift  0
5218#define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift)
5219
5220/*define for vmid field*/
5221#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4
5222#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask   0x0000000F
5223#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift  24
5224#define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift)
5225
5226
5227/*
5228** Definitions for SDMA_PKT_NOP packet
5229*/
5230
5231/*define for HEADER word*/
5232/*define for op field*/
5233#define SDMA_PKT_NOP_HEADER_op_offset 0
5234#define SDMA_PKT_NOP_HEADER_op_mask   0x000000FF
5235#define SDMA_PKT_NOP_HEADER_op_shift  0
5236#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)
5237
5238/*define for sub_op field*/
5239#define SDMA_PKT_NOP_HEADER_sub_op_offset 0
5240#define SDMA_PKT_NOP_HEADER_sub_op_mask   0x000000FF
5241#define SDMA_PKT_NOP_HEADER_sub_op_shift  8
5242#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)
5243
5244/*define for count field*/
5245#define SDMA_PKT_NOP_HEADER_count_offset 0
5246#define SDMA_PKT_NOP_HEADER_count_mask   0x00003FFF
5247#define SDMA_PKT_NOP_HEADER_count_shift  16
5248#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift)
5249
5250/*define for DATA0 word*/
5251/*define for data0 field*/
5252#define SDMA_PKT_NOP_DATA0_data0_offset 1
5253#define SDMA_PKT_NOP_DATA0_data0_mask   0xFFFFFFFF
5254#define SDMA_PKT_NOP_DATA0_data0_shift  0
5255#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift)
5256
5257
5258/*
5259** Definitions for SDMA_AQL_PKT_HEADER packet
5260*/
5261
5262/*define for HEADER word*/
5263/*define for format field*/
5264#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0
5265#define SDMA_AQL_PKT_HEADER_HEADER_format_mask   0x000000FF
5266#define SDMA_AQL_PKT_HEADER_HEADER_format_shift  0
5267#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift)
5268
5269/*define for barrier field*/
5270#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0
5271#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask   0x00000001
5272#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift  8
5273#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift)
5274
5275/*define for acquire_fence_scope field*/
5276#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0
5277#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask   0x00000003
5278#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift  9
5279#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift)
5280
5281/*define for release_fence_scope field*/
5282#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0
5283#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask   0x00000003
5284#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift  11
5285#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift)
5286
5287/*define for reserved field*/
5288#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0
5289#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask   0x00000007
5290#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift  13
5291#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift)
5292
5293/*define for op field*/
5294#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0
5295#define SDMA_AQL_PKT_HEADER_HEADER_op_mask   0x0000000F
5296#define SDMA_AQL_PKT_HEADER_HEADER_op_shift  16
5297#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift)
5298
5299/*define for subop field*/
5300#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0
5301#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask   0x00000007
5302#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift  20
5303#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift)
5304
5305/*define for cpv field*/
5306#define SDMA_AQL_PKT_HEADER_HEADER_cpv_offset 0
5307#define SDMA_AQL_PKT_HEADER_HEADER_cpv_mask   0x00000001
5308#define SDMA_AQL_PKT_HEADER_HEADER_cpv_shift  28
5309#define SDMA_AQL_PKT_HEADER_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift)
5310
5311
5312/*
5313** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet
5314*/
5315
5316/*define for HEADER word*/
5317/*define for format field*/
5318#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0
5319#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask   0x000000FF
5320#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift  0
5321#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift)
5322
5323/*define for barrier field*/
5324#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0
5325#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask   0x00000001
5326#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift  8
5327#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift)
5328
5329/*define for acquire_fence_scope field*/
5330#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0
5331#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask   0x00000003
5332#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift  9
5333#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift)
5334
5335/*define for release_fence_scope field*/
5336#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0
5337#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask   0x00000003
5338#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift  11
5339#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift)
5340
5341/*define for reserved field*/
5342#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0
5343#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask   0x00000007
5344#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift  13
5345#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift)
5346
5347/*define for op field*/
5348#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0
5349#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask   0x0000000F
5350#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift  16
5351#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift)
5352
5353/*define for subop field*/
5354#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0
5355#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask   0x00000007
5356#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift  20
5357#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift)
5358
5359/*define for cpv field*/
5360#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset 0
5361#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask   0x00000001
5362#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift  28
5363#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift)
5364
5365/*define for RESERVED_DW1 word*/
5366/*define for reserved_dw1 field*/
5367#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1
5368#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask   0xFFFFFFFF
5369#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift  0
5370#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift)
5371
5372/*define for RETURN_ADDR_LO word*/
5373/*define for return_addr_31_0 field*/
5374#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2
5375#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask   0xFFFFFFFF
5376#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift  0
5377#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift)
5378
5379/*define for RETURN_ADDR_HI word*/
5380/*define for return_addr_63_32 field*/
5381#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3
5382#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask   0xFFFFFFFF
5383#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift  0
5384#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift)
5385
5386/*define for COUNT word*/
5387/*define for count field*/
5388#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4
5389#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask   0x003FFFFF
5390#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift  0
5391#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift)
5392
5393/*define for PARAMETER word*/
5394/*define for dst_sw field*/
5395#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5
5396#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
5397#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift  16
5398#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
5399
5400/*define for dst_cache_policy field*/
5401#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 5
5402#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask   0x00000007
5403#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift  18
5404#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift)
5405
5406/*define for src_sw field*/
5407#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5
5408#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
5409#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift  24
5410#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
5411
5412/*define for src_cache_policy field*/
5413#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 5
5414#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask   0x00000007
5415#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift  26
5416#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift)
5417
5418/*define for SRC_ADDR_LO word*/
5419/*define for src_addr_31_0 field*/
5420#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6
5421#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
5422#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
5423#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
5424
5425/*define for SRC_ADDR_HI word*/
5426/*define for src_addr_63_32 field*/
5427#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7
5428#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
5429#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
5430#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
5431
5432/*define for DST_ADDR_LO word*/
5433/*define for dst_addr_31_0 field*/
5434#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8
5435#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
5436#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
5437#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
5438
5439/*define for DST_ADDR_HI word*/
5440/*define for dst_addr_63_32 field*/
5441#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9
5442#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
5443#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
5444#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
5445
5446/*define for RESERVED_DW10 word*/
5447/*define for reserved_dw10 field*/
5448#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10
5449#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask   0xFFFFFFFF
5450#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift  0
5451#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift)
5452
5453/*define for RESERVED_DW11 word*/
5454/*define for reserved_dw11 field*/
5455#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11
5456#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask   0xFFFFFFFF
5457#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift  0
5458#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift)
5459
5460/*define for RESERVED_DW12 word*/
5461/*define for reserved_dw12 field*/
5462#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12
5463#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask   0xFFFFFFFF
5464#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift  0
5465#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift)
5466
5467/*define for RESERVED_DW13 word*/
5468/*define for reserved_dw13 field*/
5469#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13
5470#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask   0xFFFFFFFF
5471#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift  0
5472#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift)
5473
5474/*define for COMPLETION_SIGNAL_LO word*/
5475/*define for completion_signal_31_0 field*/
5476#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14
5477#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask   0xFFFFFFFF
5478#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift  0
5479#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)
5480
5481/*define for COMPLETION_SIGNAL_HI word*/
5482/*define for completion_signal_63_32 field*/
5483#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15
5484#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask   0xFFFFFFFF
5485#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift  0
5486#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)
5487
5488
5489/*
5490** Definitions for SDMA_AQL_PKT_BARRIER_OR packet
5491*/
5492
5493/*define for HEADER word*/
5494/*define for format field*/
5495#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0
5496#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask   0x000000FF
5497#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift  0
5498#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift)
5499
5500/*define for barrier field*/
5501#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0
5502#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask   0x00000001
5503#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift  8
5504#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift)
5505
5506/*define for acquire_fence_scope field*/
5507#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0
5508#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask   0x00000003
5509#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift  9
5510#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift)
5511
5512/*define for release_fence_scope field*/
5513#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0
5514#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask   0x00000003
5515#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift  11
5516#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift)
5517
5518/*define for reserved field*/
5519#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0
5520#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask   0x00000007
5521#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift  13
5522#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift)
5523
5524/*define for op field*/
5525#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0
5526#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask   0x0000000F
5527#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift  16
5528#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift)
5529
5530/*define for subop field*/
5531#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0
5532#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask   0x00000007
5533#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift  20
5534#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift)
5535
5536/*define for cpv field*/
5537#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset 0
5538#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask   0x00000001
5539#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift  28
5540#define SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift)
5541
5542/*define for RESERVED_DW1 word*/
5543/*define for reserved_dw1 field*/
5544#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1
5545#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask   0xFFFFFFFF
5546#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift  0
5547#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift)
5548
5549/*define for DEPENDENT_ADDR_0_LO word*/
5550/*define for dependent_addr_0_31_0 field*/
5551#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2
5552#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask   0xFFFFFFFF
5553#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift  0
5554#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift)
5555
5556/*define for DEPENDENT_ADDR_0_HI word*/
5557/*define for dependent_addr_0_63_32 field*/
5558#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3
5559#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask   0xFFFFFFFF
5560#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift  0
5561#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift)
5562
5563/*define for DEPENDENT_ADDR_1_LO word*/
5564/*define for dependent_addr_1_31_0 field*/
5565#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4
5566#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask   0xFFFFFFFF
5567#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift  0
5568#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift)
5569
5570/*define for DEPENDENT_ADDR_1_HI word*/
5571/*define for dependent_addr_1_63_32 field*/
5572#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5
5573#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask   0xFFFFFFFF
5574#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift  0
5575#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift)
5576
5577/*define for DEPENDENT_ADDR_2_LO word*/
5578/*define for dependent_addr_2_31_0 field*/
5579#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6
5580#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask   0xFFFFFFFF
5581#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift  0
5582#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift)
5583
5584/*define for DEPENDENT_ADDR_2_HI word*/
5585/*define for dependent_addr_2_63_32 field*/
5586#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7
5587#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask   0xFFFFFFFF
5588#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift  0
5589#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift)
5590
5591/*define for DEPENDENT_ADDR_3_LO word*/
5592/*define for dependent_addr_3_31_0 field*/
5593#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8
5594#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask   0xFFFFFFFF
5595#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift  0
5596#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift)
5597
5598/*define for DEPENDENT_ADDR_3_HI word*/
5599/*define for dependent_addr_3_63_32 field*/
5600#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9
5601#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask   0xFFFFFFFF
5602#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift  0
5603#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift)
5604
5605/*define for DEPENDENT_ADDR_4_LO word*/
5606/*define for dependent_addr_4_31_0 field*/
5607#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10
5608#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask   0xFFFFFFFF
5609#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift  0
5610#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift)
5611
5612/*define for DEPENDENT_ADDR_4_HI word*/
5613/*define for dependent_addr_4_63_32 field*/
5614#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11
5615#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask   0xFFFFFFFF
5616#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift  0
5617#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift)
5618
5619/*define for CACHE_POLICY word*/
5620/*define for cache_policy0 field*/
5621#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset 12
5622#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask   0x00000007
5623#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift  0
5624#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift)
5625
5626/*define for cache_policy1 field*/
5627#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset 12
5628#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask   0x00000007
5629#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift  5
5630#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift)
5631
5632/*define for cache_policy2 field*/
5633#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset 12
5634#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask   0x00000007
5635#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift  10
5636#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift)
5637
5638/*define for cache_policy3 field*/
5639#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset 12
5640#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask   0x00000007
5641#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift  15
5642#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift)
5643
5644/*define for cache_policy4 field*/
5645#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset 12
5646#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask   0x00000007
5647#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift  20
5648#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift)
5649
5650/*define for RESERVED_DW13 word*/
5651/*define for reserved_dw13 field*/
5652#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13
5653#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask   0xFFFFFFFF
5654#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift  0
5655#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift)
5656
5657/*define for COMPLETION_SIGNAL_LO word*/
5658/*define for completion_signal_31_0 field*/
5659#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14
5660#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask   0xFFFFFFFF
5661#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift  0
5662#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)
5663
5664/*define for COMPLETION_SIGNAL_HI word*/
5665/*define for completion_signal_63_32 field*/
5666#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15
5667#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask   0xFFFFFFFF
5668#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift  0
5669#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)
5670
5671
5672#endif /* __SDMA_V6_0_0_PKT_OPEN_H_ */
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