psp_v3_1.c

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Author: Huang Rui
 23 *
 24 */
 25
 26#include <linux/firmware.h>
 27#include <linux/module.h>
 28#include <linux/pci.h>
 29
 30#include "amdgpu.h"
 31#include "amdgpu_psp.h"
 32#include "amdgpu_ucode.h"
 33#include "soc15_common.h"
 34#include "psp_v3_1.h"
 35
 36#include "mp/mp_9_0_offset.h"
 37#include "mp/mp_9_0_sh_mask.h"
 38#include "gc/gc_9_0_offset.h"
 39#include "sdma0/sdma0_4_0_offset.h"
 40#include "nbio/nbio_6_1_offset.h"
 41
 42#include "oss/osssys_4_0_offset.h"
 43#include "oss/osssys_4_0_sh_mask.h"
 44
 45MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
 46MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
 47MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
 48MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
 49MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
 50
 51
 52#define smnMP1_FIRMWARE_FLAGS 0x3010028
 53
 54static int psp_v3_1_ring_stop(struct psp_context *psp,
 55			      enum psp_ring_type ring_type);
 56
 57static int psp_v3_1_init_microcode(struct psp_context *psp)
 58{
 59	struct amdgpu_device *adev = psp->adev;
 60	char ucode_prefix[30];
 61	int err = 0;
 62
 63	DRM_DEBUG("\n");
 64
 65	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 66
 67	err = psp_init_sos_microcode(psp, ucode_prefix);
 68	if (err)
 69		return err;
 70
 71	err = psp_init_asd_microcode(psp, ucode_prefix);
 72	if (err)
 73		return err;
 74
 75	return 0;
 76}
 77
 78static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
 79{
 80	int ret;
 81	uint32_t psp_gfxdrv_command_reg = 0;
 82	struct amdgpu_device *adev = psp->adev;
 83	uint32_t sol_reg;
 84
 85	/* Check sOS sign of life register to confirm sys driver and sOS
 86	 * are already been loaded.
 87	 */
 88	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 89	if (sol_reg)
 90		return 0;
 91
 92	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 93	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 94			   0x80000000, 0x80000000, 0);
 95	if (ret)
 96		return ret;
 97
 98	/* Copy PSP System Driver binary to memory */
 99	psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
100
101	/* Provide the sys driver to bootloader */
102	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
103	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
104	psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
105	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
106	       psp_gfxdrv_command_reg);
107
108	/* there might be handshake issue with hardware which needs delay */
109	mdelay(20);
110
111	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
112			   0x80000000, 0x80000000, 0);
113
114	return ret;
115}
116
117static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
118{
119	int ret;
120	unsigned int psp_gfxdrv_command_reg = 0;
121	struct amdgpu_device *adev = psp->adev;
122	uint32_t sol_reg;
123
124	/* Check sOS sign of life register to confirm sys driver and sOS
125	 * are already been loaded.
126	 */
127	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
128	if (sol_reg)
129		return 0;
130
131	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
132	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
133			   0x80000000, 0x80000000, 0);
134	if (ret)
135		return ret;
136
137	/* Copy Secure OS binary to PSP memory */
138	psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
139
140	/* Provide the PSP secure OS to bootloader */
141	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
142	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
143	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
144	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
145	       psp_gfxdrv_command_reg);
146
147	/* there might be handshake issue with hardware which needs delay */
148	mdelay(20);
149	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
150			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
151			   PSP_WAITREG_CHANGED);
152	return ret;
153}
154
155static void psp_v3_1_reroute_ih(struct psp_context *psp)
156{
157	struct amdgpu_device *adev = psp->adev;
158	uint32_t tmp;
159
160	/* Change IH ring for VMC */
161	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
162	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
163	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
164
165	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
166	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
167	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
168
169	mdelay(20);
170	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
171		     0x80000000, 0x8000FFFF, 0);
172
173	/* Change IH ring for UMC */
174	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
175	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
176
177	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
178	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
179	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
180
181	mdelay(20);
182	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
183		     0x80000000, 0x8000FFFF, 0);
184}
185
186static int psp_v3_1_ring_create(struct psp_context *psp,
187				enum psp_ring_type ring_type)
188{
189	int ret = 0;
190	unsigned int psp_ring_reg = 0;
191	struct psp_ring *ring = &psp->km_ring;
192	struct amdgpu_device *adev = psp->adev;
193
194	psp_v3_1_reroute_ih(psp);
195
196	if (amdgpu_sriov_vf(adev)) {
197		ring->ring_wptr = 0;
198		ret = psp_v3_1_ring_stop(psp, ring_type);
199		if (ret) {
200			DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
201			return ret;
202		}
203
204		/* Write low address of the ring to C2PMSG_102 */
205		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
206		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
207		/* Write high address of the ring to C2PMSG_103 */
208		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
209		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
210		/* No size initialization for sriov  */
211		/* Write the ring initialization command to C2PMSG_101 */
212		psp_ring_reg = ring_type;
213		psp_ring_reg = psp_ring_reg << 16;
214		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
215
216		/* there might be hardware handshake issue which needs delay */
217		mdelay(20);
218
219		/* Wait for response flag (bit 31) in C2PMSG_101 */
220		ret = psp_wait_for(
221			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
222			0x80000000, 0x8000FFFF, 0);
223	} else {
224
225		/* Write low address of the ring to C2PMSG_69 */
226		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
227		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
228		/* Write high address of the ring to C2PMSG_70 */
229		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
230		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
231		/* Write size of ring to C2PMSG_71 */
232		psp_ring_reg = ring->ring_size;
233		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
234		/* Write the ring initialization command to C2PMSG_64 */
235		psp_ring_reg = ring_type;
236		psp_ring_reg = psp_ring_reg << 16;
237		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
238
239		/* there might be hardware handshake issue which needs delay */
240		mdelay(20);
241
242		/* Wait for response flag (bit 31) in C2PMSG_64 */
243		ret = psp_wait_for(
244			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
245			0x80000000, 0x8000FFFF, 0);
246	}
247	return ret;
248}
249
250static int psp_v3_1_ring_stop(struct psp_context *psp,
251			      enum psp_ring_type ring_type)
252{
253	int ret = 0;
254	struct amdgpu_device *adev = psp->adev;
255
256	/* Write the ring destroy command*/
257	if (amdgpu_sriov_vf(adev))
258		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
259				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
260	else
261		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
262				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
263
264	/* there might be handshake issue with hardware which needs delay */
265	mdelay(20);
266
267	/* Wait for response flag (bit 31) */
268	if (amdgpu_sriov_vf(adev))
269		ret = psp_wait_for(
270			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
271			0x80000000, 0x80000000, 0);
272	else
273		ret = psp_wait_for(
274			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
275			0x80000000, 0x80000000, 0);
276
277	return ret;
278}
279
280static int psp_v3_1_ring_destroy(struct psp_context *psp,
281				 enum psp_ring_type ring_type)
282{
283	int ret = 0;
284	struct psp_ring *ring = &psp->km_ring;
285	struct amdgpu_device *adev = psp->adev;
286
287	ret = psp_v3_1_ring_stop(psp, ring_type);
288	if (ret)
289		DRM_ERROR("Fail to stop psp ring\n");
290
291	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
292			      &ring->ring_mem_mc_addr,
293			      (void **)&ring->ring_mem);
294
295	return ret;
296}
297
298static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
299{
300	struct amdgpu_device *adev = psp->adev;
301	uint32_t reg;
302
303	reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
304	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
305}
306
307static int psp_v3_1_mode1_reset(struct psp_context *psp)
308{
309	int ret;
310	uint32_t offset;
311	struct amdgpu_device *adev = psp->adev;
312
313	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
314
315	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0);
316
317	if (ret) {
318		DRM_INFO("psp is not working correctly before mode1 reset!\n");
319		return -EINVAL;
320	}
321
322	/*send the mode 1 reset command*/
323	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
324
325	msleep(500);
326
327	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
328
329	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0);
330
331	if (ret) {
332		DRM_INFO("psp mode 1 reset failed!\n");
333		return -EINVAL;
334	}
335
336	DRM_INFO("psp mode1 reset succeed \n");
337
338	return 0;
339}
340
341static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
342{
343	uint32_t data;
344	struct amdgpu_device *adev = psp->adev;
345
346	if (amdgpu_sriov_vf(adev))
347		data = psp->km_ring.ring_wptr;
348	else
349		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
350	return data;
351}
352
353static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
354{
355	struct amdgpu_device *adev = psp->adev;
356
357	if (amdgpu_sriov_vf(adev)) {
358		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
359		/* send interrupt to PSP for SRIOV ring write pointer update */
360		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
361			GFX_CTRL_CMD_ID_CONSUME_CMD);
362		psp->km_ring.ring_wptr = value;
363	} else
364		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
365}
366
367static const struct psp_funcs psp_v3_1_funcs = {
368	.init_microcode = psp_v3_1_init_microcode,
369	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
370	.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
371	.ring_create = psp_v3_1_ring_create,
372	.ring_stop = psp_v3_1_ring_stop,
373	.ring_destroy = psp_v3_1_ring_destroy,
374	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
375	.mode1_reset = psp_v3_1_mode1_reset,
376	.ring_get_wptr = psp_v3_1_ring_get_wptr,
377	.ring_set_wptr = psp_v3_1_ring_set_wptr,
378};
379
380void psp_v3_1_set_psp_funcs(struct psp_context *psp)
381{
382	psp->funcs = &psp_v3_1_funcs;
383}