psp_v14_0.c

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#include <drm/drm_drv.h>
 24#include <linux/vmalloc.h>
 25#include "amdgpu.h"
 26#include "amdgpu_psp.h"
 27#include "amdgpu_ucode.h"
 28#include "soc15_common.h"
 29#include "psp_v14_0.h"
 30
 31#include "mp/mp_14_0_2_offset.h"
 32#include "mp/mp_14_0_2_sh_mask.h"
 33
 34MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");
 35MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin");
 36MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");
 37MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos_kicker.bin");
 38MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin");
 39MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta_kicker.bin");
 40MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin");
 41MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin");
 42
 43/* For large FW files the time to complete can be very long */
 44#define USBC_PD_POLLING_LIMIT_S 240
 45
 46/* Read USB-PD from LFB */
 47#define GFX_CMD_USB_PD_USE_LFB 0x480
 48
 49/* VBIOS gfl defines */
 50#define MBOX_READY_MASK 0x80000000
 51#define MBOX_STATUS_MASK 0x0000FFFF
 52#define MBOX_COMMAND_MASK 0x00FF0000
 53#define MBOX_READY_FLAG 0x80000000
 54#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
 55#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
 56#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
 57
 58/* memory training timeout define */
 59#define MEM_TRAIN_SEND_MSG_TIMEOUT_US	3000000
 60
 61static int psp_v14_0_init_microcode(struct psp_context *psp)
 62{
 63	struct amdgpu_device *adev = psp->adev;
 64	char ucode_prefix[30];
 65	int err = 0;
 66
 67	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 68
 69	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 70	case IP_VERSION(14, 0, 2):
 71	case IP_VERSION(14, 0, 3):
 72		err = psp_init_sos_microcode(psp, ucode_prefix);
 73		if (err)
 74			return err;
 75		err = psp_init_ta_microcode(psp, ucode_prefix);
 76		if (err)
 77			return err;
 78		break;
 79	case IP_VERSION(14, 0, 5):
 80		err = psp_init_toc_microcode(psp, ucode_prefix);
 81		if (err)
 82			return err;
 83		err = psp_init_ta_microcode(psp, ucode_prefix);
 84		if (err)
 85			return err;
 86		break;
 87	default:
 88		BUG();
 89	}
 90
 91	return 0;
 92}
 93
 94static bool psp_v14_0_is_sos_alive(struct psp_context *psp)
 95{
 96	struct amdgpu_device *adev = psp->adev;
 97	uint32_t sol_reg;
 98
 99	sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
100
101	return sol_reg != 0x0;
102}
103
104static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)
105{
106	struct amdgpu_device *adev = psp->adev;
107
108	int ret;
109	int retry_loop;
110
111	for (retry_loop = 0; retry_loop < 10; retry_loop++) {
112		/* Wait for bootloader to signify that is
113		    ready having bit 31 of C2PMSG_35 set to 1 */
114		ret = psp_wait_for(
115			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
116			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
117
118		if (ret == 0)
119			return 0;
120	}
121
122	return ret;
123}
124
125static int psp_v14_0_bootloader_load_component(struct psp_context  	*psp,
126					       struct psp_bin_desc 	*bin_desc,
127					       enum psp_bootloader_cmd  bl_cmd)
128{
129	int ret;
130	uint32_t psp_gfxdrv_command_reg = 0;
131	struct amdgpu_device *adev = psp->adev;
132
133	/* Check tOS sign of life register to confirm sys driver and sOS
134	 * are already been loaded.
135	 */
136	if (psp_v14_0_is_sos_alive(psp))
137		return 0;
138
139	ret = psp_v14_0_wait_for_bootloader(psp);
140	if (ret)
141		return ret;
142
143	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
144
145	/* Copy PSP KDB binary to memory */
146	memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
147
148	/* Provide the PSP KDB to bootloader */
149	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
150	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
151	psp_gfxdrv_command_reg = bl_cmd;
152	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
153	       psp_gfxdrv_command_reg);
154
155	ret = psp_v14_0_wait_for_bootloader(psp);
156
157	return ret;
158}
159
160static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp)
161{
162	return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
163}
164
165static int psp_v14_0_bootloader_load_spl(struct psp_context *psp)
166{
167	return psp_v14_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
168}
169
170static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp)
171{
172	return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
173}
174
175static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp)
176{
177	return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
178}
179
180static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp)
181{
182	return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
183}
184
185static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)
186{
187	/* dbg_drv was renamed to had_drv in psp v14 */
188	return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_HADDRV);
189}
190
191static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)
192{
193	return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
194}
195
196static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp)
197{
198	return psp_v14_0_bootloader_load_component(psp, &psp->ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV);
199}
200
201static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)
202{
203	int ret;
204	unsigned int psp_gfxdrv_command_reg = 0;
205	struct amdgpu_device *adev = psp->adev;
206
207	/* Check sOS sign of life register to confirm sys driver and sOS
208	 * are already been loaded.
209	 */
210	if (psp_v14_0_is_sos_alive(psp))
211		return 0;
212
213	ret = psp_v14_0_wait_for_bootloader(psp);
214	if (ret)
215		return ret;
216
217	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
218
219	/* Copy Secure OS binary to PSP memory */
220	memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
221
222	/* Provide the PSP secure OS to bootloader */
223	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
224	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
225	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
226	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
227	       psp_gfxdrv_command_reg);
228
229	/* there might be handshake issue with hardware which needs delay */
230	mdelay(20);
231	ret = psp_wait_for(psp,
232			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
233			   RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0,
234			   PSP_WAITREG_CHANGED);
235
236	return ret;
237}
238
239static int psp_v14_0_ring_stop(struct psp_context *psp,
240			       enum psp_ring_type ring_type)
241{
242	int ret = 0;
243	struct amdgpu_device *adev = psp->adev;
244
245	if (amdgpu_sriov_vf(adev)) {
246		/* Write the ring destroy command*/
247		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
248			     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
249		/* there might be handshake issue with hardware which needs delay */
250		mdelay(20);
251		/* Wait for response flag (bit 31) */
252		ret = psp_wait_for(
253			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
254			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
255	} else {
256		/* Write the ring destroy command*/
257		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
258			     GFX_CTRL_CMD_ID_DESTROY_RINGS);
259		/* there might be handshake issue with hardware which needs delay */
260		mdelay(20);
261		/* Wait for response flag (bit 31) */
262		ret = psp_wait_for(
263			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
264			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
265	}
266
267	return ret;
268}
269
270static int psp_v14_0_ring_create(struct psp_context *psp,
271				 enum psp_ring_type ring_type)
272{
273	int ret = 0;
274	unsigned int psp_ring_reg = 0;
275	struct psp_ring *ring = &psp->km_ring;
276	struct amdgpu_device *adev = psp->adev;
277
278	if (amdgpu_sriov_vf(adev)) {
279		ret = psp_v14_0_ring_stop(psp, ring_type);
280		if (ret) {
281			DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
282			return ret;
283		}
284
285		/* Write low address of the ring to C2PMSG_102 */
286		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
287		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
288		/* Write high address of the ring to C2PMSG_103 */
289		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
290		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
291
292		/* Write the ring initialization command to C2PMSG_101 */
293		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
294			     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
295
296		/* there might be handshake issue with hardware which needs delay */
297		mdelay(20);
298
299		/* Wait for response flag (bit 31) in C2PMSG_101 */
300		ret = psp_wait_for(
301			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
302			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
303
304	} else {
305		/* Wait for sOS ready for ring creation */
306		ret = psp_wait_for(
307			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
308			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
309		if (ret) {
310			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
311			return ret;
312		}
313
314		/* Write low address of the ring to C2PMSG_69 */
315		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
316		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
317		/* Write high address of the ring to C2PMSG_70 */
318		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
319		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
320		/* Write size of ring to C2PMSG_71 */
321		psp_ring_reg = ring->ring_size;
322		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
323		/* Write the ring initialization command to C2PMSG_64 */
324		psp_ring_reg = ring_type;
325		psp_ring_reg = psp_ring_reg << 16;
326		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
327
328		/* there might be handshake issue with hardware which needs delay */
329		mdelay(20);
330
331		/* Wait for response flag (bit 31) in C2PMSG_64 */
332		ret = psp_wait_for(
333			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
334			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
335	}
336
337	return ret;
338}
339
340static int psp_v14_0_ring_destroy(struct psp_context *psp,
341				  enum psp_ring_type ring_type)
342{
343	int ret = 0;
344	struct psp_ring *ring = &psp->km_ring;
345	struct amdgpu_device *adev = psp->adev;
346
347	ret = psp_v14_0_ring_stop(psp, ring_type);
348	if (ret)
349		DRM_ERROR("Fail to stop psp ring\n");
350
351	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
352			      &ring->ring_mem_mc_addr,
353			      (void **)&ring->ring_mem);
354
355	return ret;
356}
357
358static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp)
359{
360	uint32_t data;
361	struct amdgpu_device *adev = psp->adev;
362
363	if (amdgpu_sriov_vf(adev))
364		data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
365	else
366		data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
367
368	return data;
369}
370
371static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
372{
373	struct amdgpu_device *adev = psp->adev;
374
375	if (amdgpu_sriov_vf(adev)) {
376		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
377		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
378			     GFX_CTRL_CMD_ID_CONSUME_CMD);
379	} else
380		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
381}
382
383static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)
384{
385	int ret;
386	int i;
387	uint32_t data_32;
388	int max_wait;
389	struct amdgpu_device *adev = psp->adev;
390
391	data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
392	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32);
393	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg);
394
395	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
396	for (i = 0; i < max_wait; i++) {
397		ret = psp_wait_for(
398			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
399			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
400		if (ret == 0)
401			break;
402	}
403	if (i < max_wait)
404		ret = 0;
405	else
406		ret = -ETIME;
407
408	dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
409		  (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
410		  (ret == 0) ? "succeed" : "failed",
411		  i, adev->usec_timeout/1000);
412	return ret;
413}
414
415
416static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
417{
418	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
419	uint32_t *pcache = (uint32_t *)ctx->sys_cache;
420	struct amdgpu_device *adev = psp->adev;
421	uint32_t p2c_header[4];
422	uint32_t sz;
423	void *buf;
424	int ret, idx;
425
426	if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
427		dev_dbg(adev->dev, "Memory training is not supported.\n");
428		return 0;
429	} else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
430		dev_err(adev->dev, "Memory training initialization failure.\n");
431		return -EINVAL;
432	}
433
434	if (psp_v14_0_is_sos_alive(psp)) {
435		dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
436		return 0;
437	}
438
439	amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
440	dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
441		  pcache[0], pcache[1], pcache[2], pcache[3],
442		  p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
443
444	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
445		dev_dbg(adev->dev, "Short training depends on restore.\n");
446		ops |= PSP_MEM_TRAIN_RESTORE;
447	}
448
449	if ((ops & PSP_MEM_TRAIN_RESTORE) &&
450	    pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
451		dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
452		ops |= PSP_MEM_TRAIN_SAVE;
453	}
454
455	if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
456	    !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
457	      pcache[3] == p2c_header[3])) {
458		dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
459		ops |= PSP_MEM_TRAIN_SAVE;
460	}
461
462	if ((ops & PSP_MEM_TRAIN_SAVE) &&
463	    p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
464		dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
465		ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
466	}
467
468	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
469		ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
470		ops |= PSP_MEM_TRAIN_SAVE;
471	}
472
473	dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
474
475	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
476		/*
477		 * Long training will encroach a certain amount on the bottom of VRAM;
478		 * save the content from the bottom of VRAM to system memory
479		 * before training, and restore it after training to avoid
480		 * VRAM corruption.
481		 */
482		sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
483
484		if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
485			dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
486				  adev->gmc.visible_vram_size,
487				  adev->mman.aper_base_kaddr);
488			return -EINVAL;
489		}
490
491		buf = vmalloc(sz);
492		if (!buf) {
493			dev_err(adev->dev, "failed to allocate system memory.\n");
494			return -ENOMEM;
495		}
496
497		if (drm_dev_enter(adev_to_drm(adev), &idx)) {
498			memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
499			ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
500			if (ret) {
501				DRM_ERROR("Send long training msg failed.\n");
502				vfree(buf);
503				drm_dev_exit(idx);
504				return ret;
505			}
506
507			memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
508			amdgpu_device_flush_hdp(adev, NULL);
509			vfree(buf);
510			drm_dev_exit(idx);
511		} else {
512			vfree(buf);
513			return -ENODEV;
514		}
515	}
516
517	if (ops & PSP_MEM_TRAIN_SAVE) {
518		amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
519	}
520
521	if (ops & PSP_MEM_TRAIN_RESTORE) {
522		amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
523	}
524
525	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
526		ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
527							 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
528		if (ret) {
529			dev_err(adev->dev, "send training msg failed.\n");
530			return ret;
531		}
532	}
533	ctx->training_cnt++;
534	return 0;
535}
536
537static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
538{
539	struct amdgpu_device *adev = psp->adev;
540	uint32_t reg_status;
541	int ret, i = 0;
542
543	/*
544	 * LFB address which is aligned to 1MB address and has to be
545	 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
546	 * register
547	 */
548	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
549
550	ret = psp_wait_for(psp,
551			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
552			   0x80000000, 0x80000000, 0);
553	if (ret)
554		return ret;
555
556	/* Fireup interrupt so PSP can pick up the address */
557	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
558
559	/* FW load takes very long time */
560	do {
561		msleep(1000);
562		reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);
563
564		if (reg_status & 0x80000000)
565			goto done;
566
567	} while (++i < USBC_PD_POLLING_LIMIT_S);
568
569	return -ETIME;
570done:
571
572	if ((reg_status & 0xFFFF) != 0) {
573		DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
574				reg_status & 0xFFFF);
575		return -EIO;
576	}
577
578	return 0;
579}
580
581static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
582{
583	struct amdgpu_device *adev = psp->adev;
584	int ret;
585
586	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
587
588	ret = psp_wait_for(psp,
589			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
590			   0x80000000, 0x80000000, 0);
591	if (!ret)
592		*fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);
593
594	return ret;
595}
596
597static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)
598{
599	uint32_t reg_status = 0, reg_val = 0;
600	struct amdgpu_device *adev = psp->adev;
601	int ret;
602
603	/* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
604	reg_val |= (cmd << 16);
605	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115,  reg_val);
606
607	/* Ring the doorbell */
608	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1);
609
610	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
611		ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
612						 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
613	else
614		ret = psp_wait_for(
615			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
616			MBOX_READY_FLAG, MBOX_READY_MASK, 0);
617
618	ret = psp_wait_for(psp,
619			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
620			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);
621	if (ret) {
622		dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
623		return ret;
624	}
625
626	reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
627	if ((reg_status & 0xFFFF) != 0) {
628		dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
629				cmd, reg_status & 0xFFFF);
630		return -EIO;
631	}
632
633	return 0;
634}
635
636static int psp_v14_0_update_spirom(struct psp_context *psp,
637				   uint64_t fw_pri_mc_addr)
638{
639	struct amdgpu_device *adev = psp->adev;
640	int ret;
641
642	/* Confirm PSP is ready to start */
643	ret = psp_wait_for(psp,
644			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
645			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);
646	if (ret) {
647		dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
648		return ret;
649	}
650
651	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
652
653	ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
654	if (ret)
655		return ret;
656
657	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
658
659	ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
660	if (ret)
661		return ret;
662
663	psp->vbflash_done = true;
664
665	ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
666	if (ret)
667		return ret;
668
669	return 0;
670}
671
672static int psp_v14_0_vbflash_status(struct psp_context *psp)
673{
674	struct amdgpu_device *adev = psp->adev;
675
676	return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
677}
678
679static const struct psp_funcs psp_v14_0_funcs = {
680	.init_microcode = psp_v14_0_init_microcode,
681	.bootloader_load_kdb = psp_v14_0_bootloader_load_kdb,
682	.bootloader_load_spl = psp_v14_0_bootloader_load_spl,
683	.bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv,
684	.bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv,
685	.bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv,
686	.bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv,
687	.bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv,
688	.bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv,
689	.bootloader_load_sos = psp_v14_0_bootloader_load_sos,
690	.ring_create = psp_v14_0_ring_create,
691	.ring_stop = psp_v14_0_ring_stop,
692	.ring_destroy = psp_v14_0_ring_destroy,
693	.ring_get_wptr = psp_v14_0_ring_get_wptr,
694	.ring_set_wptr = psp_v14_0_ring_set_wptr,
695	.mem_training = psp_v14_0_memory_training,
696	.load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw,
697	.read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw,
698	.update_spirom = psp_v14_0_update_spirom,
699	.vbflash_stat = psp_v14_0_vbflash_status
700};
701
702void psp_v14_0_set_psp_funcs(struct psp_context *psp)
703{
704	psp->funcs = &psp_v14_0_funcs;
705}