psp_v13_0_4.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#include "amdgpu.h"
 24#include "amdgpu_psp.h"
 25#include "amdgpu_ucode.h"
 26#include "soc15_common.h"
 27#include "psp_v13_0_4.h"
 28
 29#include "mp/mp_13_0_4_offset.h"
 30#include "mp/mp_13_0_4_sh_mask.h"
 31
 32MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
 33MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
 34
 35static int psp_v13_0_4_init_microcode(struct psp_context *psp)
 36{
 37	struct amdgpu_device *adev = psp->adev;
 38	char ucode_prefix[30];
 39	int err = 0;
 40
 41	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 42
 43	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 44	case IP_VERSION(13, 0, 4):
 45		err = psp_init_toc_microcode(psp, ucode_prefix);
 46		if (err)
 47			return err;
 48		err = psp_init_ta_microcode(psp, ucode_prefix);
 49		if (err)
 50			return err;
 51		break;
 52	default:
 53		BUG();
 54	}
 55
 56	return 0;
 57}
 58
 59static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
 60{
 61	struct amdgpu_device *adev = psp->adev;
 62	uint32_t sol_reg;
 63
 64	sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 65
 66	return sol_reg != 0x0;
 67}
 68
 69static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
 70{
 71	struct amdgpu_device *adev = psp->adev;
 72
 73	int ret;
 74	int retry_loop;
 75
 76	for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 77		/* Wait for bootloader to signify that is
 78		    ready having bit 31 of C2PMSG_35 set to 1 */
 79		ret = psp_wait_for(
 80			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 81			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
 82
 83		if (ret == 0)
 84			return 0;
 85	}
 86
 87	return ret;
 88}
 89
 90static int psp_v13_0_4_bootloader_load_component(struct psp_context  	*psp,
 91					       struct psp_bin_desc 	*bin_desc,
 92					       enum psp_bootloader_cmd  bl_cmd)
 93{
 94	int ret;
 95	uint32_t psp_gfxdrv_command_reg = 0;
 96	struct amdgpu_device *adev = psp->adev;
 97
 98	/* Check tOS sign of life register to confirm sys driver and sOS
 99	 * are already been loaded.
100	 */
101	if (psp_v13_0_4_is_sos_alive(psp))
102		return 0;
103
104	ret = psp_v13_0_4_wait_for_bootloader(psp);
105	if (ret)
106		return ret;
107
108	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
109
110	/* Copy PSP KDB binary to memory */
111	memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
112
113	/* Provide the PSP KDB to bootloader */
114	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
115	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
116	psp_gfxdrv_command_reg = bl_cmd;
117	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
118	       psp_gfxdrv_command_reg);
119
120	ret = psp_v13_0_4_wait_for_bootloader(psp);
121
122	return ret;
123}
124
125static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
126{
127	return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
128}
129
130static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
131{
132	return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
133}
134
135static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
136{
137	return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
138}
139
140static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
141{
142	return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
143}
144
145static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
146{
147	return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
148}
149
150static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
151{
152	return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
153}
154
155static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
156{
157	int ret;
158	unsigned int psp_gfxdrv_command_reg = 0;
159	struct amdgpu_device *adev = psp->adev;
160
161	/* Check sOS sign of life register to confirm sys driver and sOS
162	 * are already been loaded.
163	 */
164	if (psp_v13_0_4_is_sos_alive(psp))
165		return 0;
166
167	ret = psp_v13_0_4_wait_for_bootloader(psp);
168	if (ret)
169		return ret;
170
171	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
172
173	/* Copy Secure OS binary to PSP memory */
174	memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
175
176	/* Provide the PSP secure OS to bootloader */
177	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
178	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
179	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
180	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
181	       psp_gfxdrv_command_reg);
182
183	/* there might be handshake issue with hardware which needs delay */
184	mdelay(20);
185	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
186			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,
187			   PSP_WAITREG_CHANGED);
188
189	return ret;
190}
191
192static int psp_v13_0_4_ring_stop(struct psp_context *psp,
193			       enum psp_ring_type ring_type)
194{
195	int ret = 0;
196	struct amdgpu_device *adev = psp->adev;
197
198	if (amdgpu_sriov_vf(adev)) {
199		/* Write the ring destroy command*/
200		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
201			     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
202		/* there might be handshake issue with hardware which needs delay */
203		mdelay(20);
204		/* Wait for response flag (bit 31) */
205		ret = psp_wait_for(
206			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
207			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
208	} else {
209		/* Write the ring destroy command*/
210		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
211			     GFX_CTRL_CMD_ID_DESTROY_RINGS);
212		/* there might be handshake issue with hardware which needs delay */
213		mdelay(20);
214		/* Wait for response flag (bit 31) */
215		ret = psp_wait_for(
216			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
217			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
218	}
219
220	return ret;
221}
222
223static int psp_v13_0_4_ring_create(struct psp_context *psp,
224				 enum psp_ring_type ring_type)
225{
226	int ret = 0;
227	unsigned int psp_ring_reg = 0;
228	struct psp_ring *ring = &psp->km_ring;
229	struct amdgpu_device *adev = psp->adev;
230
231	if (amdgpu_sriov_vf(adev)) {
232		ret = psp_v13_0_4_ring_stop(psp, ring_type);
233		if (ret) {
234			DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
235			return ret;
236		}
237
238		/* Write low address of the ring to C2PMSG_102 */
239		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
240		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
241		/* Write high address of the ring to C2PMSG_103 */
242		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
243		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
244
245		/* Write the ring initialization command to C2PMSG_101 */
246		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
247			     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
248
249		/* there might be handshake issue with hardware which needs delay */
250		mdelay(20);
251
252		/* Wait for response flag (bit 31) in C2PMSG_101 */
253		ret = psp_wait_for(
254			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
255			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
256
257	} else {
258		/* Wait for sOS ready for ring creation */
259		ret = psp_wait_for(
260			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
261			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
262		if (ret) {
263			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
264			return ret;
265		}
266
267		/* Write low address of the ring to C2PMSG_69 */
268		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
269		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
270		/* Write high address of the ring to C2PMSG_70 */
271		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
272		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
273		/* Write size of ring to C2PMSG_71 */
274		psp_ring_reg = ring->ring_size;
275		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
276		/* Write the ring initialization command to C2PMSG_64 */
277		psp_ring_reg = ring_type;
278		psp_ring_reg = psp_ring_reg << 16;
279		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
280
281		/* there might be handshake issue with hardware which needs delay */
282		mdelay(20);
283
284		/* Wait for response flag (bit 31) in C2PMSG_64 */
285		ret = psp_wait_for(
286			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
287			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
288	}
289
290	return ret;
291}
292
293static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
294				  enum psp_ring_type ring_type)
295{
296	int ret = 0;
297	struct psp_ring *ring = &psp->km_ring;
298	struct amdgpu_device *adev = psp->adev;
299
300	ret = psp_v13_0_4_ring_stop(psp, ring_type);
301	if (ret)
302		DRM_ERROR("Fail to stop psp ring\n");
303
304	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
305			      &ring->ring_mem_mc_addr,
306			      (void **)&ring->ring_mem);
307
308	return ret;
309}
310
311static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
312{
313	uint32_t data;
314	struct amdgpu_device *adev = psp->adev;
315
316	if (amdgpu_sriov_vf(adev))
317		data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
318	else
319		data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
320
321	return data;
322}
323
324static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
325{
326	struct amdgpu_device *adev = psp->adev;
327
328	if (amdgpu_sriov_vf(adev)) {
329		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
330		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
331			     GFX_CTRL_CMD_ID_CONSUME_CMD);
332	} else
333		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
334}
335
336static const struct psp_funcs psp_v13_0_4_funcs = {
337	.init_microcode = psp_v13_0_4_init_microcode,
338	.bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
339	.bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
340	.bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
341	.bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
342	.bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
343	.bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
344	.bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
345	.ring_create = psp_v13_0_4_ring_create,
346	.ring_stop = psp_v13_0_4_ring_stop,
347	.ring_destroy = psp_v13_0_4_ring_destroy,
348	.ring_get_wptr = psp_v13_0_4_ring_get_wptr,
349	.ring_set_wptr = psp_v13_0_4_ring_set_wptr,
350};
351
352void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
353{
354	psp->funcs = &psp_v13_0_4_funcs;
355}