psp_v12_0.c

  1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#include <linux/firmware.h>
 24#include <linux/module.h>
 25#include "amdgpu.h"
 26#include "amdgpu_psp.h"
 27#include "amdgpu_ucode.h"
 28#include "soc15_common.h"
 29#include "psp_v12_0.h"
 30
 31#include "mp/mp_12_0_0_offset.h"
 32#include "mp/mp_12_0_0_sh_mask.h"
 33#include "gc/gc_9_0_offset.h"
 34#include "sdma0/sdma0_4_0_offset.h"
 35#include "nbio/nbio_7_4_offset.h"
 36
 37MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
 38MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
 39MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
 40MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
 41
 42/* address block */
 43#define smnMP1_FIRMWARE_FLAGS		0x3010024
 44
 45static int psp_v12_0_init_microcode(struct psp_context *psp)
 46{
 47	struct amdgpu_device *adev = psp->adev;
 48	char ucode_prefix[30];
 49	int err = 0;
 50	DRM_DEBUG("\n");
 51
 52	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 53
 54	err = psp_init_asd_microcode(psp, ucode_prefix);
 55	if (err)
 56		return err;
 57
 58	err = psp_init_ta_microcode(psp, ucode_prefix);
 59	if (err)
 60		return err;
 61
 62	/* only supported on renoir */
 63	if (!(adev->apu_flags & AMD_APU_IS_RENOIR))
 64		adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
 65
 66	return 0;
 67}
 68
 69static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
 70{
 71	int ret;
 72	uint32_t psp_gfxdrv_command_reg = 0;
 73	struct amdgpu_device *adev = psp->adev;
 74	uint32_t sol_reg;
 75
 76	/* Check sOS sign of life register to confirm sys driver and sOS
 77	 * are already been loaded.
 78	 */
 79	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 80	if (sol_reg)
 81		return 0;
 82
 83	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 84	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 85			   0x80000000, 0x80000000, 0);
 86	if (ret)
 87		return ret;
 88
 89	/* Copy PSP System Driver binary to memory */
 90	psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
 91
 92	/* Provide the sys driver to bootloader */
 93	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 94	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
 95	psp_gfxdrv_command_reg = 1 << 16;
 96	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 97	       psp_gfxdrv_command_reg);
 98
 99	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
100			   0x80000000, 0x80000000, 0);
101
102	return ret;
103}
104
105static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
106{
107	int ret;
108	unsigned int psp_gfxdrv_command_reg = 0;
109	struct amdgpu_device *adev = psp->adev;
110	uint32_t sol_reg;
111
112	/* Check sOS sign of life register to confirm sys driver and sOS
113	 * are already been loaded.
114	 */
115	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
116	if (sol_reg)
117		return 0;
118
119	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
120	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
121			   0x80000000, 0x80000000, 0);
122	if (ret)
123		return ret;
124
125	/* Copy Secure OS binary to PSP memory */
126	psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
127
128	/* Provide the PSP secure OS to bootloader */
129	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
130	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
131	psp_gfxdrv_command_reg = 2 << 16;
132	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
133	       psp_gfxdrv_command_reg);
134
135	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
136			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
137			   PSP_WAITREG_CHANGED);
138
139	return ret;
140}
141
142static int psp_v12_0_ring_create(struct psp_context *psp,
143				enum psp_ring_type ring_type)
144{
145	int ret = 0;
146	unsigned int psp_ring_reg = 0;
147	struct psp_ring *ring = &psp->km_ring;
148	struct amdgpu_device *adev = psp->adev;
149
150	/* Write low address of the ring to C2PMSG_69 */
151	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
152	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
153	/* Write high address of the ring to C2PMSG_70 */
154	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
155	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
156	/* Write size of ring to C2PMSG_71 */
157	psp_ring_reg = ring->ring_size;
158	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
159	/* Write the ring initialization command to C2PMSG_64 */
160	psp_ring_reg = ring_type;
161	psp_ring_reg = psp_ring_reg << 16;
162	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
163
164	/* Wait for response flag (bit 31) in C2PMSG_64 */
165	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
166			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
167
168	return ret;
169}
170
171static int psp_v12_0_ring_stop(struct psp_context *psp,
172			      enum psp_ring_type ring_type)
173{
174	int ret = 0;
175	struct amdgpu_device *adev = psp->adev;
176
177	/* Write the ring destroy command*/
178	if (amdgpu_sriov_vf(adev))
179		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
180				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
181	else
182		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
183				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
184
185	/* Wait for response flag (bit 31) */
186	if (amdgpu_sriov_vf(adev))
187		ret = psp_wait_for(
188			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
189			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
190	else
191		ret = psp_wait_for(
192			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
193			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
194
195	return ret;
196}
197
198static int psp_v12_0_ring_destroy(struct psp_context *psp,
199				 enum psp_ring_type ring_type)
200{
201	int ret = 0;
202	struct psp_ring *ring = &psp->km_ring;
203	struct amdgpu_device *adev = psp->adev;
204
205	ret = psp_v12_0_ring_stop(psp, ring_type);
206	if (ret)
207		DRM_ERROR("Fail to stop psp ring\n");
208
209	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
210			      &ring->ring_mem_mc_addr,
211			      (void **)&ring->ring_mem);
212
213	return ret;
214}
215
216static int psp_v12_0_mode1_reset(struct psp_context *psp)
217{
218	int ret;
219	uint32_t offset;
220	struct amdgpu_device *adev = psp->adev;
221
222	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
223
224	ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
225			   MBOX_TOS_READY_MASK, 0);
226
227	if (ret) {
228		DRM_INFO("psp is not working correctly before mode1 reset!\n");
229		return -EINVAL;
230	}
231
232	/*send the mode 1 reset command*/
233	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
234
235	msleep(500);
236
237	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
238
239	ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
240			   0);
241
242	if (ret) {
243		DRM_INFO("psp mode 1 reset failed!\n");
244		return -EINVAL;
245	}
246
247	DRM_INFO("psp mode1 reset succeed \n");
248
249	return 0;
250}
251
252static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
253{
254	uint32_t data;
255	struct amdgpu_device *adev = psp->adev;
256
257	if (amdgpu_sriov_vf(adev))
258		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
259	else
260		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
261
262	return data;
263}
264
265static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
266{
267	struct amdgpu_device *adev = psp->adev;
268
269	if (amdgpu_sriov_vf(adev)) {
270		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
271		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
272	} else
273		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
274}
275
276static const struct psp_funcs psp_v12_0_funcs = {
277	.init_microcode = psp_v12_0_init_microcode,
278	.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
279	.bootloader_load_sos = psp_v12_0_bootloader_load_sos,
280	.ring_create = psp_v12_0_ring_create,
281	.ring_stop = psp_v12_0_ring_stop,
282	.ring_destroy = psp_v12_0_ring_destroy,
283	.mode1_reset = psp_v12_0_mode1_reset,
284	.ring_get_wptr = psp_v12_0_ring_get_wptr,
285	.ring_set_wptr = psp_v12_0_ring_set_wptr,
286};
287
288void psp_v12_0_set_psp_funcs(struct psp_context *psp)
289{
290	psp->funcs = &psp_v12_0_funcs;
291}