psp_v11_0.c

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#include <linux/firmware.h>
 24#include <linux/module.h>
 25#include <linux/vmalloc.h>
 26#include <drm/drm_drv.h>
 27
 28#include "amdgpu.h"
 29#include "amdgpu_psp.h"
 30#include "amdgpu_ras.h"
 31#include "amdgpu_ucode.h"
 32#include "soc15_common.h"
 33#include "psp_v11_0.h"
 34
 35#include "mp/mp_11_0_offset.h"
 36#include "mp/mp_11_0_sh_mask.h"
 37#include "gc/gc_9_0_offset.h"
 38#include "sdma0/sdma0_4_0_offset.h"
 39#include "nbio/nbio_7_4_offset.h"
 40
 41#include "oss/osssys_4_0_offset.h"
 42#include "oss/osssys_4_0_sh_mask.h"
 43
 44MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
 45MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
 46MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
 47MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
 48MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
 49MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
 50MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
 51MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
 52MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
 53MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
 54MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
 55MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
 56MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
 57MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
 58MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
 59MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
 60MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
 61MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
 62MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
 63MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
 64MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
 65MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
 66MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
 67MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
 68MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
 69MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
 70MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
 71
 72/* address block */
 73#define smnMP1_FIRMWARE_FLAGS		0x3010024
 74/* navi10 reg offset define */
 75#define mmRLC_GPM_UCODE_ADDR_NV10	0x5b61
 76#define mmRLC_GPM_UCODE_DATA_NV10	0x5b62
 77#define mmSDMA0_UCODE_ADDR_NV10		0x5880
 78#define mmSDMA0_UCODE_DATA_NV10		0x5881
 79/* memory training timeout define */
 80#define MEM_TRAIN_SEND_MSG_TIMEOUT_US	3000000
 81
 82/* For large FW files the time to complete can be very long */
 83#define USBC_PD_POLLING_LIMIT_S 240
 84
 85/* Read USB-PD from LFB */
 86#define GFX_CMD_USB_PD_USE_LFB 0x480
 87
 88static int psp_v11_0_init_microcode(struct psp_context *psp)
 89{
 90	struct amdgpu_device *adev = psp->adev;
 91	char ucode_prefix[30];
 92	int err = 0;
 93
 94	DRM_DEBUG("\n");
 95
 96	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 97
 98	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 99	case IP_VERSION(11, 0, 2):
100	case IP_VERSION(11, 0, 4):
101		err = psp_init_sos_microcode(psp, ucode_prefix);
102		if (err)
103			return err;
104		err = psp_init_asd_microcode(psp, ucode_prefix);
105		if (err)
106			return err;
107		err = psp_init_ta_microcode(psp, ucode_prefix);
108		adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
109		break;
110	case IP_VERSION(11, 0, 0):
111	case IP_VERSION(11, 0, 5):
112	case IP_VERSION(11, 0, 9):
113		err = psp_init_sos_microcode(psp, ucode_prefix);
114		if (err)
115			return err;
116		err = psp_init_asd_microcode(psp, ucode_prefix);
117		if (err)
118			return err;
119		err = psp_init_ta_microcode(psp, ucode_prefix);
120		adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
121		break;
122	case IP_VERSION(11, 0, 7):
123	case IP_VERSION(11, 0, 11):
124	case IP_VERSION(11, 0, 12):
125	case IP_VERSION(11, 0, 13):
126		err = psp_init_sos_microcode(psp, ucode_prefix);
127		if (err)
128			return err;
129		err = psp_init_ta_microcode(psp, ucode_prefix);
130		break;
131	case IP_VERSION(11, 5, 0):
132	case IP_VERSION(11, 5, 2):
133		err = psp_init_asd_microcode(psp, ucode_prefix);
134		if (err)
135			return err;
136		err = psp_init_toc_microcode(psp, ucode_prefix);
137		break;
138	default:
139		BUG();
140	}
141
142	return err;
143}
144
145static int psp_v11_wait_for_tos_unload(struct psp_context *psp)
146{
147	struct amdgpu_device *adev = psp->adev;
148	uint32_t sol_reg1, sol_reg2;
149	int retry_loop;
150
151	/* Wait for the TOS to be unloaded */
152	for (retry_loop = 0; retry_loop < 20; retry_loop++) {
153		sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
154		usleep_range(1000, 2000);
155		sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
156		if (sol_reg1 == sol_reg2)
157			return 0;
158	}
159	dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x",
160		RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33),
161		RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81));
162
163	return -ETIME;
164}
165
166static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
167{
168	struct amdgpu_device *adev = psp->adev;
169	int ret;
170	int retry_loop;
171
172	/* For a reset done at the end of S3, only wait for TOS to be unloaded */
173	if ((adev->in_s4 || adev->in_s3) && !(adev->flags & AMD_IS_APU) &&
174	    amdgpu_in_reset(adev))
175		return psp_v11_wait_for_tos_unload(psp);
176
177	for (retry_loop = 0; retry_loop < 20; retry_loop++) {
178		/* Wait for bootloader to signify that is
179		    ready having bit 31 of C2PMSG_35 set to 1 */
180		ret = psp_wait_for(
181			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
182			0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE);
183
184		if (ret == 0)
185			return 0;
186	}
187
188	return ret;
189}
190
191static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
192{
193	struct amdgpu_device *adev = psp->adev;
194	uint32_t sol_reg;
195
196	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
197
198	return sol_reg != 0x0;
199}
200
201static int psp_v11_0_bootloader_load_component(struct psp_context  	*psp,
202					       struct psp_bin_desc 	*bin_desc,
203					       enum psp_bootloader_cmd  bl_cmd)
204{
205	int ret;
206	uint32_t psp_gfxdrv_command_reg = 0;
207	struct amdgpu_device *adev = psp->adev;
208
209	/* Check sOS sign of life register to confirm sys driver and sOS
210	 * are already been loaded.
211	 */
212	if (psp_v11_0_is_sos_alive(psp))
213		return 0;
214
215	ret = psp_v11_0_wait_for_bootloader(psp);
216	if (ret)
217		return ret;
218
219	/* Copy PSP System Driver binary to memory */
220	psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
221
222	/* Provide the sys driver to bootloader */
223	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
224	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
225	psp_gfxdrv_command_reg = bl_cmd;
226	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
227	       psp_gfxdrv_command_reg);
228
229	ret = psp_v11_0_wait_for_bootloader(psp);
230
231	return ret;
232}
233
234static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
235{
236	return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
237}
238
239static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
240{
241	return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
242}
243
244static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
245{
246	return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
247}
248
249static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
250{
251	int ret;
252	unsigned int psp_gfxdrv_command_reg = 0;
253	struct amdgpu_device *adev = psp->adev;
254
255	/* Check sOS sign of life register to confirm sys driver and sOS
256	 * are already been loaded.
257	 */
258	if (psp_v11_0_is_sos_alive(psp))
259		return 0;
260
261	ret = psp_v11_0_wait_for_bootloader(psp);
262	if (ret)
263		return ret;
264
265	/* Copy Secure OS binary to PSP memory */
266	psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
267
268	/* Provide the PSP secure OS to bootloader */
269	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
270	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
271	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
272	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
273	       psp_gfxdrv_command_reg);
274
275	/* there might be handshake issue with hardware which needs delay */
276	mdelay(20);
277	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
278			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
279			   PSP_WAITREG_CHANGED);
280
281	return ret;
282}
283
284static int psp_v11_0_ring_stop(struct psp_context *psp,
285			      enum psp_ring_type ring_type)
286{
287	int ret = 0;
288	struct amdgpu_device *adev = psp->adev;
289
290	/* Write the ring destroy command*/
291	if (amdgpu_sriov_vf(adev))
292		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
293				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
294	else
295		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
296				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
297
298	/* there might be handshake issue with hardware which needs delay */
299	mdelay(20);
300
301	/* Wait for response flag (bit 31) */
302	if (amdgpu_sriov_vf(adev))
303		ret = psp_wait_for(
304			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
305			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
306	else
307		ret = psp_wait_for(
308			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
309			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
310
311	return ret;
312}
313
314static int psp_v11_0_ring_create(struct psp_context *psp,
315				enum psp_ring_type ring_type)
316{
317	int ret = 0;
318	unsigned int psp_ring_reg = 0;
319	struct psp_ring *ring = &psp->km_ring;
320	struct amdgpu_device *adev = psp->adev;
321
322	if (amdgpu_sriov_vf(adev)) {
323		ring->ring_wptr = 0;
324		ret = psp_v11_0_ring_stop(psp, ring_type);
325		if (ret) {
326			DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
327			return ret;
328		}
329
330		/* Write low address of the ring to C2PMSG_102 */
331		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
332		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
333		/* Write high address of the ring to C2PMSG_103 */
334		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
335		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
336
337		/* Write the ring initialization command to C2PMSG_101 */
338		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
339					     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
340
341		/* there might be handshake issue with hardware which needs delay */
342		mdelay(20);
343
344		/* Wait for response flag (bit 31) in C2PMSG_101 */
345		ret = psp_wait_for(
346			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
347			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
348
349	} else {
350		/* Wait for sOS ready for ring creation */
351		ret = psp_wait_for(
352			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
353			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
354		if (ret) {
355			DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
356			return ret;
357		}
358
359		/* Write low address of the ring to C2PMSG_69 */
360		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
361		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
362		/* Write high address of the ring to C2PMSG_70 */
363		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
364		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
365		/* Write size of ring to C2PMSG_71 */
366		psp_ring_reg = ring->ring_size;
367		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
368		/* Write the ring initialization command to C2PMSG_64 */
369		psp_ring_reg = ring_type;
370		psp_ring_reg = psp_ring_reg << 16;
371		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
372
373		/* there might be handshake issue with hardware which needs delay */
374		mdelay(20);
375
376		/* Wait for response flag (bit 31) in C2PMSG_64 */
377		ret = psp_wait_for(
378			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
379			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
380	}
381
382	return ret;
383}
384
385
386static int psp_v11_0_ring_destroy(struct psp_context *psp,
387				 enum psp_ring_type ring_type)
388{
389	int ret = 0;
390	struct psp_ring *ring = &psp->km_ring;
391	struct amdgpu_device *adev = psp->adev;
392
393	ret = psp_v11_0_ring_stop(psp, ring_type);
394	if (ret)
395		DRM_ERROR("Fail to stop psp ring\n");
396
397	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
398			      &ring->ring_mem_mc_addr,
399			      (void **)&ring->ring_mem);
400
401	return ret;
402}
403
404static int psp_v11_0_mode1_reset(struct psp_context *psp)
405{
406	int ret;
407	uint32_t offset;
408	struct amdgpu_device *adev = psp->adev;
409
410	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
411
412	ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
413			   MBOX_TOS_READY_MASK, 0);
414
415	if (ret) {
416		DRM_INFO("psp is not working correctly before mode1 reset!\n");
417		return -EINVAL;
418	}
419
420	/*send the mode 1 reset command*/
421	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
422
423	msleep(500);
424
425	return 0;
426}
427
428static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
429{
430	int ret;
431	int i;
432	uint32_t data_32;
433	int max_wait;
434	struct amdgpu_device *adev = psp->adev;
435
436	data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
437	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
438	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
439
440	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
441	for (i = 0; i < max_wait; i++) {
442		ret = psp_wait_for(
443			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
444			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
445		if (ret == 0)
446			break;
447	}
448	if (i < max_wait)
449		ret = 0;
450	else
451		ret = -ETIME;
452
453	DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
454		  (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
455		  (ret == 0) ? "succeed" : "failed",
456		  i, adev->usec_timeout/1000);
457	return ret;
458}
459
460/*
461 * save and restore process
462 */
463static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
464{
465	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
466	uint32_t *pcache = (uint32_t *)ctx->sys_cache;
467	struct amdgpu_device *adev = psp->adev;
468	uint32_t p2c_header[4];
469	uint32_t sz;
470	void *buf;
471	int ret, idx;
472
473	if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
474		DRM_DEBUG("Memory training is not supported.\n");
475		return 0;
476	} else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
477		DRM_ERROR("Memory training initialization failure.\n");
478		return -EINVAL;
479	}
480
481	if (psp_v11_0_is_sos_alive(psp)) {
482		DRM_DEBUG("SOS is alive, skip memory training.\n");
483		return 0;
484	}
485
486	amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
487	DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
488		  pcache[0], pcache[1], pcache[2], pcache[3],
489		  p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
490
491	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
492		DRM_DEBUG("Short training depends on restore.\n");
493		ops |= PSP_MEM_TRAIN_RESTORE;
494	}
495
496	if ((ops & PSP_MEM_TRAIN_RESTORE) &&
497	    pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
498		DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
499		ops |= PSP_MEM_TRAIN_SAVE;
500	}
501
502	if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
503	    !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
504	      pcache[3] == p2c_header[3])) {
505		DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
506		ops |= PSP_MEM_TRAIN_SAVE;
507	}
508
509	if ((ops & PSP_MEM_TRAIN_SAVE) &&
510	    p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
511		DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
512		ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
513	}
514
515	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
516		ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
517		ops |= PSP_MEM_TRAIN_SAVE;
518	}
519
520	DRM_DEBUG("Memory training ops:%x.\n", ops);
521
522	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
523		/*
524		 * Long training will encroach a certain amount on the bottom of VRAM;
525		 * save the content from the bottom of VRAM to system memory
526		 * before training, and restore it after training to avoid
527		 * VRAM corruption.
528		 */
529		sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
530
531		if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
532			DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
533				  adev->gmc.visible_vram_size,
534				  adev->mman.aper_base_kaddr);
535			return -EINVAL;
536		}
537
538		buf = vmalloc(sz);
539		if (!buf) {
540			DRM_ERROR("failed to allocate system memory.\n");
541			return -ENOMEM;
542		}
543
544		if (drm_dev_enter(adev_to_drm(adev), &idx)) {
545			memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
546			ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
547			if (ret) {
548				DRM_ERROR("Send long training msg failed.\n");
549				vfree(buf);
550				drm_dev_exit(idx);
551				return ret;
552			}
553
554			memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
555			amdgpu_device_flush_hdp(adev, NULL);
556			vfree(buf);
557			drm_dev_exit(idx);
558		} else {
559			vfree(buf);
560			return -ENODEV;
561		}
562	}
563
564	if (ops & PSP_MEM_TRAIN_SAVE) {
565		amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
566	}
567
568	if (ops & PSP_MEM_TRAIN_RESTORE) {
569		amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
570	}
571
572	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
573		ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
574							 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
575		if (ret) {
576			DRM_ERROR("send training msg failed.\n");
577			return ret;
578		}
579	}
580	ctx->training_cnt++;
581	return 0;
582}
583
584static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
585{
586	uint32_t data;
587	struct amdgpu_device *adev = psp->adev;
588
589	if (amdgpu_sriov_vf(adev))
590		data = psp->km_ring.ring_wptr;
591	else
592		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
593
594	return data;
595}
596
597static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
598{
599	struct amdgpu_device *adev = psp->adev;
600
601	if (amdgpu_sriov_vf(adev)) {
602		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
603		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
604		psp->km_ring.ring_wptr = value;
605	} else
606		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
607}
608
609static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
610{
611	struct amdgpu_device *adev = psp->adev;
612	uint32_t reg_status;
613	int ret, i = 0;
614
615	/*
616	 * LFB address which is aligned to 1MB address and has to be
617	 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
618	 * register
619	 */
620	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
621
622	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
623			   0x80000000, 0x80000000, 0);
624	if (ret)
625		return ret;
626
627	/* Fireup interrupt so PSP can pick up the address */
628	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
629
630	/* FW load takes very long time */
631	do {
632		msleep(1000);
633		reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
634
635		if (reg_status & 0x80000000)
636			goto done;
637
638	} while (++i < USBC_PD_POLLING_LIMIT_S);
639
640	return -ETIME;
641done:
642
643	if ((reg_status & 0xFFFF) != 0) {
644		DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
645				reg_status & 0xFFFF);
646		return -EIO;
647	}
648
649	return 0;
650}
651
652static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
653{
654	struct amdgpu_device *adev = psp->adev;
655	int ret;
656
657	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
658
659	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
660			   0x80000000, 0x80000000, 0);
661	if (!ret)
662		*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
663
664	return ret;
665}
666
667static const struct psp_funcs psp_v11_0_funcs = {
668	.init_microcode = psp_v11_0_init_microcode,
669	.bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
670	.bootloader_load_spl = psp_v11_0_bootloader_load_spl,
671	.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
672	.bootloader_load_sos = psp_v11_0_bootloader_load_sos,
673	.ring_create = psp_v11_0_ring_create,
674	.ring_stop = psp_v11_0_ring_stop,
675	.ring_destroy = psp_v11_0_ring_destroy,
676	.mode1_reset = psp_v11_0_mode1_reset,
677	.mem_training = psp_v11_0_memory_training,
678	.ring_get_wptr = psp_v11_0_ring_get_wptr,
679	.ring_set_wptr = psp_v11_0_ring_set_wptr,
680	.load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
681	.read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw,
682	.wait_for_bootloader = psp_v11_0_wait_for_bootloader
683};
684
685void psp_v11_0_set_psp_funcs(struct psp_context *psp)
686{
687	psp->funcs = &psp_v11_0_funcs;
688}