FILE
nvd.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/amdgpu/nvd.h
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef NVD_H 25#define NVD_H 26 27/** 28 * Navi's PM4 definitions 29 */ 30#define PACKET_TYPE0 0 31#define PACKET_TYPE1 1 32#define PACKET_TYPE2 2 33#define PACKET_TYPE3 3 34 35#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 36#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 37#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 38#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 39#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 40 ((reg) & 0xFFFF) | \ 41 ((n) & 0x3FFF) << 16) 42#define CP_PACKET2 0x80000000 43#define PACKET2_PAD_SHIFT 0 44#define PACKET2_PAD_MASK (0x3fffffff << 0) 45 46#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 47 48#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 49 (((op) & 0xFF) << 8) | \ 50 ((n) & 0x3FFF) << 16) 51 52#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 53 54/* Packet 3 types */ 55#define PACKET3_NOP 0x10 56#define PACKET3_SET_BASE 0x11 57#define PACKET3_BASE_INDEX(x) ((x) << 0) 58#define CE_PARTITION_BASE 3 59#define PACKET3_CLEAR_STATE 0x12 60#define PACKET3_INDEX_BUFFER_SIZE 0x13 61#define PACKET3_DISPATCH_DIRECT 0x15 62#define PACKET3_DISPATCH_INDIRECT 0x16 63#define PACKET3_INDIRECT_BUFFER_END 0x17 64#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 65#define PACKET3_ATOMIC_GDS 0x1D 66#define PACKET3_ATOMIC_MEM 0x1E 67#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0) 68#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8) 69#define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) 70#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) 71#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) 72#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x))) 73#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x))) 74#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x))) 75#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x))) 76#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0) 77#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0 78#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1 79#define PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2 80#define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3 81#define PACKET3_ATOMIC_MEM__CACHE_POLICY__LRU 0 82#define PACKET3_ATOMIC_MEM__CACHE_POLICY__STREAM 1 83#define PACKET3_ATOMIC_MEM__CACHE_POLICY__NOA 2 84#define PACKET3_ATOMIC_MEM__CACHE_POLICY__BYPASS 3 85#define PACKET3_OCCLUSION_QUERY 0x1F 86#define PACKET3_SET_PREDICATION 0x20 87#define PACKET3_REG_RMW 0x21 88#define PACKET3_COND_EXEC 0x22 89#define PACKET3_PRED_EXEC 0x23 90#define PACKET3_DRAW_INDIRECT 0x24 91#define PACKET3_DRAW_INDEX_INDIRECT 0x25 92#define PACKET3_INDEX_BASE 0x26 93#define PACKET3_DRAW_INDEX_2 0x27 94#define PACKET3_CONTEXT_CONTROL 0x28 95#define PACKET3_INDEX_TYPE 0x2A 96#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 97#define PACKET3_DRAW_INDEX_AUTO 0x2D 98#define PACKET3_NUM_INSTANCES 0x2F 99#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 100#define PACKET3_INDIRECT_BUFFER_PRIV 0x32 101#define PACKET3_INDIRECT_BUFFER_CNST 0x33 102#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 103#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 104#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 105#define PACKET3_DRAW_PREAMBLE 0x36 106#define PACKET3_WRITE_DATA 0x37 107#define WRITE_DATA_DST_SEL(x) ((x) << 8) 108 /* 0 - register 109 * 1 - memory (sync - via GRBM) 110 * 2 - gl2 111 * 3 - gds 112 * 4 - reserved 113 * 5 - memory (async - direct) 114 */ 115#define WR_ONE_ADDR (1 << 16) 116#define WR_CONFIRM (1 << 20) 117#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 118 /* 0 - LRU 119 * 1 - Stream 120 */ 121#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 122 /* 0 - me 123 * 1 - pfp 124 * 2 - ce 125 */ 126#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) 127#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16) 128#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) 129#define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) 130#define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 131#define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0) 132#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 133#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x)) 134#define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21) 135#define PACKET3_WRITE_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 22) 136#define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 24) 137#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x)) 138#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0xFF) << 0) 139#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 140#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2 141#define PACKET3_WRITE_DATA__DST_SEL__GDS 3 142#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5 143#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6 144#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0 145#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1 146#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0 147#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1 148#define PACKET3_WRITE_DATA__MODE__PF_VF_DISABLED 0 149#define PACKET3_WRITE_DATA__MODE__PF_VF_ENABLED 1 150#define PACKET3_WRITE_DATA__TEMPORAL__RT 0 151#define PACKET3_WRITE_DATA__TEMPORAL__NT 1 152#define PACKET3_WRITE_DATA__TEMPORAL__HT 2 153#define PACKET3_WRITE_DATA__TEMPORAL__LU 3 154#define PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0 155#define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1 156#define PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2 157#define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3 158#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 159#define PACKET3_MEM_SEMAPHORE 0x39 160# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 161# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 162# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 163# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 164#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A 165#define PACKET3_COPY_DW 0x3B 166#define PACKET3_WAIT_REG_MEM 0x3C 167#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 168 /* 0 - always 169 * 1 - < 170 * 2 - <= 171 * 3 - == 172 * 4 - != 173 * 5 - >= 174 * 6 - > 175 */ 176#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 177 /* 0 - reg 178 * 1 - mem 179 */ 180#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 181 /* 0 - wait_reg_mem 182 * 1 - wr_wait_wr_reg 183 */ 184#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 185 /* 0 - me 186 * 1 - pfp 187 */ 188#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0) 189#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4) 190#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6) 191#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22) 192#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24) 193#define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) 194#define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 195#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 196#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0X3FFFF) << 0) 197#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0X3FFFF) << 0) 198#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x)) 199#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 200#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x)) 201#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) 202#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) 203#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31) 204#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0 205#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1 206#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2 207#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3 208#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4 209#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5 210#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6 211#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0 212#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1 213#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0 214#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1 215#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3 216#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__LRU 0 217#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__STREAM 1 218#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__NOA 2 219#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__BYPASS 3 220#define PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0 221#define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1 222#define PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2 223#define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3 224#define PACKET3_INDIRECT_BUFFER 0x3F 225#define INDIRECT_BUFFER_VALID (1 << 23) 226#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 227 /* 0 - LRU 228 * 1 - Stream 229 * 2 - Bypass 230 */ 231#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 232#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) 233#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 234#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x)) 235#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0) 236#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20) 237#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21) 238#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23) 239#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24) 240#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28) 241#define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28) 242#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31) 243#define PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0 244#define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1 245#define PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2 246#define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3 247#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0 248#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1 249#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__NOA 2 250#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__BYPASS 3 251#define PACKET3_COND_INDIRECT_BUFFER 0x3F 252#define PACKET3_COPY_DATA 0x40 253#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0) 254#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) 255#define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13) 256#define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13) 257#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16) 258#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) 259#define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) 260#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29) 261#define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 262#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 263#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 264#define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0) 265#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) 266#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x)) 267#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x)) 268#define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 269#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 270#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 271#define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0) 272#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x)) 273#define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21) 274#define PACKET3_COPY_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 23) 275#define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 276#define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x)) 277#define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0) 278#define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x)) 279#define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0) 280#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0 281#define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1 282#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2 283#define PACKET3_COPY_DATA__SRC_SEL__GDS 3 284#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4 285#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5 286#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6 287#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7 288#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8 289#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9 290#define PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10 291#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 292#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2 293#define PACKET3_COPY_DATA__DST_SEL__GDS 3 294#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4 295#define PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5 296#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6 297#define PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0 298#define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1 299#define PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2 300#define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3 301#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0 302#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1 303#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__NOA 2 304#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__BYPASS 3 305#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0 306#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1 307#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0 308#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1 309#define PACKET3_COPY_DATA__MODE__PF_VF_DISABLED 0 310#define PACKET3_COPY_DATA__MODE__PF_VF_ENABLED 1 311#define PACKET3_COPY_DATA__DST_TEMPORAL__RT 0 312#define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1 313#define PACKET3_COPY_DATA__DST_TEMPORAL__HT 2 314#define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3 315#define PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0 316#define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1 317#define PACKET3_COPY_DATA__DST_CACHE_POLICY__NOA 2 318#define PACKET3_COPY_DATA__DST_CACHE_POLICY__BYPASS 3 319#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0 320#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1 321#define PACKET3_CP_DMA 0x41 322#define PACKET3_PFP_SYNC_ME 0x42 323#define PACKET3_SURFACE_SYNC 0x43 324#define PACKET3_ME_INITIALIZE 0x44 325#define PACKET3_COND_WRITE 0x45 326#define PACKET3_EVENT_WRITE 0x46 327#define EVENT_TYPE(x) ((x) << 0) 328#define EVENT_INDEX(x) ((x) << 8) 329 /* 0 - any non-TS event 330 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 331 * 2 - SAMPLE_PIPELINESTAT 332 * 3 - SAMPLE_STREAMOUTSTAT* 333 * 4 - *S_PARTIAL_FLUSH 334 */ 335#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) 336#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) 337#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29) 338#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 0) 339#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 340#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x)) 341#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0 342#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2 343#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4 344#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS 8 345#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS1 9 346#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS2 10 347#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS3 11 348#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__LEGACY_MODE 0 349#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE1 1 350#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__NEW_MODE 2 351#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE3 3 352#define PACKET3_EVENT_WRITE_EOP 0x47 353#define PACKET3_EVENT_WRITE_EOS 0x48 354#define PACKET3_RELEASE_MEM 0x49 355#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 356#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) 357#define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12) 358#define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13) 359#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) 360#define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15) 361#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) 362#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17) 363#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) 364#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) 365#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) 366#define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22) 367#define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) 368 /* 0 - cache_policy__me_release_mem__lru 369 * 1 - cache_policy__me_release_mem__stream 370 * 2 - cache_policy__me_release_mem__noa 371 * 3 - cache_policy__me_release_mem__bypass 372 */ 373#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) 374 375#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 376 /* 0 - discard 377 * 1 - send low 32bit data 378 * 2 - send 64bit data 379 * 3 - send 64bit GPU counter value 380 * 4 - send 64bit sys counter value 381 */ 382#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 383 /* 0 - none 384 * 1 - interrupt only (DATA_SEL = 0) 385 * 2 - interrupt when data write is confirmed 386 */ 387#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 388 /* 0 - MC 389 * 1 - TC/L2 390 */ 391 392 393 394#define PACKET3_PREAMBLE_CNTL 0x4A 395# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 396# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 397#define PACKET3_DMA_DATA 0x50 398/* 1. header 399 * 2. CONTROL 400 * 3. SRC_ADDR_LO or DATA [31:0] 401 * 4. SRC_ADDR_HI [31:0] 402 * 5. DST_ADDR_LO [31:0] 403 * 6. DST_ADDR_HI [7:0] 404 * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 405 */ 406/* CONTROL */ 407# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 408 /* 0 - ME 409 * 1 - PFP 410 */ 411# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 412 /* 0 - LRU 413 * 1 - Stream 414 */ 415# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 416 /* 0 - DST_ADDR using DAS 417 * 1 - GDS 418 * 3 - DST_ADDR using L2 419 */ 420# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 421 /* 0 - LRU 422 * 1 - Stream 423 */ 424# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 425 /* 0 - SRC_ADDR using SAS 426 * 1 - GDS 427 * 2 - DATA 428 * 3 - SRC_ADDR using L2 429 */ 430# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 431/* COMMAND */ 432# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 433 /* 0 - memory 434 * 1 - register 435 */ 436# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 437 /* 0 - memory 438 * 1 - register 439 */ 440# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 441# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 442# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 443#define PACKET3_CONTEXT_REG_RMW 0x51 444#define PACKET3_GFX_CNTX_UPDATE 0x52 445#define PACKET3_BLK_CNTX_UPDATE 0x53 446#define PACKET3_INCR_UPDT_STATE 0x55 447#define PACKET3_ACQUIRE_MEM 0x58 448/* 1. HEADER 449 * 2. COHER_CNTL [30:0] 450 * 2.1 ENGINE_SEL [31:31] 451 * 2. COHER_SIZE [31:0] 452 * 3. COHER_SIZE_HI [7:0] 453 * 4. COHER_BASE_LO [31:0] 454 * 5. COHER_BASE_HI [23:0] 455 * 7. POLL_INTERVAL [15:0] 456 * 8. GCR_CNTL [18:0] 457 */ 458#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) 459 /* 460 * 0:NOP 461 * 1:ALL 462 * 2:RANGE 463 * 3:FIRST_LAST 464 */ 465#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) 466 /* 467 * 0:ALL 468 * 1:reserved 469 * 2:RANGE 470 * 3:FIRST_LAST 471 */ 472#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) 473#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) 474#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) 475#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) 476#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) 477#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) 478#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) 479#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) 480 /* 481 * 0:ALL 482 * 1:VOL 483 * 2:RANGE 484 * 3:FIRST_LAST 485 */ 486#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) 487#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) 488#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) 489#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) 490 /* 491 * 0: PARALLEL 492 * 1: FORWARD 493 * 2: REVERSE 494 */ 495#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) 496#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x)) 497#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0) 498#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x)) 499#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0) 500#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) 501#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0) 502#define PACKET3_REWIND 0x59 503#define PACKET3_INTERRUPT 0x5A 504#define PACKET3_GEN_PDEPTE 0x5B 505#define PACKET3_INDIRECT_BUFFER_PASID 0x5C 506#define PACKET3_PRIME_UTCL2 0x5D 507#define PACKET3_LOAD_UCONFIG_REG 0x5E 508#define PACKET3_LOAD_SH_REG 0x5F 509#define PACKET3_LOAD_CONFIG_REG 0x60 510#define PACKET3_LOAD_CONTEXT_REG 0x61 511#define PACKET3_LOAD_COMPUTE_STATE 0x62 512#define PACKET3_LOAD_SH_REG_INDEX 0x63 513#define PACKET3_SET_CONFIG_REG 0x68 514#define PACKET3_SET_CONFIG_REG_START 0x00002000 515#define PACKET3_SET_CONFIG_REG_END 0x00002c00 516#define PACKET3_SET_CONTEXT_REG 0x69 517#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 518#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 519#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A 520#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 521#define PACKET3_SET_SH_REG_DI 0x72 522#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 523#define PACKET3_SET_SH_REG_DI_MULTI 0x74 524#define PACKET3_GFX_PIPE_LOCK 0x75 525#define PACKET3_SET_SH_REG 0x76 526#define PACKET3_SET_SH_REG_START 0x00002c00 527#define PACKET3_SET_SH_REG_END 0x00003000 528#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) 529#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23) 530#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28) 531#define PACKET3_SET_SH_REG__INDEX__DEFAULT 0 532#define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1 533#define PACKET3_SET_SH_REG_OFFSET 0x77 534#define PACKET3_SET_QUEUE_REG 0x78 535#define PACKET3_SET_UCONFIG_REG 0x79 536#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 537#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 538#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) 539#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 540#define PACKET3_FORWARD_HEADER 0x7C 541#define PACKET3_SCRATCH_RAM_WRITE 0x7D 542#define PACKET3_SCRATCH_RAM_READ 0x7E 543#define PACKET3_LOAD_CONST_RAM 0x80 544#define PACKET3_WRITE_CONST_RAM 0x81 545#define PACKET3_DUMP_CONST_RAM 0x83 546#define PACKET3_INCREMENT_CE_COUNTER 0x84 547#define PACKET3_INCREMENT_DE_COUNTER 0x85 548#define PACKET3_WAIT_ON_CE_COUNTER 0x86 549#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 550#define PACKET3_SWITCH_BUFFER 0x8B 551#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 552#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C 553#define PACKET3_DISPATCH_DRAW 0x8D 554#define PACKET3_DISPATCH_DRAW_ACE 0x8D 555#define PACKET3_GET_LOD_STATS 0x8E 556#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F 557#define PACKET3_FRAME_CONTROL 0x90 558# define FRAME_TMZ (1 << 0) 559# define FRAME_CMD(x) ((x) << 28) 560 /* 561 * x=0: tmz_begin 562 * x=1: tmz_end 563 */ 564#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 565#define PACKET3_WAIT_REG_MEM64 0x93 566#define PACKET3_COND_PREEMPT 0x94 567#define PACKET3_HDP_FLUSH 0x95 568#define PACKET3_COPY_DATA_RB 0x96 569#define PACKET3_INVALIDATE_TLBS 0x98 570# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 571# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 572# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 573# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 574#define PACKET3_AQL_PACKET 0x99 575#define PACKET3_DMA_DATA_FILL_MULTI 0x9A 576#define PACKET3_SET_SH_REG_INDEX 0x9B 577#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C 578#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D 579#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E 580#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 581#define PACKET3_SET_RESOURCES 0xA0 582/* 1. header 583 * 2. CONTROL 584 * 3. QUEUE_MASK_LO [31:0] 585 * 4. QUEUE_MASK_HI [31:0] 586 * 5. GWS_MASK_LO [31:0] 587 * 6. GWS_MASK_HI [31:0] 588 * 7. OAC_MASK [15:0] 589 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 590 */ 591# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 592# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 593# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 594#define PACKET3_MAP_PROCESS 0xA1 595#define PACKET3_MAP_QUEUES 0xA2 596/* 1. header 597 * 2. CONTROL 598 * 3. CONTROL2 599 * 4. MQD_ADDR_LO [31:0] 600 * 5. MQD_ADDR_HI [31:0] 601 * 6. WPTR_ADDR_LO [31:0] 602 * 7. WPTR_ADDR_HI [31:0] 603 */ 604/* CONTROL */ 605# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 606# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 607# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 608# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 609# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 610# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 611# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 612# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 613# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 614/* CONTROL2 */ 615# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 616# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 617#define PACKET3_UNMAP_QUEUES 0xA3 618/* 1. header 619 * 2. CONTROL 620 * 3. CONTROL2 621 * 4. CONTROL3 622 * 5. CONTROL4 623 * 6. CONTROL5 624 */ 625/* CONTROL */ 626# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 627 /* 0 - PREEMPT_QUEUES 628 * 1 - RESET_QUEUES 629 * 2 - DISABLE_PROCESS_QUEUES 630 * 3 - PREEMPT_QUEUES_NO_UNMAP 631 */ 632# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 633# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 634# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 635/* CONTROL2a */ 636# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 637/* CONTROL2b */ 638# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 639/* CONTROL3a */ 640# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 641/* CONTROL3b */ 642# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 643/* CONTROL4 */ 644# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 645/* CONTROL5 */ 646# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 647#define PACKET3_QUERY_STATUS 0xA4 648/* 1. header 649 * 2. CONTROL 650 * 3. CONTROL2 651 * 4. ADDR_LO [31:0] 652 * 5. ADDR_HI [31:0] 653 * 6. DATA_LO [31:0] 654 * 7. DATA_HI [31:0] 655 */ 656/* CONTROL */ 657# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 658# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 659# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 660/* CONTROL2a */ 661# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 662/* CONTROL2b */ 663# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 664# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 665#define PACKET3_RUN_LIST 0xA5 666#define PACKET3_MAP_PROCESS_VM 0xA6 667 668#define PACKET3_RUN_CLEANER_SHADER 0xD2 669/* 1. header 670 * 2. RESERVED [31:0] 671 */ 672 673/* GFX11 */ 674#define PACKET3_SET_Q_PREEMPTION_MODE 0xF0 675# define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) 676# define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0) 677 678#endif
~/
Read-only file preview.