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nbio_v4_3.c
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#include "amdgpu.h" 24#include "nbio_v4_3.h" 25 26#include "nbio/nbio_4_3_0_offset.h" 27#include "nbio/nbio_4_3_0_sh_mask.h" 28#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 29#include <uapi/linux/kfd_ioctl.h> 30 31static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev) 32{ 33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 37} 38 39static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev) 40{ 41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 42 43 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 44 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 45 46 return tmp; 47} 48 49static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 50{ 51 if (enable) 52 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 53 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 54 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 55 else 56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 57} 58 59static u32 nbio_v4_3_get_memsize(struct amdgpu_device *adev) 60{ 61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 62} 63 64static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 65 bool use_doorbell, int doorbell_index, 66 int doorbell_size) 67{ 68 if (instance == 0) { 69 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); 70 71 if (use_doorbell) { 72 doorbell_range = REG_SET_FIELD(doorbell_range, 73 S2A_DOORBELL_ENTRY_2_CTRL, 74 S2A_DOORBELL_PORT2_ENABLE, 75 0x1); 76 doorbell_range = REG_SET_FIELD(doorbell_range, 77 S2A_DOORBELL_ENTRY_2_CTRL, 78 S2A_DOORBELL_PORT2_AWID, 79 0xe); 80 doorbell_range = REG_SET_FIELD(doorbell_range, 81 S2A_DOORBELL_ENTRY_2_CTRL, 82 S2A_DOORBELL_PORT2_RANGE_OFFSET, 83 doorbell_index); 84 doorbell_range = REG_SET_FIELD(doorbell_range, 85 S2A_DOORBELL_ENTRY_2_CTRL, 86 S2A_DOORBELL_PORT2_RANGE_SIZE, 87 doorbell_size); 88 doorbell_range = REG_SET_FIELD(doorbell_range, 89 S2A_DOORBELL_ENTRY_2_CTRL, 90 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 91 0x3); 92 } else 93 doorbell_range = REG_SET_FIELD(doorbell_range, 94 S2A_DOORBELL_ENTRY_2_CTRL, 95 S2A_DOORBELL_PORT2_RANGE_SIZE, 96 0); 97 98 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 99 } 100} 101 102static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 103 int doorbell_index, int instance) 104{ 105 u32 doorbell_range; 106 107 if (instance) 108 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); 109 else 110 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); 111 112 if (use_doorbell) { 113 doorbell_range = REG_SET_FIELD(doorbell_range, 114 S2A_DOORBELL_ENTRY_4_CTRL, 115 S2A_DOORBELL_PORT4_ENABLE, 116 0x1); 117 doorbell_range = REG_SET_FIELD(doorbell_range, 118 S2A_DOORBELL_ENTRY_4_CTRL, 119 S2A_DOORBELL_PORT4_AWID, 120 instance ? 0x7 : 0x4); 121 doorbell_range = REG_SET_FIELD(doorbell_range, 122 S2A_DOORBELL_ENTRY_4_CTRL, 123 S2A_DOORBELL_PORT4_RANGE_OFFSET, 124 doorbell_index); 125 doorbell_range = REG_SET_FIELD(doorbell_range, 126 S2A_DOORBELL_ENTRY_4_CTRL, 127 S2A_DOORBELL_PORT4_RANGE_SIZE, 128 8); 129 doorbell_range = REG_SET_FIELD(doorbell_range, 130 S2A_DOORBELL_ENTRY_4_CTRL, 131 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 132 instance ? 0x7 : 0x4); 133 } else 134 doorbell_range = REG_SET_FIELD(doorbell_range, 135 S2A_DOORBELL_ENTRY_4_CTRL, 136 S2A_DOORBELL_PORT4_RANGE_SIZE, 137 0); 138 139 if (instance) 140 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 141 else 142 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 143} 144 145static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev) 146{ 147 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 148 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 149} 150 151static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev, 152 bool enable) 153{ 154 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 155 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 156} 157 158static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 159 bool enable) 160{ 161 u32 tmp = 0; 162 163 if (enable) { 164 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 165 DOORBELL_SELFRING_GPA_APER_EN, 1) | 166 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 167 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 168 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 169 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 170 171 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 172 lower_32_bits(adev->doorbell.base)); 173 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 174 upper_32_bits(adev->doorbell.base)); 175 } 176 177 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 178 tmp); 179} 180 181static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev, 182 bool use_doorbell, int doorbell_index) 183{ 184 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); 185 186 if (use_doorbell) { 187 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 188 S2A_DOORBELL_ENTRY_1_CTRL, 189 S2A_DOORBELL_PORT1_ENABLE, 190 0x1); 191 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 192 S2A_DOORBELL_ENTRY_1_CTRL, 193 S2A_DOORBELL_PORT1_AWID, 194 0x0); 195 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 196 S2A_DOORBELL_ENTRY_1_CTRL, 197 S2A_DOORBELL_PORT1_RANGE_OFFSET, 198 doorbell_index); 199 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 200 S2A_DOORBELL_ENTRY_1_CTRL, 201 S2A_DOORBELL_PORT1_RANGE_SIZE, 202 2); 203 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 204 S2A_DOORBELL_ENTRY_1_CTRL, 205 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 206 0x0); 207 } else 208 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 209 S2A_DOORBELL_ENTRY_1_CTRL, 210 S2A_DOORBELL_PORT1_RANGE_SIZE, 211 0); 212 213 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 214} 215 216static void nbio_v4_3_ih_control(struct amdgpu_device *adev) 217{ 218 u32 interrupt_cntl; 219 220 /* setup interrupt control */ 221 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 222 223 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 224 /* 225 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 226 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 227 */ 228 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 229 IH_DUMMY_RD_OVERRIDE, 0); 230 231 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 233 IH_REQ_NONSNOOP_EN, 0); 234 235 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 236} 237 238static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 239 bool enable) 240{ 241 uint32_t def, data; 242 243 if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 244 return; 245 246 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); 247 if (enable) { 248 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 249 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 250 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 251 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 252 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 253 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 254 } else { 255 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 256 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 257 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 258 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 259 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 260 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 261 } 262 263 if (def != data) 264 WREG32_SOC15(NBIO, 0, regCPM_CONTROL, data); 265} 266 267static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 268 bool enable) 269{ 270 uint32_t def, data; 271 272 if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 273 return; 274 275 /* TODO: need update in future */ 276 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); 277 if (enable) { 278 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 279 } else { 280 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 281 } 282 283 if (def != data) 284 WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data); 285} 286 287static void nbio_v4_3_get_clockgating_state(struct amdgpu_device *adev, 288 u64 *flags) 289{ 290 int data; 291 292 /* AMD_CG_SUPPORT_BIF_MGCG */ 293 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); 294 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 295 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 296 297 /* AMD_CG_SUPPORT_BIF_LS */ 298 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); 299 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 300 *flags |= AMD_CG_SUPPORT_BIF_LS; 301} 302 303static u32 nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 304{ 305 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 306} 307 308static u32 nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 309{ 310 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 311} 312 313static u32 nbio_v4_3_get_pcie_index_offset(struct amdgpu_device *adev) 314{ 315 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 316} 317 318static u32 nbio_v4_3_get_pcie_data_offset(struct amdgpu_device *adev) 319{ 320 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 321} 322 323const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = { 324 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 325 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 326 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 327 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 328 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 329 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 330 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 331 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 332 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 333 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 334 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 335 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 336}; 337 338static void nbio_v4_3_init_registers(struct amdgpu_device *adev) 339{ 340 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) { 341 uint32_t data; 342 343 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 344 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 345 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 346 } 347} 348 349static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev) 350{ 351 u32 data, rom_offset; 352 353 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 354 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 355 356 return rom_offset; 357} 358 359#ifdef CONFIG_PCIEASPM 360static void nbio_v4_3_program_ltr(struct amdgpu_device *adev) 361{ 362 uint32_t def, data; 363 364 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 365 data = 0x35EB; 366 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 367 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 368 if (def != data) 369 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 370 371 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 372 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 373 if (def != data) 374 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 375 376 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 377 if (adev->pdev->ltr_path) 378 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 379 else 380 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 381 if (def != data) 382 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 383} 384#endif 385 386static void nbio_v4_3_program_aspm(struct amdgpu_device *adev) 387{ 388#ifdef CONFIG_PCIEASPM 389 uint32_t def, data; 390 391 if (!(amdgpu_ip_version(adev, PCIE_HWIP, 0) == IP_VERSION(7, 4, 0)) && 392 !(amdgpu_ip_version(adev, PCIE_HWIP, 0) == IP_VERSION(7, 6, 0))) 393 return; 394 395 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); 396 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 397 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 398 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 399 if (def != data) 400 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); 401 402 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7); 403 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 404 if (def != data) 405 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data); 406 407 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); 408 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 409 if (def != data) 410 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); 411 412 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 413 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 414 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 415 if (def != data) 416 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 417 418 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 419 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 420 if (def != data) 421 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 422 423 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 424 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 425 if (def != data) 426 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 427 428 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 429 430 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); 431 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 432 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 433 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 434 if (def != data) 435 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); 436 437 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4); 438 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 439 if (def != data) 440 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data); 441 442 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 443 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 444 if (def != data) 445 WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 446 447 nbio_v4_3_program_ltr(adev); 448 449 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 450 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 451 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 452 if (def != data) 453 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 454 455 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 456 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 457 if (def != data) 458 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 459 460 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); 461 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 462 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 463 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 464 if (def != data) 465 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); 466 467 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); 468 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 469 if (def != data) 470 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); 471#endif 472} 473 474#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 475 476static void nbio_v4_3_set_reg_remap(struct amdgpu_device *adev) 477{ 478 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 479 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 480 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 481 } else { 482 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 483 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 484 adev->rmmio_remap.bus_addr = 0; 485 } 486} 487 488const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { 489 .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset, 490 .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset, 491 .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset, 492 .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset, 493 .get_rev_id = nbio_v4_3_get_rev_id, 494 .mc_access_enable = nbio_v4_3_mc_access_enable, 495 .get_memsize = nbio_v4_3_get_memsize, 496 .sdma_doorbell_range = nbio_v4_3_sdma_doorbell_range, 497 .vcn_doorbell_range = nbio_v4_3_vcn_doorbell_range, 498 .gc_doorbell_init = nbio_v4_3_gc_doorbell_init, 499 .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture, 500 .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture, 501 .ih_doorbell_range = nbio_v4_3_ih_doorbell_range, 502 .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating, 503 .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep, 504 .get_clockgating_state = nbio_v4_3_get_clockgating_state, 505 .ih_control = nbio_v4_3_ih_control, 506 .init_registers = nbio_v4_3_init_registers, 507 .remap_hdp_registers = nbio_v4_3_remap_hdp_registers, 508 .get_rom_offset = nbio_v4_3_get_rom_offset, 509 .program_aspm = nbio_v4_3_program_aspm, 510 .set_reg_remap = nbio_v4_3_set_reg_remap, 511}; 512 513 514static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev, 515 bool use_doorbell, int doorbell_index) 516{ 517} 518 519static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 520 bool use_doorbell, int doorbell_index, 521 int doorbell_size) 522{ 523} 524 525static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 526 int doorbell_index, int instance) 527{ 528} 529 530static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev) 531{ 532} 533 534const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = { 535 .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset, 536 .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset, 537 .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset, 538 .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset, 539 .get_rev_id = nbio_v4_3_get_rev_id, 540 .mc_access_enable = nbio_v4_3_mc_access_enable, 541 .get_memsize = nbio_v4_3_get_memsize, 542 .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range, 543 .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range, 544 .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init, 545 .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture, 546 .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture, 547 .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range, 548 .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating, 549 .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep, 550 .get_clockgating_state = nbio_v4_3_get_clockgating_state, 551 .ih_control = nbio_v4_3_ih_control, 552 .init_registers = nbio_v4_3_init_registers, 553 .remap_hdp_registers = nbio_v4_3_remap_hdp_registers, 554 .get_rom_offset = nbio_v4_3_get_rom_offset, 555 .set_reg_remap = nbio_v4_3_set_reg_remap, 556}; 557 558static int nbio_v4_3_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 559 struct amdgpu_irq_src *src, 560 unsigned type, 561 enum amdgpu_interrupt_state state) 562{ 563 /* The ras_controller_irq enablement should be done in psp bl when it 564 * tries to enable ras feature. Driver only need to set the correct interrupt 565 * vector for bare-metal and sriov use case respectively 566 */ 567 uint32_t bif_doorbell_int_cntl; 568 569 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 570 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 571 BIF_BX0_BIF_DOORBELL_INT_CNTL, 572 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE, 573 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); 574 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 575 576 return 0; 577} 578 579static int nbio_v4_3_process_err_event_athub_irq(struct amdgpu_device *adev, 580 struct amdgpu_irq_src *source, 581 struct amdgpu_iv_entry *entry) 582{ 583 /* By design, the ih cookie for err_event_athub_irq should be written 584 * to bif ring. since bif ring is not enabled, just leave process callback 585 * as a dummy one. 586 */ 587 return 0; 588} 589 590static const struct amdgpu_irq_src_funcs nbio_v4_3_ras_err_event_athub_irq_funcs = { 591 .set = nbio_v4_3_set_ras_err_event_athub_irq_state, 592 .process = nbio_v4_3_process_err_event_athub_irq, 593}; 594 595static void nbio_v4_3_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 596{ 597 uint32_t bif_doorbell_int_cntl; 598 599 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 600 if (REG_GET_FIELD(bif_doorbell_int_cntl, 601 BIF_DOORBELL_INT_CNTL, 602 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 603 /* driver has to clear the interrupt status when bif ring is disabled */ 604 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 605 BIF_DOORBELL_INT_CNTL, 606 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 607 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 608 amdgpu_ras_global_ras_isr(adev); 609 } 610} 611 612static int nbio_v4_3_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev) 613{ 614 615 int r; 616 617 /* init the irq funcs */ 618 adev->nbio.ras_err_event_athub_irq.funcs = 619 &nbio_v4_3_ras_err_event_athub_irq_funcs; 620 adev->nbio.ras_err_event_athub_irq.num_types = 1; 621 622 /* register ras err event athub interrupt 623 * nbio v4_3 uses the same irq source as nbio v7_4 */ 624 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF, 625 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 626 &adev->nbio.ras_err_event_athub_irq); 627 628 return r; 629} 630 631struct amdgpu_nbio_ras nbio_v4_3_ras = { 632 .handle_ras_err_event_athub_intr_no_bifring = nbio_v4_3_handle_ras_err_event_athub_intr_no_bifring, 633 .init_ras_err_event_athub_interrupt = nbio_v4_3_init_ras_err_event_athub_interrupt, 634};
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