mxgpu_nv.h

 1/*
 2 * Copyright 2014 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MXGPU_NV_H__
25#define __MXGPU_NV_H__
26
27#define NV_MAILBOX_POLL_ACK_TIMEDOUT	500
28#define NV_MAILBOX_POLL_MSG_TIMEDOUT	15000
29#define NV_MAILBOX_POLL_FLR_TIMEDOUT	10000
30#define NV_MAILBOX_POLL_MSG_REP_MAX	11
31
32enum idh_request {
33	IDH_REQ_GPU_INIT_ACCESS = 1,
34	IDH_REL_GPU_INIT_ACCESS,
35	IDH_REQ_GPU_FINI_ACCESS,
36	IDH_REL_GPU_FINI_ACCESS,
37	IDH_REQ_GPU_RESET_ACCESS,
38	IDH_REQ_GPU_INIT_DATA,
39
40	IDH_LOG_VF_ERROR	= 200,
41	IDH_READY_TO_RESET 	= 201,
42	IDH_RAS_POISON	= 202,
43	IDH_REQ_RAS_ERROR_COUNT = 203,
44	IDH_REQ_RAS_CPER_DUMP = 204,
45	IDH_REQ_RAS_BAD_PAGES = 205,
46	IDH_REQ_RAS_CHK_CRITI = 206
47};
48
49enum idh_event {
50	IDH_CLR_MSG_BUF	= 0,
51	IDH_READY_TO_ACCESS_GPU,
52	IDH_FLR_NOTIFICATION,
53	IDH_FLR_NOTIFICATION_CMPL,
54	IDH_SUCCESS,
55	IDH_FAIL,
56	IDH_QUERY_ALIVE,
57	IDH_REQ_GPU_INIT_DATA_READY,
58	IDH_RAS_POISON_READY,
59	IDH_PF_SOFT_FLR_NOTIFICATION,
60	IDH_RAS_ERROR_DETECTED,
61	IDH_RAS_ERROR_COUNT_READY = 11,
62	IDH_RAS_CPER_DUMP_READY = 14,
63	IDH_RAS_BAD_PAGES_READY = 15,
64	IDH_RAS_BAD_PAGES_NOTIFICATION = 16,
65	IDH_UNRECOV_ERR_NOTIFICATION = 17,
66	IDH_REQ_RAS_CHK_CRITI_READY = 18,
67
68	IDH_TEXT_MESSAGE = 255,
69};
70
71extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
72
73void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);
74int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);
75int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);
76void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);
77
78#define mmMAILBOX_CONTROL 0xE5E
79
80#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
81#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1)
82
83#define mmMAILBOX_MSGBUF_TRN_DW0 0xE56
84#define mmMAILBOX_MSGBUF_TRN_DW1 0xE57
85#define mmMAILBOX_MSGBUF_TRN_DW2 0xE58
86#define mmMAILBOX_MSGBUF_TRN_DW3 0xE59
87
88#define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A
89#define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B
90#define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C
91#define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D
92
93#define mmMAILBOX_INT_CNTL 0xE5F
94
95#endif