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mmhub_v4_1_0.c
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c
1/* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "amdgpu.h" 25#include "mmhub_v4_1_0.h" 26 27#include "mmhub/mmhub_4_1_0_offset.h" 28#include "mmhub/mmhub_4_1_0_sh_mask.h" 29 30#include "soc15_common.h" 31#include "soc24_enum.h" 32 33#define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37static const char *mmhub_client_ids_v4_1_0[][2] = { 38 [0][0] = "VMC", 39 [4][0] = "DCEDMC", 40 [6][0] = "MP0", 41 [7][0] = "MP1", 42 [8][0] = "MPIO", 43 [16][0] = "LSDMA", 44 [17][0] = "JPEG", 45 [19][0] = "VCNU", 46 [22][0] = "VSCH", 47 [23][0] = "HDP", 48 [32+23][0] = "VCNRD", 49 [3][1] = "DCEDWB", 50 [4][1] = "DCEDMC", 51 [6][1] = "MP0", 52 [7][1] = "MP1", 53 [8][1] = "MPIO", 54 [10][1] = "DBGU0", 55 [11][1] = "DBGU1", 56 [12][1] = "DBGUNBIO", 57 [14][1] = "XDP", 58 [15][1] = "OSSSYS", 59 [16][1] = "LSDMA", 60 [17][1] = "JPEG", 61 [18][1] = "VCNWR", 62 [19][1] = "VCNU", 63 [22][1] = "VSCH", 64 [23][1] = "HDP", 65}; 66 67static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid, 68 uint32_t flush_type) 69{ 70 u32 req = 0; 71 72 /* invalidate using legacy mode on vmid*/ 73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 74 PER_VMID_INVALIDATE_REQ, 1 << vmid); 75 /* Only use legacy inv on mmhub side */ 76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 78 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 79 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 80 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 82 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 83 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 84 85 return req; 86} 87 88static void 89mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 90 uint32_t status) 91{ 92 uint32_t cid, rw; 93 const char *mmhub_cid = NULL; 94 95 cid = REG_GET_FIELD(status, 96 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); 97 rw = REG_GET_FIELD(status, 98 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW); 99 100 dev_err(adev->dev, 101 "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", 102 status); 103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 104 case IP_VERSION(4, 1, 0): 105 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ? 106 mmhub_client_ids_v4_1_0[cid][rw] : NULL; 107 break; 108 default: 109 mmhub_cid = NULL; 110 break; 111 } 112 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 113 mmhub_cid ? mmhub_cid : "unknown", cid); 114 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 115 REG_GET_FIELD(status, 116 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); 117 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 118 REG_GET_FIELD(status, 119 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); 120 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 121 REG_GET_FIELD(status, 122 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); 123 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 124 REG_GET_FIELD(status, 125 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); 126 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 127} 128 129static void mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device *adev, 130 uint32_t vmid, uint64_t page_table_base) 131{ 132 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 133 134 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 135 hub->ctx_addr_distance * vmid, 136 lower_32_bits(page_table_base)); 137 138 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 139 hub->ctx_addr_distance * vmid, 140 upper_32_bits(page_table_base)); 141} 142 143static void mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 144{ 145 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 146 147 mmhub_v4_1_0_setup_vm_pt_regs(adev, 0, pt_base); 148 149 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 150 (u32)(adev->gmc.gart_start >> 12)); 151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 152 (u32)(adev->gmc.gart_start >> 44)); 153 154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 155 (u32)(adev->gmc.gart_end >> 12)); 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 157 (u32)(adev->gmc.gart_end >> 44)); 158} 159 160static void mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device *adev) 161{ 162 uint64_t value; 163 uint32_t tmp; 164 165 /* 166 * the new L1 policy will block SRIOV guest from writing 167 * these regs, and they will be programed at host. 168 * so skip programing these regs. 169 */ 170 if (amdgpu_sriov_vf(adev)) 171 return; 172 173 /* Program the AGP BAR */ 174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 176 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 177 178 /* Program the system aperture low logical page number. */ 179 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 180 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 182 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 183 184 /* Set default page address. */ 185 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + 186 adev->vm_manager.vram_base_offset; 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 188 (u32)(value >> 12)); 189 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 190 (u32)(value >> 44)); 191 192 /* Program "protection fault". */ 193 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 194 (u32)(adev->dummy_page_addr >> 12)); 195 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 196 (u32)((u64)adev->dummy_page_addr >> 44)); 197 198 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 199 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 200 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 201 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 202} 203 204static void mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device *adev) 205{ 206 uint32_t tmp; 207 208 /* Setup TLB control */ 209 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 210 211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 214 ENABLE_ADVANCED_DRIVER_MODEL, 1); 215 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 216 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 219 MTYPE, MTYPE_UC); /* UC, uncached */ 220 221 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 222} 223 224static void mmhub_v4_1_0_init_cache_regs(struct amdgpu_device *adev) 225{ 226 uint32_t tmp; 227 228 /* These registers are not accessible to VF-SRIOV. 229 * The PF will program them instead. 230 */ 231 if (amdgpu_sriov_vf(adev)) 232 return; 233 234 /* Setup L2 cache */ 235 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 238 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 239 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 240 /* XXX for emulation, Refer to closed source code.*/ 241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 242 0); 243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 245 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 246 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 247 248 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 251 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 252 253 tmp = regMMVM_L2_CNTL3_DEFAULT; 254 if (adev->gmc.translate_further) { 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 257 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 258 } else { 259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 260 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 261 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 262 } 263 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 264 265 tmp = regMMVM_L2_CNTL4_DEFAULT; 266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 267 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 268 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 269 270 tmp = regMMVM_L2_CNTL5_DEFAULT; 271 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 272 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 273} 274 275static void mmhub_v4_1_0_enable_system_domain(struct amdgpu_device *adev) 276{ 277 uint32_t tmp; 278 279 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 280 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 281 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 282 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 283 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 284 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 285} 286 287static void mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device *adev) 288{ 289 /* These registers are not accessible to VF-SRIOV. 290 * The PF will program them instead. 291 */ 292 if (amdgpu_sriov_vf(adev)) 293 return; 294 295 WREG32_SOC15(MMHUB, 0, 296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 297 0xFFFFFFFF); 298 WREG32_SOC15(MMHUB, 0, 299 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 300 0x0000000F); 301 302 WREG32_SOC15(MMHUB, 0, 303 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 304 WREG32_SOC15(MMHUB, 0, 305 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 306 307 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 308 0); 309 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 310 0); 311} 312 313static void mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device *adev) 314{ 315 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 316 int i; 317 uint32_t tmp; 318 319 for (i = 0; i <= 14; i++) { 320 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); 321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 323 adev->vm_manager.num_level); 324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 325 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 327 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 328 1); 329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 330 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 332 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 334 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 336 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 337 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 338 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 339 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 340 PAGE_TABLE_BLOCK_SIZE, 341 adev->vm_manager.block_size - 9); 342 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 343 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 344 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 345 !amdgpu_noretry); 346 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 347 i * hub->ctx_distance, tmp); 348 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 349 i * hub->ctx_addr_distance, 0); 350 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 351 i * hub->ctx_addr_distance, 0); 352 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 353 i * hub->ctx_addr_distance, 354 lower_32_bits(adev->vm_manager.max_pfn - 1)); 355 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 356 i * hub->ctx_addr_distance, 357 upper_32_bits(adev->vm_manager.max_pfn - 1)); 358 } 359 360 hub->vm_cntx_cntl = tmp; 361} 362 363static void mmhub_v4_1_0_program_invalidation(struct amdgpu_device *adev) 364{ 365 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 366 unsigned i; 367 368 for (i = 0; i < 18; ++i) { 369 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 370 i * hub->eng_addr_distance, 0xffffffff); 371 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 372 i * hub->eng_addr_distance, 0x1f); 373 } 374} 375 376static int mmhub_v4_1_0_gart_enable(struct amdgpu_device *adev) 377{ 378 /* GART Enable. */ 379 mmhub_v4_1_0_init_gart_aperture_regs(adev); 380 mmhub_v4_1_0_init_system_aperture_regs(adev); 381 mmhub_v4_1_0_init_tlb_regs(adev); 382 mmhub_v4_1_0_init_cache_regs(adev); 383 384 mmhub_v4_1_0_enable_system_domain(adev); 385 mmhub_v4_1_0_disable_identity_aperture(adev); 386 mmhub_v4_1_0_setup_vmid_config(adev); 387 mmhub_v4_1_0_program_invalidation(adev); 388 389 return 0; 390} 391 392static void mmhub_v4_1_0_gart_disable(struct amdgpu_device *adev) 393{ 394 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 395 u32 tmp; 396 u32 i; 397 398 /* Disable all tables */ 399 for (i = 0; i < 16; i++) 400 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 401 i * hub->ctx_distance, 0); 402 403 /* Setup TLB control */ 404 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 405 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 406 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 407 ENABLE_ADVANCED_DRIVER_MODEL, 0); 408 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 409 410 /* Setup L2 cache */ 411 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 412 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 413 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 414 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 415} 416 417/** 418 * mmhub_v4_1_0_set_fault_enable_default - update GART/VM fault handling 419 * 420 * @adev: amdgpu_device pointer 421 * @value: true redirects VM faults to the default page 422 */ 423static void 424mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 425{ 426 u32 tmp; 427 428 /* These registers are not accessible to VF-SRIOV. 429 * The PF will program them instead. 430 */ 431 if (amdgpu_sriov_vf(adev)) 432 return; 433 434 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 436 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 438 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 440 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 442 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 444 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 445 value); 446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 447 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 449 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 450 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 451 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 452 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 453 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 454 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 455 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 456 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 457 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 458 if (!value) { 459 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 460 CRASH_ON_NO_RETRY_FAULT, 1); 461 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 462 CRASH_ON_RETRY_FAULT, 1); 463 } 464 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 465} 466 467static const struct amdgpu_vmhub_funcs mmhub_v4_1_0_vmhub_funcs = { 468 .print_l2_protection_fault_status = mmhub_v4_1_0_print_l2_protection_fault_status, 469 .get_invalidate_req = mmhub_v4_1_0_get_invalidate_req, 470}; 471 472static void mmhub_v4_1_0_init(struct amdgpu_device *adev) 473{ 474 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 475 476 hub->ctx0_ptb_addr_lo32 = 477 SOC15_REG_OFFSET(MMHUB, 0, 478 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 479 hub->ctx0_ptb_addr_hi32 = 480 SOC15_REG_OFFSET(MMHUB, 0, 481 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 482 hub->vm_inv_eng0_sem = 483 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 484 hub->vm_inv_eng0_req = 485 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 486 hub->vm_inv_eng0_ack = 487 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 488 hub->vm_context0_cntl = 489 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 490 hub->vm_l2_pro_fault_status = 491 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32); 492 hub->vm_l2_pro_fault_cntl = 493 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 494 495 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 496 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 497 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 498 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 499 regMMVM_INVALIDATE_ENG0_REQ; 500 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 501 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 502 503 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 504 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 505 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 506 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 507 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 508 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 509 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 510 511 hub->vm_l2_bank_select_reserved_cid2 = 512 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); 513 514 hub->vm_contexts_disable = 515 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); 516 517 hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs; 518} 519 520static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev) 521{ 522 u64 base; 523 524 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 525 526 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 527 base <<= 24; 528 529 return base; 530} 531 532static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev) 533{ 534 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 535} 536 537static void 538mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 539 bool enable) 540{ 541#if 0 542 uint32_t def, data; 543#endif 544 uint32_t def1, data1, def2 = 0, data2 = 0; 545#if 0 546 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 547#endif 548 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); 549 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); 550 551 if (enable) { 552#if 0 553 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 554#endif 555 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 556 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 557 558 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 559 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 560 } else { 561#if 0 562 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 563#endif 564 data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 565 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 566 567 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 568 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 569 } 570 571#if 0 572 if (def != data) 573 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 574#endif 575 if (def1 != data1) 576 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1); 577 578 if (def2 != data2) 579 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); 580} 581 582static void 583mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 584 bool enable) 585{ 586#if 0 587 uint32_t def, data; 588 589 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 590 591 if (enable) 592 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 593 else 594 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 595 596 if (def != data) 597 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 598#endif 599} 600 601static int mmhub_v4_1_0_set_clockgating(struct amdgpu_device *adev, 602 enum amd_clockgating_state state) 603{ 604 if (amdgpu_sriov_vf(adev)) 605 return 0; 606 607 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) 608 mmhub_v4_1_0_update_medium_grain_clock_gating(adev, 609 state == AMD_CG_STATE_GATE); 610 611 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) 612 mmhub_v4_1_0_update_medium_grain_light_sleep(adev, 613 state == AMD_CG_STATE_GATE); 614 615 return 0; 616} 617 618static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 619{ 620#if 0 621 int data; 622 623 if (amdgpu_sriov_vf(adev)) 624 *flags = 0; 625 626 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 627 628 /* AMD_CG_SUPPORT_MC_MGCG */ 629 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 630 *flags |= AMD_CG_SUPPORT_MC_MGCG; 631 632 /* AMD_CG_SUPPORT_MC_LS */ 633 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 634 *flags |= AMD_CG_SUPPORT_MC_LS; 635#endif 636} 637 638const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs = { 639 .init = mmhub_v4_1_0_init, 640 .get_fb_location = mmhub_v4_1_0_get_fb_location, 641 .get_mc_fb_offset = mmhub_v4_1_0_get_mc_fb_offset, 642 .gart_enable = mmhub_v4_1_0_gart_enable, 643 .set_fault_enable_default = mmhub_v4_1_0_set_fault_enable_default, 644 .gart_disable = mmhub_v4_1_0_gart_disable, 645 .set_clockgating = mmhub_v4_1_0_set_clockgating, 646 .get_clockgating = mmhub_v4_1_0_get_clockgating, 647 .setup_vm_pt_regs = mmhub_v4_1_0_setup_vm_pt_regs, 648};
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