jpeg_v5_0_1.h

  1/*
  2 * Copyright 2024 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef __JPEG_V5_0_1_H__
 25#define __JPEG_V5_0_1_H__
 26
 27extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block;
 28
 29#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET			0x4094
 30#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET			0x1bffe
 31
 32#define regUVD_JRBC0_UVD_JRBC_RB_WPTR                                                         0x0640
 33#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX                                                1
 34#define regUVD_JRBC0_UVD_JRBC_STATUS                                                          0x0649
 35#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX                                                 1
 36#define regUVD_JRBC0_UVD_JRBC_RB_RPTR                                                         0x064a
 37#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX                                                1
 38#define regUVD_JRBC1_UVD_JRBC_RB_WPTR                                                         0x0000
 39#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 40#define regUVD_JRBC1_UVD_JRBC_STATUS                                                          0x0009
 41#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX                                                 0
 42#define regUVD_JRBC1_UVD_JRBC_RB_RPTR                                                         0x000a
 43#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 44#define regUVD_JRBC2_UVD_JRBC_RB_WPTR                                                         0x0040
 45#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 46#define regUVD_JRBC2_UVD_JRBC_STATUS                                                          0x0049
 47#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX                                                 0
 48#define regUVD_JRBC2_UVD_JRBC_RB_RPTR                                                         0x004a
 49#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 50#define regUVD_JRBC3_UVD_JRBC_RB_WPTR                                                         0x0080
 51#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 52#define regUVD_JRBC3_UVD_JRBC_STATUS                                                          0x0089
 53#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX                                                 0
 54#define regUVD_JRBC3_UVD_JRBC_RB_RPTR                                                         0x008a
 55#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 56#define regUVD_JRBC4_UVD_JRBC_RB_WPTR                                                         0x00c0
 57#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 58#define regUVD_JRBC4_UVD_JRBC_STATUS                                                          0x00c9
 59#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX                                                 0
 60#define regUVD_JRBC4_UVD_JRBC_RB_RPTR                                                         0x00ca
 61#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 62#define regUVD_JRBC5_UVD_JRBC_RB_WPTR                                                         0x0100
 63#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 64#define regUVD_JRBC5_UVD_JRBC_STATUS                                                          0x0109
 65#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX                                                 0
 66#define regUVD_JRBC5_UVD_JRBC_RB_RPTR                                                         0x010a
 67#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 68#define regUVD_JRBC6_UVD_JRBC_RB_WPTR                                                         0x0140
 69#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 70#define regUVD_JRBC6_UVD_JRBC_STATUS                                                          0x0149
 71#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX                                                 0
 72#define regUVD_JRBC6_UVD_JRBC_RB_RPTR                                                         0x014a
 73#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 74#define regUVD_JRBC7_UVD_JRBC_RB_WPTR                                                         0x0180
 75#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 76#define regUVD_JRBC7_UVD_JRBC_STATUS                                                          0x0189
 77#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX                                                 0
 78#define regUVD_JRBC7_UVD_JRBC_RB_RPTR                                                         0x018a
 79#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 80#define regUVD_JRBC8_UVD_JRBC_RB_WPTR                                                         0x01c0
 81#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
 82#define regUVD_JRBC8_UVD_JRBC_STATUS                                                          0x01c9
 83#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX                                                 0
 84#define regUVD_JRBC8_UVD_JRBC_RB_RPTR                                                         0x01ca
 85#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
 86#define regUVD_JRBC9_UVD_JRBC_RB_WPTR                                                         0x0440
 87#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX                                                1
 88#define regUVD_JRBC9_UVD_JRBC_STATUS                                                          0x0449
 89#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX                                                 1
 90#define regUVD_JRBC9_UVD_JRBC_RB_RPTR                                                         0x044a
 91#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX                                                1
 92#define regUVD_JMI0_JPEG_LMI_DROP                                                             0x0663
 93#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX                                                    1
 94#define regUVD_JMI0_UVD_JMI_CLIENT_STALL                                                      0x067a
 95#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX                                             1
 96#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS                                               0x067b
 97#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX                                      1
 98#define regJPEG_CORE_RST_CTRL                                                                 0x072e
 99#define regJPEG_CORE_RST_CTRL_BASE_IDX                                                        1
100
101#define regVCN_RRMT_CNTL                          0x0940
102#define regVCN_RRMT_CNTL_BASE_IDX                 1
103
104enum amdgpu_jpeg_v5_0_1_sub_block {
105	AMDGPU_JPEG_V5_0_1_JPEG0 = 0,
106	AMDGPU_JPEG_V5_0_1_JPEG1,
107
108	AMDGPU_JPEG_V5_0_1_MAX_SUB_BLOCK,
109};
110
111#endif /* __JPEG_V5_0_1_H__ */