jpeg_v4_0.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include "amdgpu.h"
 25#include "amdgpu_jpeg.h"
 26#include "amdgpu_pm.h"
 27#include "soc15.h"
 28#include "soc15d.h"
 29#include "jpeg_v2_0.h"
 30#include "jpeg_v4_0.h"
 31#include "mmsch_v4_0.h"
 32
 33#include "vcn/vcn_4_0_0_offset.h"
 34#include "vcn/vcn_4_0_0_sh_mask.h"
 35#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
 36
 37#define regUVD_JPEG_PITCH_INTERNAL_OFFSET                  0x401f
 38
 39static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = {
 40	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
 41	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
 42	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
 43	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
 44	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
 45	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
 46	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
 47	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
 48	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
 49	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
 50	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
 51	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
 52	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
 53};
 54
 55static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
 56static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 57static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 58static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
 59				enum amd_powergating_state state);
 60static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
 61static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
 62
 63/**
 64 * jpeg_v4_0_early_init - set function pointers
 65 *
 66 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 67 *
 68 * Set ring and irq function pointers
 69 */
 70static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block)
 71{
 72	struct amdgpu_device *adev = ip_block->adev;
 73
 74
 75	adev->jpeg.num_jpeg_inst = 1;
 76	adev->jpeg.num_jpeg_rings = 1;
 77
 78	jpeg_v4_0_set_dec_ring_funcs(adev);
 79	jpeg_v4_0_set_irq_funcs(adev);
 80	jpeg_v4_0_set_ras_funcs(adev);
 81
 82	return 0;
 83}
 84
 85/**
 86 * jpeg_v4_0_sw_init - sw init for JPEG block
 87 *
 88 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 89 *
 90 * Load firmware and sw initialization
 91 */
 92static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
 93{
 94	struct amdgpu_device *adev = ip_block->adev;
 95	struct amdgpu_ring *ring;
 96	int r;
 97
 98	/* JPEG TRAP */
 99	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
100		VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
101	if (r)
102		return r;
103
104	/* JPEG DJPEG POISON EVENT */
105	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
106			VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
107	if (r)
108		return r;
109
110	/* JPEG EJPEG POISON EVENT */
111	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
112			VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
113	if (r)
114		return r;
115
116	r = amdgpu_jpeg_sw_init(adev);
117	if (r)
118		return r;
119
120	r = amdgpu_jpeg_resume(adev);
121	if (r)
122		return r;
123
124	ring = adev->jpeg.inst->ring_dec;
125	ring->use_doorbell = true;
126	ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1);
127	ring->vm_hub = AMDGPU_MMHUB0(0);
128
129	sprintf(ring->name, "jpeg_dec");
130	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
131			     AMDGPU_RING_PRIO_DEFAULT, NULL);
132	if (r)
133		return r;
134
135	adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
136	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
137
138	r = amdgpu_jpeg_ras_sw_init(adev);
139	if (r)
140		return r;
141
142	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0));
143	if (r)
144		return r;
145
146	adev->jpeg.supported_reset =
147		amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
148	if (!amdgpu_sriov_vf(adev))
149		adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
150	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
151
152	return r;
153}
154
155/**
156 * jpeg_v4_0_sw_fini - sw fini for JPEG block
157 *
158 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
159 *
160 * JPEG suspend and free up sw allocation
161 */
162static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
163{
164	struct amdgpu_device *adev = ip_block->adev;
165	int r;
166
167	r = amdgpu_jpeg_suspend(adev);
168	if (r)
169		return r;
170
171	amdgpu_jpeg_sysfs_reset_mask_fini(adev);
172	r = amdgpu_jpeg_sw_fini(adev);
173
174	return r;
175}
176
177/**
178 * jpeg_v4_0_hw_init - start and test JPEG block
179 *
180 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
181 *
182 */
183static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
184{
185	struct amdgpu_device *adev = ip_block->adev;
186	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
187	int r;
188
189	if (amdgpu_sriov_vf(adev)) {
190		r = jpeg_v4_0_start_sriov(adev);
191		if (r)
192			return r;
193		ring->wptr = 0;
194		ring->wptr_old = 0;
195		jpeg_v4_0_dec_ring_set_wptr(ring);
196		ring->sched.ready = true;
197	} else {
198		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
199						(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
200
201		WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
202			ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
203			VCN_JPEG_DB_CTRL__EN_MASK);
204
205		r = amdgpu_ring_test_helper(ring);
206		if (r)
207			return r;
208	}
209
210	return 0;
211}
212
213/**
214 * jpeg_v4_0_hw_fini - stop the hardware block
215 *
216 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
217 *
218 * Stop the JPEG block, mark ring as not ready any more
219 */
220static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
221{
222	struct amdgpu_device *adev = ip_block->adev;
223
224	cancel_delayed_work_sync(&adev->jpeg.idle_work);
225	if (!amdgpu_sriov_vf(adev)) {
226		if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
227			RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
228			jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
229	}
230	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
231		amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
232
233	return 0;
234}
235
236/**
237 * jpeg_v4_0_suspend - suspend JPEG block
238 *
239 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
240 *
241 * HW fini and suspend JPEG block
242 */
243static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block)
244{
245	int r;
246
247	r = jpeg_v4_0_hw_fini(ip_block);
248	if (r)
249		return r;
250
251	r = amdgpu_jpeg_suspend(ip_block->adev);
252
253	return r;
254}
255
256/**
257 * jpeg_v4_0_resume - resume JPEG block
258 *
259 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
260 *
261 * Resume firmware and hw init JPEG block
262 */
263static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block)
264{
265	int r;
266
267	r = amdgpu_jpeg_resume(ip_block->adev);
268	if (r)
269		return r;
270
271	r = jpeg_v4_0_hw_init(ip_block);
272
273	return r;
274}
275
276static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev)
277{
278	uint32_t data = 0;
279
280	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
281	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
282		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
283		data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK);
284	} else {
285		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
286	}
287
288	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
289	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
290	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
291
292	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
293	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
294		| JPEG_CGC_GATE__JPEG2_DEC_MASK
295		| JPEG_CGC_GATE__JMCIF_MASK
296		| JPEG_CGC_GATE__JRBBM_MASK);
297	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
298}
299
300static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev)
301{
302	uint32_t data = 0;
303
304	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
305	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
306		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
307		data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK;
308	} else {
309		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
310	}
311
312	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
313	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
314	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
315
316	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
317	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
318		|JPEG_CGC_GATE__JPEG2_DEC_MASK
319		|JPEG_CGC_GATE__JMCIF_MASK
320		|JPEG_CGC_GATE__JRBBM_MASK);
321	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
322}
323
324static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev)
325{
326	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
327		uint32_t data = 0;
328		int r = 0;
329
330		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
331		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
332
333		r = SOC15_WAIT_ON_RREG(JPEG, 0,
334			regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
335			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
336
337		if (r) {
338			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n");
339			return r;
340		}
341	}
342
343	/* disable anti hang mechanism */
344	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
345		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
346
347	/* keep the JPEG in static PG mode */
348	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
349		~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
350
351	return 0;
352}
353
354static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev)
355{
356	/* enable anti hang mechanism */
357	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
358		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
359		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
360
361	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
362		uint32_t data = 0;
363		int r = 0;
364
365		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
366		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
367
368		r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,
369			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
370			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
371
372		if (r) {
373			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n");
374			return r;
375		}
376	}
377
378	return 0;
379}
380
381/**
382 * jpeg_v4_0_start - start JPEG block
383 *
384 * @adev: amdgpu_device pointer
385 *
386 * Setup and start the JPEG block
387 */
388static int jpeg_v4_0_start(struct amdgpu_device *adev)
389{
390	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
391	int r;
392
393	if (adev->pm.dpm_enabled)
394		amdgpu_dpm_enable_jpeg(adev, true);
395
396	/* disable power gating */
397	r = jpeg_v4_0_disable_static_power_gating(adev);
398	if (r)
399		return r;
400
401	/* JPEG disable CGC */
402	jpeg_v4_0_disable_clock_gating(adev);
403
404	/* MJPEG global tiling registers */
405	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
406		adev->gfx.config.gb_addr_config);
407
408
409	/* enable JMI channel */
410	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
411		~UVD_JMI_CNTL__SOFT_RESET_MASK);
412
413	/* enable System Interrupt for JRBC */
414	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
415		JPEG_SYS_INT_EN__DJRBC_MASK,
416		~JPEG_SYS_INT_EN__DJRBC_MASK);
417
418	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
419	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
420	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
421		lower_32_bits(ring->gpu_addr));
422	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
423		upper_32_bits(ring->gpu_addr));
424	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
425	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
426	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
427	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
428	ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
429
430	return 0;
431}
432
433static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev)
434{
435	struct amdgpu_ring *ring;
436	uint64_t ctx_addr;
437	uint32_t param, resp, expected;
438	uint32_t tmp, timeout;
439
440	struct amdgpu_mm_table *table = &adev->virt.mm_table;
441	uint32_t *table_loc;
442	uint32_t table_size;
443	uint32_t size, size_dw;
444	uint32_t init_status;
445
446	struct mmsch_v4_0_cmd_direct_write
447		direct_wt = { {0} };
448	struct mmsch_v4_0_cmd_end end = { {0} };
449	struct mmsch_v4_0_init_header header;
450
451	direct_wt.cmd_header.command_type =
452		MMSCH_COMMAND__DIRECT_REG_WRITE;
453	end.cmd_header.command_type =
454		MMSCH_COMMAND__END;
455
456	size = sizeof(struct mmsch_v4_0_init_header);
457	table_loc = (uint32_t *)table->cpu_addr;
458	memcpy(&header, (void *)table_loc, size);
459
460	header.version = MMSCH_VERSION;
461	header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);
462
463	header.jpegdec.init_status = 0;
464	header.jpegdec.table_offset = 0;
465	header.jpegdec.table_size = 0;
466
467	table_loc = (uint32_t *)table->cpu_addr;
468	table_loc += header.total_size;
469
470	table_size = 0;
471
472	ring = adev->jpeg.inst->ring_dec;
473
474	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
475		regUVD_LMI_JRBC_RB_64BIT_BAR_LOW),
476		lower_32_bits(ring->gpu_addr));
477	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
478		regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH),
479		upper_32_bits(ring->gpu_addr));
480	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
481		regUVD_JRBC_RB_SIZE), ring->ring_size / 4);
482
483	/* add end packet */
484	MMSCH_V4_0_INSERT_END();
485
486	/* refine header */
487	header.jpegdec.init_status = 0;
488	header.jpegdec.table_offset = header.total_size;
489	header.jpegdec.table_size = table_size;
490	header.total_size += table_size;
491
492	/* Update init table header in memory */
493	size = sizeof(struct mmsch_v4_0_init_header);
494	table_loc = (uint32_t *)table->cpu_addr;
495	memcpy((void *)table_loc, &header, size);
496
497	/* Perform HDP flush before writing to MMSCH registers */
498	amdgpu_device_flush_hdp(adev, NULL);
499
500	/* message MMSCH (in VCN[0]) to initialize this client
501	 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
502	 * of memory descriptor location
503	 */
504	ctx_addr = table->gpu_addr;
505	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
506	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
507
508	/* 2, update vmid of descriptor */
509	tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
510	tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
511	/* use domain0 for MM scheduler */
512	tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
513	WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
514
515	/* 3, notify mmsch about the size of this descriptor */
516	size = header.total_size;
517	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
518
519	/* 4, set resp to zero */
520	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
521
522	/* 5, kick off the initialization and wait until
523	 * MMSCH_VF_MAILBOX_RESP becomes non-zero
524	 */
525	param = 0x00000001;
526	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
527	tmp = 0;
528	timeout = 1000;
529	resp = 0;
530	expected = MMSCH_VF_MAILBOX_RESP__OK;
531	init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status;
532	while (resp != expected) {
533		resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
534
535		if (resp != 0)
536			break;
537		udelay(10);
538		tmp = tmp + 10;
539		if (tmp >= timeout) {
540			DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
541				" waiting for regMMSCH_VF_MAILBOX_RESP "\
542				"(expected=0x%08x, readback=0x%08x)\n",
543				tmp, expected, resp);
544			return -EBUSY;
545		}
546	}
547	if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
548			&& init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
549		DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status);
550		return -EINVAL;
551	}
552
553	return 0;
554
555}
556
557/**
558 * jpeg_v4_0_stop - stop JPEG block
559 *
560 * @adev: amdgpu_device pointer
561 *
562 * stop the JPEG block
563 */
564static int jpeg_v4_0_stop(struct amdgpu_device *adev)
565{
566	int r;
567
568	/* reset JMI */
569	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
570		UVD_JMI_CNTL__SOFT_RESET_MASK,
571		~UVD_JMI_CNTL__SOFT_RESET_MASK);
572
573	jpeg_v4_0_enable_clock_gating(adev);
574
575	/* enable power gating */
576	r = jpeg_v4_0_enable_static_power_gating(adev);
577	if (r)
578		return r;
579
580	if (adev->pm.dpm_enabled)
581		amdgpu_dpm_enable_jpeg(adev, false);
582
583	return 0;
584}
585
586/**
587 * jpeg_v4_0_dec_ring_get_rptr - get read pointer
588 *
589 * @ring: amdgpu_ring pointer
590 *
591 * Returns the current hardware read pointer
592 */
593static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
594{
595	struct amdgpu_device *adev = ring->adev;
596
597	return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
598}
599
600/**
601 * jpeg_v4_0_dec_ring_get_wptr - get write pointer
602 *
603 * @ring: amdgpu_ring pointer
604 *
605 * Returns the current hardware write pointer
606 */
607static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
608{
609	struct amdgpu_device *adev = ring->adev;
610
611	if (ring->use_doorbell)
612		return *ring->wptr_cpu_addr;
613	else
614		return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
615}
616
617/**
618 * jpeg_v4_0_dec_ring_set_wptr - set write pointer
619 *
620 * @ring: amdgpu_ring pointer
621 *
622 * Commits the write pointer to the hardware
623 */
624static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
625{
626	struct amdgpu_device *adev = ring->adev;
627
628	if (ring->use_doorbell) {
629		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
630		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
631	} else {
632		WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
633	}
634}
635
636static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
637{
638	struct amdgpu_device *adev = ip_block->adev;
639	int ret = 1;
640
641	ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
642		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
643		UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
644
645	return ret;
646}
647
648static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
649{
650	struct amdgpu_device *adev = ip_block->adev;
651
652	return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
653		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
654		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
655}
656
657static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
658					  enum amd_clockgating_state state)
659{
660	struct amdgpu_device *adev = ip_block->adev;
661	bool enable = state == AMD_CG_STATE_GATE;
662
663	if (enable) {
664		if (!jpeg_v4_0_is_idle(ip_block))
665			return -EBUSY;
666		jpeg_v4_0_enable_clock_gating(adev);
667	} else {
668		jpeg_v4_0_disable_clock_gating(adev);
669	}
670
671	return 0;
672}
673
674static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
675					  enum amd_powergating_state state)
676{
677	struct amdgpu_device *adev = ip_block->adev;
678	int ret;
679
680	if (amdgpu_sriov_vf(adev)) {
681		adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
682		return 0;
683	}
684
685	if (state == adev->jpeg.cur_state)
686		return 0;
687
688	if (state == AMD_PG_STATE_GATE)
689		ret = jpeg_v4_0_stop(adev);
690	else
691		ret = jpeg_v4_0_start(adev);
692
693	if (!ret)
694		adev->jpeg.cur_state = state;
695
696	return ret;
697}
698
699static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
700					struct amdgpu_irq_src *source,
701					unsigned int type,
702					enum amdgpu_interrupt_state state)
703{
704	return 0;
705}
706
707static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
708				      struct amdgpu_irq_src *source,
709				      struct amdgpu_iv_entry *entry)
710{
711	DRM_DEBUG("IH: JPEG TRAP\n");
712
713	switch (entry->src_id) {
714	case VCN_4_0__SRCID__JPEG_DECODE:
715		amdgpu_fence_process(adev->jpeg.inst->ring_dec);
716		break;
717	default:
718		DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
719			  entry->src_id, entry->src_data[0]);
720		break;
721	}
722
723	return 0;
724}
725
726static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring,
727				unsigned int vmid,
728				struct amdgpu_fence *timedout_fence)
729{
730	int r;
731
732	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
733	r = jpeg_v4_0_stop(ring->adev);
734	if (r)
735		return r;
736	r = jpeg_v4_0_start(ring->adev);
737	if (r)
738		return r;
739	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
740}
741
742static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
743	.name = "jpeg_v4_0",
744	.early_init = jpeg_v4_0_early_init,
745	.sw_init = jpeg_v4_0_sw_init,
746	.sw_fini = jpeg_v4_0_sw_fini,
747	.hw_init = jpeg_v4_0_hw_init,
748	.hw_fini = jpeg_v4_0_hw_fini,
749	.suspend = jpeg_v4_0_suspend,
750	.resume = jpeg_v4_0_resume,
751	.is_idle = jpeg_v4_0_is_idle,
752	.wait_for_idle = jpeg_v4_0_wait_for_idle,
753	.set_clockgating_state = jpeg_v4_0_set_clockgating_state,
754	.set_powergating_state = jpeg_v4_0_set_powergating_state,
755	.dump_ip_state = amdgpu_jpeg_dump_ip_state,
756	.print_ip_state = amdgpu_jpeg_print_ip_state,
757};
758
759static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
760	.type = AMDGPU_RING_TYPE_VCN_JPEG,
761	.align_mask = 0xf,
762	.get_rptr = jpeg_v4_0_dec_ring_get_rptr,
763	.get_wptr = jpeg_v4_0_dec_ring_get_wptr,
764	.set_wptr = jpeg_v4_0_dec_ring_set_wptr,
765	.parse_cs = amdgpu_jpeg_dec_parse_cs,
766	.emit_frame_size =
767		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
768		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
769		8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */
770		18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */
771		8 + 16,
772	.emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */
773	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
774	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
775	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
776	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
777	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
778	.insert_nop = jpeg_v2_0_dec_ring_nop,
779	.insert_start = jpeg_v2_0_dec_ring_insert_start,
780	.insert_end = jpeg_v2_0_dec_ring_insert_end,
781	.pad_ib = amdgpu_ring_generic_pad_ib,
782	.begin_use = amdgpu_jpeg_ring_begin_use,
783	.end_use = amdgpu_jpeg_ring_end_use,
784	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
785	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
786	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
787	.reset = jpeg_v4_0_ring_reset,
788};
789
790static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
791{
792	adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs;
793}
794
795static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {
796	.process = jpeg_v4_0_process_interrupt,
797};
798
799static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = {
800	.set = jpeg_v4_0_set_ras_interrupt_state,
801	.process = amdgpu_jpeg_process_poison_irq,
802};
803
804static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev)
805{
806	adev->jpeg.inst->irq.num_types = 1;
807	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
808
809	adev->jpeg.inst->ras_poison_irq.num_types = 1;
810	adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
811}
812
813const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = {
814	.type = AMD_IP_BLOCK_TYPE_JPEG,
815	.major = 4,
816	.minor = 0,
817	.rev = 0,
818	.funcs = &jpeg_v4_0_ip_funcs,
819};
820
821static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
822		uint32_t instance, uint32_t sub_block)
823{
824	uint32_t poison_stat = 0, reg_value = 0;
825
826	switch (sub_block) {
827	case AMDGPU_JPEG_V4_0_JPEG0:
828		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);
829		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
830		break;
831	case AMDGPU_JPEG_V4_0_JPEG1:
832		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);
833		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
834		break;
835	default:
836		break;
837	}
838
839	if (poison_stat)
840		dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
841			instance, sub_block);
842
843	return poison_stat;
844}
845
846static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
847{
848	uint32_t inst = 0, sub = 0, poison_stat = 0;
849
850	for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
851		for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++)
852			poison_stat +=
853				jpeg_v4_0_query_poison_by_instance(adev, inst, sub);
854
855	return !!poison_stat;
856}
857
858const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = {
859	.query_poison_status = jpeg_v4_0_query_ras_poison_status,
860};
861
862static struct amdgpu_jpeg_ras jpeg_v4_0_ras = {
863	.ras_block = {
864		.hw_ops = &jpeg_v4_0_ras_hw_ops,
865		.ras_late_init = amdgpu_jpeg_ras_late_init,
866	},
867};
868
869static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev)
870{
871	switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) {
872	case IP_VERSION(4, 0, 0):
873		adev->jpeg.ras = &jpeg_v4_0_ras;
874		break;
875	default:
876		break;
877	}
878}