jpeg_v2_0.c

  1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include "amdgpu.h"
 25#include "amdgpu_jpeg.h"
 26#include "amdgpu_pm.h"
 27#include "soc15.h"
 28#include "soc15d.h"
 29#include "jpeg_v2_0.h"
 30
 31#include "vcn/vcn_2_0_0_offset.h"
 32#include "vcn/vcn_2_0_0_sh_mask.h"
 33#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
 34
 35static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = {
 36	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
 37	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
 38	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
 39	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
 40	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
 41	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
 42	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
 43	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
 44	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
 45	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
 46	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),
 47	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
 48	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),
 49};
 50
 51static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 52static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
 53static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
 54				enum amd_powergating_state state);
 55
 56/**
 57 * jpeg_v2_0_early_init - set function pointers
 58 *
 59 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 60 *
 61 * Set ring and irq function pointers
 62 */
 63static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block)
 64{
 65	struct amdgpu_device *adev = ip_block->adev;
 66
 67	adev->jpeg.num_jpeg_inst = 1;
 68	adev->jpeg.num_jpeg_rings = 1;
 69
 70	jpeg_v2_0_set_dec_ring_funcs(adev);
 71	jpeg_v2_0_set_irq_funcs(adev);
 72
 73	return 0;
 74}
 75
 76/**
 77 * jpeg_v2_0_sw_init - sw init for JPEG block
 78 *
 79 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 80 *
 81 * Load firmware and sw initialization
 82 */
 83static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
 84{
 85	struct amdgpu_device *adev = ip_block->adev;
 86	struct amdgpu_ring *ring;
 87	int r;
 88
 89	/* JPEG TRAP */
 90	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 91		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
 92	if (r)
 93		return r;
 94
 95	r = amdgpu_jpeg_sw_init(adev);
 96	if (r)
 97		return r;
 98
 99	r = amdgpu_jpeg_resume(adev);
100	if (r)
101		return r;
102
103	ring = adev->jpeg.inst->ring_dec;
104	ring->use_doorbell = true;
105	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
106	ring->vm_hub = AMDGPU_MMHUB0(0);
107	sprintf(ring->name, "jpeg_dec");
108	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
109			     0, AMDGPU_RING_PRIO_DEFAULT, NULL);
110	if (r)
111		return r;
112
113	adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
114	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
115
116	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0));
117	if (r)
118		return r;
119
120	adev->jpeg.supported_reset =
121		amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
122	if (!amdgpu_sriov_vf(adev))
123		adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
124	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
125
126	return r;
127}
128
129/**
130 * jpeg_v2_0_sw_fini - sw fini for JPEG block
131 *
132 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
133 *
134 * JPEG suspend and free up sw allocation
135 */
136static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
137{
138	int r;
139	struct amdgpu_device *adev = ip_block->adev;
140
141	r = amdgpu_jpeg_suspend(adev);
142	if (r)
143		return r;
144
145	amdgpu_jpeg_sysfs_reset_mask_fini(adev);
146
147	r = amdgpu_jpeg_sw_fini(adev);
148
149	return r;
150}
151
152/**
153 * jpeg_v2_0_hw_init - start and test JPEG block
154 *
155 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
156 *
157 */
158static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
159{
160	struct amdgpu_device *adev = ip_block->adev;
161	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
162
163	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
164		(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
165
166	return amdgpu_ring_test_helper(ring);
167}
168
169/**
170 * jpeg_v2_0_hw_fini - stop the hardware block
171 *
172 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
173 *
174 * Stop the JPEG block, mark ring as not ready any more
175 */
176static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
177{
178	struct amdgpu_device *adev = ip_block->adev;
179
180	cancel_delayed_work_sync(&adev->jpeg.idle_work);
181
182	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
183	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
184		jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
185
186	return 0;
187}
188
189/**
190 * jpeg_v2_0_suspend - suspend JPEG block
191 *
192 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
193 *
194 * HW fini and suspend JPEG block
195 */
196static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block)
197{
198	int r;
199
200	r = jpeg_v2_0_hw_fini(ip_block);
201	if (r)
202		return r;
203
204	r = amdgpu_jpeg_suspend(ip_block->adev);
205
206	return r;
207}
208
209/**
210 * jpeg_v2_0_resume - resume JPEG block
211 *
212 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
213 *
214 * Resume firmware and hw init JPEG block
215 */
216static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block)
217{
218	int r;
219
220	r = amdgpu_jpeg_resume(ip_block->adev);
221	if (r)
222		return r;
223
224	r = jpeg_v2_0_hw_init(ip_block);
225
226	return r;
227}
228
229static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
230{
231	uint32_t data;
232	int r = 0;
233
234	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
235		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
236		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
237
238		r = SOC15_WAIT_ON_RREG(JPEG, 0,
239			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
240			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
241
242		if (r) {
243			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
244			return r;
245		}
246	}
247
248	/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
249	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
250	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
251
252	return 0;
253}
254
255static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
256{
257	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
258		uint32_t data;
259		int r = 0;
260
261		data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
262		data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
263		data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
264		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
265
266		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
267		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
268
269		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
270			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
271			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
272
273		if (r) {
274			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
275			return r;
276		}
277	}
278
279	return 0;
280}
281
282static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
283{
284	uint32_t data;
285
286	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
287	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
288		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
289	else
290		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
291
292	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
293	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
294	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
295
296	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
297	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
298		| JPEG_CGC_GATE__JPEG2_DEC_MASK
299		| JPEG_CGC_GATE__JPEG_ENC_MASK
300		| JPEG_CGC_GATE__JMCIF_MASK
301		| JPEG_CGC_GATE__JRBBM_MASK);
302	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
303}
304
305static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
306{
307	uint32_t data;
308
309	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
310	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
311		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
312	else
313		data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
314
315	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
316	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
317	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
318
319	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
320	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
321		|JPEG_CGC_GATE__JPEG2_DEC_MASK
322		|JPEG_CGC_GATE__JPEG_ENC_MASK
323		|JPEG_CGC_GATE__JMCIF_MASK
324		|JPEG_CGC_GATE__JRBBM_MASK);
325	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
326}
327
328/**
329 * jpeg_v2_0_start - start JPEG block
330 *
331 * @adev: amdgpu_device pointer
332 *
333 * Setup and start the JPEG block
334 */
335static int jpeg_v2_0_start(struct amdgpu_device *adev)
336{
337	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
338	int r;
339
340	if (adev->pm.dpm_enabled)
341		amdgpu_dpm_enable_jpeg(adev, true);
342
343	/* disable power gating */
344	r = jpeg_v2_0_disable_power_gating(adev);
345	if (r)
346		return r;
347
348	/* JPEG disable CGC */
349	jpeg_v2_0_disable_clock_gating(adev);
350
351	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
352
353	/* enable JMI channel */
354	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
355		~UVD_JMI_CNTL__SOFT_RESET_MASK);
356
357	/* enable System Interrupt for JRBC */
358	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
359		JPEG_SYS_INT_EN__DJRBC_MASK,
360		~JPEG_SYS_INT_EN__DJRBC_MASK);
361
362	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
363	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
364	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
365		lower_32_bits(ring->gpu_addr));
366	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
367		upper_32_bits(ring->gpu_addr));
368	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
369	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
370	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
371	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
372	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
373
374	return 0;
375}
376
377/**
378 * jpeg_v2_0_stop - stop JPEG block
379 *
380 * @adev: amdgpu_device pointer
381 *
382 * stop the JPEG block
383 */
384static int jpeg_v2_0_stop(struct amdgpu_device *adev)
385{
386	int r;
387
388	/* reset JMI */
389	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
390		UVD_JMI_CNTL__SOFT_RESET_MASK,
391		~UVD_JMI_CNTL__SOFT_RESET_MASK);
392
393	/* enable JPEG CGC */
394	jpeg_v2_0_enable_clock_gating(adev);
395
396	/* enable power gating */
397	r = jpeg_v2_0_enable_power_gating(adev);
398	if (r)
399		return r;
400
401	if (adev->pm.dpm_enabled)
402		amdgpu_dpm_enable_jpeg(adev, false);
403
404	return 0;
405}
406
407/**
408 * jpeg_v2_0_dec_ring_get_rptr - get read pointer
409 *
410 * @ring: amdgpu_ring pointer
411 *
412 * Returns the current hardware read pointer
413 */
414static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
415{
416	struct amdgpu_device *adev = ring->adev;
417
418	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
419}
420
421/**
422 * jpeg_v2_0_dec_ring_get_wptr - get write pointer
423 *
424 * @ring: amdgpu_ring pointer
425 *
426 * Returns the current hardware write pointer
427 */
428static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
429{
430	struct amdgpu_device *adev = ring->adev;
431
432	if (ring->use_doorbell)
433		return *ring->wptr_cpu_addr;
434	else
435		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
436}
437
438/**
439 * jpeg_v2_0_dec_ring_set_wptr - set write pointer
440 *
441 * @ring: amdgpu_ring pointer
442 *
443 * Commits the write pointer to the hardware
444 */
445static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
446{
447	struct amdgpu_device *adev = ring->adev;
448
449	if (ring->use_doorbell) {
450		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
451		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
452	} else {
453		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
454	}
455}
456
457/**
458 * jpeg_v2_0_dec_ring_insert_start - insert a start command
459 *
460 * @ring: amdgpu_ring pointer
461 *
462 * Write a start command to the ring.
463 */
464void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
465{
466	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
467		0, 0, PACKETJ_TYPE0));
468	amdgpu_ring_write(ring, 0x68e04);
469
470	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
471		0, 0, PACKETJ_TYPE0));
472	amdgpu_ring_write(ring, 0x80010000);
473}
474
475/**
476 * jpeg_v2_0_dec_ring_insert_end - insert a end command
477 *
478 * @ring: amdgpu_ring pointer
479 *
480 * Write a end command to the ring.
481 */
482void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
483{
484	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
485		0, 0, PACKETJ_TYPE0));
486	amdgpu_ring_write(ring, 0x68e04);
487
488	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
489		0, 0, PACKETJ_TYPE0));
490	amdgpu_ring_write(ring, 0x00010000);
491}
492
493/**
494 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
495 *
496 * @ring: amdgpu_ring pointer
497 * @addr: address
498 * @seq: sequence number
499 * @flags: fence related flags
500 *
501 * Write a fence and a trap command to the ring.
502 */
503void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
504				unsigned flags)
505{
506	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
507
508	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
509		0, 0, PACKETJ_TYPE0));
510	amdgpu_ring_write(ring, seq);
511
512	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
513		0, 0, PACKETJ_TYPE0));
514	amdgpu_ring_write(ring, seq);
515
516	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
517		0, 0, PACKETJ_TYPE0));
518	amdgpu_ring_write(ring, lower_32_bits(addr));
519
520	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
521		0, 0, PACKETJ_TYPE0));
522	amdgpu_ring_write(ring, upper_32_bits(addr));
523
524	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
525		0, 0, PACKETJ_TYPE0));
526	amdgpu_ring_write(ring, 0x8);
527
528	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
529		0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
530	amdgpu_ring_write(ring, 0);
531
532	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
533		0, 0, PACKETJ_TYPE0));
534	amdgpu_ring_write(ring, 0x3fbc);
535
536	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
537		0, 0, PACKETJ_TYPE0));
538	amdgpu_ring_write(ring, 0x1);
539
540	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
541	amdgpu_ring_write(ring, 0);
542}
543
544/**
545 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
546 *
547 * @ring: amdgpu_ring pointer
548 * @job: job to retrieve vmid from
549 * @ib: indirect buffer to execute
550 * @flags: unused
551 *
552 * Write ring commands to execute the indirect buffer.
553 */
554void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
555				struct amdgpu_job *job,
556				struct amdgpu_ib *ib,
557				uint32_t flags)
558{
559	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
560
561	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
562		0, 0, PACKETJ_TYPE0));
563	amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
564
565	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
566		0, 0, PACKETJ_TYPE0));
567
568	if (ring->funcs->parse_cs)
569		amdgpu_ring_write(ring, 0);
570	else
571		amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
572
573	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
574		0, 0, PACKETJ_TYPE0));
575	amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
576
577	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
578		0, 0, PACKETJ_TYPE0));
579	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
580
581	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
582		0, 0, PACKETJ_TYPE0));
583	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
584
585	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
586		0, 0, PACKETJ_TYPE0));
587	amdgpu_ring_write(ring, ib->length_dw);
588
589	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
590		0, 0, PACKETJ_TYPE0));
591	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
592
593	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
594		0, 0, PACKETJ_TYPE0));
595	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
596
597	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
598	amdgpu_ring_write(ring, 0);
599
600	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
601		0, 0, PACKETJ_TYPE0));
602	amdgpu_ring_write(ring, 0x01400200);
603
604	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
605		0, 0, PACKETJ_TYPE0));
606	amdgpu_ring_write(ring, 0x2);
607
608	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
609		0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
610	amdgpu_ring_write(ring, 0x2);
611}
612
613void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
614				uint32_t val, uint32_t mask)
615{
616	uint32_t reg_offset = (reg << 2);
617
618	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
619		0, 0, PACKETJ_TYPE0));
620	amdgpu_ring_write(ring, 0x01400200);
621
622	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
623		0, 0, PACKETJ_TYPE0));
624	amdgpu_ring_write(ring, val);
625
626	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
627		0, 0, PACKETJ_TYPE0));
628	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
629		amdgpu_ring_write(ring, 0);
630		amdgpu_ring_write(ring,
631			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
632	} else {
633		amdgpu_ring_write(ring, reg_offset);
634		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
635			0, 0, PACKETJ_TYPE3));
636	}
637	amdgpu_ring_write(ring, mask);
638}
639
640void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
641				unsigned vmid, uint64_t pd_addr)
642{
643	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
644	uint32_t data0, data1, mask;
645
646	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
647
648	/* wait for register write */
649	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
650	data1 = lower_32_bits(pd_addr);
651	mask = 0xffffffff;
652	jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
653}
654
655void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
656{
657	uint32_t reg_offset = (reg << 2);
658
659	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
660		0, 0, PACKETJ_TYPE0));
661	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
662		amdgpu_ring_write(ring, 0);
663		amdgpu_ring_write(ring,
664			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
665	} else {
666		amdgpu_ring_write(ring, reg_offset);
667		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
668			0, 0, PACKETJ_TYPE0));
669	}
670	amdgpu_ring_write(ring, val);
671}
672
673void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
674{
675	int i;
676
677	WARN_ON(ring->wptr % 2 || count % 2);
678
679	for (i = 0; i < count / 2; i++) {
680		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
681		amdgpu_ring_write(ring, 0);
682	}
683}
684
685static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
686{
687	struct amdgpu_device *adev = ip_block->adev;
688
689	return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
690		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
691		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
692}
693
694static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
695{
696	struct amdgpu_device *adev = ip_block->adev;
697	int ret;
698
699	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
700		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
701
702	return ret;
703}
704
705static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
706					  enum amd_clockgating_state state)
707{
708	struct amdgpu_device *adev = ip_block->adev;
709	bool enable = (state == AMD_CG_STATE_GATE);
710
711	if (enable) {
712		if (!jpeg_v2_0_is_idle(ip_block))
713			return -EBUSY;
714		jpeg_v2_0_enable_clock_gating(adev);
715	} else {
716		jpeg_v2_0_disable_clock_gating(adev);
717	}
718
719	return 0;
720}
721
722static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
723					enum amd_powergating_state state)
724{
725	struct amdgpu_device *adev = ip_block->adev;
726	int ret;
727
728	if (state == adev->jpeg.cur_state)
729		return 0;
730
731	if (state == AMD_PG_STATE_GATE)
732		ret = jpeg_v2_0_stop(adev);
733	else
734		ret = jpeg_v2_0_start(adev);
735
736	if (!ret)
737		adev->jpeg.cur_state = state;
738
739	return ret;
740}
741
742static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
743					struct amdgpu_irq_src *source,
744					unsigned type,
745					enum amdgpu_interrupt_state state)
746{
747	return 0;
748}
749
750static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
751				      struct amdgpu_irq_src *source,
752				      struct amdgpu_iv_entry *entry)
753{
754	DRM_DEBUG("IH: JPEG TRAP\n");
755
756	switch (entry->src_id) {
757	case VCN_2_0__SRCID__JPEG_DECODE:
758		amdgpu_fence_process(adev->jpeg.inst->ring_dec);
759		break;
760	default:
761		DRM_ERROR("Unhandled interrupt: %d %d\n",
762			  entry->src_id, entry->src_data[0]);
763		break;
764	}
765
766	return 0;
767}
768
769static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring,
770				unsigned int vmid,
771				struct amdgpu_fence *timedout_fence)
772{
773	int r;
774
775	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
776	r = jpeg_v2_0_stop(ring->adev);
777	if (r)
778		return r;
779	r = jpeg_v2_0_start(ring->adev);
780	if (r)
781		return r;
782	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
783}
784
785static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
786	.name = "jpeg_v2_0",
787	.early_init = jpeg_v2_0_early_init,
788	.sw_init = jpeg_v2_0_sw_init,
789	.sw_fini = jpeg_v2_0_sw_fini,
790	.hw_init = jpeg_v2_0_hw_init,
791	.hw_fini = jpeg_v2_0_hw_fini,
792	.suspend = jpeg_v2_0_suspend,
793	.resume = jpeg_v2_0_resume,
794	.is_idle = jpeg_v2_0_is_idle,
795	.wait_for_idle = jpeg_v2_0_wait_for_idle,
796	.set_clockgating_state = jpeg_v2_0_set_clockgating_state,
797	.set_powergating_state = jpeg_v2_0_set_powergating_state,
798	.dump_ip_state = amdgpu_jpeg_dump_ip_state,
799	.print_ip_state = amdgpu_jpeg_print_ip_state,
800};
801
802static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
803	.type = AMDGPU_RING_TYPE_VCN_JPEG,
804	.align_mask = 0xf,
805	.get_rptr = jpeg_v2_0_dec_ring_get_rptr,
806	.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
807	.set_wptr = jpeg_v2_0_dec_ring_set_wptr,
808	.parse_cs = amdgpu_jpeg_dec_parse_cs,
809	.emit_frame_size =
810		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
811		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
812		8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
813		18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
814		8 + 16,
815	.emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
816	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
817	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
818	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
819	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
820	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
821	.insert_nop = jpeg_v2_0_dec_ring_nop,
822	.insert_start = jpeg_v2_0_dec_ring_insert_start,
823	.insert_end = jpeg_v2_0_dec_ring_insert_end,
824	.pad_ib = amdgpu_ring_generic_pad_ib,
825	.begin_use = amdgpu_jpeg_ring_begin_use,
826	.end_use = amdgpu_jpeg_ring_end_use,
827	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
828	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
829	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
830	.reset = jpeg_v2_0_ring_reset,
831};
832
833static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
834{
835	adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;
836}
837
838static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
839	.set = jpeg_v2_0_set_interrupt_state,
840	.process = jpeg_v2_0_process_interrupt,
841};
842
843static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
844{
845	adev->jpeg.inst->irq.num_types = 1;
846	adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
847}
848
849const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
850		.type = AMD_IP_BLOCK_TYPE_JPEG,
851		.major = 2,
852		.minor = 0,
853		.rev = 0,
854		.funcs = &jpeg_v2_0_ip_funcs,
855};