ih_v6_0.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include <linux/pci.h>
 25
 26#include "amdgpu.h"
 27#include "amdgpu_ih.h"
 28
 29#include "oss/osssys_6_0_0_offset.h"
 30#include "oss/osssys_6_0_0_sh_mask.h"
 31
 32#include "soc15_common.h"
 33#include "ih_v6_0.h"
 34
 35#define MAX_REARM_RETRY 10
 36
 37static void ih_v6_0_set_interrupt_funcs(struct amdgpu_device *adev);
 38
 39/**
 40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
 41 *
 42 * @adev: amdgpu_device pointer
 43 *
 44 * Initialize register offset ih rings (IH_V6_0).
 45 */
 46static void ih_v6_0_init_register_offset(struct amdgpu_device *adev)
 47{
 48	struct amdgpu_ih_regs *ih_regs;
 49
 50	/* ih ring 2 is removed
 51	 * ih ring and ih ring 1 are available */
 52	if (adev->irq.ih.ring_size) {
 53		ih_regs = &adev->irq.ih.ih_regs;
 54		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
 55		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
 56		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
 57		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
 58		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
 59		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
 60		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
 61		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
 62		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
 63	}
 64
 65	if (adev->irq.ih1.ring_size) {
 66		ih_regs = &adev->irq.ih1.ih_regs;
 67		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
 68		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
 69		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
 70		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
 71		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
 72		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
 73		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
 74	}
 75}
 76
 77/**
 78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
 79 *
 80 * @adev: amdgpu_device pointer
 81 * @threshold: threshold to trigger the wptr reporting
 82 * @timeout: timeout to trigger the wptr reporting
 83 * @enabled: Enable/disable timeout flush mechanism
 84 *
 85 * threshold input range: 0 ~ 15, default 0,
 86 * real_threshold = 2^threshold
 87 * timeout input range: 0 ~ 20, default 8,
 88 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
 89 *
 90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
 91 */
 92static void
 93force_update_wptr_for_self_int(struct amdgpu_device *adev,
 94			       u32 threshold, u32 timeout, bool enabled)
 95{
 96	u32 ih_cntl, ih_rb_cntl;
 97
 98	ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);
 99	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);
100
101	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
102				SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
103	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
104				SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
105	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106				   RB_USED_INT_THRESHOLD, threshold);
107
108	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
109		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
110			return;
111	} else {
112		WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
113	}
114
115	WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
116}
117
118/**
119 * ih_v6_0_toggle_ring_interrupts - toggle the interrupt ring buffer
120 *
121 * @adev: amdgpu_device pointer
122 * @ih: amdgpu_ih_ring pointer
123 * @enable: true - enable the interrupts, false - disable the interrupts
124 *
125 * Toggle the interrupt ring buffer (IH_V6_0)
126 */
127static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev,
128					  struct amdgpu_ih_ring *ih,
129					  bool enable)
130{
131	struct amdgpu_ih_regs *ih_regs;
132	uint32_t tmp;
133
134	ih_regs = &ih->ih_regs;
135
136	tmp = RREG32(ih_regs->ih_rb_cntl);
137	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
138
139	if (enable) {
140		/* Unset the CLEAR_OVERFLOW bit to make sure the next step
141		 * is switching the bit from 0 to 1
142		 */
143		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
144		if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
145			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
146				return -ETIMEDOUT;
147		} else {
148			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
149		}
150
151		/* Clear RB_OVERFLOW bit */
152		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
153		if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
154			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
155				return -ETIMEDOUT;
156		} else {
157			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
158		}
159
160		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
161		 * can be detected.
162		 */
163		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
164	}
165
166	/* enable_intr field is only valid in ring0 */
167	if (ih == &adev->irq.ih)
168		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
169
170	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
171		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
172			return -ETIMEDOUT;
173	} else {
174		WREG32(ih_regs->ih_rb_cntl, tmp);
175	}
176
177	if (enable) {
178		ih->enabled = true;
179	} else {
180		/* set rptr, wptr to 0 */
181		WREG32(ih_regs->ih_rb_rptr, 0);
182		WREG32(ih_regs->ih_rb_wptr, 0);
183		ih->enabled = false;
184		ih->rptr = 0;
185	}
186
187	return 0;
188}
189
190/**
191 * ih_v6_0_toggle_interrupts - Toggle all the available interrupt ring buffers
192 *
193 * @adev: amdgpu_device pointer
194 * @enable: enable or disable interrupt ring buffers
195 *
196 * Toggle all the available interrupt ring buffers (IH_V6_0).
197 */
198static int ih_v6_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
199{
200	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
201	int i;
202	int r;
203
204	for (i = 0; i < ARRAY_SIZE(ih); i++) {
205		if (ih[i]->ring_size) {
206			r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable);
207			if (r)
208				return r;
209		}
210	}
211
212	return 0;
213}
214
215static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
216{
217	int rb_bufsz = order_base_2(ih->ring_size / 4);
218
219	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
220				   MC_SPACE, ih->use_bus_addr ? 2 : 4);
221	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
222				   WPTR_OVERFLOW_CLEAR, 1);
223	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
224				   WPTR_OVERFLOW_ENABLE, 1);
225	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
226	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
227	 * value is written to memory
228	 */
229	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
230				   WPTR_WRITEBACK_ENABLE, 1);
231	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
232	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
233	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
234
235	return ih_rb_cntl;
236}
237
238static uint32_t ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih)
239{
240	u32 ih_doorbell_rtpr = 0;
241
242	if (ih->use_doorbell) {
243		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
244						 IH_DOORBELL_RPTR, OFFSET,
245						 ih->doorbell_index);
246		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
247						 IH_DOORBELL_RPTR,
248						 ENABLE, 1);
249	} else {
250		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
251						 IH_DOORBELL_RPTR,
252						 ENABLE, 0);
253	}
254	return ih_doorbell_rtpr;
255}
256
257/**
258 * ih_v6_0_enable_ring - enable an ih ring buffer
259 *
260 * @adev: amdgpu_device pointer
261 * @ih: amdgpu_ih_ring pointer
262 *
263 * Enable an ih ring buffer (IH_V6_0)
264 */
265static int ih_v6_0_enable_ring(struct amdgpu_device *adev,
266				      struct amdgpu_ih_ring *ih)
267{
268	struct amdgpu_ih_regs *ih_regs;
269	uint32_t tmp;
270
271	ih_regs = &ih->ih_regs;
272
273	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
274	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
275	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
276
277	tmp = RREG32(ih_regs->ih_rb_cntl);
278	tmp = ih_v6_0_rb_cntl(ih, tmp);
279	if (ih == &adev->irq.ih)
280		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
281	if (ih == &adev->irq.ih1) {
282		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
283		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
284	}
285
286	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
287		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
288			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
289			return -ETIMEDOUT;
290		}
291	} else {
292		WREG32(ih_regs->ih_rb_cntl, tmp);
293	}
294
295	if (ih == &adev->irq.ih) {
296		/* set the ih ring 0 writeback address whether it's enabled or not */
297		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
298		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
299	}
300
301	/* set rptr, wptr to 0 */
302	WREG32(ih_regs->ih_rb_wptr, 0);
303	WREG32(ih_regs->ih_rb_rptr, 0);
304
305	WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih));
306
307	return 0;
308}
309
310/**
311 * ih_v6_0_irq_init - init and enable the interrupt ring
312 *
313 * @adev: amdgpu_device pointer
314 *
315 * Allocate a ring buffer for the interrupt controller,
316 * enable the RLC, disable interrupts, enable the IH
317 * ring buffer and enable it.
318 * Called at device load and reume.
319 * Returns 0 for success, errors for failure.
320 */
321static int ih_v6_0_irq_init(struct amdgpu_device *adev)
322{
323	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
324	u32 ih_chicken;
325	u32 tmp;
326	int ret;
327	int i;
328
329	/* disable irqs */
330	ret = ih_v6_0_toggle_interrupts(adev, false);
331	if (ret)
332		return ret;
333
334	adev->nbio.funcs->ih_control(adev);
335
336	if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
337		     (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) {
338		if (ih[0]->use_bus_addr) {
339			ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);
340			ih_chicken = REG_SET_FIELD(ih_chicken,
341					IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
342			WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken);
343		}
344	}
345
346	for (i = 0; i < ARRAY_SIZE(ih); i++) {
347		if (ih[i]->ring_size) {
348			ret = ih_v6_0_enable_ring(adev, ih[i]);
349			if (ret)
350				return ret;
351		}
352		ih[i]->overflow = false;
353	}
354
355	/* update doorbell range for ih ring 0 */
356	adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
357					    ih[0]->doorbell_index);
358
359	tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
360	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
361			    CLIENT18_IS_STORM_CLIENT, 1);
362	WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
363
364	tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
365	tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
366	WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
367
368	/* GC/MMHUB UTCL2 page fault interrupts are configured as
369	 * MSI storm capable interrupts by deafult. The delay is
370	 * used to avoid ISR being called too frequently
371	 * when page fault happens on several continuous page
372	 * and thus avoid MSI storm */
373	tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
374	tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
375			    DELAY, 3);
376	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
377
378	/* Redirect the interrupts to IH RB1 for dGPU */
379	if (adev->irq.ih1.ring_size) {
380		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
381		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
382		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
383
384		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
385		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
386		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
387		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
388				    SOURCE_ID_MATCH_ENABLE, 0x1);
389
390		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
391	}
392
393	pci_set_master(adev->pdev);
394
395	/* enable interrupts */
396	ret = ih_v6_0_toggle_interrupts(adev, true);
397	if (ret)
398		return ret;
399	/* enable wptr force update for self int */
400	force_update_wptr_for_self_int(adev, 0, 8, true);
401
402	if (adev->irq.ih_soft.ring_size)
403		adev->irq.ih_soft.enabled = true;
404
405	return 0;
406}
407
408/**
409 * ih_v6_0_irq_disable - disable interrupts
410 *
411 * @adev: amdgpu_device pointer
412 *
413 * Disable interrupts on the hw.
414 */
415static void ih_v6_0_irq_disable(struct amdgpu_device *adev)
416{
417	force_update_wptr_for_self_int(adev, 0, 8, false);
418	ih_v6_0_toggle_interrupts(adev, false);
419
420	/* Wait and acknowledge irq */
421	mdelay(1);
422}
423
424/**
425 * ih_v6_0_get_wptr - get the IH ring buffer wptr
426 *
427 * @adev: amdgpu_device pointer
428 * @ih: amdgpu_ih_ring pointer
429 *
430 * Get the IH ring buffer wptr from either the register
431 * or the writeback memory buffer.  Also check for
432 * ring buffer overflow and deal with it.
433 * Returns the value of the wptr.
434 */
435static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
436			      struct amdgpu_ih_ring *ih)
437{
438	u32 wptr, tmp;
439	struct amdgpu_ih_regs *ih_regs;
440
441	wptr = le32_to_cpu(*ih->wptr_cpu);
442	ih_regs = &ih->ih_regs;
443
444	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
445		goto out;
446
447	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
448	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
449		goto out;
450	if (!amdgpu_sriov_vf(adev))
451		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
452	else
453		ih->overflow = true;
454
455	/* When a ring buffer overflow happen start parsing interrupt
456	 * from the last not overwritten vector (wptr + 32). Hopefully
457	 * this should allow us to catch up.
458	 */
459	tmp = (wptr + 32) & ih->ptr_mask;
460	dev_warn(adev->dev, "IH ring buffer overflow "
461		 "(0x%08X, 0x%08X, 0x%08X)\n",
462		 wptr, ih->rptr, tmp);
463	ih->rptr = tmp;
464
465	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
466	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
467	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
468
469	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
470	 * can be detected.
471	 */
472	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
473	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
474out:
475	return (wptr & ih->ptr_mask);
476}
477
478/**
479 * ih_v6_0_irq_rearm - rearm IRQ if lost
480 *
481 * @adev: amdgpu_device pointer
482 * @ih: amdgpu_ih_ring pointer
483 *
484 */
485static void ih_v6_0_irq_rearm(struct amdgpu_device *adev,
486			       struct amdgpu_ih_ring *ih)
487{
488	uint32_t v = 0;
489	uint32_t i = 0;
490	struct amdgpu_ih_regs *ih_regs;
491
492	ih_regs = &ih->ih_regs;
493
494	/* Rearm IRQ / re-write doorbell if doorbell write is lost */
495	for (i = 0; i < MAX_REARM_RETRY; i++) {
496		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
497		if ((v < ih->ring_size) && (v != ih->rptr))
498			WDOORBELL32(ih->doorbell_index, ih->rptr);
499		else
500			break;
501	}
502}
503
504/**
505 * ih_v6_0_set_rptr - set the IH ring buffer rptr
506 *
507 * @adev: amdgpu_device pointer
508 * @ih: amdgpu_ih_ring pointer
509 *
510 * Set the IH ring buffer rptr.
511 */
512static void ih_v6_0_set_rptr(struct amdgpu_device *adev,
513			       struct amdgpu_ih_ring *ih)
514{
515	struct amdgpu_ih_regs *ih_regs;
516
517	if (ih->use_doorbell) {
518		/* XXX check if swapping is necessary on BE */
519		*ih->rptr_cpu = ih->rptr;
520		WDOORBELL32(ih->doorbell_index, ih->rptr);
521
522		if (amdgpu_sriov_vf(adev))
523			ih_v6_0_irq_rearm(adev, ih);
524	} else {
525		ih_regs = &ih->ih_regs;
526		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
527	}
528}
529
530/**
531 * ih_v6_0_self_irq - dispatch work for ring 1
532 *
533 * @adev: amdgpu_device pointer
534 * @source: irq source
535 * @entry: IV with WPTR update
536 *
537 * Update the WPTR from the IV and schedule work to handle the entries.
538 */
539static int ih_v6_0_self_irq(struct amdgpu_device *adev,
540			      struct amdgpu_irq_src *source,
541			      struct amdgpu_iv_entry *entry)
542{
543	uint32_t wptr = cpu_to_le32(entry->src_data[0]);
544
545	switch (entry->ring_id) {
546	case 1:
547		*adev->irq.ih1.wptr_cpu = wptr;
548		schedule_work(&adev->irq.ih1_work);
549		break;
550	default:
551		break;
552	}
553	return 0;
554}
555
556static const struct amdgpu_irq_src_funcs ih_v6_0_self_irq_funcs = {
557	.process = ih_v6_0_self_irq,
558};
559
560static void ih_v6_0_set_self_irq_funcs(struct amdgpu_device *adev)
561{
562	adev->irq.self_irq.num_types = 0;
563	adev->irq.self_irq.funcs = &ih_v6_0_self_irq_funcs;
564}
565
566static int ih_v6_0_early_init(struct amdgpu_ip_block *ip_block)
567{
568	struct amdgpu_device *adev = ip_block->adev;
569
570	ih_v6_0_set_interrupt_funcs(adev);
571	ih_v6_0_set_self_irq_funcs(adev);
572	return 0;
573}
574
575static int ih_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
576{
577	int r;
578	struct amdgpu_device *adev = ip_block->adev;
579	bool use_bus_addr;
580
581	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
582			      &adev->irq.self_irq);
583
584	if (r)
585		return r;
586
587	/* use gpu virtual address for ih ring
588	 * until ih_checken is programmed to allow
589	 * use bus address for ih ring by psp bl */
590	use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP;
591	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
592	if (r)
593		return r;
594
595	adev->irq.ih.use_doorbell = true;
596	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
597
598	if (!(adev->flags & AMD_IS_APU)) {
599		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
600					use_bus_addr);
601		if (r)
602			return r;
603
604		adev->irq.ih1.use_doorbell = true;
605		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
606	}
607
608	/* initialize ih control register offset */
609	ih_v6_0_init_register_offset(adev);
610
611	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
612	if (r)
613		return r;
614
615	r = amdgpu_irq_init(adev);
616
617	return r;
618}
619
620static int ih_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
621{
622	struct amdgpu_device *adev = ip_block->adev;
623
624	amdgpu_irq_fini_sw(adev);
625
626	return 0;
627}
628
629static int ih_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
630{
631	int r;
632	struct amdgpu_device *adev = ip_block->adev;
633
634	r = ih_v6_0_irq_init(adev);
635	if (r)
636		return r;
637
638	return 0;
639}
640
641static int ih_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
642{
643	ih_v6_0_irq_disable(ip_block->adev);
644
645	return 0;
646}
647
648static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block)
649{
650	return ih_v6_0_hw_fini(ip_block);
651}
652
653static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block)
654{
655	return ih_v6_0_hw_init(ip_block);
656}
657
658static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
659{
660	/* todo */
661	return true;
662}
663
664static int ih_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
665{
666	/* todo */
667	return -ETIMEDOUT;
668}
669
670static int ih_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
671{
672	/* todo */
673	return 0;
674}
675
676static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,
677					       bool enable)
678{
679	uint32_t data, def, field_val;
680
681	if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
682		def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);
683		field_val = enable ? 0 : 1;
684		data = REG_SET_FIELD(data, IH_CLK_CTRL,
685				     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
686		data = REG_SET_FIELD(data, IH_CLK_CTRL,
687				     OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
688		data = REG_SET_FIELD(data, IH_CLK_CTRL,
689				     LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
690		data = REG_SET_FIELD(data, IH_CLK_CTRL,
691				     DYN_CLK_SOFT_OVERRIDE, field_val);
692		data = REG_SET_FIELD(data, IH_CLK_CTRL,
693				     REG_CLK_SOFT_OVERRIDE, field_val);
694		if (def != data)
695			WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data);
696	}
697}
698
699static int ih_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
700					   enum amd_clockgating_state state)
701{
702	struct amdgpu_device *adev = ip_block->adev;
703
704	ih_v6_0_update_clockgating_state(adev,
705				state == AMD_CG_STATE_GATE);
706	return 0;
707}
708
709static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
710					       bool enable)
711{
712	uint32_t ih_mem_pwr_cntl;
713
714	/* Disable ih sram power cntl before switch powergating mode */
715	ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);
716	ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
717					IH_BUFFER_MEM_POWER_CTRL_EN, 0);
718	WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
719
720	/* It is recommended to set mem powergating mode to DS mode */
721	if (enable) {
722		/* mem power mode */
723		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
724						IH_BUFFER_MEM_POWER_LS_EN, 0);
725		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
726						IH_BUFFER_MEM_POWER_DS_EN, 1);
727		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
728						IH_BUFFER_MEM_POWER_SD_EN, 0);
729		/* cam mem power mode */
730		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
731						IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
732		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
733						IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1);
734		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
735						IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
736		/* re-enable power cntl */
737		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
738						IH_BUFFER_MEM_POWER_CTRL_EN, 1);
739	} else {
740		/* mem power mode */
741		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
742						IH_BUFFER_MEM_POWER_LS_EN, 0);
743		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
744						IH_BUFFER_MEM_POWER_DS_EN, 0);
745		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
746						IH_BUFFER_MEM_POWER_SD_EN, 0);
747		/* cam mem power mode */
748		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
749						IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
750		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
751						IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0);
752		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
753						IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
754		/* re-enable power cntl*/
755		ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
756						IH_BUFFER_MEM_POWER_CTRL_EN, 1);
757	}
758
759	WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
760}
761
762static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
763					 enum amd_powergating_state state)
764{
765	struct amdgpu_device *adev = ip_block->adev;
766	bool enable = (state == AMD_PG_STATE_GATE);
767
768	if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
769		ih_v6_0_update_ih_mem_power_gating(adev, enable);
770
771	return 0;
772}
773
774static void ih_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
775{
776	struct amdgpu_device *adev = ip_block->adev;
777
778	if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))
779		*flags |= AMD_CG_SUPPORT_IH_CG;
780}
781
782static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
783	.name = "ih_v6_0",
784	.early_init = ih_v6_0_early_init,
785	.sw_init = ih_v6_0_sw_init,
786	.sw_fini = ih_v6_0_sw_fini,
787	.hw_init = ih_v6_0_hw_init,
788	.hw_fini = ih_v6_0_hw_fini,
789	.suspend = ih_v6_0_suspend,
790	.resume = ih_v6_0_resume,
791	.is_idle = ih_v6_0_is_idle,
792	.wait_for_idle = ih_v6_0_wait_for_idle,
793	.soft_reset = ih_v6_0_soft_reset,
794	.set_clockgating_state = ih_v6_0_set_clockgating_state,
795	.set_powergating_state = ih_v6_0_set_powergating_state,
796	.get_clockgating_state = ih_v6_0_get_clockgating_state,
797};
798
799static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
800	.get_wptr = ih_v6_0_get_wptr,
801	.decode_iv = amdgpu_ih_decode_iv_helper,
802	.decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
803	.set_rptr = ih_v6_0_set_rptr
804};
805
806static void ih_v6_0_set_interrupt_funcs(struct amdgpu_device *adev)
807{
808	adev->irq.ih_funcs = &ih_v6_0_funcs;
809}
810
811const struct amdgpu_ip_block_version ih_v6_0_ip_block = {
812	.type = AMD_IP_BLOCK_TYPE_IH,
813	.major = 6,
814	.minor = 0,
815	.rev = 0,
816	.funcs = &ih_v6_0_ip_funcs,
817};