hdp_v7_0.c

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#include "amdgpu.h"
 24#include "hdp_v7_0.h"
 25
 26#include "hdp/hdp_7_0_0_offset.h"
 27#include "hdp/hdp_7_0_0_sh_mask.h"
 28#include <uapi/linux/kfd_ioctl.h>
 29
 30static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
 31					 bool enable)
 32{
 33	uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 34	uint32_t hdp_mem_pwr_cntl;
 35
 36	if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 37				AMD_CG_SUPPORT_HDP_DS |
 38				AMD_CG_SUPPORT_HDP_SD)))
 39		return;
 40
 41	hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
 42	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
 43
 44	/* Before doing clock/power mode switch,
 45	 * forced on IPH & RC clock */
 46	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 47				     RC_MEM_CLK_SOFT_OVERRIDE, 1);
 48	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
 49
 50	/* disable clock and power gating before any changing */
 51	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 52					 ATOMIC_MEM_POWER_CTRL_EN, 0);
 53	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 54					 ATOMIC_MEM_POWER_LS_EN, 0);
 55	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 56					 ATOMIC_MEM_POWER_DS_EN, 0);
 57	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 58					 ATOMIC_MEM_POWER_SD_EN, 0);
 59	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 60					 RC_MEM_POWER_CTRL_EN, 0);
 61	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 62					 RC_MEM_POWER_LS_EN, 0);
 63	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 64					 RC_MEM_POWER_DS_EN, 0);
 65	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 66					 RC_MEM_POWER_SD_EN, 0);
 67	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 68
 69	/* Already disabled above. The actions below are for "enabled" only */
 70	if (enable) {
 71		/* only one clock gating mode (LS/DS/SD) can be enabled */
 72		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 73			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 74							 HDP_MEM_POWER_CTRL,
 75							 ATOMIC_MEM_POWER_SD_EN, 1);
 76			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 77							 HDP_MEM_POWER_CTRL,
 78							 RC_MEM_POWER_SD_EN, 1);
 79		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 80			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 81							 HDP_MEM_POWER_CTRL,
 82							 ATOMIC_MEM_POWER_LS_EN, 1);
 83			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 84							 HDP_MEM_POWER_CTRL,
 85							 RC_MEM_POWER_LS_EN, 1);
 86		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 87			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 88							 HDP_MEM_POWER_CTRL,
 89							 ATOMIC_MEM_POWER_DS_EN, 1);
 90			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 91							 HDP_MEM_POWER_CTRL,
 92							 RC_MEM_POWER_DS_EN, 1);
 93		}
 94
 95		/* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
 96		 * be set for SRAM LS/DS/SD */
 97		if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
 98				      AMD_CG_SUPPORT_HDP_SD)) {
 99			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
100							 ATOMIC_MEM_POWER_CTRL_EN, 1);
101			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
102							 RC_MEM_POWER_CTRL_EN, 1);
103			WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
104		}
105	}
106
107	/* disable IPH & RC clock override after clock/power mode changing */
108	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
109				     RC_MEM_CLK_SOFT_OVERRIDE, 0);
110	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
111}
112
113static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
114					    u64 *flags)
115{
116	uint32_t tmp;
117
118	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
119	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
120	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
121		*flags |= AMD_CG_SUPPORT_HDP_LS;
122	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
123		*flags |= AMD_CG_SUPPORT_HDP_DS;
124	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
125		*flags |= AMD_CG_SUPPORT_HDP_SD;
126}
127
128const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
129	.flush_hdp = amdgpu_hdp_generic_flush,
130	.update_clock_gating = hdp_v7_0_update_clock_gating,
131	.get_clock_gating_state = hdp_v7_0_get_clockgating_state,
132};