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gmc_v9_0.c
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/firmware.h> 25#include <linux/pci.h> 26 27#include <drm/drm_cache.h> 28 29#include "amdgpu.h" 30#include "gmc_v9_0.h" 31#include "amdgpu_atomfirmware.h" 32#include "amdgpu_gem.h" 33 34#include "gc/gc_9_0_sh_mask.h" 35#include "dce/dce_12_0_offset.h" 36#include "dce/dce_12_0_sh_mask.h" 37#include "vega10_enum.h" 38#include "mmhub/mmhub_1_0_offset.h" 39#include "athub/athub_1_0_sh_mask.h" 40#include "athub/athub_1_0_offset.h" 41#include "oss/osssys_4_0_offset.h" 42 43#include "soc15.h" 44#include "soc15d.h" 45#include "soc15_common.h" 46#include "umc/umc_6_0_sh_mask.h" 47 48#include "gfxhub_v1_0.h" 49#include "mmhub_v1_0.h" 50#include "athub_v1_0.h" 51#include "gfxhub_v1_1.h" 52#include "gfxhub_v1_2.h" 53#include "mmhub_v9_4.h" 54#include "mmhub_v1_7.h" 55#include "mmhub_v1_8.h" 56#include "umc_v6_1.h" 57#include "umc_v6_0.h" 58#include "umc_v6_7.h" 59#include "umc_v12_0.h" 60#include "hdp_v4_0.h" 61#include "mca_v3_0.h" 62 63#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65#include "amdgpu_ras.h" 66#include "amdgpu_xgmi.h" 67 68/* add these here since we already include dce12 headers and these are for DCN */ 69#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81static const char * const gfxhub_client_ids[] = { 82 "CB", 83 "DB", 84 "IA", 85 "WD", 86 "CPF", 87 "CPC", 88 "CPG", 89 "RLC", 90 "TCP", 91 "SQC (inst)", 92 "SQC (data)", 93 "SQG", 94 "PA", 95}; 96 97static const char *mmhub_client_ids_raven[][2] = { 98 [0][0] = "MP1", 99 [1][0] = "MP0", 100 [2][0] = "VCN", 101 [3][0] = "VCNU", 102 [4][0] = "HDP", 103 [5][0] = "DCE", 104 [13][0] = "UTCL2", 105 [19][0] = "TLS", 106 [26][0] = "OSS", 107 [27][0] = "SDMA0", 108 [0][1] = "MP1", 109 [1][1] = "MP0", 110 [2][1] = "VCN", 111 [3][1] = "VCNU", 112 [4][1] = "HDP", 113 [5][1] = "XDP", 114 [6][1] = "DBGU0", 115 [7][1] = "DCE", 116 [8][1] = "DCEDWB0", 117 [9][1] = "DCEDWB1", 118 [26][1] = "OSS", 119 [27][1] = "SDMA0", 120}; 121 122static const char *mmhub_client_ids_renoir[][2] = { 123 [0][0] = "MP1", 124 [1][0] = "MP0", 125 [2][0] = "HDP", 126 [4][0] = "DCEDMC", 127 [5][0] = "DCEVGA", 128 [13][0] = "UTCL2", 129 [19][0] = "TLS", 130 [26][0] = "OSS", 131 [27][0] = "SDMA0", 132 [28][0] = "VCN", 133 [29][0] = "VCNU", 134 [30][0] = "JPEG", 135 [0][1] = "MP1", 136 [1][1] = "MP0", 137 [2][1] = "HDP", 138 [3][1] = "XDP", 139 [6][1] = "DBGU0", 140 [7][1] = "DCEDMC", 141 [8][1] = "DCEVGA", 142 [9][1] = "DCEDWB", 143 [26][1] = "OSS", 144 [27][1] = "SDMA0", 145 [28][1] = "VCN", 146 [29][1] = "VCNU", 147 [30][1] = "JPEG", 148}; 149 150static const char *mmhub_client_ids_vega10[][2] = { 151 [0][0] = "MP0", 152 [1][0] = "UVD", 153 [2][0] = "UVDU", 154 [3][0] = "HDP", 155 [13][0] = "UTCL2", 156 [14][0] = "OSS", 157 [15][0] = "SDMA1", 158 [32+0][0] = "VCE0", 159 [32+1][0] = "VCE0U", 160 [32+2][0] = "XDMA", 161 [32+3][0] = "DCE", 162 [32+4][0] = "MP1", 163 [32+14][0] = "SDMA0", 164 [0][1] = "MP0", 165 [1][1] = "UVD", 166 [2][1] = "UVDU", 167 [3][1] = "DBGU0", 168 [4][1] = "HDP", 169 [5][1] = "XDP", 170 [14][1] = "OSS", 171 [15][1] = "SDMA0", 172 [32+0][1] = "VCE0", 173 [32+1][1] = "VCE0U", 174 [32+2][1] = "XDMA", 175 [32+3][1] = "DCE", 176 [32+4][1] = "DCEDWB", 177 [32+5][1] = "MP1", 178 [32+6][1] = "DBGU1", 179 [32+14][1] = "SDMA1", 180}; 181 182static const char *mmhub_client_ids_vega12[][2] = { 183 [0][0] = "MP0", 184 [1][0] = "VCE0", 185 [2][0] = "VCE0U", 186 [3][0] = "HDP", 187 [13][0] = "UTCL2", 188 [14][0] = "OSS", 189 [15][0] = "SDMA1", 190 [32+0][0] = "DCE", 191 [32+1][0] = "XDMA", 192 [32+2][0] = "UVD", 193 [32+3][0] = "UVDU", 194 [32+4][0] = "MP1", 195 [32+15][0] = "SDMA0", 196 [0][1] = "MP0", 197 [1][1] = "VCE0", 198 [2][1] = "VCE0U", 199 [3][1] = "DBGU0", 200 [4][1] = "HDP", 201 [5][1] = "XDP", 202 [14][1] = "OSS", 203 [15][1] = "SDMA0", 204 [32+0][1] = "DCE", 205 [32+1][1] = "DCEDWB", 206 [32+2][1] = "XDMA", 207 [32+3][1] = "UVD", 208 [32+4][1] = "UVDU", 209 [32+5][1] = "MP1", 210 [32+6][1] = "DBGU1", 211 [32+15][1] = "SDMA1", 212}; 213 214static const char *mmhub_client_ids_vega20[][2] = { 215 [0][0] = "XDMA", 216 [1][0] = "DCE", 217 [2][0] = "VCE0", 218 [3][0] = "VCE0U", 219 [4][0] = "UVD", 220 [5][0] = "UVD1U", 221 [13][0] = "OSS", 222 [14][0] = "HDP", 223 [15][0] = "SDMA0", 224 [32+0][0] = "UVD", 225 [32+1][0] = "UVDU", 226 [32+2][0] = "MP1", 227 [32+3][0] = "MP0", 228 [32+12][0] = "UTCL2", 229 [32+14][0] = "SDMA1", 230 [0][1] = "XDMA", 231 [1][1] = "DCE", 232 [2][1] = "DCEDWB", 233 [3][1] = "VCE0", 234 [4][1] = "VCE0U", 235 [5][1] = "UVD1", 236 [6][1] = "UVD1U", 237 [7][1] = "DBGU0", 238 [8][1] = "XDP", 239 [13][1] = "OSS", 240 [14][1] = "HDP", 241 [15][1] = "SDMA0", 242 [32+0][1] = "UVD", 243 [32+1][1] = "UVDU", 244 [32+2][1] = "DBGU1", 245 [32+3][1] = "MP1", 246 [32+4][1] = "MP0", 247 [32+14][1] = "SDMA1", 248}; 249 250static const char *mmhub_client_ids_arcturus[][2] = { 251 [0][0] = "DBGU1", 252 [1][0] = "XDP", 253 [2][0] = "MP1", 254 [14][0] = "HDP", 255 [171][0] = "JPEG", 256 [172][0] = "VCN", 257 [173][0] = "VCNU", 258 [203][0] = "JPEG1", 259 [204][0] = "VCN1", 260 [205][0] = "VCN1U", 261 [256][0] = "SDMA0", 262 [257][0] = "SDMA1", 263 [258][0] = "SDMA2", 264 [259][0] = "SDMA3", 265 [260][0] = "SDMA4", 266 [261][0] = "SDMA5", 267 [262][0] = "SDMA6", 268 [263][0] = "SDMA7", 269 [384][0] = "OSS", 270 [0][1] = "DBGU1", 271 [1][1] = "XDP", 272 [2][1] = "MP1", 273 [14][1] = "HDP", 274 [171][1] = "JPEG", 275 [172][1] = "VCN", 276 [173][1] = "VCNU", 277 [203][1] = "JPEG1", 278 [204][1] = "VCN1", 279 [205][1] = "VCN1U", 280 [256][1] = "SDMA0", 281 [257][1] = "SDMA1", 282 [258][1] = "SDMA2", 283 [259][1] = "SDMA3", 284 [260][1] = "SDMA4", 285 [261][1] = "SDMA5", 286 [262][1] = "SDMA6", 287 [263][1] = "SDMA7", 288 [384][1] = "OSS", 289}; 290 291static const char *mmhub_client_ids_aldebaran[][2] = { 292 [2][0] = "MP1", 293 [3][0] = "MP0", 294 [32+1][0] = "DBGU_IO0", 295 [32+2][0] = "DBGU_IO2", 296 [32+4][0] = "MPIO", 297 [96+11][0] = "JPEG0", 298 [96+12][0] = "VCN0", 299 [96+13][0] = "VCNU0", 300 [128+11][0] = "JPEG1", 301 [128+12][0] = "VCN1", 302 [128+13][0] = "VCNU1", 303 [160+1][0] = "XDP", 304 [160+14][0] = "HDP", 305 [256+0][0] = "SDMA0", 306 [256+1][0] = "SDMA1", 307 [256+2][0] = "SDMA2", 308 [256+3][0] = "SDMA3", 309 [256+4][0] = "SDMA4", 310 [384+0][0] = "OSS", 311 [2][1] = "MP1", 312 [3][1] = "MP0", 313 [32+1][1] = "DBGU_IO0", 314 [32+2][1] = "DBGU_IO2", 315 [32+4][1] = "MPIO", 316 [96+11][1] = "JPEG0", 317 [96+12][1] = "VCN0", 318 [96+13][1] = "VCNU0", 319 [128+11][1] = "JPEG1", 320 [128+12][1] = "VCN1", 321 [128+13][1] = "VCNU1", 322 [160+1][1] = "XDP", 323 [160+14][1] = "HDP", 324 [256+0][1] = "SDMA0", 325 [256+1][1] = "SDMA1", 326 [256+2][1] = "SDMA2", 327 [256+3][1] = "SDMA3", 328 [256+4][1] = "SDMA4", 329 [384+0][1] = "OSS", 330}; 331 332static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 335}; 336 337static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 340}; 341 342static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 343 (0x000143c0 + 0x00000000), 344 (0x000143c0 + 0x00000800), 345 (0x000143c0 + 0x00001000), 346 (0x000143c0 + 0x00001800), 347 (0x000543c0 + 0x00000000), 348 (0x000543c0 + 0x00000800), 349 (0x000543c0 + 0x00001000), 350 (0x000543c0 + 0x00001800), 351 (0x000943c0 + 0x00000000), 352 (0x000943c0 + 0x00000800), 353 (0x000943c0 + 0x00001000), 354 (0x000943c0 + 0x00001800), 355 (0x000d43c0 + 0x00000000), 356 (0x000d43c0 + 0x00000800), 357 (0x000d43c0 + 0x00001000), 358 (0x000d43c0 + 0x00001800), 359 (0x001143c0 + 0x00000000), 360 (0x001143c0 + 0x00000800), 361 (0x001143c0 + 0x00001000), 362 (0x001143c0 + 0x00001800), 363 (0x001543c0 + 0x00000000), 364 (0x001543c0 + 0x00000800), 365 (0x001543c0 + 0x00001000), 366 (0x001543c0 + 0x00001800), 367 (0x001943c0 + 0x00000000), 368 (0x001943c0 + 0x00000800), 369 (0x001943c0 + 0x00001000), 370 (0x001943c0 + 0x00001800), 371 (0x001d43c0 + 0x00000000), 372 (0x001d43c0 + 0x00000800), 373 (0x001d43c0 + 0x00001000), 374 (0x001d43c0 + 0x00001800), 375}; 376 377static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 378 (0x000143e0 + 0x00000000), 379 (0x000143e0 + 0x00000800), 380 (0x000143e0 + 0x00001000), 381 (0x000143e0 + 0x00001800), 382 (0x000543e0 + 0x00000000), 383 (0x000543e0 + 0x00000800), 384 (0x000543e0 + 0x00001000), 385 (0x000543e0 + 0x00001800), 386 (0x000943e0 + 0x00000000), 387 (0x000943e0 + 0x00000800), 388 (0x000943e0 + 0x00001000), 389 (0x000943e0 + 0x00001800), 390 (0x000d43e0 + 0x00000000), 391 (0x000d43e0 + 0x00000800), 392 (0x000d43e0 + 0x00001000), 393 (0x000d43e0 + 0x00001800), 394 (0x001143e0 + 0x00000000), 395 (0x001143e0 + 0x00000800), 396 (0x001143e0 + 0x00001000), 397 (0x001143e0 + 0x00001800), 398 (0x001543e0 + 0x00000000), 399 (0x001543e0 + 0x00000800), 400 (0x001543e0 + 0x00001000), 401 (0x001543e0 + 0x00001800), 402 (0x001943e0 + 0x00000000), 403 (0x001943e0 + 0x00000800), 404 (0x001943e0 + 0x00001000), 405 (0x001943e0 + 0x00001800), 406 (0x001d43e0 + 0x00000000), 407 (0x001d43e0 + 0x00000800), 408 (0x001d43e0 + 0x00001000), 409 (0x001d43e0 + 0x00001800), 410}; 411 412static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 413 struct amdgpu_irq_src *src, 414 unsigned int type, 415 enum amdgpu_interrupt_state state) 416{ 417 u32 bits, i, tmp, reg; 418 419 /* Devices newer then VEGA10/12 shall have these programming 420 * sequences performed by PSP BL 421 */ 422 if (adev->asic_type >= CHIP_VEGA20) 423 return 0; 424 425 bits = 0x7f; 426 427 switch (state) { 428 case AMDGPU_IRQ_STATE_DISABLE: 429 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 430 reg = ecc_umc_mcumc_ctrl_addrs[i]; 431 tmp = RREG32(reg); 432 tmp &= ~bits; 433 WREG32(reg, tmp); 434 } 435 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 436 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 437 tmp = RREG32(reg); 438 tmp &= ~bits; 439 WREG32(reg, tmp); 440 } 441 break; 442 case AMDGPU_IRQ_STATE_ENABLE: 443 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 444 reg = ecc_umc_mcumc_ctrl_addrs[i]; 445 tmp = RREG32(reg); 446 tmp |= bits; 447 WREG32(reg, tmp); 448 } 449 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 450 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 451 tmp = RREG32(reg); 452 tmp |= bits; 453 WREG32(reg, tmp); 454 } 455 break; 456 default: 457 break; 458 } 459 460 return 0; 461} 462 463static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 464 struct amdgpu_irq_src *src, 465 unsigned int type, 466 enum amdgpu_interrupt_state state) 467{ 468 struct amdgpu_vmhub *hub; 469 u32 tmp, reg, bits, i, j; 470 471 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 478 479 switch (state) { 480 case AMDGPU_IRQ_STATE_DISABLE: 481 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 482 hub = &adev->vmhub[j]; 483 for (i = 0; i < 16; i++) { 484 reg = hub->vm_context0_cntl + i; 485 486 /* This works because this interrupt is only 487 * enabled at init/resume and disabled in 488 * fini/suspend, so the overall state doesn't 489 * change over the course of suspend/resume. 490 */ 491 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 492 continue; 493 494 if (j >= AMDGPU_MMHUB0(0)) 495 tmp = RREG32_SOC15_IP(MMHUB, reg); 496 else 497 tmp = RREG32_XCC(reg, j); 498 499 tmp &= ~bits; 500 501 if (j >= AMDGPU_MMHUB0(0)) 502 WREG32_SOC15_IP(MMHUB, reg, tmp); 503 else 504 WREG32_XCC(reg, tmp, j); 505 } 506 } 507 break; 508 case AMDGPU_IRQ_STATE_ENABLE: 509 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 510 hub = &adev->vmhub[j]; 511 for (i = 0; i < 16; i++) { 512 reg = hub->vm_context0_cntl + i; 513 514 /* This works because this interrupt is only 515 * enabled at init/resume and disabled in 516 * fini/suspend, so the overall state doesn't 517 * change over the course of suspend/resume. 518 */ 519 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 520 continue; 521 522 if (j >= AMDGPU_MMHUB0(0)) 523 tmp = RREG32_SOC15_IP(MMHUB, reg); 524 else 525 tmp = RREG32_XCC(reg, j); 526 527 tmp |= bits; 528 529 if (j >= AMDGPU_MMHUB0(0)) 530 WREG32_SOC15_IP(MMHUB, reg, tmp); 531 else 532 WREG32_XCC(reg, tmp, j); 533 } 534 } 535 break; 536 default: 537 break; 538 } 539 540 return 0; 541} 542 543static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 544 struct amdgpu_irq_src *source, 545 struct amdgpu_iv_entry *entry) 546{ 547 bool retry_fault = !!(entry->src_data[1] & 548 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 549 bool write_fault = !!(entry->src_data[1] & 550 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, entry->timestamp, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, entry->timestamp, write_fault)) 622 return 1; 623 } 624 } 625 626 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 627 return 1; 628 629 if (!printk_ratelimit()) 630 return 0; 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 634 retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 636 637 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 638 if (task_info) { 639 amdgpu_vm_print_task_info(adev, task_info); 640 amdgpu_vm_put_task_info(task_info); 641 } 642 643 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 644 addr, entry->client_id, 645 soc15_ih_clientid_name[entry->client_id]); 646 647 if (amdgpu_is_multi_aid(adev)) 648 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 649 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 650 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 651 652 if (amdgpu_sriov_vf(adev)) 653 return 0; 654 655 /* 656 * Issue a dummy read to wait for the status register to 657 * be updated to avoid reading an incorrect value due to 658 * the new fast GRBM interface. 659 */ 660 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 661 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 662 RREG32(hub->vm_l2_pro_fault_status); 663 664 status = RREG32(hub->vm_l2_pro_fault_status); 665 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 666 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 667 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 668 669 /* for fed error, kfd will handle it, return directly */ 670 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 671 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 672 return 0; 673 674 /* Only print L2 fault status if the status register could be read and 675 * contains useful information 676 */ 677 if (!status) 678 return 0; 679 680 if (!amdgpu_sriov_vf(adev)) 681 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 682 683 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 684 685 dev_err(adev->dev, 686 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 687 status); 688 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 689 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 690 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 691 gfxhub_client_ids[cid], 692 cid); 693 } else { 694 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 695 case IP_VERSION(9, 0, 0): 696 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ? 697 mmhub_client_ids_vega10[cid][rw] : NULL; 698 break; 699 case IP_VERSION(9, 3, 0): 700 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ? 701 mmhub_client_ids_vega12[cid][rw] : NULL; 702 break; 703 case IP_VERSION(9, 4, 0): 704 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ? 705 mmhub_client_ids_vega20[cid][rw] : NULL; 706 break; 707 case IP_VERSION(9, 4, 1): 708 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ? 709 mmhub_client_ids_arcturus[cid][rw] : NULL; 710 break; 711 case IP_VERSION(9, 1, 0): 712 case IP_VERSION(9, 2, 0): 713 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ? 714 mmhub_client_ids_raven[cid][rw] : NULL; 715 break; 716 case IP_VERSION(1, 5, 0): 717 case IP_VERSION(2, 4, 0): 718 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ? 719 mmhub_client_ids_renoir[cid][rw] : NULL; 720 break; 721 case IP_VERSION(1, 8, 0): 722 case IP_VERSION(9, 4, 2): 723 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ? 724 mmhub_client_ids_aldebaran[cid][rw] : NULL; 725 break; 726 default: 727 mmhub_cid = NULL; 728 break; 729 } 730 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 731 mmhub_cid ? mmhub_cid : "unknown", cid); 732 } 733 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 734 REG_GET_FIELD(status, 735 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 736 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 737 REG_GET_FIELD(status, 738 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 739 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 740 REG_GET_FIELD(status, 741 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 742 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 743 REG_GET_FIELD(status, 744 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 745 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 746 return 0; 747} 748 749static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 750 .set = gmc_v9_0_vm_fault_interrupt_state, 751 .process = gmc_v9_0_process_interrupt, 752}; 753 754 755static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 756 .set = gmc_v9_0_ecc_interrupt_state, 757 .process = amdgpu_umc_process_ecc_irq, 758}; 759 760static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 761{ 762 adev->gmc.vm_fault.num_types = 1; 763 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 764 765 if (!amdgpu_sriov_vf(adev) && 766 !adev->gmc.xgmi.connected_to_cpu && 767 !adev->gmc.is_app_apu) { 768 adev->gmc.ecc_irq.num_types = 1; 769 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 770 } 771} 772 773static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 774 uint32_t flush_type) 775{ 776 u32 req = 0; 777 778 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 779 PER_VMID_INVALIDATE_REQ, 1 << vmid); 780 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 782 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 783 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 784 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 785 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 786 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 787 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 788 789 return req; 790} 791 792/** 793 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 794 * 795 * @adev: amdgpu_device pointer 796 * @vmhub: vmhub type 797 * 798 */ 799static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 800 uint32_t vmhub) 801{ 802 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 803 amdgpu_is_multi_aid(adev)) 804 return false; 805 806 return ((vmhub == AMDGPU_MMHUB0(0) || 807 vmhub == AMDGPU_MMHUB1(0)) && 808 (!amdgpu_sriov_vf(adev)) && 809 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 810 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 811} 812 813static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 814 uint8_t vmid, uint16_t *p_pasid) 815{ 816 uint32_t value; 817 818 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 819 + vmid); 820 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 821 822 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 823} 824 825/* 826 * GART 827 * VMID 0 is the physical GPU addresses as used by the kernel. 828 * VMIDs 1-15 are used for userspace clients and are handled 829 * by the amdgpu vm/hsa code. 830 */ 831 832/** 833 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 834 * 835 * @adev: amdgpu_device pointer 836 * @vmid: vm instance to flush 837 * @vmhub: which hub to flush 838 * @flush_type: the flush type 839 * 840 * Flush the TLB for the requested page table using certain type. 841 */ 842static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 843 uint32_t vmhub, uint32_t flush_type) 844{ 845 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 846 u32 j, inv_req, tmp, sem, req, ack, inst; 847 const unsigned int eng = 17; 848 struct amdgpu_vmhub *hub; 849 850 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 851 852 hub = &adev->vmhub[vmhub]; 853 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 854 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 855 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 856 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 857 858 if (vmhub >= AMDGPU_MMHUB0(0)) 859 inst = 0; 860 else 861 inst = vmhub; 862 863 /* This is necessary for SRIOV as well as for GFXOFF to function 864 * properly under bare metal 865 */ 866 if (adev->gfx.kiq[inst].ring.sched.ready && 867 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 868 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 869 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 870 871 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 872 1 << vmid, inst); 873 return; 874 } 875 876 /* This path is needed before KIQ/MES/GFXOFF are set up */ 877 spin_lock(&adev->gmc.invalidate_lock); 878 879 /* 880 * It may lose gpuvm invalidate acknowldege state across power-gating 881 * off cycle, add semaphore acquire before invalidation and semaphore 882 * release after invalidation to avoid entering power gated state 883 * to WA the Issue 884 */ 885 886 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 887 if (use_semaphore) { 888 for (j = 0; j < adev->usec_timeout; j++) { 889 /* a read return value of 1 means semaphore acquire */ 890 if (vmhub >= AMDGPU_MMHUB0(0)) 891 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 892 else 893 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 894 if (tmp & 0x1) 895 break; 896 udelay(1); 897 } 898 899 if (j >= adev->usec_timeout) 900 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 901 } 902 903 if (vmhub >= AMDGPU_MMHUB0(0)) 904 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 905 else 906 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 907 908 /* 909 * Issue a dummy read to wait for the ACK register to 910 * be cleared to avoid a false ACK due to the new fast 911 * GRBM interface. 912 */ 913 if ((vmhub == AMDGPU_GFXHUB(0)) && 914 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 915 RREG32_NO_KIQ(req); 916 917 for (j = 0; j < adev->usec_timeout; j++) { 918 if (vmhub >= AMDGPU_MMHUB0(0)) 919 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 920 else 921 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 922 if (tmp & (1 << vmid)) 923 break; 924 udelay(1); 925 } 926 927 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 928 if (use_semaphore) { 929 /* 930 * add semaphore release after invalidation, 931 * write with 0 means semaphore release 932 */ 933 if (vmhub >= AMDGPU_MMHUB0(0)) 934 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 935 else 936 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 937 } 938 939 spin_unlock(&adev->gmc.invalidate_lock); 940 941 if (j < adev->usec_timeout) 942 return; 943 944 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 945} 946 947/** 948 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 949 * 950 * @adev: amdgpu_device pointer 951 * @pasid: pasid to be flush 952 * @flush_type: the flush type 953 * @all_hub: flush all hubs 954 * @inst: is used to select which instance of KIQ to use for the invalidation 955 * 956 * Flush the TLB for the requested pasid. 957 */ 958static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 959 uint16_t pasid, uint32_t flush_type, 960 bool all_hub, uint32_t inst) 961{ 962 uint16_t queried; 963 int i, vmid; 964 965 for (vmid = 1; vmid < 16; vmid++) { 966 bool valid; 967 968 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 969 &queried); 970 if (!valid || queried != pasid) 971 continue; 972 973 if (all_hub) { 974 for_each_set_bit(i, adev->vmhubs_mask, 975 AMDGPU_MAX_VMHUBS) 976 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 977 flush_type); 978 } else { 979 gmc_v9_0_flush_gpu_tlb(adev, vmid, 980 AMDGPU_GFXHUB(0), 981 flush_type); 982 } 983 } 984} 985 986static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 987 unsigned int vmid, uint64_t pd_addr) 988{ 989 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 990 struct amdgpu_device *adev = ring->adev; 991 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 992 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 993 unsigned int eng = ring->vm_inv_eng; 994 995 /* 996 * It may lose gpuvm invalidate acknowldege state across power-gating 997 * off cycle, add semaphore acquire before invalidation and semaphore 998 * release after invalidation to avoid entering power gated state 999 * to WA the Issue 1000 */ 1001 1002 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1003 if (use_semaphore) 1004 /* a read return value of 1 means semaphore acuqire */ 1005 amdgpu_ring_emit_reg_wait(ring, 1006 hub->vm_inv_eng0_sem + 1007 hub->eng_distance * eng, 0x1, 0x1); 1008 1009 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1010 (hub->ctx_addr_distance * vmid), 1011 lower_32_bits(pd_addr)); 1012 1013 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1014 (hub->ctx_addr_distance * vmid), 1015 upper_32_bits(pd_addr)); 1016 1017 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1018 hub->eng_distance * eng, 1019 hub->vm_inv_eng0_ack + 1020 hub->eng_distance * eng, 1021 req, 1 << vmid); 1022 1023 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1024 if (use_semaphore) 1025 /* 1026 * add semaphore release after invalidation, 1027 * write with 0 means semaphore release 1028 */ 1029 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1030 hub->eng_distance * eng, 0); 1031 1032 return pd_addr; 1033} 1034 1035static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1036 unsigned int pasid) 1037{ 1038 struct amdgpu_device *adev = ring->adev; 1039 uint32_t reg; 1040 1041 /* Do nothing because there's no lut register for mmhub1. */ 1042 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1043 return; 1044 1045 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1046 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1047 else 1048 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1049 1050 amdgpu_ring_emit_wreg(ring, reg, pasid); 1051} 1052 1053/* 1054 * PTE format on VEGA 10: 1055 * 63:59 reserved 1056 * 58:57 mtype 1057 * 56 F 1058 * 55 L 1059 * 54 P 1060 * 53 SW 1061 * 52 T 1062 * 50:48 reserved 1063 * 47:12 4k physical page base address 1064 * 11:7 fragment 1065 * 6 write 1066 * 5 read 1067 * 4 exe 1068 * 3 Z 1069 * 2 snooped 1070 * 1 system 1071 * 0 valid 1072 * 1073 * PDE format on VEGA 10: 1074 * 63:59 block fragment size 1075 * 58:55 reserved 1076 * 54 P 1077 * 53:48 reserved 1078 * 47:6 physical base address of PD or PTE 1079 * 5:3 reserved 1080 * 2 C 1081 * 1 system 1082 * 0 valid 1083 */ 1084 1085static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1086 uint64_t *addr, uint64_t *flags) 1087{ 1088 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1089 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1090 BUG_ON(*addr & 0xFFFF00000000003FULL); 1091 1092 if (!adev->gmc.translate_further) 1093 return; 1094 1095 if (level == AMDGPU_VM_PDB1) { 1096 /* Set the block fragment size */ 1097 if (!(*flags & AMDGPU_PDE_PTE)) 1098 *flags |= AMDGPU_PDE_BFS(0x9); 1099 1100 } else if (level == AMDGPU_VM_PDB0) { 1101 if (*flags & AMDGPU_PDE_PTE) { 1102 *flags &= ~AMDGPU_PDE_PTE; 1103 if (!(*flags & AMDGPU_PTE_VALID)) 1104 *addr |= 1 << PAGE_SHIFT; 1105 } else { 1106 *flags |= AMDGPU_PTE_TF; 1107 } 1108 } 1109} 1110 1111static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1112 struct amdgpu_vm *vm, 1113 struct amdgpu_bo *bo, 1114 uint32_t vm_flags, 1115 uint64_t *flags) 1116{ 1117 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1118 bool is_vram = bo->tbo.resource && 1119 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1120 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1121 AMDGPU_GEM_CREATE_EXT_COHERENT); 1122 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1123 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1124 unsigned int mtype_local, mtype; 1125 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1126 bool snoop = false; 1127 bool is_local; 1128 1129 dma_resv_assert_held(bo->tbo.base.resv); 1130 1131 switch (gc_ip_version) { 1132 case IP_VERSION(9, 4, 1): 1133 case IP_VERSION(9, 4, 2): 1134 if (is_vram) { 1135 if (bo_adev == adev) { 1136 if (uncached) 1137 mtype = MTYPE_UC; 1138 else if (coherent) 1139 mtype = MTYPE_CC; 1140 else 1141 mtype = MTYPE_RW; 1142 /* FIXME: is this still needed? Or does 1143 * amdgpu_ttm_tt_pde_flags already handle this? 1144 */ 1145 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1146 adev->gmc.xgmi.connected_to_cpu) 1147 snoop = true; 1148 } else { 1149 if (uncached || coherent) 1150 mtype = MTYPE_UC; 1151 else 1152 mtype = MTYPE_NC; 1153 if (amdgpu_xgmi_same_hive(adev, bo_adev)) 1154 snoop = true; 1155 } 1156 } else { 1157 if (uncached || coherent) 1158 mtype = MTYPE_UC; 1159 else 1160 mtype = MTYPE_NC; 1161 /* FIXME: is this still needed? Or does 1162 * amdgpu_ttm_tt_pde_flags already handle this? 1163 */ 1164 snoop = true; 1165 } 1166 break; 1167 case IP_VERSION(9, 4, 3): 1168 case IP_VERSION(9, 4, 4): 1169 case IP_VERSION(9, 5, 0): 1170 /* Only local VRAM BOs or system memory on non-NUMA APUs 1171 * can be assumed to be local in their entirety. Choose 1172 * MTYPE_NC as safe fallback for all system memory BOs on 1173 * NUMA systems. Their MTYPE can be overridden per-page in 1174 * gmc_v9_0_override_vm_pte_flags. 1175 */ 1176 mtype_local = MTYPE_RW; 1177 if (amdgpu_mtype_local == 1) { 1178 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1179 mtype_local = MTYPE_NC; 1180 } else if (amdgpu_mtype_local == 2) { 1181 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1182 mtype_local = MTYPE_CC; 1183 } else { 1184 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1185 } 1186 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1187 num_possible_nodes() <= 1) || 1188 (is_vram && adev == bo_adev && 1189 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1190 snoop = true; 1191 if (uncached) { 1192 mtype = MTYPE_UC; 1193 } else if (ext_coherent) { 1194 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1195 } else if (adev->flags & AMD_IS_APU) { 1196 mtype = is_local ? mtype_local : MTYPE_NC; 1197 } else { 1198 /* dGPU */ 1199 if (is_local) 1200 mtype = mtype_local; 1201 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1202 mtype = MTYPE_UC; 1203 else 1204 mtype = MTYPE_NC; 1205 } 1206 1207 break; 1208 default: 1209 if (uncached || coherent) 1210 mtype = MTYPE_UC; 1211 else 1212 mtype = MTYPE_NC; 1213 1214 /* FIXME: is this still needed? Or does 1215 * amdgpu_ttm_tt_pde_flags already handle this? 1216 */ 1217 if (!is_vram) 1218 snoop = true; 1219 } 1220 1221 if (mtype != MTYPE_NC) 1222 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1223 1224 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1225} 1226 1227static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1228 struct amdgpu_vm *vm, 1229 struct amdgpu_bo *bo, 1230 uint32_t vm_flags, 1231 uint64_t *flags) 1232{ 1233 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 1234 *flags |= AMDGPU_PTE_EXECUTABLE; 1235 else 1236 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1237 1238 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 1239 case AMDGPU_VM_MTYPE_DEFAULT: 1240 case AMDGPU_VM_MTYPE_NC: 1241 default: 1242 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC); 1243 break; 1244 case AMDGPU_VM_MTYPE_WC: 1245 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC); 1246 break; 1247 case AMDGPU_VM_MTYPE_RW: 1248 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW); 1249 break; 1250 case AMDGPU_VM_MTYPE_CC: 1251 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1252 break; 1253 case AMDGPU_VM_MTYPE_UC: 1254 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC); 1255 break; 1256 } 1257 1258 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 1259 *flags |= AMDGPU_PTE_PRT; 1260 *flags &= ~AMDGPU_PTE_VALID; 1261 } 1262 1263 if ((*flags & AMDGPU_PTE_VALID) && bo) 1264 gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags); 1265} 1266 1267static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1268 struct amdgpu_vm *vm, 1269 uint64_t addr, uint64_t *flags) 1270{ 1271 int local_node, nid; 1272 1273 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1274 * memory can use more efficient MTYPEs. 1275 */ 1276 if (!(adev->flags & AMD_IS_APU) || 1277 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1278 return; 1279 1280 /* Only direct-mapped memory allows us to determine the NUMA node from 1281 * the DMA address. 1282 */ 1283 if (!adev->ram_is_direct_mapped) { 1284 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1285 return; 1286 } 1287 1288 /* MTYPE_NC is the same default and can be overridden. 1289 * MTYPE_UC will be present if the memory is extended-coherent 1290 * and can also be overridden. 1291 */ 1292 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1293 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1294 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1295 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1296 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1297 return; 1298 } 1299 1300 /* FIXME: Only supported on native mode for now. For carve-out, the 1301 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1302 * memory partitions are not associated with different NUMA nodes. 1303 */ 1304 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1305 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1306 } else { 1307 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1308 return; 1309 } 1310 1311 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1312 * page or NUMA nodes. 1313 */ 1314 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1315 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1316 return; 1317 } 1318 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1319 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1320 vm->mem_id, local_node, nid); 1321 if (nid == local_node) { 1322 uint64_t old_flags = *flags; 1323 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1324 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1325 unsigned int mtype_local = MTYPE_RW; 1326 1327 if (amdgpu_mtype_local == 1) 1328 mtype_local = MTYPE_NC; 1329 else if (amdgpu_mtype_local == 2) 1330 mtype_local = MTYPE_CC; 1331 1332 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1333 } else { 1334 /* MTYPE_UC case */ 1335 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1336 } 1337 1338 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1339 old_flags, *flags); 1340 } 1341} 1342 1343static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1344{ 1345 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1346 unsigned int size; 1347 1348 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1349 1350 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1351 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1352 } else { 1353 u32 viewport; 1354 1355 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1356 case IP_VERSION(1, 0, 0): 1357 case IP_VERSION(1, 0, 1): 1358 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1359 size = (REG_GET_FIELD(viewport, 1360 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1361 REG_GET_FIELD(viewport, 1362 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1363 4); 1364 break; 1365 case IP_VERSION(2, 1, 0): 1366 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1367 size = (REG_GET_FIELD(viewport, 1368 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1369 REG_GET_FIELD(viewport, 1370 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1371 4); 1372 break; 1373 default: 1374 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1375 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1376 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1377 4); 1378 break; 1379 } 1380 } 1381 1382 return size; 1383} 1384 1385static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1386{ 1387 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1388 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1389 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1390 return true; 1391 } 1392 1393 return false; 1394} 1395 1396static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1397 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1398 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1399 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1400 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1401 .get_vm_pde = gmc_v9_0_get_vm_pde, 1402 .get_vm_pte = gmc_v9_0_get_vm_pte, 1403 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1404 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1405 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, 1406 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1407 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1408}; 1409 1410static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1411{ 1412 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1413} 1414 1415static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1416{ 1417 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1418 case IP_VERSION(6, 0, 0): 1419 adev->umc.funcs = &umc_v6_0_funcs; 1420 break; 1421 case IP_VERSION(6, 1, 1): 1422 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1423 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1424 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1425 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1426 adev->umc.retire_unit = 1; 1427 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1428 adev->umc.ras = &umc_v6_1_ras; 1429 break; 1430 case IP_VERSION(6, 1, 2): 1431 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1432 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1433 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1434 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1435 adev->umc.retire_unit = 1; 1436 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1437 adev->umc.ras = &umc_v6_1_ras; 1438 break; 1439 case IP_VERSION(6, 7, 0): 1440 adev->umc.max_ras_err_cnt_per_query = 1441 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1442 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1443 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1444 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1445 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1446 if (!adev->gmc.xgmi.connected_to_cpu) 1447 adev->umc.ras = &umc_v6_7_ras; 1448 if (1 & adev->smuio.funcs->get_die_id(adev)) 1449 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1450 else 1451 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1452 break; 1453 case IP_VERSION(12, 0, 0): 1454 case IP_VERSION(12, 5, 0): 1455 adev->umc.max_ras_err_cnt_per_query = 1456 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1457 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1458 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1459 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1460 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1461 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1462 adev->umc.ras = &umc_v12_0_ras; 1463 break; 1464 default: 1465 break; 1466 } 1467} 1468 1469static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1470{ 1471 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1472 case IP_VERSION(9, 4, 1): 1473 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1474 break; 1475 case IP_VERSION(9, 4, 2): 1476 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1477 break; 1478 case IP_VERSION(1, 8, 0): 1479 case IP_VERSION(1, 8, 1): 1480 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1481 break; 1482 default: 1483 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1484 break; 1485 } 1486} 1487 1488static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1489{ 1490 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1491 case IP_VERSION(9, 4, 0): 1492 adev->mmhub.ras = &mmhub_v1_0_ras; 1493 break; 1494 case IP_VERSION(9, 4, 1): 1495 adev->mmhub.ras = &mmhub_v9_4_ras; 1496 break; 1497 case IP_VERSION(9, 4, 2): 1498 adev->mmhub.ras = &mmhub_v1_7_ras; 1499 break; 1500 case IP_VERSION(1, 8, 0): 1501 case IP_VERSION(1, 8, 1): 1502 adev->mmhub.ras = &mmhub_v1_8_ras; 1503 break; 1504 default: 1505 /* mmhub ras is not available */ 1506 break; 1507 } 1508} 1509 1510static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1511{ 1512 if (amdgpu_is_multi_aid(adev)) 1513 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1514 else 1515 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1516} 1517 1518static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1519{ 1520 adev->hdp.ras = &hdp_v4_0_ras; 1521} 1522 1523static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1524{ 1525 struct amdgpu_mca *mca = &adev->mca; 1526 1527 /* is UMC the right IP to check for MCA? Maybe DF? */ 1528 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1529 case IP_VERSION(6, 7, 0): 1530 if (!adev->gmc.xgmi.connected_to_cpu) { 1531 mca->mp0.ras = &mca_v3_0_mp0_ras; 1532 mca->mp1.ras = &mca_v3_0_mp1_ras; 1533 mca->mpio.ras = &mca_v3_0_mpio_ras; 1534 } 1535 break; 1536 default: 1537 break; 1538 } 1539} 1540 1541static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1542{ 1543 if (!adev->gmc.xgmi.connected_to_cpu) 1544 adev->gmc.xgmi.ras = &xgmi_ras; 1545} 1546 1547static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1548{ 1549 enum amdgpu_memory_partition mode; 1550 uint32_t supp_modes; 1551 int i; 1552 1553 adev->gmc.supported_nps_modes = 0; 1554 1555 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1556 return; 1557 1558 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1559 1560 /* Mode detected by hardware and supported modes available */ 1561 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) { 1562 while ((i = ffs(supp_modes))) { 1563 if (AMDGPU_ALL_NPS_MASK & BIT(i)) 1564 adev->gmc.supported_nps_modes |= BIT(i); 1565 supp_modes &= supp_modes - 1; 1566 } 1567 } else { 1568 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1569 * supported modes as 0. 1570 */ 1571 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1572 case IP_VERSION(9, 4, 3): 1573 case IP_VERSION(9, 4, 4): 1574 adev->gmc.supported_nps_modes = 1575 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1576 BIT(AMDGPU_NPS4_PARTITION_MODE); 1577 break; 1578 default: 1579 break; 1580 } 1581 } 1582} 1583 1584static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1585{ 1586 struct amdgpu_device *adev = ip_block->adev; 1587 1588 /* 1589 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1590 * in their IP discovery tables 1591 */ 1592 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1593 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1594 amdgpu_is_multi_aid(adev)) 1595 adev->gmc.xgmi.supported = true; 1596 1597 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1598 adev->gmc.xgmi.supported = true; 1599 adev->gmc.xgmi.connected_to_cpu = 1600 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1601 } 1602 1603 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1604 enum amdgpu_pkg_type pkg_type = 1605 adev->smuio.funcs->get_pkg_type(adev); 1606 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1607 * and the APU, can be in used two possible modes: 1608 * - carveout mode 1609 * - native APU mode 1610 * "is_app_apu" can be used to identify the APU in the native 1611 * mode. 1612 */ 1613 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1614 !pci_resource_len(adev->pdev, 0)); 1615 } 1616 1617 gmc_v9_0_set_gmc_funcs(adev); 1618 gmc_v9_0_set_irq_funcs(adev); 1619 gmc_v9_0_set_umc_funcs(adev); 1620 gmc_v9_0_set_mmhub_funcs(adev); 1621 gmc_v9_0_set_mmhub_ras_funcs(adev); 1622 gmc_v9_0_set_gfxhub_funcs(adev); 1623 gmc_v9_0_set_hdp_ras_funcs(adev); 1624 gmc_v9_0_set_mca_ras_funcs(adev); 1625 gmc_v9_0_set_xgmi_ras_funcs(adev); 1626 1627 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1628 adev->gmc.shared_aperture_end = 1629 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1630 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1631 adev->gmc.private_aperture_end = 1632 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1633 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1634 1635 return 0; 1636} 1637 1638static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1639{ 1640 struct amdgpu_device *adev = ip_block->adev; 1641 int r; 1642 1643 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1644 if (r) 1645 return r; 1646 1647 /* 1648 * Workaround performance drop issue with VBIOS enables partial 1649 * writes, while disables HBM ECC for vega10. 1650 */ 1651 if (!amdgpu_sriov_vf(adev) && 1652 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1653 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1654 if (adev->df.funcs && 1655 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1656 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1657 } 1658 } 1659 1660 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1661 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1662 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1663 } 1664 1665 r = amdgpu_gmc_ras_late_init(adev); 1666 if (r) 1667 return r; 1668 1669 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1670} 1671 1672static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1673 struct amdgpu_gmc *mc) 1674{ 1675 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1676 1677 amdgpu_gmc_set_agp_default(adev, mc); 1678 1679 /* add the xgmi offset of the physical node */ 1680 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1681 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1682 amdgpu_gmc_sysvm_location(adev, mc); 1683 } else { 1684 amdgpu_gmc_vram_location(adev, mc, base); 1685 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1686 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1687 amdgpu_gmc_agp_location(adev, mc); 1688 } 1689 /* base offset of vram pages */ 1690 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1691 1692 /* XXX: add the xgmi offset of the physical node? */ 1693 adev->vm_manager.vram_base_offset += 1694 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1695} 1696 1697/** 1698 * gmc_v9_0_mc_init - initialize the memory controller driver params 1699 * 1700 * @adev: amdgpu_device pointer 1701 * 1702 * Look up the amount of vram, vram width, and decide how to place 1703 * vram and gart within the GPU's physical address space. 1704 * Returns 0 for success. 1705 */ 1706static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1707{ 1708 int r; 1709 1710 /* size in MB on si */ 1711 if (!adev->gmc.is_app_apu) { 1712 adev->gmc.mc_vram_size = 1713 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1714 } else { 1715 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1716 adev->gmc.mc_vram_size = 0; 1717 } 1718 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1719 1720 if (!(adev->flags & AMD_IS_APU) && 1721 !adev->gmc.xgmi.connected_to_cpu) { 1722 r = amdgpu_device_resize_fb_bar(adev); 1723 if (r) 1724 return r; 1725 } 1726 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1727 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1728 1729#ifdef CONFIG_X86_64 1730 /* 1731 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1732 * interface can use VRAM through here as it appears system reserved 1733 * memory in host address space. 1734 * 1735 * For APUs, VRAM is just the stolen system memory and can be accessed 1736 * directly. 1737 * 1738 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1739 */ 1740 1741 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1742 if ((!amdgpu_sriov_vf(adev) && 1743 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1744 (adev->gmc.xgmi.supported && 1745 adev->gmc.xgmi.connected_to_cpu)) { 1746 adev->gmc.aper_base = 1747 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1748 adev->gmc.xgmi.physical_node_id * 1749 adev->gmc.xgmi.node_segment_size; 1750 adev->gmc.aper_size = adev->gmc.real_vram_size; 1751 } 1752 1753#endif 1754 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1755 1756 /* set the gart size */ 1757 if (amdgpu_gart_size == -1) { 1758 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1759 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1760 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1761 case IP_VERSION(9, 4, 0): 1762 case IP_VERSION(9, 4, 1): 1763 case IP_VERSION(9, 4, 2): 1764 case IP_VERSION(9, 4, 3): 1765 case IP_VERSION(9, 4, 4): 1766 case IP_VERSION(9, 5, 0): 1767 default: 1768 adev->gmc.gart_size = 512ULL << 20; 1769 break; 1770 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1771 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1772 case IP_VERSION(9, 3, 0): 1773 adev->gmc.gart_size = 1024ULL << 20; 1774 break; 1775 } 1776 } else { 1777 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1778 } 1779 1780 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1781 1782 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1783 1784 return 0; 1785} 1786 1787static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1788{ 1789 int r; 1790 1791 if (adev->gart.bo) { 1792 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1793 return 0; 1794 } 1795 1796 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1797 adev->gmc.vmid0_page_table_depth = 1; 1798 adev->gmc.vmid0_page_table_block_size = 12; 1799 } else { 1800 adev->gmc.vmid0_page_table_depth = 0; 1801 adev->gmc.vmid0_page_table_block_size = 0; 1802 } 1803 1804 /* Initialize common gart structure */ 1805 r = amdgpu_gart_init(adev); 1806 if (r) 1807 return r; 1808 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1809 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1810 AMDGPU_PTE_EXECUTABLE; 1811 1812 if (!adev->gmc.real_vram_size) { 1813 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1814 r = amdgpu_gart_table_ram_alloc(adev); 1815 if (r) 1816 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1817 } else { 1818 r = amdgpu_gart_table_vram_alloc(adev); 1819 if (r) 1820 return r; 1821 1822 if (amdgpu_gmc_is_pdb0_enabled(adev)) 1823 r = amdgpu_gmc_pdb0_alloc(adev); 1824 } 1825 1826 return r; 1827} 1828 1829/** 1830 * gmc_v9_0_save_registers - saves regs 1831 * 1832 * @adev: amdgpu_device pointer 1833 * 1834 * This saves potential register values that should be 1835 * restored upon resume 1836 */ 1837static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1838{ 1839 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1840 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1841 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1842} 1843 1844static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1845{ 1846 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 1847 u32 vram_info; 1848 1849 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1850 adev->gmc.vram_width = 128 * 64; 1851 1852 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1853 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1854 1855 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && 1856 adev->rev_id == 0x3) 1857 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1858 1859 if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { 1860 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1861 adev->gmc.vram_vendor = vram_info & 0xF; 1862 } 1863} 1864 1865static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 1866{ 1867 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1868 struct amdgpu_device *adev = ip_block->adev; 1869 unsigned long inst_mask = adev->aid_mask; 1870 1871 adev->gfxhub.funcs->init(adev); 1872 1873 adev->mmhub.funcs->init(adev); 1874 1875 spin_lock_init(&adev->gmc.invalidate_lock); 1876 1877 if (amdgpu_is_multi_aid(adev)) { 1878 gmc_v9_4_3_init_vram_info(adev); 1879 } else if (!adev->bios) { 1880 if (adev->flags & AMD_IS_APU) { 1881 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1882 adev->gmc.vram_width = 64 * 64; 1883 } else { 1884 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1885 adev->gmc.vram_width = 128 * 64; 1886 } 1887 } else { 1888 r = amdgpu_atomfirmware_get_vram_info(adev, 1889 &vram_width, &vram_type, &vram_vendor); 1890 if (amdgpu_sriov_vf(adev)) 1891 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1892 * and DF related registers is not readable, seems hardcord is the 1893 * only way to set the correct vram_width 1894 */ 1895 adev->gmc.vram_width = 2048; 1896 else if (amdgpu_emu_mode != 1) 1897 adev->gmc.vram_width = vram_width; 1898 1899 if (!adev->gmc.vram_width) { 1900 int chansize, numchan; 1901 1902 /* hbm memory channel size */ 1903 if (adev->flags & AMD_IS_APU) 1904 chansize = 64; 1905 else 1906 chansize = 128; 1907 if (adev->df.funcs && 1908 adev->df.funcs->get_hbm_channel_number) { 1909 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1910 adev->gmc.vram_width = numchan * chansize; 1911 } 1912 } 1913 1914 adev->gmc.vram_type = vram_type; 1915 adev->gmc.vram_vendor = vram_vendor; 1916 } 1917 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1918 case IP_VERSION(9, 1, 0): 1919 case IP_VERSION(9, 2, 2): 1920 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1921 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1922 1923 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1924 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1925 } else { 1926 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1927 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1928 adev->gmc.translate_further = 1929 adev->vm_manager.num_level > 1; 1930 } 1931 break; 1932 case IP_VERSION(9, 0, 1): 1933 case IP_VERSION(9, 2, 1): 1934 case IP_VERSION(9, 4, 0): 1935 case IP_VERSION(9, 3, 0): 1936 case IP_VERSION(9, 4, 2): 1937 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1938 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1939 1940 /* 1941 * To fulfill 4-level page support, 1942 * vm size is 256TB (48bit), maximum size of Vega10, 1943 * block size 512 (9bit) 1944 */ 1945 1946 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1947 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1948 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1949 break; 1950 case IP_VERSION(9, 4, 1): 1951 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1952 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1953 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 1954 1955 /* Keep the vm size same with Vega20 */ 1956 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1957 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1958 break; 1959 case IP_VERSION(9, 4, 3): 1960 case IP_VERSION(9, 4, 4): 1961 case IP_VERSION(9, 5, 0): 1962 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 1963 NUM_XCC(adev->gfx.xcc_mask)); 1964 1965 inst_mask <<= AMDGPU_MMHUB0(0); 1966 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 1967 1968 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1969 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1970 break; 1971 default: 1972 break; 1973 } 1974 1975 /* This interrupt is VMC page fault.*/ 1976 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1977 &adev->gmc.vm_fault); 1978 if (r) 1979 return r; 1980 1981 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 1982 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1983 &adev->gmc.vm_fault); 1984 if (r) 1985 return r; 1986 } 1987 1988 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1989 &adev->gmc.vm_fault); 1990 1991 if (r) 1992 return r; 1993 1994 if (!amdgpu_sriov_vf(adev) && 1995 !adev->gmc.xgmi.connected_to_cpu && 1996 !adev->gmc.is_app_apu) { 1997 /* interrupt sent to DF. */ 1998 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1999 &adev->gmc.ecc_irq); 2000 if (r) 2001 return r; 2002 } 2003 2004 /* Set the internal MC address mask 2005 * This is the max address of the GPU's 2006 * internal address space. 2007 */ 2008 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2009 2010 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2011 IP_VERSION(9, 4, 2) ? 2012 48 : 2013 44; 2014 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2015 if (r) { 2016 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2017 return r; 2018 } 2019 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2020 2021 r = gmc_v9_0_mc_init(adev); 2022 if (r) 2023 return r; 2024 2025 amdgpu_gmc_get_vbios_allocations(adev); 2026 2027 if (amdgpu_is_multi_aid(adev)) { 2028 r = amdgpu_gmc_init_mem_ranges(adev); 2029 if (r) 2030 return r; 2031 } 2032 2033 /* Memory manager */ 2034 r = amdgpu_bo_init(adev); 2035 if (r) 2036 return r; 2037 2038 r = gmc_v9_0_gart_init(adev); 2039 if (r) 2040 return r; 2041 2042 gmc_v9_0_init_nps_details(adev); 2043 /* 2044 * number of VMs 2045 * VMID 0 is reserved for System 2046 * amdgpu graphics/compute will use VMIDs 1..n-1 2047 * amdkfd will use VMIDs n..15 2048 * 2049 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2050 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2051 * for video processing. 2052 */ 2053 adev->vm_manager.first_kfd_vmid = 2054 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2055 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2056 amdgpu_is_multi_aid(adev)) ? 2057 3 : 2058 8; 2059 2060 amdgpu_vm_manager_init(adev); 2061 2062 gmc_v9_0_save_registers(adev); 2063 2064 r = amdgpu_gmc_ras_sw_init(adev); 2065 if (r) 2066 return r; 2067 2068 if (amdgpu_is_multi_aid(adev)) 2069 amdgpu_gmc_sysfs_init(adev); 2070 2071 return 0; 2072} 2073 2074static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2075{ 2076 struct amdgpu_device *adev = ip_block->adev; 2077 2078 if (amdgpu_is_multi_aid(adev)) 2079 amdgpu_gmc_sysfs_fini(adev); 2080 2081 amdgpu_gmc_ras_fini(adev); 2082 amdgpu_gem_force_release(adev); 2083 amdgpu_vm_manager_fini(adev); 2084 if (!adev->gmc.real_vram_size) { 2085 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2086 amdgpu_gart_table_ram_free(adev); 2087 } else { 2088 amdgpu_gart_table_vram_free(adev); 2089 } 2090 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2091 amdgpu_bo_fini(adev); 2092 2093 adev->gmc.num_mem_partitions = 0; 2094 kfree(adev->gmc.mem_partitions); 2095 2096 return 0; 2097} 2098 2099static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2100{ 2101 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2102 case IP_VERSION(9, 0, 0): 2103 if (amdgpu_sriov_vf(adev)) 2104 break; 2105 fallthrough; 2106 case IP_VERSION(9, 4, 0): 2107 soc15_program_register_sequence(adev, 2108 golden_settings_mmhub_1_0_0, 2109 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2110 soc15_program_register_sequence(adev, 2111 golden_settings_athub_1_0_0, 2112 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2113 break; 2114 case IP_VERSION(9, 1, 0): 2115 case IP_VERSION(9, 2, 0): 2116 /* TODO for renoir */ 2117 soc15_program_register_sequence(adev, 2118 golden_settings_athub_1_0_0, 2119 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2120 break; 2121 default: 2122 break; 2123 } 2124} 2125 2126/** 2127 * gmc_v9_0_restore_registers - restores regs 2128 * 2129 * @adev: amdgpu_device pointer 2130 * 2131 * This restores register values, saved at suspend. 2132 */ 2133void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2134{ 2135 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2136 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2137 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2138 WARN_ON(adev->gmc.sdpif_register != 2139 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2140 } 2141} 2142 2143/** 2144 * gmc_v9_0_gart_enable - gart enable 2145 * 2146 * @adev: amdgpu_device pointer 2147 */ 2148static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2149{ 2150 int r; 2151 2152 if (amdgpu_gmc_is_pdb0_enabled(adev)) 2153 amdgpu_gmc_init_pdb0(adev); 2154 2155 if (adev->gart.bo == NULL) { 2156 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2157 return -EINVAL; 2158 } 2159 2160 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2161 2162 if (!adev->in_s0ix) { 2163 r = adev->gfxhub.funcs->gart_enable(adev); 2164 if (r) 2165 return r; 2166 } 2167 2168 r = adev->mmhub.funcs->gart_enable(adev); 2169 if (r) 2170 return r; 2171 2172 DRM_INFO("PCIE GART of %uM enabled.\n", 2173 (unsigned int)(adev->gmc.gart_size >> 20)); 2174 if (adev->gmc.pdb0_bo) 2175 DRM_INFO("PDB0 located at 0x%016llX\n", 2176 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2177 DRM_INFO("PTB located at 0x%016llX\n", 2178 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2179 2180 return 0; 2181} 2182 2183static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2184{ 2185 struct amdgpu_device *adev = ip_block->adev; 2186 bool value; 2187 int i, r; 2188 2189 adev->gmc.flush_pasid_uses_kiq = true; 2190 2191 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2192 * (type 2), which flushes both. Due to a race condition with 2193 * concurrent memory accesses using the same TLB cache line, we still 2194 * need a second TLB flush after this. 2195 */ 2196 adev->gmc.flush_tlb_needs_extra_type_2 = 2197 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2198 adev->gmc.xgmi.num_physical_nodes; 2199 2200 /* The sequence of these two function calls matters.*/ 2201 gmc_v9_0_init_golden_registers(adev); 2202 2203 if (adev->mode_info.num_crtc) { 2204 /* Lockout access through VGA aperture*/ 2205 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2206 /* disable VGA render */ 2207 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2208 } 2209 2210 if (adev->mmhub.funcs->update_power_gating) 2211 adev->mmhub.funcs->update_power_gating(adev, true); 2212 2213 adev->hdp.funcs->init_registers(adev); 2214 2215 /* After HDP is initialized, flush HDP.*/ 2216 amdgpu_device_flush_hdp(adev, NULL); 2217 2218 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2219 value = false; 2220 else 2221 value = true; 2222 2223 if (!amdgpu_sriov_vf(adev)) { 2224 if (!adev->in_s0ix) 2225 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2226 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2227 } 2228 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2229 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2230 continue; 2231 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2232 } 2233 2234 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2235 adev->umc.funcs->init_registers(adev); 2236 2237 r = gmc_v9_0_gart_enable(adev); 2238 if (r) 2239 return r; 2240 2241 if (amdgpu_emu_mode == 1) 2242 return amdgpu_gmc_vram_checking(adev); 2243 2244 return 0; 2245} 2246 2247/** 2248 * gmc_v9_0_gart_disable - gart disable 2249 * 2250 * @adev: amdgpu_device pointer 2251 * 2252 * This disables all VM page table. 2253 */ 2254static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2255{ 2256 if (!adev->in_s0ix) 2257 adev->gfxhub.funcs->gart_disable(adev); 2258 adev->mmhub.funcs->gart_disable(adev); 2259} 2260 2261static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2262{ 2263 struct amdgpu_device *adev = ip_block->adev; 2264 2265 gmc_v9_0_gart_disable(adev); 2266 2267 if (amdgpu_sriov_vf(adev)) { 2268 /* full access mode, so don't touch any GMC register */ 2269 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2270 return 0; 2271 } 2272 2273 /* 2274 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2275 * a correct cached state for GMC. Otherwise, the "gate" again 2276 * operation on S3 resuming will fail due to wrong cached state. 2277 */ 2278 if (adev->mmhub.funcs->update_power_gating) 2279 adev->mmhub.funcs->update_power_gating(adev, false); 2280 2281 /* 2282 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2283 * are not enabled. 2284 */ 2285 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2286 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2287 2288 if (adev->gmc.ecc_irq.funcs && 2289 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2290 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2291 } 2292 2293 return 0; 2294} 2295 2296static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2297{ 2298 return gmc_v9_0_hw_fini(ip_block); 2299} 2300 2301static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2302{ 2303 struct amdgpu_device *adev = ip_block->adev; 2304 int r; 2305 2306 /* If a reset is done for NPS mode switch, read the memory range 2307 * information again. 2308 */ 2309 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2310 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2311 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2312 } 2313 2314 r = gmc_v9_0_hw_init(ip_block); 2315 if (r) 2316 return r; 2317 2318 amdgpu_vmid_reset_all(ip_block->adev); 2319 2320 return 0; 2321} 2322 2323static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block) 2324{ 2325 /* MC is always ready in GMC v9.*/ 2326 return true; 2327} 2328 2329static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2330{ 2331 /* There is no need to wait for MC idle in GMC v9.*/ 2332 return 0; 2333} 2334 2335static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2336{ 2337 /* XXX for emulation.*/ 2338 return 0; 2339} 2340 2341static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2342 enum amd_clockgating_state state) 2343{ 2344 struct amdgpu_device *adev = ip_block->adev; 2345 2346 adev->mmhub.funcs->set_clockgating(adev, state); 2347 2348 athub_v1_0_set_clockgating(adev, state); 2349 2350 return 0; 2351} 2352 2353static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2354{ 2355 struct amdgpu_device *adev = ip_block->adev; 2356 2357 adev->mmhub.funcs->get_clockgating(adev, flags); 2358 2359 athub_v1_0_get_clockgating(adev, flags); 2360} 2361 2362static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2363 enum amd_powergating_state state) 2364{ 2365 return 0; 2366} 2367 2368const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2369 .name = "gmc_v9_0", 2370 .early_init = gmc_v9_0_early_init, 2371 .late_init = gmc_v9_0_late_init, 2372 .sw_init = gmc_v9_0_sw_init, 2373 .sw_fini = gmc_v9_0_sw_fini, 2374 .hw_init = gmc_v9_0_hw_init, 2375 .hw_fini = gmc_v9_0_hw_fini, 2376 .suspend = gmc_v9_0_suspend, 2377 .resume = gmc_v9_0_resume, 2378 .is_idle = gmc_v9_0_is_idle, 2379 .wait_for_idle = gmc_v9_0_wait_for_idle, 2380 .soft_reset = gmc_v9_0_soft_reset, 2381 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2382 .set_powergating_state = gmc_v9_0_set_powergating_state, 2383 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2384}; 2385 2386const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2387 .type = AMD_IP_BLOCK_TYPE_GMC, 2388 .major = 9, 2389 .minor = 0, 2390 .rev = 0, 2391 .funcs = &gmc_v9_0_ip_funcs, 2392};
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