gmc_v7_0.c

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/firmware.h>
  25#include <linux/module.h>
  26#include <linux/pci.h>
  27
  28#include <drm/drm_cache.h>
  29#include "amdgpu.h"
  30#include "cikd.h"
  31#include "cik.h"
  32#include "gmc_v7_0.h"
  33#include "amdgpu_ucode.h"
  34#include "amdgpu_amdkfd.h"
  35#include "amdgpu_gem.h"
  36
  37#include "bif/bif_4_1_d.h"
  38#include "bif/bif_4_1_sh_mask.h"
  39
  40#include "gmc/gmc_7_1_d.h"
  41#include "gmc/gmc_7_1_sh_mask.h"
  42
  43#include "oss/oss_2_0_d.h"
  44#include "oss/oss_2_0_sh_mask.h"
  45
  46#include "dce/dce_8_0_d.h"
  47#include "dce/dce_8_0_sh_mask.h"
  48
  49#include "amdgpu_atombios.h"
  50
  51#include "ivsrcid/ivsrcid_vislands30.h"
  52
  53static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
  54static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
  56
  57MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
  58MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
  59MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  60
  61static const u32 golden_settings_iceland_a11[] = {
  62	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  66};
  67
  68static const u32 iceland_mgcg_cgcg_init[] = {
  69	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  70};
  71
  72static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  73{
  74	switch (adev->asic_type) {
  75	case CHIP_TOPAZ:
  76		amdgpu_device_program_register_sequence(adev,
  77							iceland_mgcg_cgcg_init,
  78							ARRAY_SIZE(iceland_mgcg_cgcg_init));
  79		amdgpu_device_program_register_sequence(adev,
  80							golden_settings_iceland_a11,
  81							ARRAY_SIZE(golden_settings_iceland_a11));
  82		break;
  83	default:
  84		break;
  85	}
  86}
  87
  88static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  89{
  90	struct amdgpu_ip_block *ip_block;
  91	u32 blackout;
  92
  93	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
  94	if (!ip_block)
  95		return;
  96
  97	gmc_v7_0_wait_for_idle(ip_block);
  98
  99	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 100	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 101		/* Block CPU access */
 102		WREG32(mmBIF_FB_EN, 0);
 103		/* blackout the MC */
 104		blackout = REG_SET_FIELD(blackout,
 105					 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 106		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 107	}
 108	/* wait for the MC to settle */
 109	udelay(100);
 110}
 111
 112static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 113{
 114	u32 tmp;
 115
 116	/* unblackout the MC */
 117	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 118	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 119	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 120	/* allow CPU access */
 121	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 122	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 123	WREG32(mmBIF_FB_EN, tmp);
 124}
 125
 126/**
 127 * gmc_v7_0_init_microcode - load ucode images from disk
 128 *
 129 * @adev: amdgpu_device pointer
 130 *
 131 * Use the firmware interface to load the ucode images into
 132 * the driver (not loaded into hw).
 133 * Returns 0 on success, error on failure.
 134 */
 135static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 136{
 137	const char *chip_name;
 138	int err;
 139
 140	DRM_DEBUG("\n");
 141
 142	switch (adev->asic_type) {
 143	case CHIP_BONAIRE:
 144		chip_name = "bonaire";
 145		break;
 146	case CHIP_HAWAII:
 147		chip_name = "hawaii";
 148		break;
 149	case CHIP_TOPAZ:
 150		chip_name = "topaz";
 151		break;
 152	case CHIP_KAVERI:
 153	case CHIP_KABINI:
 154	case CHIP_MULLINS:
 155		return 0;
 156	default:
 157		return -EINVAL;
 158	}
 159
 160	err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED,
 161				   "amdgpu/%s_mc.bin", chip_name);
 162	if (err) {
 163		pr_err("cik_mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);
 164		amdgpu_ucode_release(&adev->gmc.fw);
 165	}
 166	return err;
 167}
 168
 169/**
 170 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 171 *
 172 * @adev: amdgpu_device pointer
 173 *
 174 * Load the GDDR MC ucode into the hw (CIK).
 175 * Returns 0 on success, error on failure.
 176 */
 177static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 178{
 179	const struct mc_firmware_header_v1_0 *hdr;
 180	const __le32 *fw_data = NULL;
 181	const __le32 *io_mc_regs = NULL;
 182	u32 running;
 183	int i, ucode_size, regs_size;
 184
 185	if (!adev->gmc.fw)
 186		return -EINVAL;
 187
 188	hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 189	amdgpu_ucode_print_mc_hdr(&hdr->header);
 190
 191	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 192	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 193	io_mc_regs = (const __le32 *)
 194		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 195	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 196	fw_data = (const __le32 *)
 197		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 198
 199	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 200
 201	if (running == 0) {
 202		/* reset the engine and set to writable */
 203		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 204		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 205
 206		/* load mc io regs */
 207		for (i = 0; i < regs_size; i++) {
 208			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 209			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 210		}
 211		/* load the MC ucode */
 212		for (i = 0; i < ucode_size; i++)
 213			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 214
 215		/* put the engine back into the active state */
 216		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 217		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 218		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 219
 220		/* wait for training to complete */
 221		for (i = 0; i < adev->usec_timeout; i++) {
 222			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 223					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 224				break;
 225			udelay(1);
 226		}
 227		for (i = 0; i < adev->usec_timeout; i++) {
 228			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 229					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 230				break;
 231			udelay(1);
 232		}
 233	}
 234
 235	return 0;
 236}
 237
 238static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 239				       struct amdgpu_gmc *mc)
 240{
 241	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 242
 243	base <<= 24;
 244
 245	amdgpu_gmc_set_agp_default(adev, mc);
 246	amdgpu_gmc_vram_location(adev, mc, base);
 247	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
 248}
 249
 250/**
 251 * gmc_v7_0_mc_program - program the GPU memory controller
 252 *
 253 * @adev: amdgpu_device pointer
 254 *
 255 * Set the location of vram, gart, and AGP in the GPU's
 256 * physical address space (CIK).
 257 */
 258static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 259{
 260	struct amdgpu_ip_block *ip_block;
 261	u32 tmp;
 262	int i, j;
 263
 264	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
 265	if (!ip_block)
 266		return;
 267
 268	/* Initialize HDP */
 269	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 270		WREG32((0xb05 + j), 0x00000000);
 271		WREG32((0xb06 + j), 0x00000000);
 272		WREG32((0xb07 + j), 0x00000000);
 273		WREG32((0xb08 + j), 0x00000000);
 274		WREG32((0xb09 + j), 0x00000000);
 275	}
 276	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 277
 278	if (gmc_v7_0_wait_for_idle(ip_block))
 279		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 280
 281	if (adev->mode_info.num_crtc) {
 282		/* Lockout access through VGA aperture*/
 283		tmp = RREG32(mmVGA_HDP_CONTROL);
 284		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 285		WREG32(mmVGA_HDP_CONTROL, tmp);
 286
 287		/* disable VGA render */
 288		tmp = RREG32(mmVGA_RENDER_CONTROL);
 289		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 290		WREG32(mmVGA_RENDER_CONTROL, tmp);
 291	}
 292	/* Update configuration */
 293	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 294	       adev->gmc.vram_start >> 12);
 295	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 296	       adev->gmc.vram_end >> 12);
 297	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 298	       adev->mem_scratch.gpu_addr >> 12);
 299	WREG32(mmMC_VM_AGP_BASE, 0);
 300	WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
 301	WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
 302	if (gmc_v7_0_wait_for_idle(ip_block))
 303		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 304
 305	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 306
 307	tmp = RREG32(mmHDP_MISC_CNTL);
 308	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 309	WREG32(mmHDP_MISC_CNTL, tmp);
 310
 311	tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 312	WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 313}
 314
 315/**
 316 * gmc_v7_0_mc_init - initialize the memory controller driver params
 317 *
 318 * @adev: amdgpu_device pointer
 319 *
 320 * Look up the amount of vram, vram width, and decide how to place
 321 * vram and gart within the GPU's physical address space (CIK).
 322 * Returns 0 for success.
 323 */
 324static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 325{
 326	int r;
 327
 328	adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 329	if (!adev->gmc.vram_width) {
 330		u32 tmp;
 331		int chansize, numchan;
 332
 333		/* Get VRAM informations */
 334		tmp = RREG32(mmMC_ARB_RAMCFG);
 335		if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
 336			chansize = 64;
 337		else
 338			chansize = 32;
 339
 340		tmp = RREG32(mmMC_SHARED_CHMAP);
 341		switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 342		case 0:
 343		default:
 344			numchan = 1;
 345			break;
 346		case 1:
 347			numchan = 2;
 348			break;
 349		case 2:
 350			numchan = 4;
 351			break;
 352		case 3:
 353			numchan = 8;
 354			break;
 355		case 4:
 356			numchan = 3;
 357			break;
 358		case 5:
 359			numchan = 6;
 360			break;
 361		case 6:
 362			numchan = 10;
 363			break;
 364		case 7:
 365			numchan = 12;
 366			break;
 367		case 8:
 368			numchan = 16;
 369			break;
 370		}
 371		adev->gmc.vram_width = numchan * chansize;
 372	}
 373	/* size in MB on si */
 374	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 375	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 376
 377	if (!(adev->flags & AMD_IS_APU)) {
 378		r = amdgpu_device_resize_fb_bar(adev);
 379		if (r)
 380			return r;
 381	}
 382	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 383	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 384
 385#ifdef CONFIG_X86_64
 386	if ((adev->flags & AMD_IS_APU) &&
 387	    adev->gmc.real_vram_size > adev->gmc.aper_size &&
 388	    !amdgpu_passthrough(adev)) {
 389		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 390		adev->gmc.aper_size = adev->gmc.real_vram_size;
 391	}
 392#endif
 393
 394	adev->gmc.visible_vram_size = adev->gmc.aper_size;
 395
 396	/* set the gart size */
 397	if (amdgpu_gart_size == -1) {
 398		switch (adev->asic_type) {
 399		case CHIP_TOPAZ:     /* no MM engines */
 400		default:
 401			adev->gmc.gart_size = 256ULL << 20;
 402			break;
 403#ifdef CONFIG_DRM_AMDGPU_CIK
 404		case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
 405		case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
 406		case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
 407		case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
 408		case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
 409			adev->gmc.gart_size = 1024ULL << 20;
 410			break;
 411#endif
 412		}
 413	} else {
 414		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 415	}
 416
 417	adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
 418	gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
 419
 420	return 0;
 421}
 422
 423/**
 424 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
 425 *
 426 * @adev: amdgpu_device pointer
 427 * @pasid: pasid to be flush
 428 * @flush_type: type of flush
 429 * @all_hub: flush all hubs
 430 * @inst: is used to select which instance of KIQ to use for the invalidation
 431 *
 432 * Flush the TLB for the requested pasid.
 433 */
 434static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 435					 uint16_t pasid, uint32_t flush_type,
 436					 bool all_hub, uint32_t inst)
 437{
 438	u32 mask = 0x0;
 439	int vmid;
 440
 441	for (vmid = 1; vmid < 16; vmid++) {
 442		u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 443
 444		if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 445		    (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
 446			mask |= 1 << vmid;
 447	}
 448
 449	WREG32(mmVM_INVALIDATE_REQUEST, mask);
 450	RREG32(mmVM_INVALIDATE_RESPONSE);
 451}
 452
 453/*
 454 * GART
 455 * VMID 0 is the physical GPU addresses as used by the kernel.
 456 * VMIDs 1-15 are used for userspace clients and are handled
 457 * by the amdgpu vm/hsa code.
 458 */
 459
 460/**
 461 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
 462 *
 463 * @adev: amdgpu_device pointer
 464 * @vmid: vm instance to flush
 465 * @vmhub: which hub to flush
 466 * @flush_type: type of flush
 467 * *
 468 * Flush the TLB for the requested page table (CIK).
 469 */
 470static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 471					uint32_t vmhub, uint32_t flush_type)
 472{
 473	/* bits 0-15 are the VM contexts0-15 */
 474	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 475}
 476
 477static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 478					    unsigned int vmid, uint64_t pd_addr)
 479{
 480	uint32_t reg;
 481
 482	if (vmid < 8)
 483		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 484	else
 485		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 486	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 487
 488	/* bits 0-15 are the VM contexts0-15 */
 489	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 490
 491	return pd_addr;
 492}
 493
 494static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
 495					unsigned int pasid)
 496{
 497	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 498}
 499
 500static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
 501				uint64_t *addr, uint64_t *flags)
 502{
 503	BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 504}
 505
 506static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
 507				struct amdgpu_vm *vm,
 508				struct amdgpu_bo *bo,
 509				uint32_t vm_flags,
 510				uint64_t *flags)
 511{
 512	*flags &= ~AMDGPU_PTE_EXECUTABLE;
 513	*flags &= ~AMDGPU_PTE_PRT;
 514}
 515
 516/**
 517 * gmc_v7_0_set_fault_enable_default - update VM fault handling
 518 *
 519 * @adev: amdgpu_device pointer
 520 * @value: true redirects VM faults to the default page
 521 */
 522static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 523					      bool value)
 524{
 525	u32 tmp;
 526
 527	tmp = RREG32(mmVM_CONTEXT1_CNTL);
 528	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 529			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 530	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 531			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 532	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 533			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 534	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 535			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 536	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 537			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 538	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 539			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 540	WREG32(mmVM_CONTEXT1_CNTL, tmp);
 541}
 542
 543/**
 544 * gmc_v7_0_set_prt - set PRT VM fault
 545 *
 546 * @adev: amdgpu_device pointer
 547 * @enable: enable/disable VM fault handling for PRT
 548 */
 549static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 550{
 551	uint32_t tmp;
 552
 553	if (enable && !adev->gmc.prt_warning) {
 554		dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 555		adev->gmc.prt_warning = true;
 556	}
 557
 558	tmp = RREG32(mmVM_PRT_CNTL);
 559	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 560			    CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 561	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 562			    CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 563	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 564			    TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 565	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 566			    TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 567	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 568			    L2_CACHE_STORE_INVALID_ENTRIES, enable);
 569	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 570			    L1_TLB_STORE_INVALID_ENTRIES, enable);
 571	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 572			    MASK_PDE0_FAULT, enable);
 573	WREG32(mmVM_PRT_CNTL, tmp);
 574
 575	if (enable) {
 576		uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>
 577			AMDGPU_GPU_PAGE_SHIFT;
 578		uint32_t high = adev->vm_manager.max_pfn -
 579			(AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);
 580
 581		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 582		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 583		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 584		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 585		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 586		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 587		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 588		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 589	} else {
 590		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 591		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 592		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 593		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 594		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 595		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 596		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 597		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 598	}
 599}
 600
 601/**
 602 * gmc_v7_0_gart_enable - gart enable
 603 *
 604 * @adev: amdgpu_device pointer
 605 *
 606 * This sets up the TLBs, programs the page tables for VMID0,
 607 * sets up the hw for VMIDs 1-15 which are allocated on
 608 * demand, and sets up the global locations for the LDS, GDS,
 609 * and GPUVM for FSA64 clients (CIK).
 610 * Returns 0 for success, errors for failure.
 611 */
 612static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 613{
 614	uint64_t table_addr;
 615	u32 tmp, field;
 616	int i;
 617
 618	if (adev->gart.bo == NULL) {
 619		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 620		return -EINVAL;
 621	}
 622	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 623	table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 624
 625	/* Setup TLB control */
 626	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 627	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 628	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 629	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 630	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 631	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 632	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 633	/* Setup L2 cache */
 634	tmp = RREG32(mmVM_L2_CNTL);
 635	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 636	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 637	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 638	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 639	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 640	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 641	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 642	WREG32(mmVM_L2_CNTL, tmp);
 643	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 644	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 645	WREG32(mmVM_L2_CNTL2, tmp);
 646
 647	field = adev->vm_manager.fragment_size;
 648	tmp = RREG32(mmVM_L2_CNTL3);
 649	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 650	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 651	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 652	WREG32(mmVM_L2_CNTL3, tmp);
 653	/* setup context0 */
 654	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 655	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 656	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 657	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 658			(u32)(adev->dummy_page_addr >> 12));
 659	WREG32(mmVM_CONTEXT0_CNTL2, 0);
 660	tmp = RREG32(mmVM_CONTEXT0_CNTL);
 661	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 662	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 663	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 664	WREG32(mmVM_CONTEXT0_CNTL, tmp);
 665
 666	WREG32(0x575, 0);
 667	WREG32(0x576, 0);
 668	WREG32(0x577, 0);
 669
 670	/* empty context1-15 */
 671	/* FIXME start with 4G, once using 2 level pt switch to full
 672	 * vm size space
 673	 */
 674	/* set vm size, must be a multiple of 4 */
 675	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 676	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 677	for (i = 1; i < AMDGPU_NUM_VMID; i++) {
 678		if (i < 8)
 679			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 680			       table_addr >> 12);
 681		else
 682			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 683			       table_addr >> 12);
 684	}
 685
 686	/* enable context1-15 */
 687	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 688	       (u32)(adev->dummy_page_addr >> 12));
 689	WREG32(mmVM_CONTEXT1_CNTL2, 4);
 690	tmp = RREG32(mmVM_CONTEXT1_CNTL);
 691	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 692	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 693	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 694			    adev->vm_manager.block_size - 9);
 695	WREG32(mmVM_CONTEXT1_CNTL, tmp);
 696	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 697		gmc_v7_0_set_fault_enable_default(adev, false);
 698	else
 699		gmc_v7_0_set_fault_enable_default(adev, true);
 700
 701	if (adev->asic_type == CHIP_KAVERI) {
 702		tmp = RREG32(mmCHUB_CONTROL);
 703		tmp &= ~BYPASS_VM;
 704		WREG32(mmCHUB_CONTROL, tmp);
 705	}
 706
 707	gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
 708	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 709		 (unsigned int)(adev->gmc.gart_size >> 20),
 710		 (unsigned long long)table_addr);
 711	return 0;
 712}
 713
 714static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 715{
 716	int r;
 717
 718	if (adev->gart.bo) {
 719		WARN(1, "R600 PCIE GART already initialized\n");
 720		return 0;
 721	}
 722	/* Initialize common gart structure */
 723	r = amdgpu_gart_init(adev);
 724	if (r)
 725		return r;
 726	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 727	adev->gart.gart_pte_flags = 0;
 728	return amdgpu_gart_table_vram_alloc(adev);
 729}
 730
 731/**
 732 * gmc_v7_0_gart_disable - gart disable
 733 *
 734 * @adev: amdgpu_device pointer
 735 *
 736 * This disables all VM page table (CIK).
 737 */
 738static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 739{
 740	u32 tmp;
 741
 742	/* Disable all tables */
 743	WREG32(mmVM_CONTEXT0_CNTL, 0);
 744	WREG32(mmVM_CONTEXT1_CNTL, 0);
 745	/* Setup TLB control */
 746	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 747	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 748	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 749	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 750	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 751	/* Setup L2 cache */
 752	tmp = RREG32(mmVM_L2_CNTL);
 753	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 754	WREG32(mmVM_L2_CNTL, tmp);
 755	WREG32(mmVM_L2_CNTL2, 0);
 756}
 757
 758/**
 759 * gmc_v7_0_vm_decode_fault - print human readable fault info
 760 *
 761 * @adev: amdgpu_device pointer
 762 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 763 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 764 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
 765 * @pasid: debug logging only - no functional use
 766 *
 767 * Print human readable fault information (CIK).
 768 */
 769static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 770				     u32 addr, u32 mc_client, unsigned int pasid)
 771{
 772	u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 773	u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 774					PROTECTIONS);
 775	char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 776		(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 777	u32 mc_id;
 778
 779	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 780			      MEMORY_CLIENT_ID);
 781
 782	dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 783	       protections, vmid, pasid, addr,
 784	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 785			     MEMORY_CLIENT_RW) ?
 786	       "write" : "read", block, mc_client, mc_id);
 787}
 788
 789
 790static const u32 mc_cg_registers[] = {
 791	mmMC_HUB_MISC_HUB_CG,
 792	mmMC_HUB_MISC_SIP_CG,
 793	mmMC_HUB_MISC_VM_CG,
 794	mmMC_XPB_CLK_GAT,
 795	mmATC_MISC_CG,
 796	mmMC_CITF_MISC_WR_CG,
 797	mmMC_CITF_MISC_RD_CG,
 798	mmMC_CITF_MISC_VM_CG,
 799	mmVM_L2_CG,
 800};
 801
 802static const u32 mc_cg_ls_en[] = {
 803	MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 804	MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 805	MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 806	MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 807	ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 808	MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 809	MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 810	MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 811	VM_L2_CG__MEM_LS_ENABLE_MASK,
 812};
 813
 814static const u32 mc_cg_en[] = {
 815	MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 816	MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 817	MC_HUB_MISC_VM_CG__ENABLE_MASK,
 818	MC_XPB_CLK_GAT__ENABLE_MASK,
 819	ATC_MISC_CG__ENABLE_MASK,
 820	MC_CITF_MISC_WR_CG__ENABLE_MASK,
 821	MC_CITF_MISC_RD_CG__ENABLE_MASK,
 822	MC_CITF_MISC_VM_CG__ENABLE_MASK,
 823	VM_L2_CG__ENABLE_MASK,
 824};
 825
 826static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 827				  bool enable)
 828{
 829	int i;
 830	u32 orig, data;
 831
 832	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 833		orig = data = RREG32(mc_cg_registers[i]);
 834		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 835			data |= mc_cg_ls_en[i];
 836		else
 837			data &= ~mc_cg_ls_en[i];
 838		if (data != orig)
 839			WREG32(mc_cg_registers[i], data);
 840	}
 841}
 842
 843static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 844				    bool enable)
 845{
 846	int i;
 847	u32 orig, data;
 848
 849	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 850		orig = data = RREG32(mc_cg_registers[i]);
 851		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 852			data |= mc_cg_en[i];
 853		else
 854			data &= ~mc_cg_en[i];
 855		if (data != orig)
 856			WREG32(mc_cg_registers[i], data);
 857	}
 858}
 859
 860static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 861				     bool enable)
 862{
 863	u32 orig, data;
 864
 865	orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 866
 867	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 868		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 869		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 870		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 871		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 872	} else {
 873		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 874		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 875		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 876		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 877	}
 878
 879	if (orig != data)
 880		WREG32_PCIE(ixPCIE_CNTL2, data);
 881}
 882
 883static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 884				     bool enable)
 885{
 886	u32 orig, data;
 887
 888	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 889
 890	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 891		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 892	else
 893		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 894
 895	if (orig != data)
 896		WREG32(mmHDP_HOST_PATH_CNTL, data);
 897}
 898
 899static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 900				   bool enable)
 901{
 902	u32 orig, data;
 903
 904	orig = data = RREG32(mmHDP_MEM_POWER_LS);
 905
 906	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 907		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 908	else
 909		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 910
 911	if (orig != data)
 912		WREG32(mmHDP_MEM_POWER_LS, data);
 913}
 914
 915static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 916{
 917	switch (mc_seq_vram_type) {
 918	case MC_SEQ_MISC0__MT__GDDR1:
 919		return AMDGPU_VRAM_TYPE_GDDR1;
 920	case MC_SEQ_MISC0__MT__DDR2:
 921		return AMDGPU_VRAM_TYPE_DDR2;
 922	case MC_SEQ_MISC0__MT__GDDR3:
 923		return AMDGPU_VRAM_TYPE_GDDR3;
 924	case MC_SEQ_MISC0__MT__GDDR4:
 925		return AMDGPU_VRAM_TYPE_GDDR4;
 926	case MC_SEQ_MISC0__MT__GDDR5:
 927		return AMDGPU_VRAM_TYPE_GDDR5;
 928	case MC_SEQ_MISC0__MT__HBM:
 929		return AMDGPU_VRAM_TYPE_HBM;
 930	case MC_SEQ_MISC0__MT__DDR3:
 931		return AMDGPU_VRAM_TYPE_DDR3;
 932	default:
 933		return AMDGPU_VRAM_TYPE_UNKNOWN;
 934	}
 935}
 936
 937static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block)
 938{
 939	struct amdgpu_device *adev = ip_block->adev;
 940
 941	gmc_v7_0_set_gmc_funcs(adev);
 942	gmc_v7_0_set_irq_funcs(adev);
 943
 944	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 945	adev->gmc.shared_aperture_end =
 946		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 947	adev->gmc.private_aperture_start =
 948		adev->gmc.shared_aperture_end + 1;
 949	adev->gmc.private_aperture_end =
 950		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 951	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
 952
 953	return 0;
 954}
 955
 956static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block)
 957{
 958	struct amdgpu_device *adev = ip_block->adev;
 959
 960	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 961		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 962	else
 963		return 0;
 964}
 965
 966static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
 967{
 968	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 969	unsigned int size;
 970
 971	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 972		size = AMDGPU_VBIOS_VGA_ALLOCATION;
 973	} else {
 974		u32 viewport = RREG32(mmVIEWPORT_SIZE);
 975
 976		size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 977			REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 978			4);
 979	}
 980
 981	return size;
 982}
 983
 984static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
 985{
 986	int r;
 987	struct amdgpu_device *adev = ip_block->adev;
 988
 989	set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 990
 991	if (adev->flags & AMD_IS_APU) {
 992		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 993	} else {
 994		u32 tmp = RREG32(mmMC_SEQ_MISC0);
 995
 996		tmp &= MC_SEQ_MISC0__MT__MASK;
 997		adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 998	}
 999
1000	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1001	if (r)
1002		return r;
1003
1004	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1005	if (r)
1006		return r;
1007
1008	/* Adjust VM size here.
1009	 * Currently set to 4GB ((1 << 20) 4k pages).
1010	 * Max GPUVM size for cayman and SI is 40 bits.
1011	 */
1012	amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1013
1014	/* Set the internal MC address mask
1015	 * This is the max address of the GPU's
1016	 * internal address space.
1017	 */
1018	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1019
1020	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1021	if (r) {
1022		pr_warn("No suitable DMA available\n");
1023		return r;
1024	}
1025	adev->need_swiotlb = drm_need_swiotlb(40);
1026
1027	r = gmc_v7_0_init_microcode(adev);
1028	if (r) {
1029		DRM_ERROR("Failed to load mc firmware!\n");
1030		return r;
1031	}
1032
1033	r = gmc_v7_0_mc_init(adev);
1034	if (r)
1035		return r;
1036
1037	amdgpu_gmc_get_vbios_allocations(adev);
1038
1039	/* Memory manager */
1040	r = amdgpu_bo_init(adev);
1041	if (r)
1042		return r;
1043
1044	r = gmc_v7_0_gart_init(adev);
1045	if (r)
1046		return r;
1047
1048	/*
1049	 * number of VMs
1050	 * VMID 0 is reserved for System
1051	 * amdgpu graphics/compute will use VMIDs 1-7
1052	 * amdkfd will use VMIDs 8-15
1053	 */
1054	adev->vm_manager.first_kfd_vmid = 8;
1055	amdgpu_vm_manager_init(adev);
1056
1057	/* base offset of vram pages */
1058	if (adev->flags & AMD_IS_APU) {
1059		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1060
1061		tmp <<= 22;
1062		adev->vm_manager.vram_base_offset = tmp;
1063	} else {
1064		adev->vm_manager.vram_base_offset = 0;
1065	}
1066
1067	adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1068					GFP_KERNEL);
1069	if (!adev->gmc.vm_fault_info)
1070		return -ENOMEM;
1071	atomic_set_release(&adev->gmc.vm_fault_info_updated, 0);
1072
1073	return 0;
1074}
1075
1076static int gmc_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
1077{
1078	struct amdgpu_device *adev = ip_block->adev;
1079
1080	amdgpu_gem_force_release(adev);
1081	amdgpu_vm_manager_fini(adev);
1082	kfree(adev->gmc.vm_fault_info);
1083	amdgpu_gart_table_vram_free(adev);
1084	amdgpu_bo_fini(adev);
1085	amdgpu_ucode_release(&adev->gmc.fw);
1086
1087	return 0;
1088}
1089
1090static int gmc_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
1091{
1092	int r;
1093	struct amdgpu_device *adev = ip_block->adev;
1094
1095	gmc_v7_0_init_golden_registers(adev);
1096
1097	gmc_v7_0_mc_program(adev);
1098
1099	if (!(adev->flags & AMD_IS_APU)) {
1100		r = gmc_v7_0_mc_load_microcode(adev);
1101		if (r) {
1102			DRM_ERROR("Failed to load MC firmware!\n");
1103			return r;
1104		}
1105	}
1106
1107	r = gmc_v7_0_gart_enable(adev);
1108	if (r)
1109		return r;
1110
1111	if (amdgpu_emu_mode == 1)
1112		return amdgpu_gmc_vram_checking(adev);
1113
1114	return 0;
1115}
1116
1117static int gmc_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
1118{
1119	struct amdgpu_device *adev = ip_block->adev;
1120
1121	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1122	gmc_v7_0_gart_disable(adev);
1123
1124	return 0;
1125}
1126
1127static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block)
1128{
1129	gmc_v7_0_hw_fini(ip_block);
1130
1131	return 0;
1132}
1133
1134static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block)
1135{
1136	int r;
1137
1138	r = gmc_v7_0_hw_init(ip_block);
1139	if (r)
1140		return r;
1141
1142	amdgpu_vmid_reset_all(ip_block->adev);
1143
1144	return 0;
1145}
1146
1147static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
1148{
1149	struct amdgpu_device *adev = ip_block->adev;
1150	u32 tmp = RREG32(mmSRBM_STATUS);
1151
1152	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1153		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1154		return false;
1155
1156	return true;
1157}
1158
1159static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1160{
1161	unsigned int i;
1162	struct amdgpu_device *adev = ip_block->adev;
1163
1164	for (i = 0; i < adev->usec_timeout; i++) {
1165		if (gmc_v7_0_is_idle(ip_block))
1166			return 0;
1167		udelay(1);
1168	}
1169	return -ETIMEDOUT;
1170
1171}
1172
1173static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
1174{
1175	struct amdgpu_device *adev = ip_block->adev;
1176	u32 srbm_soft_reset = 0;
1177	u32 tmp = RREG32(mmSRBM_STATUS);
1178
1179	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1180		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1181						SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1182
1183	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1184		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1185		if (!(adev->flags & AMD_IS_APU))
1186			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1187							SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1188	}
1189
1190	if (srbm_soft_reset) {
1191		gmc_v7_0_mc_stop(adev);
1192		if (gmc_v7_0_wait_for_idle(ip_block))
1193			dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1194
1195		tmp = RREG32(mmSRBM_SOFT_RESET);
1196		tmp |= srbm_soft_reset;
1197		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1198		WREG32(mmSRBM_SOFT_RESET, tmp);
1199		tmp = RREG32(mmSRBM_SOFT_RESET);
1200
1201		udelay(50);
1202
1203		tmp &= ~srbm_soft_reset;
1204		WREG32(mmSRBM_SOFT_RESET, tmp);
1205		tmp = RREG32(mmSRBM_SOFT_RESET);
1206
1207		/* Wait a little for things to settle down */
1208		udelay(50);
1209
1210		gmc_v7_0_mc_resume(adev);
1211		udelay(50);
1212	}
1213
1214	return 0;
1215}
1216
1217static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1218					     struct amdgpu_irq_src *src,
1219					     unsigned int type,
1220					     enum amdgpu_interrupt_state state)
1221{
1222	u32 tmp;
1223	u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1224		    VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1225		    VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226		    VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1227		    VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1228		    VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1229
1230	switch (state) {
1231	case AMDGPU_IRQ_STATE_DISABLE:
1232		/* system context */
1233		tmp = RREG32(mmVM_CONTEXT0_CNTL);
1234		tmp &= ~bits;
1235		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1236		/* VMs */
1237		tmp = RREG32(mmVM_CONTEXT1_CNTL);
1238		tmp &= ~bits;
1239		WREG32(mmVM_CONTEXT1_CNTL, tmp);
1240		break;
1241	case AMDGPU_IRQ_STATE_ENABLE:
1242		/* system context */
1243		tmp = RREG32(mmVM_CONTEXT0_CNTL);
1244		tmp |= bits;
1245		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1246		/* VMs */
1247		tmp = RREG32(mmVM_CONTEXT1_CNTL);
1248		tmp |= bits;
1249		WREG32(mmVM_CONTEXT1_CNTL, tmp);
1250		break;
1251	default:
1252		break;
1253	}
1254
1255	return 0;
1256}
1257
1258static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1259				      struct amdgpu_irq_src *source,
1260				      struct amdgpu_iv_entry *entry)
1261{
1262	u32 addr, status, mc_client, vmid;
1263
1264	/* Delegate to the soft IRQ handler ring */
1265	if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) {
1266		amdgpu_irq_delegate(adev, entry, 4);
1267		return 1;
1268	}
1269
1270	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1271	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1272	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1273	/* reset addr and status */
1274	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1275
1276	if (!addr && !status)
1277		return 0;
1278
1279	amdgpu_vm_update_fault_cache(adev, entry->pasid,
1280				     ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1281
1282	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1283		gmc_v7_0_set_fault_enable_default(adev, false);
1284
1285	if (printk_ratelimit()) {
1286		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1287			entry->src_id, entry->src_data[0]);
1288		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1289			addr);
1290		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1291			status);
1292		gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1293					 entry->pasid);
1294	}
1295
1296	vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1297			     VMID);
1298	if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1299		&& !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) {
1300		struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1301		u32 protections = REG_GET_FIELD(status,
1302					VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1303					PROTECTIONS);
1304
1305		info->vmid = vmid;
1306		info->mc_id = REG_GET_FIELD(status,
1307					    VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1308					    MEMORY_CLIENT_ID);
1309		info->status = status;
1310		info->page_addr = addr;
1311		info->prot_valid = protections & 0x7 ? true : false;
1312		info->prot_read = protections & 0x8 ? true : false;
1313		info->prot_write = protections & 0x10 ? true : false;
1314		info->prot_exec = protections & 0x20 ? true : false;
1315		atomic_set_release(&adev->gmc.vm_fault_info_updated, 1);
1316	}
1317
1318	return 0;
1319}
1320
1321static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1322					  enum amd_clockgating_state state)
1323{
1324	bool gate = false;
1325	struct amdgpu_device *adev = ip_block->adev;
1326
1327	if (state == AMD_CG_STATE_GATE)
1328		gate = true;
1329
1330	if (!(adev->flags & AMD_IS_APU)) {
1331		gmc_v7_0_enable_mc_mgcg(adev, gate);
1332		gmc_v7_0_enable_mc_ls(adev, gate);
1333	}
1334	gmc_v7_0_enable_bif_mgls(adev, gate);
1335	gmc_v7_0_enable_hdp_mgcg(adev, gate);
1336	gmc_v7_0_enable_hdp_ls(adev, gate);
1337
1338	return 0;
1339}
1340
1341static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1342					  enum amd_powergating_state state)
1343{
1344	return 0;
1345}
1346
1347static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1348	.name = "gmc_v7_0",
1349	.early_init = gmc_v7_0_early_init,
1350	.late_init = gmc_v7_0_late_init,
1351	.sw_init = gmc_v7_0_sw_init,
1352	.sw_fini = gmc_v7_0_sw_fini,
1353	.hw_init = gmc_v7_0_hw_init,
1354	.hw_fini = gmc_v7_0_hw_fini,
1355	.suspend = gmc_v7_0_suspend,
1356	.resume = gmc_v7_0_resume,
1357	.is_idle = gmc_v7_0_is_idle,
1358	.wait_for_idle = gmc_v7_0_wait_for_idle,
1359	.soft_reset = gmc_v7_0_soft_reset,
1360	.set_clockgating_state = gmc_v7_0_set_clockgating_state,
1361	.set_powergating_state = gmc_v7_0_set_powergating_state,
1362};
1363
1364static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1365	.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1366	.flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1367	.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1368	.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1369	.set_prt = gmc_v7_0_set_prt,
1370	.get_vm_pde = gmc_v7_0_get_vm_pde,
1371	.get_vm_pte = gmc_v7_0_get_vm_pte,
1372	.get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1373};
1374
1375static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1376	.set = gmc_v7_0_vm_fault_interrupt_state,
1377	.process = gmc_v7_0_process_interrupt,
1378};
1379
1380static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1381{
1382	adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1383}
1384
1385static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1386{
1387	adev->gmc.vm_fault.num_types = 1;
1388	adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1389}
1390
1391const struct amdgpu_ip_block_version gmc_v7_0_ip_block = {
1392	.type = AMD_IP_BLOCK_TYPE_GMC,
1393	.major = 7,
1394	.minor = 0,
1395	.rev = 0,
1396	.funcs = &gmc_v7_0_ip_funcs,
1397};
1398
1399const struct amdgpu_ip_block_version gmc_v7_4_ip_block = {
1400	.type = AMD_IP_BLOCK_TYPE_GMC,
1401	.major = 7,
1402	.minor = 4,
1403	.rev = 0,
1404	.funcs = &gmc_v7_0_ip_funcs,
1405};