gfx_v7_0.c

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/firmware.h>
  25#include <linux/module.h>
  26
  27#include "amdgpu.h"
  28#include "amdgpu_ih.h"
  29#include "amdgpu_gfx.h"
  30#include "cikd.h"
  31#include "cik.h"
  32#include "cik_structs.h"
  33#include "atom.h"
  34#include "amdgpu_ucode.h"
  35#include "clearstate_ci.h"
  36
  37#include "dce/dce_8_0_d.h"
  38#include "dce/dce_8_0_sh_mask.h"
  39
  40#include "bif/bif_4_1_d.h"
  41#include "bif/bif_4_1_sh_mask.h"
  42
  43#include "gca/gfx_7_0_d.h"
  44#include "gca/gfx_7_2_enum.h"
  45#include "gca/gfx_7_2_sh_mask.h"
  46
  47#include "gmc/gmc_7_0_d.h"
  48#include "gmc/gmc_7_0_sh_mask.h"
  49
  50#include "oss/oss_2_0_d.h"
  51#include "oss/oss_2_0_sh_mask.h"
  52
  53#define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
  54
  55#define GFX7_NUM_GFX_RINGS     1
  56#define GFX7_MEC_HPD_SIZE      2048
  57
  58#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
  59#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
  60
  61static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  62static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  63static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  64
  65MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin");
  66MODULE_FIRMWARE("amdgpu/bonaire_me.bin");
  67MODULE_FIRMWARE("amdgpu/bonaire_ce.bin");
  68MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin");
  69MODULE_FIRMWARE("amdgpu/bonaire_mec.bin");
  70
  71MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin");
  72MODULE_FIRMWARE("amdgpu/hawaii_me.bin");
  73MODULE_FIRMWARE("amdgpu/hawaii_ce.bin");
  74MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin");
  75MODULE_FIRMWARE("amdgpu/hawaii_mec.bin");
  76
  77MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin");
  78MODULE_FIRMWARE("amdgpu/kaveri_me.bin");
  79MODULE_FIRMWARE("amdgpu/kaveri_ce.bin");
  80MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin");
  81MODULE_FIRMWARE("amdgpu/kaveri_mec.bin");
  82MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin");
  83
  84MODULE_FIRMWARE("amdgpu/kabini_pfp.bin");
  85MODULE_FIRMWARE("amdgpu/kabini_me.bin");
  86MODULE_FIRMWARE("amdgpu/kabini_ce.bin");
  87MODULE_FIRMWARE("amdgpu/kabini_rlc.bin");
  88MODULE_FIRMWARE("amdgpu/kabini_mec.bin");
  89
  90MODULE_FIRMWARE("amdgpu/mullins_pfp.bin");
  91MODULE_FIRMWARE("amdgpu/mullins_me.bin");
  92MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
  93MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
  94MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
  95
  96static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = {
  97	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  98	{mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  99	{mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 100	{mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 101	{mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 102	{mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 103	{mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 104	{mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 105	{mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 106	{mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 107	{mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 108	{mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 109	{mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 110	{mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 111	{mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 112	{mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 113};
 114
 115static const u32 spectre_rlc_save_restore_register_list[] = {
 116	(0x0e00 << 16) | (0xc12c >> 2),
 117	0x00000000,
 118	(0x0e00 << 16) | (0xc140 >> 2),
 119	0x00000000,
 120	(0x0e00 << 16) | (0xc150 >> 2),
 121	0x00000000,
 122	(0x0e00 << 16) | (0xc15c >> 2),
 123	0x00000000,
 124	(0x0e00 << 16) | (0xc168 >> 2),
 125	0x00000000,
 126	(0x0e00 << 16) | (0xc170 >> 2),
 127	0x00000000,
 128	(0x0e00 << 16) | (0xc178 >> 2),
 129	0x00000000,
 130	(0x0e00 << 16) | (0xc204 >> 2),
 131	0x00000000,
 132	(0x0e00 << 16) | (0xc2b4 >> 2),
 133	0x00000000,
 134	(0x0e00 << 16) | (0xc2b8 >> 2),
 135	0x00000000,
 136	(0x0e00 << 16) | (0xc2bc >> 2),
 137	0x00000000,
 138	(0x0e00 << 16) | (0xc2c0 >> 2),
 139	0x00000000,
 140	(0x0e00 << 16) | (0x8228 >> 2),
 141	0x00000000,
 142	(0x0e00 << 16) | (0x829c >> 2),
 143	0x00000000,
 144	(0x0e00 << 16) | (0x869c >> 2),
 145	0x00000000,
 146	(0x0600 << 16) | (0x98f4 >> 2),
 147	0x00000000,
 148	(0x0e00 << 16) | (0x98f8 >> 2),
 149	0x00000000,
 150	(0x0e00 << 16) | (0x9900 >> 2),
 151	0x00000000,
 152	(0x0e00 << 16) | (0xc260 >> 2),
 153	0x00000000,
 154	(0x0e00 << 16) | (0x90e8 >> 2),
 155	0x00000000,
 156	(0x0e00 << 16) | (0x3c000 >> 2),
 157	0x00000000,
 158	(0x0e00 << 16) | (0x3c00c >> 2),
 159	0x00000000,
 160	(0x0e00 << 16) | (0x8c1c >> 2),
 161	0x00000000,
 162	(0x0e00 << 16) | (0x9700 >> 2),
 163	0x00000000,
 164	(0x0e00 << 16) | (0xcd20 >> 2),
 165	0x00000000,
 166	(0x4e00 << 16) | (0xcd20 >> 2),
 167	0x00000000,
 168	(0x5e00 << 16) | (0xcd20 >> 2),
 169	0x00000000,
 170	(0x6e00 << 16) | (0xcd20 >> 2),
 171	0x00000000,
 172	(0x7e00 << 16) | (0xcd20 >> 2),
 173	0x00000000,
 174	(0x8e00 << 16) | (0xcd20 >> 2),
 175	0x00000000,
 176	(0x9e00 << 16) | (0xcd20 >> 2),
 177	0x00000000,
 178	(0xae00 << 16) | (0xcd20 >> 2),
 179	0x00000000,
 180	(0xbe00 << 16) | (0xcd20 >> 2),
 181	0x00000000,
 182	(0x0e00 << 16) | (0x89bc >> 2),
 183	0x00000000,
 184	(0x0e00 << 16) | (0x8900 >> 2),
 185	0x00000000,
 186	0x3,
 187	(0x0e00 << 16) | (0xc130 >> 2),
 188	0x00000000,
 189	(0x0e00 << 16) | (0xc134 >> 2),
 190	0x00000000,
 191	(0x0e00 << 16) | (0xc1fc >> 2),
 192	0x00000000,
 193	(0x0e00 << 16) | (0xc208 >> 2),
 194	0x00000000,
 195	(0x0e00 << 16) | (0xc264 >> 2),
 196	0x00000000,
 197	(0x0e00 << 16) | (0xc268 >> 2),
 198	0x00000000,
 199	(0x0e00 << 16) | (0xc26c >> 2),
 200	0x00000000,
 201	(0x0e00 << 16) | (0xc270 >> 2),
 202	0x00000000,
 203	(0x0e00 << 16) | (0xc274 >> 2),
 204	0x00000000,
 205	(0x0e00 << 16) | (0xc278 >> 2),
 206	0x00000000,
 207	(0x0e00 << 16) | (0xc27c >> 2),
 208	0x00000000,
 209	(0x0e00 << 16) | (0xc280 >> 2),
 210	0x00000000,
 211	(0x0e00 << 16) | (0xc284 >> 2),
 212	0x00000000,
 213	(0x0e00 << 16) | (0xc288 >> 2),
 214	0x00000000,
 215	(0x0e00 << 16) | (0xc28c >> 2),
 216	0x00000000,
 217	(0x0e00 << 16) | (0xc290 >> 2),
 218	0x00000000,
 219	(0x0e00 << 16) | (0xc294 >> 2),
 220	0x00000000,
 221	(0x0e00 << 16) | (0xc298 >> 2),
 222	0x00000000,
 223	(0x0e00 << 16) | (0xc29c >> 2),
 224	0x00000000,
 225	(0x0e00 << 16) | (0xc2a0 >> 2),
 226	0x00000000,
 227	(0x0e00 << 16) | (0xc2a4 >> 2),
 228	0x00000000,
 229	(0x0e00 << 16) | (0xc2a8 >> 2),
 230	0x00000000,
 231	(0x0e00 << 16) | (0xc2ac  >> 2),
 232	0x00000000,
 233	(0x0e00 << 16) | (0xc2b0 >> 2),
 234	0x00000000,
 235	(0x0e00 << 16) | (0x301d0 >> 2),
 236	0x00000000,
 237	(0x0e00 << 16) | (0x30238 >> 2),
 238	0x00000000,
 239	(0x0e00 << 16) | (0x30250 >> 2),
 240	0x00000000,
 241	(0x0e00 << 16) | (0x30254 >> 2),
 242	0x00000000,
 243	(0x0e00 << 16) | (0x30258 >> 2),
 244	0x00000000,
 245	(0x0e00 << 16) | (0x3025c >> 2),
 246	0x00000000,
 247	(0x4e00 << 16) | (0xc900 >> 2),
 248	0x00000000,
 249	(0x5e00 << 16) | (0xc900 >> 2),
 250	0x00000000,
 251	(0x6e00 << 16) | (0xc900 >> 2),
 252	0x00000000,
 253	(0x7e00 << 16) | (0xc900 >> 2),
 254	0x00000000,
 255	(0x8e00 << 16) | (0xc900 >> 2),
 256	0x00000000,
 257	(0x9e00 << 16) | (0xc900 >> 2),
 258	0x00000000,
 259	(0xae00 << 16) | (0xc900 >> 2),
 260	0x00000000,
 261	(0xbe00 << 16) | (0xc900 >> 2),
 262	0x00000000,
 263	(0x4e00 << 16) | (0xc904 >> 2),
 264	0x00000000,
 265	(0x5e00 << 16) | (0xc904 >> 2),
 266	0x00000000,
 267	(0x6e00 << 16) | (0xc904 >> 2),
 268	0x00000000,
 269	(0x7e00 << 16) | (0xc904 >> 2),
 270	0x00000000,
 271	(0x8e00 << 16) | (0xc904 >> 2),
 272	0x00000000,
 273	(0x9e00 << 16) | (0xc904 >> 2),
 274	0x00000000,
 275	(0xae00 << 16) | (0xc904 >> 2),
 276	0x00000000,
 277	(0xbe00 << 16) | (0xc904 >> 2),
 278	0x00000000,
 279	(0x4e00 << 16) | (0xc908 >> 2),
 280	0x00000000,
 281	(0x5e00 << 16) | (0xc908 >> 2),
 282	0x00000000,
 283	(0x6e00 << 16) | (0xc908 >> 2),
 284	0x00000000,
 285	(0x7e00 << 16) | (0xc908 >> 2),
 286	0x00000000,
 287	(0x8e00 << 16) | (0xc908 >> 2),
 288	0x00000000,
 289	(0x9e00 << 16) | (0xc908 >> 2),
 290	0x00000000,
 291	(0xae00 << 16) | (0xc908 >> 2),
 292	0x00000000,
 293	(0xbe00 << 16) | (0xc908 >> 2),
 294	0x00000000,
 295	(0x4e00 << 16) | (0xc90c >> 2),
 296	0x00000000,
 297	(0x5e00 << 16) | (0xc90c >> 2),
 298	0x00000000,
 299	(0x6e00 << 16) | (0xc90c >> 2),
 300	0x00000000,
 301	(0x7e00 << 16) | (0xc90c >> 2),
 302	0x00000000,
 303	(0x8e00 << 16) | (0xc90c >> 2),
 304	0x00000000,
 305	(0x9e00 << 16) | (0xc90c >> 2),
 306	0x00000000,
 307	(0xae00 << 16) | (0xc90c >> 2),
 308	0x00000000,
 309	(0xbe00 << 16) | (0xc90c >> 2),
 310	0x00000000,
 311	(0x4e00 << 16) | (0xc910 >> 2),
 312	0x00000000,
 313	(0x5e00 << 16) | (0xc910 >> 2),
 314	0x00000000,
 315	(0x6e00 << 16) | (0xc910 >> 2),
 316	0x00000000,
 317	(0x7e00 << 16) | (0xc910 >> 2),
 318	0x00000000,
 319	(0x8e00 << 16) | (0xc910 >> 2),
 320	0x00000000,
 321	(0x9e00 << 16) | (0xc910 >> 2),
 322	0x00000000,
 323	(0xae00 << 16) | (0xc910 >> 2),
 324	0x00000000,
 325	(0xbe00 << 16) | (0xc910 >> 2),
 326	0x00000000,
 327	(0x0e00 << 16) | (0xc99c >> 2),
 328	0x00000000,
 329	(0x0e00 << 16) | (0x9834 >> 2),
 330	0x00000000,
 331	(0x0000 << 16) | (0x30f00 >> 2),
 332	0x00000000,
 333	(0x0001 << 16) | (0x30f00 >> 2),
 334	0x00000000,
 335	(0x0000 << 16) | (0x30f04 >> 2),
 336	0x00000000,
 337	(0x0001 << 16) | (0x30f04 >> 2),
 338	0x00000000,
 339	(0x0000 << 16) | (0x30f08 >> 2),
 340	0x00000000,
 341	(0x0001 << 16) | (0x30f08 >> 2),
 342	0x00000000,
 343	(0x0000 << 16) | (0x30f0c >> 2),
 344	0x00000000,
 345	(0x0001 << 16) | (0x30f0c >> 2),
 346	0x00000000,
 347	(0x0600 << 16) | (0x9b7c >> 2),
 348	0x00000000,
 349	(0x0e00 << 16) | (0x8a14 >> 2),
 350	0x00000000,
 351	(0x0e00 << 16) | (0x8a18 >> 2),
 352	0x00000000,
 353	(0x0600 << 16) | (0x30a00 >> 2),
 354	0x00000000,
 355	(0x0e00 << 16) | (0x8bf0 >> 2),
 356	0x00000000,
 357	(0x0e00 << 16) | (0x8bcc >> 2),
 358	0x00000000,
 359	(0x0e00 << 16) | (0x8b24 >> 2),
 360	0x00000000,
 361	(0x0e00 << 16) | (0x30a04 >> 2),
 362	0x00000000,
 363	(0x0600 << 16) | (0x30a10 >> 2),
 364	0x00000000,
 365	(0x0600 << 16) | (0x30a14 >> 2),
 366	0x00000000,
 367	(0x0600 << 16) | (0x30a18 >> 2),
 368	0x00000000,
 369	(0x0600 << 16) | (0x30a2c >> 2),
 370	0x00000000,
 371	(0x0e00 << 16) | (0xc700 >> 2),
 372	0x00000000,
 373	(0x0e00 << 16) | (0xc704 >> 2),
 374	0x00000000,
 375	(0x0e00 << 16) | (0xc708 >> 2),
 376	0x00000000,
 377	(0x0e00 << 16) | (0xc768 >> 2),
 378	0x00000000,
 379	(0x0400 << 16) | (0xc770 >> 2),
 380	0x00000000,
 381	(0x0400 << 16) | (0xc774 >> 2),
 382	0x00000000,
 383	(0x0400 << 16) | (0xc778 >> 2),
 384	0x00000000,
 385	(0x0400 << 16) | (0xc77c >> 2),
 386	0x00000000,
 387	(0x0400 << 16) | (0xc780 >> 2),
 388	0x00000000,
 389	(0x0400 << 16) | (0xc784 >> 2),
 390	0x00000000,
 391	(0x0400 << 16) | (0xc788 >> 2),
 392	0x00000000,
 393	(0x0400 << 16) | (0xc78c >> 2),
 394	0x00000000,
 395	(0x0400 << 16) | (0xc798 >> 2),
 396	0x00000000,
 397	(0x0400 << 16) | (0xc79c >> 2),
 398	0x00000000,
 399	(0x0400 << 16) | (0xc7a0 >> 2),
 400	0x00000000,
 401	(0x0400 << 16) | (0xc7a4 >> 2),
 402	0x00000000,
 403	(0x0400 << 16) | (0xc7a8 >> 2),
 404	0x00000000,
 405	(0x0400 << 16) | (0xc7ac >> 2),
 406	0x00000000,
 407	(0x0400 << 16) | (0xc7b0 >> 2),
 408	0x00000000,
 409	(0x0400 << 16) | (0xc7b4 >> 2),
 410	0x00000000,
 411	(0x0e00 << 16) | (0x9100 >> 2),
 412	0x00000000,
 413	(0x0e00 << 16) | (0x3c010 >> 2),
 414	0x00000000,
 415	(0x0e00 << 16) | (0x92a8 >> 2),
 416	0x00000000,
 417	(0x0e00 << 16) | (0x92ac >> 2),
 418	0x00000000,
 419	(0x0e00 << 16) | (0x92b4 >> 2),
 420	0x00000000,
 421	(0x0e00 << 16) | (0x92b8 >> 2),
 422	0x00000000,
 423	(0x0e00 << 16) | (0x92bc >> 2),
 424	0x00000000,
 425	(0x0e00 << 16) | (0x92c0 >> 2),
 426	0x00000000,
 427	(0x0e00 << 16) | (0x92c4 >> 2),
 428	0x00000000,
 429	(0x0e00 << 16) | (0x92c8 >> 2),
 430	0x00000000,
 431	(0x0e00 << 16) | (0x92cc >> 2),
 432	0x00000000,
 433	(0x0e00 << 16) | (0x92d0 >> 2),
 434	0x00000000,
 435	(0x0e00 << 16) | (0x8c00 >> 2),
 436	0x00000000,
 437	(0x0e00 << 16) | (0x8c04 >> 2),
 438	0x00000000,
 439	(0x0e00 << 16) | (0x8c20 >> 2),
 440	0x00000000,
 441	(0x0e00 << 16) | (0x8c38 >> 2),
 442	0x00000000,
 443	(0x0e00 << 16) | (0x8c3c >> 2),
 444	0x00000000,
 445	(0x0e00 << 16) | (0xae00 >> 2),
 446	0x00000000,
 447	(0x0e00 << 16) | (0x9604 >> 2),
 448	0x00000000,
 449	(0x0e00 << 16) | (0xac08 >> 2),
 450	0x00000000,
 451	(0x0e00 << 16) | (0xac0c >> 2),
 452	0x00000000,
 453	(0x0e00 << 16) | (0xac10 >> 2),
 454	0x00000000,
 455	(0x0e00 << 16) | (0xac14 >> 2),
 456	0x00000000,
 457	(0x0e00 << 16) | (0xac58 >> 2),
 458	0x00000000,
 459	(0x0e00 << 16) | (0xac68 >> 2),
 460	0x00000000,
 461	(0x0e00 << 16) | (0xac6c >> 2),
 462	0x00000000,
 463	(0x0e00 << 16) | (0xac70 >> 2),
 464	0x00000000,
 465	(0x0e00 << 16) | (0xac74 >> 2),
 466	0x00000000,
 467	(0x0e00 << 16) | (0xac78 >> 2),
 468	0x00000000,
 469	(0x0e00 << 16) | (0xac7c >> 2),
 470	0x00000000,
 471	(0x0e00 << 16) | (0xac80 >> 2),
 472	0x00000000,
 473	(0x0e00 << 16) | (0xac84 >> 2),
 474	0x00000000,
 475	(0x0e00 << 16) | (0xac88 >> 2),
 476	0x00000000,
 477	(0x0e00 << 16) | (0xac8c >> 2),
 478	0x00000000,
 479	(0x0e00 << 16) | (0x970c >> 2),
 480	0x00000000,
 481	(0x0e00 << 16) | (0x9714 >> 2),
 482	0x00000000,
 483	(0x0e00 << 16) | (0x9718 >> 2),
 484	0x00000000,
 485	(0x0e00 << 16) | (0x971c >> 2),
 486	0x00000000,
 487	(0x0e00 << 16) | (0x31068 >> 2),
 488	0x00000000,
 489	(0x4e00 << 16) | (0x31068 >> 2),
 490	0x00000000,
 491	(0x5e00 << 16) | (0x31068 >> 2),
 492	0x00000000,
 493	(0x6e00 << 16) | (0x31068 >> 2),
 494	0x00000000,
 495	(0x7e00 << 16) | (0x31068 >> 2),
 496	0x00000000,
 497	(0x8e00 << 16) | (0x31068 >> 2),
 498	0x00000000,
 499	(0x9e00 << 16) | (0x31068 >> 2),
 500	0x00000000,
 501	(0xae00 << 16) | (0x31068 >> 2),
 502	0x00000000,
 503	(0xbe00 << 16) | (0x31068 >> 2),
 504	0x00000000,
 505	(0x0e00 << 16) | (0xcd10 >> 2),
 506	0x00000000,
 507	(0x0e00 << 16) | (0xcd14 >> 2),
 508	0x00000000,
 509	(0x0e00 << 16) | (0x88b0 >> 2),
 510	0x00000000,
 511	(0x0e00 << 16) | (0x88b4 >> 2),
 512	0x00000000,
 513	(0x0e00 << 16) | (0x88b8 >> 2),
 514	0x00000000,
 515	(0x0e00 << 16) | (0x88bc >> 2),
 516	0x00000000,
 517	(0x0400 << 16) | (0x89c0 >> 2),
 518	0x00000000,
 519	(0x0e00 << 16) | (0x88c4 >> 2),
 520	0x00000000,
 521	(0x0e00 << 16) | (0x88c8 >> 2),
 522	0x00000000,
 523	(0x0e00 << 16) | (0x88d0 >> 2),
 524	0x00000000,
 525	(0x0e00 << 16) | (0x88d4 >> 2),
 526	0x00000000,
 527	(0x0e00 << 16) | (0x88d8 >> 2),
 528	0x00000000,
 529	(0x0e00 << 16) | (0x8980 >> 2),
 530	0x00000000,
 531	(0x0e00 << 16) | (0x30938 >> 2),
 532	0x00000000,
 533	(0x0e00 << 16) | (0x3093c >> 2),
 534	0x00000000,
 535	(0x0e00 << 16) | (0x30940 >> 2),
 536	0x00000000,
 537	(0x0e00 << 16) | (0x89a0 >> 2),
 538	0x00000000,
 539	(0x0e00 << 16) | (0x30900 >> 2),
 540	0x00000000,
 541	(0x0e00 << 16) | (0x30904 >> 2),
 542	0x00000000,
 543	(0x0e00 << 16) | (0x89b4 >> 2),
 544	0x00000000,
 545	(0x0e00 << 16) | (0x3c210 >> 2),
 546	0x00000000,
 547	(0x0e00 << 16) | (0x3c214 >> 2),
 548	0x00000000,
 549	(0x0e00 << 16) | (0x3c218 >> 2),
 550	0x00000000,
 551	(0x0e00 << 16) | (0x8904 >> 2),
 552	0x00000000,
 553	0x5,
 554	(0x0e00 << 16) | (0x8c28 >> 2),
 555	(0x0e00 << 16) | (0x8c2c >> 2),
 556	(0x0e00 << 16) | (0x8c30 >> 2),
 557	(0x0e00 << 16) | (0x8c34 >> 2),
 558	(0x0e00 << 16) | (0x9600 >> 2),
 559};
 560
 561static const u32 kalindi_rlc_save_restore_register_list[] = {
 562	(0x0e00 << 16) | (0xc12c >> 2),
 563	0x00000000,
 564	(0x0e00 << 16) | (0xc140 >> 2),
 565	0x00000000,
 566	(0x0e00 << 16) | (0xc150 >> 2),
 567	0x00000000,
 568	(0x0e00 << 16) | (0xc15c >> 2),
 569	0x00000000,
 570	(0x0e00 << 16) | (0xc168 >> 2),
 571	0x00000000,
 572	(0x0e00 << 16) | (0xc170 >> 2),
 573	0x00000000,
 574	(0x0e00 << 16) | (0xc204 >> 2),
 575	0x00000000,
 576	(0x0e00 << 16) | (0xc2b4 >> 2),
 577	0x00000000,
 578	(0x0e00 << 16) | (0xc2b8 >> 2),
 579	0x00000000,
 580	(0x0e00 << 16) | (0xc2bc >> 2),
 581	0x00000000,
 582	(0x0e00 << 16) | (0xc2c0 >> 2),
 583	0x00000000,
 584	(0x0e00 << 16) | (0x8228 >> 2),
 585	0x00000000,
 586	(0x0e00 << 16) | (0x829c >> 2),
 587	0x00000000,
 588	(0x0e00 << 16) | (0x869c >> 2),
 589	0x00000000,
 590	(0x0600 << 16) | (0x98f4 >> 2),
 591	0x00000000,
 592	(0x0e00 << 16) | (0x98f8 >> 2),
 593	0x00000000,
 594	(0x0e00 << 16) | (0x9900 >> 2),
 595	0x00000000,
 596	(0x0e00 << 16) | (0xc260 >> 2),
 597	0x00000000,
 598	(0x0e00 << 16) | (0x90e8 >> 2),
 599	0x00000000,
 600	(0x0e00 << 16) | (0x3c000 >> 2),
 601	0x00000000,
 602	(0x0e00 << 16) | (0x3c00c >> 2),
 603	0x00000000,
 604	(0x0e00 << 16) | (0x8c1c >> 2),
 605	0x00000000,
 606	(0x0e00 << 16) | (0x9700 >> 2),
 607	0x00000000,
 608	(0x0e00 << 16) | (0xcd20 >> 2),
 609	0x00000000,
 610	(0x4e00 << 16) | (0xcd20 >> 2),
 611	0x00000000,
 612	(0x5e00 << 16) | (0xcd20 >> 2),
 613	0x00000000,
 614	(0x6e00 << 16) | (0xcd20 >> 2),
 615	0x00000000,
 616	(0x7e00 << 16) | (0xcd20 >> 2),
 617	0x00000000,
 618	(0x0e00 << 16) | (0x89bc >> 2),
 619	0x00000000,
 620	(0x0e00 << 16) | (0x8900 >> 2),
 621	0x00000000,
 622	0x3,
 623	(0x0e00 << 16) | (0xc130 >> 2),
 624	0x00000000,
 625	(0x0e00 << 16) | (0xc134 >> 2),
 626	0x00000000,
 627	(0x0e00 << 16) | (0xc1fc >> 2),
 628	0x00000000,
 629	(0x0e00 << 16) | (0xc208 >> 2),
 630	0x00000000,
 631	(0x0e00 << 16) | (0xc264 >> 2),
 632	0x00000000,
 633	(0x0e00 << 16) | (0xc268 >> 2),
 634	0x00000000,
 635	(0x0e00 << 16) | (0xc26c >> 2),
 636	0x00000000,
 637	(0x0e00 << 16) | (0xc270 >> 2),
 638	0x00000000,
 639	(0x0e00 << 16) | (0xc274 >> 2),
 640	0x00000000,
 641	(0x0e00 << 16) | (0xc28c >> 2),
 642	0x00000000,
 643	(0x0e00 << 16) | (0xc290 >> 2),
 644	0x00000000,
 645	(0x0e00 << 16) | (0xc294 >> 2),
 646	0x00000000,
 647	(0x0e00 << 16) | (0xc298 >> 2),
 648	0x00000000,
 649	(0x0e00 << 16) | (0xc2a0 >> 2),
 650	0x00000000,
 651	(0x0e00 << 16) | (0xc2a4 >> 2),
 652	0x00000000,
 653	(0x0e00 << 16) | (0xc2a8 >> 2),
 654	0x00000000,
 655	(0x0e00 << 16) | (0xc2ac >> 2),
 656	0x00000000,
 657	(0x0e00 << 16) | (0x301d0 >> 2),
 658	0x00000000,
 659	(0x0e00 << 16) | (0x30238 >> 2),
 660	0x00000000,
 661	(0x0e00 << 16) | (0x30250 >> 2),
 662	0x00000000,
 663	(0x0e00 << 16) | (0x30254 >> 2),
 664	0x00000000,
 665	(0x0e00 << 16) | (0x30258 >> 2),
 666	0x00000000,
 667	(0x0e00 << 16) | (0x3025c >> 2),
 668	0x00000000,
 669	(0x4e00 << 16) | (0xc900 >> 2),
 670	0x00000000,
 671	(0x5e00 << 16) | (0xc900 >> 2),
 672	0x00000000,
 673	(0x6e00 << 16) | (0xc900 >> 2),
 674	0x00000000,
 675	(0x7e00 << 16) | (0xc900 >> 2),
 676	0x00000000,
 677	(0x4e00 << 16) | (0xc904 >> 2),
 678	0x00000000,
 679	(0x5e00 << 16) | (0xc904 >> 2),
 680	0x00000000,
 681	(0x6e00 << 16) | (0xc904 >> 2),
 682	0x00000000,
 683	(0x7e00 << 16) | (0xc904 >> 2),
 684	0x00000000,
 685	(0x4e00 << 16) | (0xc908 >> 2),
 686	0x00000000,
 687	(0x5e00 << 16) | (0xc908 >> 2),
 688	0x00000000,
 689	(0x6e00 << 16) | (0xc908 >> 2),
 690	0x00000000,
 691	(0x7e00 << 16) | (0xc908 >> 2),
 692	0x00000000,
 693	(0x4e00 << 16) | (0xc90c >> 2),
 694	0x00000000,
 695	(0x5e00 << 16) | (0xc90c >> 2),
 696	0x00000000,
 697	(0x6e00 << 16) | (0xc90c >> 2),
 698	0x00000000,
 699	(0x7e00 << 16) | (0xc90c >> 2),
 700	0x00000000,
 701	(0x4e00 << 16) | (0xc910 >> 2),
 702	0x00000000,
 703	(0x5e00 << 16) | (0xc910 >> 2),
 704	0x00000000,
 705	(0x6e00 << 16) | (0xc910 >> 2),
 706	0x00000000,
 707	(0x7e00 << 16) | (0xc910 >> 2),
 708	0x00000000,
 709	(0x0e00 << 16) | (0xc99c >> 2),
 710	0x00000000,
 711	(0x0e00 << 16) | (0x9834 >> 2),
 712	0x00000000,
 713	(0x0000 << 16) | (0x30f00 >> 2),
 714	0x00000000,
 715	(0x0000 << 16) | (0x30f04 >> 2),
 716	0x00000000,
 717	(0x0000 << 16) | (0x30f08 >> 2),
 718	0x00000000,
 719	(0x0000 << 16) | (0x30f0c >> 2),
 720	0x00000000,
 721	(0x0600 << 16) | (0x9b7c >> 2),
 722	0x00000000,
 723	(0x0e00 << 16) | (0x8a14 >> 2),
 724	0x00000000,
 725	(0x0e00 << 16) | (0x8a18 >> 2),
 726	0x00000000,
 727	(0x0600 << 16) | (0x30a00 >> 2),
 728	0x00000000,
 729	(0x0e00 << 16) | (0x8bf0 >> 2),
 730	0x00000000,
 731	(0x0e00 << 16) | (0x8bcc >> 2),
 732	0x00000000,
 733	(0x0e00 << 16) | (0x8b24 >> 2),
 734	0x00000000,
 735	(0x0e00 << 16) | (0x30a04 >> 2),
 736	0x00000000,
 737	(0x0600 << 16) | (0x30a10 >> 2),
 738	0x00000000,
 739	(0x0600 << 16) | (0x30a14 >> 2),
 740	0x00000000,
 741	(0x0600 << 16) | (0x30a18 >> 2),
 742	0x00000000,
 743	(0x0600 << 16) | (0x30a2c >> 2),
 744	0x00000000,
 745	(0x0e00 << 16) | (0xc700 >> 2),
 746	0x00000000,
 747	(0x0e00 << 16) | (0xc704 >> 2),
 748	0x00000000,
 749	(0x0e00 << 16) | (0xc708 >> 2),
 750	0x00000000,
 751	(0x0e00 << 16) | (0xc768 >> 2),
 752	0x00000000,
 753	(0x0400 << 16) | (0xc770 >> 2),
 754	0x00000000,
 755	(0x0400 << 16) | (0xc774 >> 2),
 756	0x00000000,
 757	(0x0400 << 16) | (0xc798 >> 2),
 758	0x00000000,
 759	(0x0400 << 16) | (0xc79c >> 2),
 760	0x00000000,
 761	(0x0e00 << 16) | (0x9100 >> 2),
 762	0x00000000,
 763	(0x0e00 << 16) | (0x3c010 >> 2),
 764	0x00000000,
 765	(0x0e00 << 16) | (0x8c00 >> 2),
 766	0x00000000,
 767	(0x0e00 << 16) | (0x8c04 >> 2),
 768	0x00000000,
 769	(0x0e00 << 16) | (0x8c20 >> 2),
 770	0x00000000,
 771	(0x0e00 << 16) | (0x8c38 >> 2),
 772	0x00000000,
 773	(0x0e00 << 16) | (0x8c3c >> 2),
 774	0x00000000,
 775	(0x0e00 << 16) | (0xae00 >> 2),
 776	0x00000000,
 777	(0x0e00 << 16) | (0x9604 >> 2),
 778	0x00000000,
 779	(0x0e00 << 16) | (0xac08 >> 2),
 780	0x00000000,
 781	(0x0e00 << 16) | (0xac0c >> 2),
 782	0x00000000,
 783	(0x0e00 << 16) | (0xac10 >> 2),
 784	0x00000000,
 785	(0x0e00 << 16) | (0xac14 >> 2),
 786	0x00000000,
 787	(0x0e00 << 16) | (0xac58 >> 2),
 788	0x00000000,
 789	(0x0e00 << 16) | (0xac68 >> 2),
 790	0x00000000,
 791	(0x0e00 << 16) | (0xac6c >> 2),
 792	0x00000000,
 793	(0x0e00 << 16) | (0xac70 >> 2),
 794	0x00000000,
 795	(0x0e00 << 16) | (0xac74 >> 2),
 796	0x00000000,
 797	(0x0e00 << 16) | (0xac78 >> 2),
 798	0x00000000,
 799	(0x0e00 << 16) | (0xac7c >> 2),
 800	0x00000000,
 801	(0x0e00 << 16) | (0xac80 >> 2),
 802	0x00000000,
 803	(0x0e00 << 16) | (0xac84 >> 2),
 804	0x00000000,
 805	(0x0e00 << 16) | (0xac88 >> 2),
 806	0x00000000,
 807	(0x0e00 << 16) | (0xac8c >> 2),
 808	0x00000000,
 809	(0x0e00 << 16) | (0x970c >> 2),
 810	0x00000000,
 811	(0x0e00 << 16) | (0x9714 >> 2),
 812	0x00000000,
 813	(0x0e00 << 16) | (0x9718 >> 2),
 814	0x00000000,
 815	(0x0e00 << 16) | (0x971c >> 2),
 816	0x00000000,
 817	(0x0e00 << 16) | (0x31068 >> 2),
 818	0x00000000,
 819	(0x4e00 << 16) | (0x31068 >> 2),
 820	0x00000000,
 821	(0x5e00 << 16) | (0x31068 >> 2),
 822	0x00000000,
 823	(0x6e00 << 16) | (0x31068 >> 2),
 824	0x00000000,
 825	(0x7e00 << 16) | (0x31068 >> 2),
 826	0x00000000,
 827	(0x0e00 << 16) | (0xcd10 >> 2),
 828	0x00000000,
 829	(0x0e00 << 16) | (0xcd14 >> 2),
 830	0x00000000,
 831	(0x0e00 << 16) | (0x88b0 >> 2),
 832	0x00000000,
 833	(0x0e00 << 16) | (0x88b4 >> 2),
 834	0x00000000,
 835	(0x0e00 << 16) | (0x88b8 >> 2),
 836	0x00000000,
 837	(0x0e00 << 16) | (0x88bc >> 2),
 838	0x00000000,
 839	(0x0400 << 16) | (0x89c0 >> 2),
 840	0x00000000,
 841	(0x0e00 << 16) | (0x88c4 >> 2),
 842	0x00000000,
 843	(0x0e00 << 16) | (0x88c8 >> 2),
 844	0x00000000,
 845	(0x0e00 << 16) | (0x88d0 >> 2),
 846	0x00000000,
 847	(0x0e00 << 16) | (0x88d4 >> 2),
 848	0x00000000,
 849	(0x0e00 << 16) | (0x88d8 >> 2),
 850	0x00000000,
 851	(0x0e00 << 16) | (0x8980 >> 2),
 852	0x00000000,
 853	(0x0e00 << 16) | (0x30938 >> 2),
 854	0x00000000,
 855	(0x0e00 << 16) | (0x3093c >> 2),
 856	0x00000000,
 857	(0x0e00 << 16) | (0x30940 >> 2),
 858	0x00000000,
 859	(0x0e00 << 16) | (0x89a0 >> 2),
 860	0x00000000,
 861	(0x0e00 << 16) | (0x30900 >> 2),
 862	0x00000000,
 863	(0x0e00 << 16) | (0x30904 >> 2),
 864	0x00000000,
 865	(0x0e00 << 16) | (0x89b4 >> 2),
 866	0x00000000,
 867	(0x0e00 << 16) | (0x3e1fc >> 2),
 868	0x00000000,
 869	(0x0e00 << 16) | (0x3c210 >> 2),
 870	0x00000000,
 871	(0x0e00 << 16) | (0x3c214 >> 2),
 872	0x00000000,
 873	(0x0e00 << 16) | (0x3c218 >> 2),
 874	0x00000000,
 875	(0x0e00 << 16) | (0x8904 >> 2),
 876	0x00000000,
 877	0x5,
 878	(0x0e00 << 16) | (0x8c28 >> 2),
 879	(0x0e00 << 16) | (0x8c2c >> 2),
 880	(0x0e00 << 16) | (0x8c30 >> 2),
 881	(0x0e00 << 16) | (0x8c34 >> 2),
 882	(0x0e00 << 16) | (0x9600 >> 2),
 883};
 884
 885static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 886static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer);
 887static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 888static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 889
 890static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 891{
 892	amdgpu_ucode_release(&adev->gfx.pfp_fw);
 893	amdgpu_ucode_release(&adev->gfx.me_fw);
 894	amdgpu_ucode_release(&adev->gfx.ce_fw);
 895	amdgpu_ucode_release(&adev->gfx.mec_fw);
 896	amdgpu_ucode_release(&adev->gfx.mec2_fw);
 897	amdgpu_ucode_release(&adev->gfx.rlc_fw);
 898}
 899
 900/*
 901 * Core functions
 902 */
 903/**
 904 * gfx_v7_0_init_microcode - load ucode images from disk
 905 *
 906 * @adev: amdgpu_device pointer
 907 *
 908 * Use the firmware interface to load the ucode images into
 909 * the driver (not loaded into hw).
 910 * Returns 0 on success, error on failure.
 911 */
 912static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 913{
 914	const char *chip_name;
 915	int err;
 916
 917	DRM_DEBUG("\n");
 918
 919	switch (adev->asic_type) {
 920	case CHIP_BONAIRE:
 921		chip_name = "bonaire";
 922		break;
 923	case CHIP_HAWAII:
 924		chip_name = "hawaii";
 925		break;
 926	case CHIP_KAVERI:
 927		chip_name = "kaveri";
 928		break;
 929	case CHIP_KABINI:
 930		chip_name = "kabini";
 931		break;
 932	case CHIP_MULLINS:
 933		chip_name = "mullins";
 934		break;
 935	default:
 936		BUG();
 937	}
 938
 939	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
 940				   AMDGPU_UCODE_REQUIRED,
 941				   "amdgpu/%s_pfp.bin", chip_name);
 942	if (err)
 943		goto out;
 944
 945	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
 946				   AMDGPU_UCODE_REQUIRED,
 947				   "amdgpu/%s_me.bin", chip_name);
 948	if (err)
 949		goto out;
 950
 951	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
 952				   AMDGPU_UCODE_REQUIRED,
 953				   "amdgpu/%s_ce.bin", chip_name);
 954	if (err)
 955		goto out;
 956
 957	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
 958				   AMDGPU_UCODE_REQUIRED,
 959				   "amdgpu/%s_mec.bin", chip_name);
 960	if (err)
 961		goto out;
 962
 963	if (adev->asic_type == CHIP_KAVERI) {
 964		err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
 965					   AMDGPU_UCODE_REQUIRED,
 966					   "amdgpu/%s_mec2.bin", chip_name);
 967		if (err)
 968			goto out;
 969	}
 970
 971	err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
 972				   AMDGPU_UCODE_REQUIRED,
 973				   "amdgpu/%s_rlc.bin", chip_name);
 974out:
 975	if (err) {
 976		pr_err("gfx7: Failed to load firmware %s gfx firmware\n", chip_name);
 977		gfx_v7_0_free_microcode(adev);
 978	}
 979	return err;
 980}
 981
 982/**
 983 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 984 *
 985 * @adev: amdgpu_device pointer
 986 *
 987 * Starting with SI, the tiling setup is done globally in a
 988 * set of 32 tiling modes.  Rather than selecting each set of
 989 * parameters per surface as on older asics, we just select
 990 * which index in the tiling table we want to use, and the
 991 * surface uses those parameters (CIK).
 992 */
 993static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
 994{
 995	const u32 num_tile_mode_states =
 996			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 997	const u32 num_secondary_tile_mode_states =
 998			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 999	u32 reg_offset, split_equal_to_row_size;
1000	uint32_t *tile, *macrotile;
1001
1002	tile = adev->gfx.config.tile_mode_array;
1003	macrotile = adev->gfx.config.macrotile_mode_array;
1004
1005	switch (adev->gfx.config.mem_row_size_in_kb) {
1006	case 1:
1007		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1008		break;
1009	case 2:
1010	default:
1011		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1012		break;
1013	case 4:
1014		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1015		break;
1016	}
1017
1018	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1019		tile[reg_offset] = 0;
1020	for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1021		macrotile[reg_offset] = 0;
1022
1023	switch (adev->asic_type) {
1024	case CHIP_BONAIRE:
1025		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1027			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1028			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1029		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1030			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1031			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1032			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1033		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1035			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1036			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1037		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1040			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1044			   TILE_SPLIT(split_equal_to_row_size));
1045		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1046			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1048		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1049			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1050			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1051			   TILE_SPLIT(split_equal_to_row_size));
1052		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1053		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1054			   PIPE_CONFIG(ADDR_SURF_P4_16x16));
1055		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1056			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1058		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1059			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1060			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1061			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1062		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1063			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1064			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1065			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1066		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1067		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1070		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1073			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1075			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1077			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1078		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1079			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1080			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1081			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1082		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1083		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1084			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1086			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1087		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1088			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1089			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1090		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1091			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1094		tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1095			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1096			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1097			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1098		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1099			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1102		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1103		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1104			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1105			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1106			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1107		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1108			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1109			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1110			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1111		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1112			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1116			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1118		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1119			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1121			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1122		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1123			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1125			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1126		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1127
1128		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1129				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1130				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1131				NUM_BANKS(ADDR_SURF_16_BANK));
1132		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1133				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1134				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1135				NUM_BANKS(ADDR_SURF_16_BANK));
1136		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1137				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1138				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1139				NUM_BANKS(ADDR_SURF_16_BANK));
1140		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1142				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1143				NUM_BANKS(ADDR_SURF_16_BANK));
1144		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1146				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1147				NUM_BANKS(ADDR_SURF_16_BANK));
1148		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151				NUM_BANKS(ADDR_SURF_8_BANK));
1152		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1155				NUM_BANKS(ADDR_SURF_4_BANK));
1156		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1157				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1158				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159				NUM_BANKS(ADDR_SURF_16_BANK));
1160		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1161				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1162				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163				NUM_BANKS(ADDR_SURF_16_BANK));
1164		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1166				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1167				NUM_BANKS(ADDR_SURF_16_BANK));
1168		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1170				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171				NUM_BANKS(ADDR_SURF_16_BANK));
1172		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175				NUM_BANKS(ADDR_SURF_16_BANK));
1176		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179				NUM_BANKS(ADDR_SURF_8_BANK));
1180		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183				NUM_BANKS(ADDR_SURF_4_BANK));
1184
1185		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1186			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1187		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1188			if (reg_offset != 7)
1189				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1190		break;
1191	case CHIP_HAWAII:
1192		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1194			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1195			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1196		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1197			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1198			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1199			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1200		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1201			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1202			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1203			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1204		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1207			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1211			   TILE_SPLIT(split_equal_to_row_size));
1212		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1213			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1215			   TILE_SPLIT(split_equal_to_row_size));
1216		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1217			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1219			   TILE_SPLIT(split_equal_to_row_size));
1220		tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1221			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1222			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223			   TILE_SPLIT(split_equal_to_row_size));
1224		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1225			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1226		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1227			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1228			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1229		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1230			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1231			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1232			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1233		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1234			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1235			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1236			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1237		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1238			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1239			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1240			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1241		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1242			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1244		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1247			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1248		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1249			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1250			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1251			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1252		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1253			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1254			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1255			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1256		tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1257			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1258			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1260		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1261			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1264		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1265			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1267		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1268			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1269			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1270			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1271		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1272			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1274			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1275		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1276			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1277			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1278			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1279		tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1280			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1281			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1284			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1286			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1288			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1292			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1293			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1296			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1298		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1299			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1300			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1301			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1302		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1303			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1304			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1305			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1306		tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1307			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1308			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1309			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1310
1311		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1312				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1313				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1314				NUM_BANKS(ADDR_SURF_16_BANK));
1315		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1316				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1317				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1318				NUM_BANKS(ADDR_SURF_16_BANK));
1319		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1320				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1321				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1322				NUM_BANKS(ADDR_SURF_16_BANK));
1323		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1325				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1326				NUM_BANKS(ADDR_SURF_16_BANK));
1327		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1329				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1330				NUM_BANKS(ADDR_SURF_8_BANK));
1331		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334				NUM_BANKS(ADDR_SURF_4_BANK));
1335		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338				NUM_BANKS(ADDR_SURF_4_BANK));
1339		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342				NUM_BANKS(ADDR_SURF_16_BANK));
1343		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346				NUM_BANKS(ADDR_SURF_16_BANK));
1347		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350				NUM_BANKS(ADDR_SURF_16_BANK));
1351		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354				NUM_BANKS(ADDR_SURF_8_BANK));
1355		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358				NUM_BANKS(ADDR_SURF_16_BANK));
1359		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1362				NUM_BANKS(ADDR_SURF_8_BANK));
1363		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366				NUM_BANKS(ADDR_SURF_4_BANK));
1367
1368		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1369			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1370		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1371			if (reg_offset != 7)
1372				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1373		break;
1374	case CHIP_KABINI:
1375	case CHIP_KAVERI:
1376	case CHIP_MULLINS:
1377	default:
1378		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1379			   PIPE_CONFIG(ADDR_SURF_P2) |
1380			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1381			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1382		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1383			   PIPE_CONFIG(ADDR_SURF_P2) |
1384			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1385			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1386		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1387			   PIPE_CONFIG(ADDR_SURF_P2) |
1388			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1389			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1390		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391			   PIPE_CONFIG(ADDR_SURF_P2) |
1392			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1393			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395			   PIPE_CONFIG(ADDR_SURF_P2) |
1396			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1397			   TILE_SPLIT(split_equal_to_row_size));
1398		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1399			   PIPE_CONFIG(ADDR_SURF_P2) |
1400			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1401		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1402			   PIPE_CONFIG(ADDR_SURF_P2) |
1403			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1404			   TILE_SPLIT(split_equal_to_row_size));
1405		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1406		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1407			   PIPE_CONFIG(ADDR_SURF_P2));
1408		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1409			   PIPE_CONFIG(ADDR_SURF_P2) |
1410			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1411		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412			    PIPE_CONFIG(ADDR_SURF_P2) |
1413			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1414			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1415		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1416			    PIPE_CONFIG(ADDR_SURF_P2) |
1417			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1418			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1419		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1420		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421			    PIPE_CONFIG(ADDR_SURF_P2) |
1422			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1423		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424			    PIPE_CONFIG(ADDR_SURF_P2) |
1425			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1426			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1428			    PIPE_CONFIG(ADDR_SURF_P2) |
1429			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1430			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1431		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1432			    PIPE_CONFIG(ADDR_SURF_P2) |
1433			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1434			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1435		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1436		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1437			    PIPE_CONFIG(ADDR_SURF_P2) |
1438			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1439			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1440		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1441			    PIPE_CONFIG(ADDR_SURF_P2) |
1442			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1443		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1444			    PIPE_CONFIG(ADDR_SURF_P2) |
1445			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1446			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1447		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1448			    PIPE_CONFIG(ADDR_SURF_P2) |
1449			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1450			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1451		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1452			    PIPE_CONFIG(ADDR_SURF_P2) |
1453			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1454			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1455		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1456		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1457			    PIPE_CONFIG(ADDR_SURF_P2) |
1458			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1459			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1460		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1461			    PIPE_CONFIG(ADDR_SURF_P2) |
1462			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1463			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1464		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1465			    PIPE_CONFIG(ADDR_SURF_P2) |
1466			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1467			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1469			    PIPE_CONFIG(ADDR_SURF_P2) |
1470			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1471		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1472			    PIPE_CONFIG(ADDR_SURF_P2) |
1473			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1474			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1475		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1476			    PIPE_CONFIG(ADDR_SURF_P2) |
1477			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1478			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1479		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1480
1481		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1482				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1483				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1484				NUM_BANKS(ADDR_SURF_8_BANK));
1485		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1486				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1487				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1488				NUM_BANKS(ADDR_SURF_8_BANK));
1489		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1490				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1491				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1492				NUM_BANKS(ADDR_SURF_8_BANK));
1493		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1495				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1496				NUM_BANKS(ADDR_SURF_8_BANK));
1497		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1499				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1500				NUM_BANKS(ADDR_SURF_8_BANK));
1501		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1503				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504				NUM_BANKS(ADDR_SURF_8_BANK));
1505		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508				NUM_BANKS(ADDR_SURF_8_BANK));
1509		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1510				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1511				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512				NUM_BANKS(ADDR_SURF_16_BANK));
1513		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1514				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1515				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516				NUM_BANKS(ADDR_SURF_16_BANK));
1517		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1518				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1519				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1520				NUM_BANKS(ADDR_SURF_16_BANK));
1521		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1522				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1523				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524				NUM_BANKS(ADDR_SURF_16_BANK));
1525		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1527				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528				NUM_BANKS(ADDR_SURF_16_BANK));
1529		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532				NUM_BANKS(ADDR_SURF_16_BANK));
1533		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536				NUM_BANKS(ADDR_SURF_8_BANK));
1537
1538		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1539			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1540		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1541			if (reg_offset != 7)
1542				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1543		break;
1544	}
1545}
1546
1547/**
1548 * gfx_v7_0_select_se_sh - select which SE, SH to address
1549 *
1550 * @adev: amdgpu_device pointer
1551 * @se_num: shader engine to address
1552 * @sh_num: sh block to address
1553 * @instance: Certain registers are instanced per SE or SH.
1554 *            0xffffffff means broadcast to all SEs or SHs (CIK).
1555 * @xcc_id: xcc accelerated compute core id
1556 * Select which SE, SH combinations to address.
1557 */
1558static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1559				  u32 se_num, u32 sh_num, u32 instance,
1560				  int xcc_id)
1561{
1562	u32 data;
1563
1564	if (instance == 0xffffffff)
1565		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1566	else
1567		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1568
1569	if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1570		data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1571			GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1572	else if (se_num == 0xffffffff)
1573		data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1574			(sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1575	else if (sh_num == 0xffffffff)
1576		data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1577			(se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1578	else
1579		data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1580			(se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1581	WREG32(mmGRBM_GFX_INDEX, data);
1582}
1583
1584/**
1585 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1586 *
1587 * @adev: amdgpu_device pointer
1588 *
1589 * Calculates the bitmask of enabled RBs (CIK).
1590 * Returns the enabled RB bitmask.
1591 */
1592static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1593{
1594	u32 data, mask;
1595
1596	data = RREG32(mmCC_RB_BACKEND_DISABLE);
1597	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1598
1599	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1600	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1601
1602	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1603					 adev->gfx.config.max_sh_per_se);
1604
1605	return (~data) & mask;
1606}
1607
1608static void
1609gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1610{
1611	switch (adev->asic_type) {
1612	case CHIP_BONAIRE:
1613		*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1614			  SE_XSEL(1) | SE_YSEL(1);
1615		*rconf1 |= 0x0;
1616		break;
1617	case CHIP_HAWAII:
1618		*rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1619			  RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1620			  PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1621			  SE_YSEL(3);
1622		*rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1623			   SE_PAIR_YSEL(2);
1624		break;
1625	case CHIP_KAVERI:
1626		*rconf |= RB_MAP_PKR0(2);
1627		*rconf1 |= 0x0;
1628		break;
1629	case CHIP_KABINI:
1630	case CHIP_MULLINS:
1631		*rconf |= 0x0;
1632		*rconf1 |= 0x0;
1633		break;
1634	default:
1635		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1636		break;
1637	}
1638}
1639
1640static void
1641gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1642					u32 raster_config, u32 raster_config_1,
1643					unsigned rb_mask, unsigned num_rb)
1644{
1645	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1646	unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1647	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1648	unsigned rb_per_se = num_rb / num_se;
1649	unsigned se_mask[4];
1650	unsigned se;
1651
1652	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1653	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1654	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1655	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1656
1657	WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1658	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1659	WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1660
1661	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1662			     (!se_mask[2] && !se_mask[3]))) {
1663		raster_config_1 &= ~SE_PAIR_MAP_MASK;
1664
1665		if (!se_mask[0] && !se_mask[1]) {
1666			raster_config_1 |=
1667				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1668		} else {
1669			raster_config_1 |=
1670				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1671		}
1672	}
1673
1674	for (se = 0; se < num_se; se++) {
1675		unsigned raster_config_se = raster_config;
1676		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1677		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1678		int idx = (se / 2) * 2;
1679
1680		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1681			raster_config_se &= ~SE_MAP_MASK;
1682
1683			if (!se_mask[idx]) {
1684				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1685			} else {
1686				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1687			}
1688		}
1689
1690		pkr0_mask &= rb_mask;
1691		pkr1_mask &= rb_mask;
1692		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1693			raster_config_se &= ~PKR_MAP_MASK;
1694
1695			if (!pkr0_mask) {
1696				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1697			} else {
1698				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1699			}
1700		}
1701
1702		if (rb_per_se >= 2) {
1703			unsigned rb0_mask = 1 << (se * rb_per_se);
1704			unsigned rb1_mask = rb0_mask << 1;
1705
1706			rb0_mask &= rb_mask;
1707			rb1_mask &= rb_mask;
1708			if (!rb0_mask || !rb1_mask) {
1709				raster_config_se &= ~RB_MAP_PKR0_MASK;
1710
1711				if (!rb0_mask) {
1712					raster_config_se |=
1713						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1714				} else {
1715					raster_config_se |=
1716						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1717				}
1718			}
1719
1720			if (rb_per_se > 2) {
1721				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1722				rb1_mask = rb0_mask << 1;
1723				rb0_mask &= rb_mask;
1724				rb1_mask &= rb_mask;
1725				if (!rb0_mask || !rb1_mask) {
1726					raster_config_se &= ~RB_MAP_PKR1_MASK;
1727
1728					if (!rb0_mask) {
1729						raster_config_se |=
1730							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1731					} else {
1732						raster_config_se |=
1733							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1734					}
1735				}
1736			}
1737		}
1738
1739		/* GRBM_GFX_INDEX has a different offset on CI+ */
1740		gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
1741		WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1742		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1743	}
1744
1745	/* GRBM_GFX_INDEX has a different offset on CI+ */
1746	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1747}
1748
1749/**
1750 * gfx_v7_0_setup_rb - setup the RBs on the asic
1751 *
1752 * @adev: amdgpu_device pointer
1753 *
1754 * Configures per-SE/SH RB registers (CIK).
1755 */
1756static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1757{
1758	int i, j;
1759	u32 data;
1760	u32 raster_config = 0, raster_config_1 = 0;
1761	u32 active_rbs = 0;
1762	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1763					adev->gfx.config.max_sh_per_se;
1764	unsigned num_rb_pipes;
1765
1766	mutex_lock(&adev->grbm_idx_mutex);
1767	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1768		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1769			gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1770			data = gfx_v7_0_get_rb_active_bitmap(adev);
1771			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1772					       rb_bitmap_width_per_sh);
1773		}
1774	}
1775	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1776
1777	adev->gfx.config.backend_enable_mask = active_rbs;
1778	adev->gfx.config.num_rbs = hweight32(active_rbs);
1779
1780	num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1781			     adev->gfx.config.max_shader_engines, 16);
1782
1783	gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1784
1785	if (!adev->gfx.config.backend_enable_mask ||
1786			adev->gfx.config.num_rbs >= num_rb_pipes) {
1787		WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1788		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1789	} else {
1790		gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1791							adev->gfx.config.backend_enable_mask,
1792							num_rb_pipes);
1793	}
1794
1795	/* cache the values for userspace */
1796	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1797		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1798			gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1799			adev->gfx.config.rb_config[i][j].rb_backend_disable =
1800				RREG32(mmCC_RB_BACKEND_DISABLE);
1801			adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1802				RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1803			adev->gfx.config.rb_config[i][j].raster_config =
1804				RREG32(mmPA_SC_RASTER_CONFIG);
1805			adev->gfx.config.rb_config[i][j].raster_config_1 =
1806				RREG32(mmPA_SC_RASTER_CONFIG_1);
1807		}
1808	}
1809	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1810	mutex_unlock(&adev->grbm_idx_mutex);
1811}
1812
1813#define DEFAULT_SH_MEM_BASES	(0x6000)
1814/**
1815 * gfx_v7_0_init_compute_vmid - gart enable
1816 *
1817 * @adev: amdgpu_device pointer
1818 *
1819 * Initialize compute vmid sh_mem registers
1820 *
1821 */
1822static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1823{
1824	int i;
1825	uint32_t sh_mem_config;
1826	uint32_t sh_mem_bases;
1827
1828	/*
1829	 * Configure apertures:
1830	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1831	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1832	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1833	*/
1834	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1835	sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1836			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1837	sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1838	mutex_lock(&adev->srbm_mutex);
1839	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1840		cik_srbm_select(adev, 0, 0, 0, i);
1841		/* CP and shaders */
1842		WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1843		WREG32(mmSH_MEM_APE1_BASE, 1);
1844		WREG32(mmSH_MEM_APE1_LIMIT, 0);
1845		WREG32(mmSH_MEM_BASES, sh_mem_bases);
1846	}
1847	cik_srbm_select(adev, 0, 0, 0, 0);
1848	mutex_unlock(&adev->srbm_mutex);
1849
1850	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1851	   access. These should be enabled by FW for target VMIDs. */
1852	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1853		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
1854		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
1855		WREG32(amdgpu_gds_reg_offset[i].gws, 0);
1856		WREG32(amdgpu_gds_reg_offset[i].oa, 0);
1857	}
1858}
1859
1860static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
1861{
1862	int vmid;
1863
1864	/*
1865	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1866	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
1867	 * the driver can enable them for graphics. VMID0 should maintain
1868	 * access so that HWS firmware can save/restore entries.
1869	 */
1870	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
1871		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
1872		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
1873		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
1874		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
1875	}
1876}
1877
1878static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1879{
1880	adev->gfx.config.double_offchip_lds_buf = 1;
1881}
1882
1883/**
1884 * gfx_v7_0_constants_init - setup the 3D engine
1885 *
1886 * @adev: amdgpu_device pointer
1887 *
1888 * init the gfx constants such as the 3D engine, tiling configuration
1889 * registers, maximum number of quad pipes, render backends...
1890 */
1891static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
1892{
1893	u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1894	u32 tmp;
1895	int i;
1896
1897	WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1898
1899	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1900	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1901	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1902
1903	gfx_v7_0_tiling_mode_table_init(adev);
1904
1905	gfx_v7_0_setup_rb(adev);
1906	gfx_v7_0_get_cu_info(adev);
1907	gfx_v7_0_config_init(adev);
1908
1909	/* set HW defaults for 3D engine */
1910	WREG32(mmCP_MEQ_THRESHOLDS,
1911	       (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1912	       (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1913
1914	mutex_lock(&adev->grbm_idx_mutex);
1915	/*
1916	 * making sure that the following register writes will be broadcasted
1917	 * to all the shaders
1918	 */
1919	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1920
1921	/* XXX SH_MEM regs */
1922	/* where to put LDS, scratch, GPUVM in FSA64 space */
1923	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1924				   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1925	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1926				   MTYPE_NC);
1927	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1928				   MTYPE_UC);
1929	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1930
1931	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1932				   SWIZZLE_ENABLE, 1);
1933	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1934				   ELEMENT_SIZE, 1);
1935	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1936				   INDEX_STRIDE, 3);
1937	WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1938
1939	mutex_lock(&adev->srbm_mutex);
1940	for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1941		if (i == 0)
1942			sh_mem_base = 0;
1943		else
1944			sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1945		cik_srbm_select(adev, 0, 0, 0, i);
1946		/* CP and shaders */
1947		WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1948		WREG32(mmSH_MEM_APE1_BASE, 1);
1949		WREG32(mmSH_MEM_APE1_LIMIT, 0);
1950		WREG32(mmSH_MEM_BASES, sh_mem_base);
1951	}
1952	cik_srbm_select(adev, 0, 0, 0, 0);
1953	mutex_unlock(&adev->srbm_mutex);
1954
1955	gfx_v7_0_init_compute_vmid(adev);
1956	gfx_v7_0_init_gds_vmid(adev);
1957
1958	WREG32(mmSX_DEBUG_1, 0x20);
1959
1960	WREG32(mmTA_CNTL_AUX, 0x00010000);
1961
1962	tmp = RREG32(mmSPI_CONFIG_CNTL);
1963	tmp |= 0x03000000;
1964	WREG32(mmSPI_CONFIG_CNTL, tmp);
1965
1966	WREG32(mmSQ_CONFIG, 1);
1967
1968	WREG32(mmDB_DEBUG, 0);
1969
1970	tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1971	tmp |= 0x00000400;
1972	WREG32(mmDB_DEBUG2, tmp);
1973
1974	tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1975	tmp |= 0x00020200;
1976	WREG32(mmDB_DEBUG3, tmp);
1977
1978	tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1979	tmp |= 0x00018208;
1980	WREG32(mmCB_HW_CONTROL, tmp);
1981
1982	WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1983
1984	WREG32(mmPA_SC_FIFO_SIZE,
1985		((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1986		(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1987		(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1988		(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1989
1990	WREG32(mmVGT_NUM_INSTANCES, 1);
1991
1992	WREG32(mmCP_PERFMON_CNTL, 0);
1993
1994	WREG32(mmSQ_CONFIG, 0);
1995
1996	WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1997		((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1998		(255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1999
2000	WREG32(mmVGT_CACHE_INVALIDATION,
2001		(VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2002		(ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2003
2004	WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2005	WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2006
2007	WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2008			(3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2009	WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2010
2011	tmp = RREG32(mmSPI_ARB_PRIORITY);
2012	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2013	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2014	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2015	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2016	WREG32(mmSPI_ARB_PRIORITY, tmp);
2017
2018	mutex_unlock(&adev->grbm_idx_mutex);
2019
2020	udelay(50);
2021}
2022
2023/**
2024 * gfx_v7_0_ring_test_ring - basic gfx ring test
2025 *
2026 * @ring: amdgpu_ring structure holding ring information
2027 *
2028 * Allocate a scratch register and write to it using the gfx ring (CIK).
2029 * Provides a basic gfx ring test to verify that the ring is working.
2030 * Used by gfx_v7_0_cp_gfx_resume();
2031 * Returns 0 on success, error on failure.
2032 */
2033static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2034{
2035	struct amdgpu_device *adev = ring->adev;
2036	uint32_t tmp = 0;
2037	unsigned i;
2038	int r;
2039
2040	WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
2041	r = amdgpu_ring_alloc(ring, 3);
2042	if (r)
2043		return r;
2044
2045	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2046	amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
2047	amdgpu_ring_write(ring, 0xDEADBEEF);
2048	amdgpu_ring_commit(ring);
2049
2050	for (i = 0; i < adev->usec_timeout; i++) {
2051		tmp = RREG32(mmSCRATCH_REG0);
2052		if (tmp == 0xDEADBEEF)
2053			break;
2054		udelay(1);
2055	}
2056	if (i >= adev->usec_timeout)
2057		r = -ETIMEDOUT;
2058	return r;
2059}
2060
2061/**
2062 * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp
2063 *
2064 * @ring: amdgpu_ring structure holding ring information
2065 *
2066 * Emits an hdp flush on the cp.
2067 */
2068static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2069{
2070	u32 ref_and_mask;
2071	int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2072
2073	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2074		switch (ring->me) {
2075		case 1:
2076			ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2077			break;
2078		case 2:
2079			ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2080			break;
2081		default:
2082			return;
2083		}
2084	} else {
2085		ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2086	}
2087
2088	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2089	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2090				 WAIT_REG_MEM_FUNCTION(3) |  /* == */
2091				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2092	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2093	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2094	amdgpu_ring_write(ring, ref_and_mask);
2095	amdgpu_ring_write(ring, ref_and_mask);
2096	amdgpu_ring_write(ring, 0x20); /* poll interval */
2097}
2098
2099static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2100{
2101	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2102	amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2103		EVENT_INDEX(4));
2104
2105	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2106	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2107		EVENT_INDEX(0));
2108}
2109
2110/**
2111 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2112 *
2113 * @ring: amdgpu_ring structure holding ring information
2114 * @addr: address
2115 * @seq: sequence number
2116 * @flags: fence related flags
2117 *
2118 * Emits a fence sequence number on the gfx ring and flushes
2119 * GPU caches.
2120 */
2121static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2122					 u64 seq, unsigned flags)
2123{
2124	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2125	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2126	bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
2127
2128	/* Workaround for cache flush problems. First send a dummy EOP
2129	 * event down the pipe with seq one below.
2130	 */
2131	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2132	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2133				 EOP_TC_ACTION_EN |
2134				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2135				 EVENT_INDEX(5)));
2136	amdgpu_ring_write(ring, addr & 0xfffffffc);
2137	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2138				DATA_SEL(1) | INT_SEL(0));
2139	amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2140	amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2141
2142	/* Then send the real EOP event down the pipe. */
2143	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2144	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2145				 EOP_TC_ACTION_EN |
2146				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2147				 EVENT_INDEX(5) |
2148				 (exec ? EOP_EXEC : 0)));
2149	amdgpu_ring_write(ring, addr & 0xfffffffc);
2150	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2151				DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2152	amdgpu_ring_write(ring, lower_32_bits(seq));
2153	amdgpu_ring_write(ring, upper_32_bits(seq));
2154}
2155
2156/**
2157 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2158 *
2159 * @ring: amdgpu_ring structure holding ring information
2160 * @addr: address
2161 * @seq: sequence number
2162 * @flags: fence related flags
2163 *
2164 * Emits a fence sequence number on the compute ring and flushes
2165 * GPU caches.
2166 */
2167static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2168					     u64 addr, u64 seq,
2169					     unsigned flags)
2170{
2171	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2172	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2173
2174	/* RELEASE_MEM - flush caches, send int */
2175	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2176	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2177				 EOP_TC_ACTION_EN |
2178				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2179				 EVENT_INDEX(5)));
2180	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2181	amdgpu_ring_write(ring, addr & 0xfffffffc);
2182	amdgpu_ring_write(ring, upper_32_bits(addr));
2183	amdgpu_ring_write(ring, lower_32_bits(seq));
2184	amdgpu_ring_write(ring, upper_32_bits(seq));
2185}
2186
2187/*
2188 * IB stuff
2189 */
2190/**
2191 * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring
2192 *
2193 * @ring: amdgpu_ring structure holding ring information
2194 * @job: job to retrieve vmid from
2195 * @ib: amdgpu indirect buffer object
2196 * @flags: options (AMDGPU_HAVE_CTX_SWITCH)
2197 *
2198 * Emits an DE (drawing engine) or CE (constant engine) IB
2199 * on the gfx ring.  IBs are usually generated by userspace
2200 * acceleration drivers and submitted to the kernel for
2201 * scheduling on the ring.  This function schedules the IB
2202 * on the gfx ring for execution by the GPU.
2203 */
2204static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2205					struct amdgpu_job *job,
2206					struct amdgpu_ib *ib,
2207					uint32_t flags)
2208{
2209	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2210	u32 header, control = 0;
2211
2212	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
2213	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2214		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2215		amdgpu_ring_write(ring, 0);
2216	}
2217
2218	if (ib->flags & AMDGPU_IB_FLAG_CE)
2219		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2220	else
2221		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2222
2223	control |= ib->length_dw | (vmid << 24);
2224
2225	amdgpu_ring_write(ring, header);
2226	amdgpu_ring_write(ring,
2227#ifdef __BIG_ENDIAN
2228			  (2 << 0) |
2229#endif
2230			  (ib->gpu_addr & 0xFFFFFFFC));
2231	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2232	amdgpu_ring_write(ring, control);
2233}
2234
2235static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2236					  struct amdgpu_job *job,
2237					  struct amdgpu_ib *ib,
2238					  uint32_t flags)
2239{
2240	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2241	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2242
2243	/* Currently, there is a high possibility to get wave ID mismatch
2244	 * between ME and GDS, leading to a hw deadlock, because ME generates
2245	 * different wave IDs than the GDS expects. This situation happens
2246	 * randomly when at least 5 compute pipes use GDS ordered append.
2247	 * The wave IDs generated by ME are also wrong after suspend/resume.
2248	 * Those are probably bugs somewhere else in the kernel driver.
2249	 *
2250	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2251	 * GDS to 0 for this ring (me/pipe).
2252	 */
2253	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2254		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2255		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
2256		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2257	}
2258
2259	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2260	amdgpu_ring_write(ring,
2261#ifdef __BIG_ENDIAN
2262					  (2 << 0) |
2263#endif
2264					  (ib->gpu_addr & 0xFFFFFFFC));
2265	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2266	amdgpu_ring_write(ring, control);
2267}
2268
2269static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2270{
2271	uint32_t dw2 = 0;
2272
2273	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2274	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2275		gfx_v7_0_ring_emit_vgt_flush(ring);
2276		/* set load_global_config & load_global_uconfig */
2277		dw2 |= 0x8001;
2278		/* set load_cs_sh_regs */
2279		dw2 |= 0x01000000;
2280		/* set load_per_context_state & load_gfx_sh_regs */
2281		dw2 |= 0x10002;
2282	}
2283
2284	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2285	amdgpu_ring_write(ring, dw2);
2286	amdgpu_ring_write(ring, 0);
2287}
2288
2289/**
2290 * gfx_v7_0_ring_test_ib - basic ring IB test
2291 *
2292 * @ring: amdgpu_ring structure holding ring information
2293 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
2294 *
2295 * Allocate an IB and execute it on the gfx ring (CIK).
2296 * Provides a basic gfx ring test to verify that IBs are working.
2297 * Returns 0 on success, error on failure.
2298 */
2299static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2300{
2301	struct amdgpu_device *adev = ring->adev;
2302	struct amdgpu_ib ib;
2303	struct dma_fence *f = NULL;
2304	uint32_t tmp = 0;
2305	long r;
2306
2307	WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
2308	memset(&ib, 0, sizeof(ib));
2309	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
2310	if (r)
2311		return r;
2312
2313	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2314	ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
2315	ib.ptr[2] = 0xDEADBEEF;
2316	ib.length_dw = 3;
2317
2318	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2319	if (r)
2320		goto error;
2321
2322	r = dma_fence_wait_timeout(f, false, timeout);
2323	if (r == 0) {
2324		r = -ETIMEDOUT;
2325		goto error;
2326	} else if (r < 0) {
2327		goto error;
2328	}
2329	tmp = RREG32(mmSCRATCH_REG0);
2330	if (tmp == 0xDEADBEEF)
2331		r = 0;
2332	else
2333		r = -EINVAL;
2334
2335error:
2336	amdgpu_ib_free(&ib, NULL);
2337	dma_fence_put(f);
2338	return r;
2339}
2340
2341/*
2342 * CP.
2343 * On CIK, gfx and compute now have independent command processors.
2344 *
2345 * GFX
2346 * Gfx consists of a single ring and can process both gfx jobs and
2347 * compute jobs.  The gfx CP consists of three microengines (ME):
2348 * PFP - Pre-Fetch Parser
2349 * ME - Micro Engine
2350 * CE - Constant Engine
2351 * The PFP and ME make up what is considered the Drawing Engine (DE).
2352 * The CE is an asynchronous engine used for updating buffer desciptors
2353 * used by the DE so that they can be loaded into cache in parallel
2354 * while the DE is processing state update packets.
2355 *
2356 * Compute
2357 * The compute CP consists of two microengines (ME):
2358 * MEC1 - Compute MicroEngine 1
2359 * MEC2 - Compute MicroEngine 2
2360 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2361 * The queues are exposed to userspace and are programmed directly
2362 * by the compute runtime.
2363 */
2364/**
2365 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2366 *
2367 * @adev: amdgpu_device pointer
2368 * @enable: enable or disable the MEs
2369 *
2370 * Halts or unhalts the gfx MEs.
2371 */
2372static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2373{
2374	if (enable)
2375		WREG32(mmCP_ME_CNTL, 0);
2376	else
2377		WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
2378				      CP_ME_CNTL__PFP_HALT_MASK |
2379				      CP_ME_CNTL__CE_HALT_MASK));
2380	udelay(50);
2381}
2382
2383/**
2384 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2385 *
2386 * @adev: amdgpu_device pointer
2387 *
2388 * Loads the gfx PFP, ME, and CE ucode.
2389 * Returns 0 for success, -EINVAL if the ucode is not available.
2390 */
2391static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2392{
2393	const struct gfx_firmware_header_v1_0 *pfp_hdr;
2394	const struct gfx_firmware_header_v1_0 *ce_hdr;
2395	const struct gfx_firmware_header_v1_0 *me_hdr;
2396	const __le32 *fw_data;
2397	unsigned i, fw_size;
2398
2399	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2400		return -EINVAL;
2401
2402	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2403	ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2404	me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2405
2406	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2407	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2408	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2409	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2410	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2411	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2412	adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2413	adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2414	adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2415
2416	gfx_v7_0_cp_gfx_enable(adev, false);
2417
2418	/* PFP */
2419	fw_data = (const __le32 *)
2420		(adev->gfx.pfp_fw->data +
2421		 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2422	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2423	WREG32(mmCP_PFP_UCODE_ADDR, 0);
2424	for (i = 0; i < fw_size; i++)
2425		WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2426	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2427
2428	/* CE */
2429	fw_data = (const __le32 *)
2430		(adev->gfx.ce_fw->data +
2431		 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2432	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2433	WREG32(mmCP_CE_UCODE_ADDR, 0);
2434	for (i = 0; i < fw_size; i++)
2435		WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2436	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2437
2438	/* ME */
2439	fw_data = (const __le32 *)
2440		(adev->gfx.me_fw->data +
2441		 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2442	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2443	WREG32(mmCP_ME_RAM_WADDR, 0);
2444	for (i = 0; i < fw_size; i++)
2445		WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2446	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2447
2448	return 0;
2449}
2450
2451/**
2452 * gfx_v7_0_cp_gfx_start - start the gfx ring
2453 *
2454 * @adev: amdgpu_device pointer
2455 *
2456 * Enables the ring and loads the clear state context and other
2457 * packets required to init the ring.
2458 * Returns 0 for success, error for failure.
2459 */
2460static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2461{
2462	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2463	const struct cs_section_def *sect = NULL;
2464	const struct cs_extent_def *ext = NULL;
2465	int r, i;
2466
2467	/* init the CP */
2468	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2469	WREG32(mmCP_ENDIAN_SWAP, 0);
2470	WREG32(mmCP_DEVICE_ID, 1);
2471
2472	gfx_v7_0_cp_gfx_enable(adev, true);
2473
2474	r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2475	if (r) {
2476		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2477		return r;
2478	}
2479
2480	/* init the CE partitions.  CE only used for gfx on CIK */
2481	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2482	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2483	amdgpu_ring_write(ring, 0x8000);
2484	amdgpu_ring_write(ring, 0x8000);
2485
2486	/* clear state buffer */
2487	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2488	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2489
2490	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2491	amdgpu_ring_write(ring, 0x80000000);
2492	amdgpu_ring_write(ring, 0x80000000);
2493
2494	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2495		for (ext = sect->section; ext->extent != NULL; ++ext) {
2496			if (sect->id == SECT_CONTEXT) {
2497				amdgpu_ring_write(ring,
2498						  PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2499				amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2500				for (i = 0; i < ext->reg_count; i++)
2501					amdgpu_ring_write(ring, ext->extent[i]);
2502			}
2503		}
2504	}
2505
2506	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2507	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2508	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2509	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2510
2511	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2512	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2513
2514	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2515	amdgpu_ring_write(ring, 0);
2516
2517	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2518	amdgpu_ring_write(ring, 0x00000316);
2519	amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2520	amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2521
2522	amdgpu_ring_commit(ring);
2523
2524	return 0;
2525}
2526
2527/**
2528 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2529 *
2530 * @adev: amdgpu_device pointer
2531 *
2532 * Program the location and size of the gfx ring buffer
2533 * and test it to make sure it's working.
2534 * Returns 0 for success, error for failure.
2535 */
2536static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2537{
2538	struct amdgpu_ring *ring;
2539	u32 tmp;
2540	u32 rb_bufsz;
2541	u64 rb_addr, rptr_addr;
2542	int r;
2543
2544	WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2545	if (adev->asic_type != CHIP_HAWAII)
2546		WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2547
2548	/* Set the write pointer delay */
2549	WREG32(mmCP_RB_WPTR_DELAY, 0);
2550
2551	/* set the RB to use vmid 0 */
2552	WREG32(mmCP_RB_VMID, 0);
2553
2554	WREG32(mmSCRATCH_ADDR, 0);
2555
2556	/* ring 0 - compute and gfx */
2557	/* Set ring buffer size */
2558	ring = &adev->gfx.gfx_ring[0];
2559	rb_bufsz = order_base_2(ring->ring_size / 8);
2560	tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2561#ifdef __BIG_ENDIAN
2562	tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2563#endif
2564	WREG32(mmCP_RB0_CNTL, tmp);
2565
2566	/* Initialize the ring buffer's read and write pointers */
2567	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2568	ring->wptr = 0;
2569	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2570
2571	/* set the wb address whether it's enabled or not */
2572	rptr_addr = ring->rptr_gpu_addr;
2573	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2574	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2575
2576	/* scratch register shadowing is no longer supported */
2577	WREG32(mmSCRATCH_UMSK, 0);
2578
2579	mdelay(1);
2580	WREG32(mmCP_RB0_CNTL, tmp);
2581
2582	rb_addr = ring->gpu_addr >> 8;
2583	WREG32(mmCP_RB0_BASE, rb_addr);
2584	WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2585
2586	/* start the ring */
2587	gfx_v7_0_cp_gfx_start(adev);
2588	r = amdgpu_ring_test_helper(ring);
2589	if (r)
2590		return r;
2591
2592	return 0;
2593}
2594
2595static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2596{
2597	return *ring->rptr_cpu_addr;
2598}
2599
2600static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2601{
2602	struct amdgpu_device *adev = ring->adev;
2603
2604	return RREG32(mmCP_RB0_WPTR);
2605}
2606
2607static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2608{
2609	struct amdgpu_device *adev = ring->adev;
2610
2611	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2612	(void)RREG32(mmCP_RB0_WPTR);
2613}
2614
2615static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2616{
2617	/* XXX check if swapping is necessary on BE */
2618	return *ring->wptr_cpu_addr;
2619}
2620
2621static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2622{
2623	struct amdgpu_device *adev = ring->adev;
2624
2625	/* XXX check if swapping is necessary on BE */
2626	*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
2627	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2628}
2629
2630/**
2631 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2632 *
2633 * @adev: amdgpu_device pointer
2634 * @enable: enable or disable the MEs
2635 *
2636 * Halts or unhalts the compute MEs.
2637 */
2638static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2639{
2640	if (enable)
2641		WREG32(mmCP_MEC_CNTL, 0);
2642	else
2643		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2644				       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2645	udelay(50);
2646}
2647
2648/**
2649 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2650 *
2651 * @adev: amdgpu_device pointer
2652 *
2653 * Loads the compute MEC1&2 ucode.
2654 * Returns 0 for success, -EINVAL if the ucode is not available.
2655 */
2656static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2657{
2658	const struct gfx_firmware_header_v1_0 *mec_hdr;
2659	const __le32 *fw_data;
2660	unsigned i, fw_size;
2661
2662	if (!adev->gfx.mec_fw)
2663		return -EINVAL;
2664
2665	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2666	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2667	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2668	adev->gfx.mec_feature_version = le32_to_cpu(
2669					mec_hdr->ucode_feature_version);
2670
2671	gfx_v7_0_cp_compute_enable(adev, false);
2672
2673	/* MEC1 */
2674	fw_data = (const __le32 *)
2675		(adev->gfx.mec_fw->data +
2676		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2677	fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2678	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2679	for (i = 0; i < fw_size; i++)
2680		WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2681	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2682
2683	if (adev->asic_type == CHIP_KAVERI) {
2684		const struct gfx_firmware_header_v1_0 *mec2_hdr;
2685
2686		if (!adev->gfx.mec2_fw)
2687			return -EINVAL;
2688
2689		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2690		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2691		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2692		adev->gfx.mec2_feature_version = le32_to_cpu(
2693				mec2_hdr->ucode_feature_version);
2694
2695		/* MEC2 */
2696		fw_data = (const __le32 *)
2697			(adev->gfx.mec2_fw->data +
2698			 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2699		fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2700		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2701		for (i = 0; i < fw_size; i++)
2702			WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2703		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2704	}
2705
2706	return 0;
2707}
2708
2709/**
2710 * gfx_v7_0_cp_compute_fini - stop the compute queues
2711 *
2712 * @adev: amdgpu_device pointer
2713 *
2714 * Stop the compute queues and tear down the driver queue
2715 * info.
2716 */
2717static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2718{
2719	int i;
2720
2721	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2722		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2723
2724		amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2725	}
2726}
2727
2728static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2729{
2730	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2731}
2732
2733static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2734{
2735	int r;
2736	u32 *hpd;
2737	size_t mec_hpd_size;
2738
2739	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2740
2741	/* take ownership of the relevant compute queues */
2742	amdgpu_gfx_compute_queue_acquire(adev);
2743
2744	/* allocate space for ALL pipes (even the ones we don't own) */
2745	mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2746		* GFX7_MEC_HPD_SIZE * 2;
2747
2748	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2749				      AMDGPU_GEM_DOMAIN_VRAM |
2750				      AMDGPU_GEM_DOMAIN_GTT,
2751				      &adev->gfx.mec.hpd_eop_obj,
2752				      &adev->gfx.mec.hpd_eop_gpu_addr,
2753				      (void **)&hpd);
2754	if (r) {
2755		dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2756		gfx_v7_0_mec_fini(adev);
2757		return r;
2758	}
2759
2760	/* clear memory.  Not sure if this is required or not */
2761	memset(hpd, 0, mec_hpd_size);
2762
2763	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2764	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2765
2766	return 0;
2767}
2768
2769static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2770				       int mec, int pipe)
2771{
2772	u64 eop_gpu_addr;
2773	u32 tmp;
2774	size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2775			    * GFX7_MEC_HPD_SIZE * 2;
2776
2777	mutex_lock(&adev->srbm_mutex);
2778	eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2779
2780	cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2781
2782	/* write the EOP addr */
2783	WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2784	WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2785
2786	/* set the VMID assigned */
2787	WREG32(mmCP_HPD_EOP_VMID, 0);
2788
2789	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2790	tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2791	tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2792	tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2793	WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2794
2795	cik_srbm_select(adev, 0, 0, 0, 0);
2796	mutex_unlock(&adev->srbm_mutex);
2797}
2798
2799static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2800{
2801	int i;
2802
2803	/* disable the queue if it's active */
2804	if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2805		WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2806		for (i = 0; i < adev->usec_timeout; i++) {
2807			if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2808				break;
2809			udelay(1);
2810		}
2811
2812		if (i == adev->usec_timeout)
2813			return -ETIMEDOUT;
2814
2815		WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2816		WREG32(mmCP_HQD_PQ_RPTR, 0);
2817		WREG32(mmCP_HQD_PQ_WPTR, 0);
2818	}
2819
2820	return 0;
2821}
2822
2823static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2824			     struct cik_mqd *mqd,
2825			     uint64_t mqd_gpu_addr,
2826			     struct amdgpu_ring *ring)
2827{
2828	u64 hqd_gpu_addr;
2829	u64 wb_gpu_addr;
2830
2831	/* init the mqd struct */
2832	memset(mqd, 0, sizeof(struct cik_mqd));
2833
2834	mqd->header = 0xC0310800;
2835	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2836	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2837	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2838	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2839
2840	/* enable doorbell? */
2841	mqd->cp_hqd_pq_doorbell_control =
2842		RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2843	if (ring->use_doorbell)
2844		mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2845	else
2846		mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2847
2848	/* set the pointer to the MQD */
2849	mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2850	mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2851
2852	/* set MQD vmid to 0 */
2853	mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2854	mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2855
2856	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2857	hqd_gpu_addr = ring->gpu_addr >> 8;
2858	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2859	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2860
2861	/* set up the HQD, this is similar to CP_RB0_CNTL */
2862	mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2863	mqd->cp_hqd_pq_control &=
2864		~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2865				CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2866
2867	mqd->cp_hqd_pq_control |=
2868		order_base_2(ring->ring_size / 8);
2869	mqd->cp_hqd_pq_control |=
2870		(order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2871#ifdef __BIG_ENDIAN
2872	mqd->cp_hqd_pq_control |=
2873		2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2874#endif
2875	mqd->cp_hqd_pq_control &=
2876		~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2877				CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2878				CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2879	mqd->cp_hqd_pq_control |=
2880		CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2881		CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2882
2883	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2884	wb_gpu_addr = ring->wptr_gpu_addr;
2885	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2886	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2887
2888	/* set the wb address whether it's enabled or not */
2889	wb_gpu_addr = ring->rptr_gpu_addr;
2890	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2891	mqd->cp_hqd_pq_rptr_report_addr_hi =
2892		upper_32_bits(wb_gpu_addr) & 0xffff;
2893
2894	/* enable the doorbell if requested */
2895	if (ring->use_doorbell) {
2896		mqd->cp_hqd_pq_doorbell_control =
2897			RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2898		mqd->cp_hqd_pq_doorbell_control &=
2899			~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2900		mqd->cp_hqd_pq_doorbell_control |=
2901			(ring->doorbell_index <<
2902			 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2903		mqd->cp_hqd_pq_doorbell_control |=
2904			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2905		mqd->cp_hqd_pq_doorbell_control &=
2906			~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2907					CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2908
2909	} else {
2910		mqd->cp_hqd_pq_doorbell_control = 0;
2911	}
2912
2913	/* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2914	ring->wptr = 0;
2915	mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2916	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2917
2918	/* set the vmid for the queue */
2919	mqd->cp_hqd_vmid = 0;
2920
2921	/* defaults */
2922	mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
2923	mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
2924	mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
2925	mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
2926	mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
2927	mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
2928	mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
2929	mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
2930	mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
2931	mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
2932	mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
2933	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2934	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
2935	mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
2936	mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
2937	mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
2938
2939	/* activate the queue */
2940	mqd->cp_hqd_active = 1;
2941}
2942
2943static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
2944{
2945	uint32_t tmp;
2946	uint32_t mqd_reg;
2947	uint32_t *mqd_data;
2948
2949	/* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
2950	mqd_data = &mqd->cp_mqd_base_addr_lo;
2951
2952	/* disable wptr polling */
2953	tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2954	tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2955	WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2956
2957	/* program all HQD registers */
2958	for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
2959		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
2960
2961	/* activate the HQD */
2962	for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
2963		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
2964
2965	return 0;
2966}
2967
2968static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
2969{
2970	int r;
2971	u64 mqd_gpu_addr;
2972	struct cik_mqd *mqd;
2973	struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
2974
2975	r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
2976				      AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
2977				      &mqd_gpu_addr, (void **)&mqd);
2978	if (r) {
2979		dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2980		return r;
2981	}
2982
2983	mutex_lock(&adev->srbm_mutex);
2984	cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2985
2986	gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
2987	gfx_v7_0_mqd_deactivate(adev);
2988	gfx_v7_0_mqd_commit(adev, mqd);
2989
2990	cik_srbm_select(adev, 0, 0, 0, 0);
2991	mutex_unlock(&adev->srbm_mutex);
2992
2993	amdgpu_bo_kunmap(ring->mqd_obj);
2994	amdgpu_bo_unreserve(ring->mqd_obj);
2995	return 0;
2996}
2997
2998/**
2999 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3000 *
3001 * @adev: amdgpu_device pointer
3002 *
3003 * Program the compute queues and test them to make sure they
3004 * are working.
3005 * Returns 0 for success, error for failure.
3006 */
3007static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3008{
3009	int r, i, j;
3010	u32 tmp;
3011	struct amdgpu_ring *ring;
3012
3013	/* fix up chicken bits */
3014	tmp = RREG32(mmCP_CPF_DEBUG);
3015	tmp |= (1 << 23);
3016	WREG32(mmCP_CPF_DEBUG, tmp);
3017
3018	/* init all pipes (even the ones we don't own) */
3019	for (i = 0; i < adev->gfx.mec.num_mec; i++)
3020		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3021			gfx_v7_0_compute_pipe_init(adev, i, j);
3022
3023	/* init the queues */
3024	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3025		r = gfx_v7_0_compute_queue_init(adev, i);
3026		if (r) {
3027			gfx_v7_0_cp_compute_fini(adev);
3028			return r;
3029		}
3030	}
3031
3032	gfx_v7_0_cp_compute_enable(adev, true);
3033
3034	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3035		ring = &adev->gfx.compute_ring[i];
3036		amdgpu_ring_test_helper(ring);
3037	}
3038
3039	return 0;
3040}
3041
3042static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3043{
3044	gfx_v7_0_cp_gfx_enable(adev, enable);
3045	gfx_v7_0_cp_compute_enable(adev, enable);
3046}
3047
3048static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3049{
3050	int r;
3051
3052	r = gfx_v7_0_cp_gfx_load_microcode(adev);
3053	if (r)
3054		return r;
3055	r = gfx_v7_0_cp_compute_load_microcode(adev);
3056	if (r)
3057		return r;
3058
3059	return 0;
3060}
3061
3062static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3063					       bool enable)
3064{
3065	u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3066
3067	if (enable)
3068		tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3069				CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3070	else
3071		tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3072				CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3073	WREG32(mmCP_INT_CNTL_RING0, tmp);
3074}
3075
3076static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3077{
3078	int r;
3079
3080	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3081
3082	r = gfx_v7_0_cp_load_microcode(adev);
3083	if (r)
3084		return r;
3085
3086	r = gfx_v7_0_cp_gfx_resume(adev);
3087	if (r)
3088		return r;
3089	r = gfx_v7_0_cp_compute_resume(adev);
3090	if (r)
3091		return r;
3092
3093	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3094
3095	return 0;
3096}
3097
3098/**
3099 * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP
3100 *
3101 * @ring: the ring to emit the commands to
3102 *
3103 * Sync the command pipeline with the PFP. E.g. wait for everything
3104 * to be completed.
3105 */
3106static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3107{
3108	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3109	uint32_t seq = ring->fence_drv.sync_seq;
3110	uint64_t addr = ring->fence_drv.gpu_addr;
3111
3112	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3113	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3114				 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3115				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3116	amdgpu_ring_write(ring, addr & 0xfffffffc);
3117	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3118	amdgpu_ring_write(ring, seq);
3119	amdgpu_ring_write(ring, 0xffffffff);
3120	amdgpu_ring_write(ring, 4); /* poll interval */
3121
3122	if (usepfp) {
3123		/* sync CE with ME to prevent CE fetch CEIB before context switch done */
3124		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3125		amdgpu_ring_write(ring, 0);
3126		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3127		amdgpu_ring_write(ring, 0);
3128	}
3129}
3130
3131/*
3132 * vm
3133 * VMID 0 is the physical GPU addresses as used by the kernel.
3134 * VMIDs 1-15 are used for userspace clients and are handled
3135 * by the amdgpu vm/hsa code.
3136 */
3137/**
3138 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3139 *
3140 * @ring: amdgpu_ring pointer
3141 * @vmid: vmid number to use
3142 * @pd_addr: address
3143 *
3144 * Update the page table base and flush the VM TLB
3145 * using the CP (CIK).
3146 */
3147static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3148					unsigned vmid, uint64_t pd_addr)
3149{
3150	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3151
3152	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3153
3154	/* wait for the invalidate to complete */
3155	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3156	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3157				 WAIT_REG_MEM_FUNCTION(0) |  /* always */
3158				 WAIT_REG_MEM_ENGINE(0))); /* me */
3159	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3160	amdgpu_ring_write(ring, 0);
3161	amdgpu_ring_write(ring, 0); /* ref */
3162	amdgpu_ring_write(ring, 0); /* mask */
3163	amdgpu_ring_write(ring, 0x20); /* poll interval */
3164
3165	/* compute doesn't have PFP */
3166	if (usepfp) {
3167		/* sync PFP to ME, otherwise we might get invalid PFP reads */
3168		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3169		amdgpu_ring_write(ring, 0x0);
3170
3171		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
3172		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3173		amdgpu_ring_write(ring, 0);
3174		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3175		amdgpu_ring_write(ring, 0);
3176	}
3177}
3178
3179static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3180				    uint32_t reg, uint32_t val)
3181{
3182	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3183
3184	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3185	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3186				 WRITE_DATA_DST_SEL(0)));
3187	amdgpu_ring_write(ring, reg);
3188	amdgpu_ring_write(ring, 0);
3189	amdgpu_ring_write(ring, val);
3190}
3191
3192/*
3193 * RLC
3194 * The RLC is a multi-purpose microengine that handles a
3195 * variety of functions.
3196 */
3197static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3198{
3199	const u32 *src_ptr;
3200	u32 dws;
3201	const struct cs_section_def *cs_data;
3202	int r;
3203
3204	/* allocate rlc buffers */
3205	if (adev->flags & AMD_IS_APU) {
3206		if (adev->asic_type == CHIP_KAVERI) {
3207			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3208			adev->gfx.rlc.reg_list_size =
3209				(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3210		} else {
3211			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3212			adev->gfx.rlc.reg_list_size =
3213				(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3214		}
3215	}
3216	adev->gfx.rlc.cs_data = ci_cs_data;
3217	adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3218	adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3219
3220	src_ptr = adev->gfx.rlc.reg_list;
3221	dws = adev->gfx.rlc.reg_list_size;
3222	dws += (5 * 16) + 48 + 48 + 64;
3223
3224	cs_data = adev->gfx.rlc.cs_data;
3225
3226	if (src_ptr) {
3227		/* init save restore block */
3228		r = amdgpu_gfx_rlc_init_sr(adev, dws);
3229		if (r)
3230			return r;
3231	}
3232
3233	if (cs_data) {
3234		/* init clear state block */
3235		r = amdgpu_gfx_rlc_init_csb(adev);
3236		if (r)
3237			return r;
3238	}
3239
3240	if (adev->gfx.rlc.cp_table_size) {
3241		r = amdgpu_gfx_rlc_init_cpt(adev);
3242		if (r)
3243			return r;
3244	}
3245
3246	/* init spm vmid with 0xf */
3247	if (adev->gfx.rlc.funcs->update_spm_vmid)
3248		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
3249
3250	return 0;
3251}
3252
3253static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3254{
3255	u32 tmp;
3256
3257	tmp = RREG32(mmRLC_LB_CNTL);
3258	if (enable)
3259		tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3260	else
3261		tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3262	WREG32(mmRLC_LB_CNTL, tmp);
3263}
3264
3265static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3266{
3267	u32 i, j, k;
3268	u32 mask;
3269
3270	mutex_lock(&adev->grbm_idx_mutex);
3271	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3272		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3273			gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3274			for (k = 0; k < adev->usec_timeout; k++) {
3275				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3276					break;
3277				udelay(1);
3278			}
3279		}
3280	}
3281	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3282	mutex_unlock(&adev->grbm_idx_mutex);
3283
3284	mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3285		RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3286		RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3287		RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3288	for (k = 0; k < adev->usec_timeout; k++) {
3289		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3290			break;
3291		udelay(1);
3292	}
3293}
3294
3295static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3296{
3297	u32 tmp;
3298
3299	tmp = RREG32(mmRLC_CNTL);
3300	if (tmp != rlc)
3301		WREG32(mmRLC_CNTL, rlc);
3302}
3303
3304static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3305{
3306	u32 data, orig;
3307
3308	orig = data = RREG32(mmRLC_CNTL);
3309
3310	if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3311		u32 i;
3312
3313		data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3314		WREG32(mmRLC_CNTL, data);
3315
3316		for (i = 0; i < adev->usec_timeout; i++) {
3317			if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3318				break;
3319			udelay(1);
3320		}
3321
3322		gfx_v7_0_wait_for_rlc_serdes(adev);
3323	}
3324
3325	return orig;
3326}
3327
3328static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev)
3329{
3330	return true;
3331}
3332
3333static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
3334{
3335	u32 tmp, i, mask;
3336
3337	tmp = 0x1 | (1 << 1);
3338	WREG32(mmRLC_GPR_REG2, tmp);
3339
3340	mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3341		RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3342	for (i = 0; i < adev->usec_timeout; i++) {
3343		if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3344			break;
3345		udelay(1);
3346	}
3347
3348	for (i = 0; i < adev->usec_timeout; i++) {
3349		if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3350			break;
3351		udelay(1);
3352	}
3353}
3354
3355static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
3356{
3357	u32 tmp;
3358
3359	tmp = 0x1 | (0 << 1);
3360	WREG32(mmRLC_GPR_REG2, tmp);
3361}
3362
3363/**
3364 * gfx_v7_0_rlc_stop - stop the RLC ME
3365 *
3366 * @adev: amdgpu_device pointer
3367 *
3368 * Halt the RLC ME (MicroEngine) (CIK).
3369 */
3370static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3371{
3372	WREG32(mmRLC_CNTL, 0);
3373
3374	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3375
3376	gfx_v7_0_wait_for_rlc_serdes(adev);
3377}
3378
3379/**
3380 * gfx_v7_0_rlc_start - start the RLC ME
3381 *
3382 * @adev: amdgpu_device pointer
3383 *
3384 * Unhalt the RLC ME (MicroEngine) (CIK).
3385 */
3386static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3387{
3388	WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3389
3390	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3391
3392	udelay(50);
3393}
3394
3395static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3396{
3397	u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3398
3399	tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3400	WREG32(mmGRBM_SOFT_RESET, tmp);
3401	udelay(50);
3402	tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3403	WREG32(mmGRBM_SOFT_RESET, tmp);
3404	udelay(50);
3405}
3406
3407/**
3408 * gfx_v7_0_rlc_resume - setup the RLC hw
3409 *
3410 * @adev: amdgpu_device pointer
3411 *
3412 * Initialize the RLC registers, load the ucode,
3413 * and start the RLC (CIK).
3414 * Returns 0 for success, -EINVAL if the ucode is not available.
3415 */
3416static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3417{
3418	const struct rlc_firmware_header_v1_0 *hdr;
3419	const __le32 *fw_data;
3420	unsigned i, fw_size;
3421	u32 tmp;
3422
3423	if (!adev->gfx.rlc_fw)
3424		return -EINVAL;
3425
3426	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3427	amdgpu_ucode_print_rlc_hdr(&hdr->header);
3428	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3429	adev->gfx.rlc_feature_version = le32_to_cpu(
3430					hdr->ucode_feature_version);
3431
3432	adev->gfx.rlc.funcs->stop(adev);
3433
3434	/* disable CG */
3435	tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3436	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3437
3438	adev->gfx.rlc.funcs->reset(adev);
3439
3440	gfx_v7_0_init_pg(adev);
3441
3442	WREG32(mmRLC_LB_CNTR_INIT, 0);
3443	WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3444
3445	mutex_lock(&adev->grbm_idx_mutex);
3446	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3447	WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3448	WREG32(mmRLC_LB_PARAMS, 0x00600408);
3449	WREG32(mmRLC_LB_CNTL, 0x80000004);
3450	mutex_unlock(&adev->grbm_idx_mutex);
3451
3452	WREG32(mmRLC_MC_CNTL, 0);
3453	WREG32(mmRLC_UCODE_CNTL, 0);
3454
3455	fw_data = (const __le32 *)
3456		(adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3457	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3458	WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3459	for (i = 0; i < fw_size; i++)
3460		WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3461	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3462
3463	/* XXX - find out what chips support lbpw */
3464	gfx_v7_0_enable_lbpw(adev, false);
3465
3466	if (adev->asic_type == CHIP_BONAIRE)
3467		WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3468
3469	adev->gfx.rlc.funcs->start(adev);
3470
3471	return 0;
3472}
3473
3474static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
3475{
3476	u32 data;
3477
3478	amdgpu_gfx_off_ctrl(adev, false);
3479
3480	data = RREG32(mmRLC_SPM_VMID);
3481
3482	data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
3483	data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
3484
3485	WREG32(mmRLC_SPM_VMID, data);
3486
3487	amdgpu_gfx_off_ctrl(adev, true);
3488}
3489
3490static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3491{
3492	u32 data, orig, tmp, tmp2;
3493
3494	orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3495
3496	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3497		gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3498
3499		tmp = gfx_v7_0_halt_rlc(adev);
3500
3501		mutex_lock(&adev->grbm_idx_mutex);
3502		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3503		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3504		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3505		tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3506			RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3507			RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3508		WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3509		mutex_unlock(&adev->grbm_idx_mutex);
3510
3511		gfx_v7_0_update_rlc(adev, tmp);
3512
3513		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3514		if (orig != data)
3515			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3516
3517	} else {
3518		gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3519
3520		RREG32(mmCB_CGTT_SCLK_CTRL);
3521		RREG32(mmCB_CGTT_SCLK_CTRL);
3522		RREG32(mmCB_CGTT_SCLK_CTRL);
3523		RREG32(mmCB_CGTT_SCLK_CTRL);
3524
3525		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3526		if (orig != data)
3527			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3528
3529		gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3530	}
3531}
3532
3533static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3534{
3535	u32 data, orig, tmp = 0;
3536
3537	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3538		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3539			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3540				orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3541				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3542				if (orig != data)
3543					WREG32(mmCP_MEM_SLP_CNTL, data);
3544			}
3545		}
3546
3547		orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3548		data |= 0x00000001;
3549		data &= 0xfffffffd;
3550		if (orig != data)
3551			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3552
3553		tmp = gfx_v7_0_halt_rlc(adev);
3554
3555		mutex_lock(&adev->grbm_idx_mutex);
3556		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3557		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3558		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3559		data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3560			RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3561		WREG32(mmRLC_SERDES_WR_CTRL, data);
3562		mutex_unlock(&adev->grbm_idx_mutex);
3563
3564		gfx_v7_0_update_rlc(adev, tmp);
3565
3566		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3567			orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3568			data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3569			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3570			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3571			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3572			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3573			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3574				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3575			data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3576			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3577			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3578			if (orig != data)
3579				WREG32(mmCGTS_SM_CTRL_REG, data);
3580		}
3581	} else {
3582		orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3583		data |= 0x00000003;
3584		if (orig != data)
3585			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3586
3587		data = RREG32(mmRLC_MEM_SLP_CNTL);
3588		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3589			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3590			WREG32(mmRLC_MEM_SLP_CNTL, data);
3591		}
3592
3593		data = RREG32(mmCP_MEM_SLP_CNTL);
3594		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3595			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3596			WREG32(mmCP_MEM_SLP_CNTL, data);
3597		}
3598
3599		orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3600		data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3601		if (orig != data)
3602			WREG32(mmCGTS_SM_CTRL_REG, data);
3603
3604		tmp = gfx_v7_0_halt_rlc(adev);
3605
3606		mutex_lock(&adev->grbm_idx_mutex);
3607		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3608		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3609		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3610		data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3611		WREG32(mmRLC_SERDES_WR_CTRL, data);
3612		mutex_unlock(&adev->grbm_idx_mutex);
3613
3614		gfx_v7_0_update_rlc(adev, tmp);
3615	}
3616}
3617
3618static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3619			       bool enable)
3620{
3621	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3622	/* order matters! */
3623	if (enable) {
3624		gfx_v7_0_enable_mgcg(adev, true);
3625		gfx_v7_0_enable_cgcg(adev, true);
3626	} else {
3627		gfx_v7_0_enable_cgcg(adev, false);
3628		gfx_v7_0_enable_mgcg(adev, false);
3629	}
3630	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3631}
3632
3633static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3634						bool enable)
3635{
3636	u32 data, orig;
3637
3638	orig = data = RREG32(mmRLC_PG_CNTL);
3639	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3640		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3641	else
3642		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3643	if (orig != data)
3644		WREG32(mmRLC_PG_CNTL, data);
3645}
3646
3647static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3648						bool enable)
3649{
3650	u32 data, orig;
3651
3652	orig = data = RREG32(mmRLC_PG_CNTL);
3653	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3654		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3655	else
3656		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3657	if (orig != data)
3658		WREG32(mmRLC_PG_CNTL, data);
3659}
3660
3661static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3662{
3663	u32 data, orig;
3664
3665	orig = data = RREG32(mmRLC_PG_CNTL);
3666	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3667		data &= ~0x8000;
3668	else
3669		data |= 0x8000;
3670	if (orig != data)
3671		WREG32(mmRLC_PG_CNTL, data);
3672}
3673
3674static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3675{
3676	u32 data, orig;
3677
3678	orig = data = RREG32(mmRLC_PG_CNTL);
3679	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3680		data &= ~0x2000;
3681	else
3682		data |= 0x2000;
3683	if (orig != data)
3684		WREG32(mmRLC_PG_CNTL, data);
3685}
3686
3687static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev)
3688{
3689	if (adev->asic_type == CHIP_KAVERI)
3690		return 5;
3691	else
3692		return 4;
3693}
3694
3695static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3696				     bool enable)
3697{
3698	u32 data, orig;
3699
3700	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3701		orig = data = RREG32(mmRLC_PG_CNTL);
3702		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3703		if (orig != data)
3704			WREG32(mmRLC_PG_CNTL, data);
3705
3706		orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3707		data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3708		if (orig != data)
3709			WREG32(mmRLC_AUTO_PG_CTRL, data);
3710	} else {
3711		orig = data = RREG32(mmRLC_PG_CNTL);
3712		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3713		if (orig != data)
3714			WREG32(mmRLC_PG_CNTL, data);
3715
3716		orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3717		data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3718		if (orig != data)
3719			WREG32(mmRLC_AUTO_PG_CTRL, data);
3720
3721		data = RREG32(mmDB_RENDER_CONTROL);
3722	}
3723}
3724
3725static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3726						 u32 bitmap)
3727{
3728	u32 data;
3729
3730	if (!bitmap)
3731		return;
3732
3733	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3734	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3735
3736	WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3737}
3738
3739static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3740{
3741	u32 data, mask;
3742
3743	data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3744	data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3745
3746	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3747	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3748
3749	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3750
3751	return (~data) & mask;
3752}
3753
3754static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3755{
3756	u32 tmp;
3757
3758	WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3759
3760	tmp = RREG32(mmRLC_MAX_PG_CU);
3761	tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3762	tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3763	WREG32(mmRLC_MAX_PG_CU, tmp);
3764}
3765
3766static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3767					    bool enable)
3768{
3769	u32 data, orig;
3770
3771	orig = data = RREG32(mmRLC_PG_CNTL);
3772	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3773		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3774	else
3775		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3776	if (orig != data)
3777		WREG32(mmRLC_PG_CNTL, data);
3778}
3779
3780static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3781					     bool enable)
3782{
3783	u32 data, orig;
3784
3785	orig = data = RREG32(mmRLC_PG_CNTL);
3786	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3787		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3788	else
3789		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3790	if (orig != data)
3791		WREG32(mmRLC_PG_CNTL, data);
3792}
3793
3794#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3795#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3796
3797static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3798{
3799	u32 data, orig;
3800	u32 i;
3801
3802	if (adev->gfx.rlc.cs_data) {
3803		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3804		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3805		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3806		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3807	} else {
3808		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3809		for (i = 0; i < 3; i++)
3810			WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3811	}
3812	if (adev->gfx.rlc.reg_list) {
3813		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3814		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3815			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3816	}
3817
3818	orig = data = RREG32(mmRLC_PG_CNTL);
3819	data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3820	if (orig != data)
3821		WREG32(mmRLC_PG_CNTL, data);
3822
3823	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3824	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3825
3826	data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3827	data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3828	data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3829	WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3830
3831	data = 0x10101010;
3832	WREG32(mmRLC_PG_DELAY, data);
3833
3834	data = RREG32(mmRLC_PG_DELAY_2);
3835	data &= ~0xff;
3836	data |= 0x3;
3837	WREG32(mmRLC_PG_DELAY_2, data);
3838
3839	data = RREG32(mmRLC_AUTO_PG_CTRL);
3840	data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3841	data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3842	WREG32(mmRLC_AUTO_PG_CTRL, data);
3843
3844}
3845
3846static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3847{
3848	gfx_v7_0_enable_gfx_cgpg(adev, enable);
3849	gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3850	gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3851}
3852
3853static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3854{
3855	u32 count = 0;
3856	const struct cs_section_def *sect = NULL;
3857	const struct cs_extent_def *ext = NULL;
3858
3859	if (adev->gfx.rlc.cs_data == NULL)
3860		return 0;
3861
3862	/* begin clear state */
3863	count += 2;
3864	/* context control state */
3865	count += 3;
3866
3867	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3868		for (ext = sect->section; ext->extent != NULL; ++ext) {
3869			if (sect->id == SECT_CONTEXT)
3870				count += 2 + ext->reg_count;
3871			else
3872				return 0;
3873		}
3874	}
3875	/* pa_sc_raster_config/pa_sc_raster_config1 */
3876	count += 4;
3877	/* end clear state */
3878	count += 2;
3879	/* clear state */
3880	count += 2;
3881
3882	return count;
3883}
3884
3885static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
3886{
3887	u32 count = 0;
3888
3889	if (adev->gfx.rlc.cs_data == NULL)
3890		return;
3891	if (buffer == NULL)
3892		return;
3893
3894	count = amdgpu_gfx_csb_preamble_start(buffer);
3895	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);
3896
3897	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3898	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3899	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
3900	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
3901
3902	amdgpu_gfx_csb_preamble_end(buffer, count);
3903}
3904
3905static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
3906{
3907	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3908			      AMD_PG_SUPPORT_GFX_SMG |
3909			      AMD_PG_SUPPORT_GFX_DMG |
3910			      AMD_PG_SUPPORT_CP |
3911			      AMD_PG_SUPPORT_GDS |
3912			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
3913		gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
3914		gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
3915		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3916			gfx_v7_0_init_gfx_cgpg(adev);
3917			gfx_v7_0_enable_cp_pg(adev, true);
3918			gfx_v7_0_enable_gds_pg(adev, true);
3919		}
3920		gfx_v7_0_init_ao_cu_mask(adev);
3921		gfx_v7_0_update_gfx_pg(adev, true);
3922	}
3923}
3924
3925static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
3926{
3927	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3928			      AMD_PG_SUPPORT_GFX_SMG |
3929			      AMD_PG_SUPPORT_GFX_DMG |
3930			      AMD_PG_SUPPORT_CP |
3931			      AMD_PG_SUPPORT_GDS |
3932			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
3933		gfx_v7_0_update_gfx_pg(adev, false);
3934		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3935			gfx_v7_0_enable_cp_pg(adev, false);
3936			gfx_v7_0_enable_gds_pg(adev, false);
3937		}
3938	}
3939}
3940
3941/**
3942 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
3943 *
3944 * @adev: amdgpu_device pointer
3945 *
3946 * Fetches a GPU clock counter snapshot (SI).
3947 * Returns the 64 bit clock counter snapshot.
3948 */
3949static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3950{
3951	uint64_t clock;
3952
3953	mutex_lock(&adev->gfx.gpu_clock_mutex);
3954	WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3955	clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3956		((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3957	mutex_unlock(&adev->gfx.gpu_clock_mutex);
3958	return clock;
3959}
3960
3961static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3962					  uint32_t vmid,
3963					  uint32_t gds_base, uint32_t gds_size,
3964					  uint32_t gws_base, uint32_t gws_size,
3965					  uint32_t oa_base, uint32_t oa_size)
3966{
3967	/* GDS Base */
3968	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3969	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3970				WRITE_DATA_DST_SEL(0)));
3971	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3972	amdgpu_ring_write(ring, 0);
3973	amdgpu_ring_write(ring, gds_base);
3974
3975	/* GDS Size */
3976	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3977	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3978				WRITE_DATA_DST_SEL(0)));
3979	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3980	amdgpu_ring_write(ring, 0);
3981	amdgpu_ring_write(ring, gds_size);
3982
3983	/* GWS */
3984	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3985	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3986				WRITE_DATA_DST_SEL(0)));
3987	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3988	amdgpu_ring_write(ring, 0);
3989	amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3990
3991	/* OA */
3992	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3993	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3994				WRITE_DATA_DST_SEL(0)));
3995	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3996	amdgpu_ring_write(ring, 0);
3997	amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3998}
3999
4000static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4001{
4002	struct amdgpu_device *adev = ring->adev;
4003	uint32_t value = 0;
4004
4005	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4006	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4007	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4008	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4009	WREG32(mmSQ_CMD, value);
4010}
4011
4012static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4013{
4014	WREG32(mmSQ_IND_INDEX,
4015		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4016		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4017		(address << SQ_IND_INDEX__INDEX__SHIFT) |
4018		(SQ_IND_INDEX__FORCE_READ_MASK));
4019	return RREG32(mmSQ_IND_DATA);
4020}
4021
4022static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4023			   uint32_t wave, uint32_t thread,
4024			   uint32_t regno, uint32_t num, uint32_t *out)
4025{
4026	WREG32(mmSQ_IND_INDEX,
4027		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4028		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4029		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4030		(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4031		(SQ_IND_INDEX__FORCE_READ_MASK) |
4032		(SQ_IND_INDEX__AUTO_INCR_MASK));
4033	while (num--)
4034		*(out++) = RREG32(mmSQ_IND_DATA);
4035}
4036
4037static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4038{
4039	/* type 0 wave data */
4040	dst[(*no_fields)++] = 0;
4041	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4042	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4043	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4044	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4045	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4046	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4047	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4048	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4049	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4050	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4051	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4052	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4053	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4054	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4055	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4056	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4057	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4058	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4059	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
4060}
4061
4062static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4063				     uint32_t wave, uint32_t start,
4064				     uint32_t size, uint32_t *dst)
4065{
4066	wave_read_regs(
4067		adev, simd, wave, 0,
4068		start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4069}
4070
4071static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4072				  u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4073{
4074	cik_srbm_select(adev, me, pipe, q, vm);
4075}
4076
4077static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4078	.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4079	.select_se_sh = &gfx_v7_0_select_se_sh,
4080	.read_wave_data = &gfx_v7_0_read_wave_data,
4081	.read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4082	.select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
4083};
4084
4085static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4086	.is_rlc_enabled = gfx_v7_0_is_rlc_enabled,
4087	.set_safe_mode = gfx_v7_0_set_safe_mode,
4088	.unset_safe_mode = gfx_v7_0_unset_safe_mode,
4089	.init = gfx_v7_0_rlc_init,
4090	.get_csb_size = gfx_v7_0_get_csb_size,
4091	.get_csb_buffer = gfx_v7_0_get_csb_buffer,
4092	.get_cp_table_num = gfx_v7_0_cp_pg_table_num,
4093	.resume = gfx_v7_0_rlc_resume,
4094	.stop = gfx_v7_0_rlc_stop,
4095	.reset = gfx_v7_0_rlc_reset,
4096	.start = gfx_v7_0_rlc_start,
4097	.update_spm_vmid = gfx_v7_0_update_spm_vmid
4098};
4099
4100static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block)
4101{
4102	struct amdgpu_device *adev = ip_block->adev;
4103
4104	adev->gfx.xcc_mask = 1;
4105	adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4106	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4107					  AMDGPU_MAX_COMPUTE_RINGS);
4108	adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4109	adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4110	gfx_v7_0_set_ring_funcs(adev);
4111	gfx_v7_0_set_irq_funcs(adev);
4112	gfx_v7_0_set_gds_init(adev);
4113
4114	return 0;
4115}
4116
4117static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block)
4118{
4119	struct amdgpu_device *adev = ip_block->adev;
4120	int r;
4121
4122	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4123	if (r)
4124		return r;
4125
4126	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4127	if (r)
4128		return r;
4129
4130	return 0;
4131}
4132
4133static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4134{
4135	u32 gb_addr_config;
4136	u32 mc_arb_ramcfg;
4137	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4138	u32 tmp;
4139
4140	switch (adev->asic_type) {
4141	case CHIP_BONAIRE:
4142		adev->gfx.config.max_shader_engines = 2;
4143		adev->gfx.config.max_tile_pipes = 4;
4144		adev->gfx.config.max_cu_per_sh = 7;
4145		adev->gfx.config.max_sh_per_se = 1;
4146		adev->gfx.config.max_backends_per_se = 2;
4147		adev->gfx.config.max_texture_channel_caches = 4;
4148		adev->gfx.config.max_gprs = 256;
4149		adev->gfx.config.max_gs_threads = 32;
4150		adev->gfx.config.max_hw_contexts = 8;
4151
4152		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4153		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4154		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4155		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4156		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4157		break;
4158	case CHIP_HAWAII:
4159		adev->gfx.config.max_shader_engines = 4;
4160		adev->gfx.config.max_tile_pipes = 16;
4161		adev->gfx.config.max_cu_per_sh = 11;
4162		adev->gfx.config.max_sh_per_se = 1;
4163		adev->gfx.config.max_backends_per_se = 4;
4164		adev->gfx.config.max_texture_channel_caches = 16;
4165		adev->gfx.config.max_gprs = 256;
4166		adev->gfx.config.max_gs_threads = 32;
4167		adev->gfx.config.max_hw_contexts = 8;
4168
4169		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4170		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4171		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4172		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4173		gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4174		break;
4175	case CHIP_KAVERI:
4176		adev->gfx.config.max_shader_engines = 1;
4177		adev->gfx.config.max_tile_pipes = 4;
4178		adev->gfx.config.max_cu_per_sh = 8;
4179		adev->gfx.config.max_backends_per_se = 2;
4180		adev->gfx.config.max_sh_per_se = 1;
4181		adev->gfx.config.max_texture_channel_caches = 4;
4182		adev->gfx.config.max_gprs = 256;
4183		adev->gfx.config.max_gs_threads = 16;
4184		adev->gfx.config.max_hw_contexts = 8;
4185
4186		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4187		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4188		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4189		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4190		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4191		break;
4192	case CHIP_KABINI:
4193	case CHIP_MULLINS:
4194	default:
4195		adev->gfx.config.max_shader_engines = 1;
4196		adev->gfx.config.max_tile_pipes = 2;
4197		adev->gfx.config.max_cu_per_sh = 2;
4198		adev->gfx.config.max_sh_per_se = 1;
4199		adev->gfx.config.max_backends_per_se = 1;
4200		adev->gfx.config.max_texture_channel_caches = 2;
4201		adev->gfx.config.max_gprs = 256;
4202		adev->gfx.config.max_gs_threads = 16;
4203		adev->gfx.config.max_hw_contexts = 8;
4204
4205		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4206		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4207		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4208		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4209		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4210		break;
4211	}
4212
4213	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4214	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4215
4216	adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
4217				MC_ARB_RAMCFG, NOOFBANK);
4218	adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
4219				MC_ARB_RAMCFG, NOOFRANKS);
4220
4221	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4222	adev->gfx.config.mem_max_burst_length_bytes = 256;
4223	if (adev->flags & AMD_IS_APU) {
4224		/* Get memory bank mapping mode. */
4225		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4226		dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4227		dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4228
4229		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4230		dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4231		dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4232
4233		/* Validate settings in case only one DIMM installed. */
4234		if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4235			dimm00_addr_map = 0;
4236		if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4237			dimm01_addr_map = 0;
4238		if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4239			dimm10_addr_map = 0;
4240		if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4241			dimm11_addr_map = 0;
4242
4243		/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4244		/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4245		if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4246			adev->gfx.config.mem_row_size_in_kb = 2;
4247		else
4248			adev->gfx.config.mem_row_size_in_kb = 1;
4249	} else {
4250		tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4251		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4252		if (adev->gfx.config.mem_row_size_in_kb > 4)
4253			adev->gfx.config.mem_row_size_in_kb = 4;
4254	}
4255	/* XXX use MC settings? */
4256	adev->gfx.config.shader_engine_tile_size = 32;
4257	adev->gfx.config.num_gpus = 1;
4258	adev->gfx.config.multi_gpu_tile_size = 64;
4259
4260	/* fix up row size */
4261	gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4262	switch (adev->gfx.config.mem_row_size_in_kb) {
4263	case 1:
4264	default:
4265		gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4266		break;
4267	case 2:
4268		gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4269		break;
4270	case 4:
4271		gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4272		break;
4273	}
4274	adev->gfx.config.gb_addr_config = gb_addr_config;
4275}
4276
4277static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4278					int mec, int pipe, int queue)
4279{
4280	int r;
4281	unsigned irq_type;
4282	struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4283
4284	/* mec0 is me1 */
4285	ring->me = mec + 1;
4286	ring->pipe = pipe;
4287	ring->queue = queue;
4288
4289	ring->ring_obj = NULL;
4290	ring->use_doorbell = true;
4291	ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
4292	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4293
4294	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4295		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4296		+ ring->pipe;
4297
4298	/* type-2 packets are deprecated on MEC, use type-3 instead */
4299	r = amdgpu_ring_init(adev, ring, 1024,
4300			     &adev->gfx.eop_irq, irq_type,
4301			     AMDGPU_RING_PRIO_DEFAULT, NULL);
4302	if (r)
4303		return r;
4304
4305
4306	return 0;
4307}
4308
4309static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
4310{
4311	struct amdgpu_ring *ring;
4312	struct amdgpu_device *adev = ip_block->adev;
4313	int i, j, k, r, ring_id;
4314
4315	switch (adev->asic_type) {
4316	case CHIP_KAVERI:
4317		adev->gfx.mec.num_mec = 2;
4318		break;
4319	case CHIP_BONAIRE:
4320	case CHIP_HAWAII:
4321	case CHIP_KABINI:
4322	case CHIP_MULLINS:
4323	default:
4324		adev->gfx.mec.num_mec = 1;
4325		break;
4326	}
4327	adev->gfx.mec.num_pipe_per_mec = 4;
4328	adev->gfx.mec.num_queue_per_pipe = 8;
4329
4330	/* EOP Event */
4331	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4332	if (r)
4333		return r;
4334
4335	/* Privileged reg */
4336	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
4337			      &adev->gfx.priv_reg_irq);
4338	if (r)
4339		return r;
4340
4341	/* Privileged inst */
4342	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
4343			      &adev->gfx.priv_inst_irq);
4344	if (r)
4345		return r;
4346
4347	r = gfx_v7_0_init_microcode(adev);
4348	if (r) {
4349		DRM_ERROR("Failed to load gfx firmware!\n");
4350		return r;
4351	}
4352
4353	r = adev->gfx.rlc.funcs->init(adev);
4354	if (r) {
4355		DRM_ERROR("Failed to init rlc BOs!\n");
4356		return r;
4357	}
4358
4359	/* allocate mec buffers */
4360	r = gfx_v7_0_mec_init(adev);
4361	if (r) {
4362		DRM_ERROR("Failed to init MEC BOs!\n");
4363		return r;
4364	}
4365
4366	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4367		ring = &adev->gfx.gfx_ring[i];
4368		ring->ring_obj = NULL;
4369		sprintf(ring->name, "gfx");
4370		r = amdgpu_ring_init(adev, ring, 1024,
4371				     &adev->gfx.eop_irq,
4372				     AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
4373				     AMDGPU_RING_PRIO_DEFAULT, NULL);
4374		if (r)
4375			return r;
4376	}
4377
4378	/* set up the compute queues - allocate horizontally across pipes */
4379	ring_id = 0;
4380	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4381		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4382			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4383				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4384								     k, j))
4385					continue;
4386
4387				r = gfx_v7_0_compute_ring_init(adev,
4388								ring_id,
4389								i, k, j);
4390				if (r)
4391					return r;
4392
4393				ring_id++;
4394			}
4395		}
4396	}
4397
4398	adev->gfx.ce_ram_size = 0x8000;
4399
4400	gfx_v7_0_gpu_early_init(adev);
4401
4402	adev->gfx.gfx_supported_reset =
4403		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4404	adev->gfx.compute_supported_reset =
4405		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4406
4407	return r;
4408}
4409
4410static int gfx_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
4411{
4412	struct amdgpu_device *adev = ip_block->adev;
4413	int i;
4414
4415	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4416		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4417	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4418		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4419
4420	gfx_v7_0_cp_compute_fini(adev);
4421	amdgpu_gfx_rlc_fini(adev);
4422	gfx_v7_0_mec_fini(adev);
4423	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4424				&adev->gfx.rlc.clear_state_gpu_addr,
4425				(void **)&adev->gfx.rlc.cs_ptr);
4426	if (adev->gfx.rlc.cp_table_size) {
4427		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4428				&adev->gfx.rlc.cp_table_gpu_addr,
4429				(void **)&adev->gfx.rlc.cp_table_ptr);
4430	}
4431	gfx_v7_0_free_microcode(adev);
4432
4433	return 0;
4434}
4435
4436static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
4437{
4438	int r;
4439	struct amdgpu_device *adev = ip_block->adev;
4440
4441	gfx_v7_0_constants_init(adev);
4442
4443	/* init CSB */
4444	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4445	/* init rlc */
4446	r = adev->gfx.rlc.funcs->resume(adev);
4447	if (r)
4448		return r;
4449
4450	r = gfx_v7_0_cp_resume(adev);
4451	if (r)
4452		return r;
4453
4454	return r;
4455}
4456
4457static int gfx_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
4458{
4459	struct amdgpu_device *adev = ip_block->adev;
4460
4461	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4462	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4463	gfx_v7_0_cp_enable(adev, false);
4464	adev->gfx.rlc.funcs->stop(adev);
4465	gfx_v7_0_fini_pg(adev);
4466
4467	return 0;
4468}
4469
4470static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block)
4471{
4472	return gfx_v7_0_hw_fini(ip_block);
4473}
4474
4475static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)
4476{
4477	return gfx_v7_0_hw_init(ip_block);
4478}
4479
4480static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
4481{
4482	struct amdgpu_device *adev = ip_block->adev;
4483
4484	if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4485		return false;
4486	else
4487		return true;
4488}
4489
4490static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
4491{
4492	unsigned i;
4493	u32 tmp;
4494	struct amdgpu_device *adev = ip_block->adev;
4495
4496	for (i = 0; i < adev->usec_timeout; i++) {
4497		/* read MC_STATUS */
4498		tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4499
4500		if (!tmp)
4501			return 0;
4502		udelay(1);
4503	}
4504	return -ETIMEDOUT;
4505}
4506
4507static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
4508{
4509	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4510	u32 tmp;
4511	struct amdgpu_device *adev = ip_block->adev;
4512
4513	/* GRBM_STATUS */
4514	tmp = RREG32(mmGRBM_STATUS);
4515	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4516		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4517		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4518		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4519		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4520		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4521		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4522			GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4523
4524	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4525		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4526		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4527	}
4528
4529	/* GRBM_STATUS2 */
4530	tmp = RREG32(mmGRBM_STATUS2);
4531	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4532		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4533
4534	/* SRBM_STATUS */
4535	tmp = RREG32(mmSRBM_STATUS);
4536	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4537		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4538
4539	if (grbm_soft_reset || srbm_soft_reset) {
4540		/* disable CG/PG */
4541		gfx_v7_0_fini_pg(adev);
4542		gfx_v7_0_update_cg(adev, false);
4543
4544		/* stop the rlc */
4545		adev->gfx.rlc.funcs->stop(adev);
4546
4547		/* Disable GFX parsing/prefetching */
4548		WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4549
4550		/* Disable MEC parsing/prefetching */
4551		WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4552
4553		if (grbm_soft_reset) {
4554			tmp = RREG32(mmGRBM_SOFT_RESET);
4555			tmp |= grbm_soft_reset;
4556			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4557			WREG32(mmGRBM_SOFT_RESET, tmp);
4558			tmp = RREG32(mmGRBM_SOFT_RESET);
4559
4560			udelay(50);
4561
4562			tmp &= ~grbm_soft_reset;
4563			WREG32(mmGRBM_SOFT_RESET, tmp);
4564			tmp = RREG32(mmGRBM_SOFT_RESET);
4565		}
4566
4567		if (srbm_soft_reset) {
4568			tmp = RREG32(mmSRBM_SOFT_RESET);
4569			tmp |= srbm_soft_reset;
4570			dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4571			WREG32(mmSRBM_SOFT_RESET, tmp);
4572			tmp = RREG32(mmSRBM_SOFT_RESET);
4573
4574			udelay(50);
4575
4576			tmp &= ~srbm_soft_reset;
4577			WREG32(mmSRBM_SOFT_RESET, tmp);
4578			tmp = RREG32(mmSRBM_SOFT_RESET);
4579		}
4580		/* Wait a little for things to settle down */
4581		udelay(50);
4582	}
4583	return 0;
4584}
4585
4586static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4587						 enum amdgpu_interrupt_state state)
4588{
4589	u32 cp_int_cntl;
4590
4591	switch (state) {
4592	case AMDGPU_IRQ_STATE_DISABLE:
4593		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4594		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4595		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4596		break;
4597	case AMDGPU_IRQ_STATE_ENABLE:
4598		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4599		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4600		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4601		break;
4602	default:
4603		break;
4604	}
4605}
4606
4607static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4608						     int me, int pipe,
4609						     enum amdgpu_interrupt_state state)
4610{
4611	u32 mec_int_cntl, mec_int_cntl_reg;
4612
4613	/*
4614	 * amdgpu controls only the first MEC. That's why this function only
4615	 * handles the setting of interrupts for this specific MEC. All other
4616	 * pipes' interrupts are set by amdkfd.
4617	 */
4618
4619	if (me == 1) {
4620		switch (pipe) {
4621		case 0:
4622			mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4623			break;
4624		case 1:
4625			mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4626			break;
4627		case 2:
4628			mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4629			break;
4630		case 3:
4631			mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4632			break;
4633		default:
4634			DRM_DEBUG("invalid pipe %d\n", pipe);
4635			return;
4636		}
4637	} else {
4638		DRM_DEBUG("invalid me %d\n", me);
4639		return;
4640	}
4641
4642	switch (state) {
4643	case AMDGPU_IRQ_STATE_DISABLE:
4644		mec_int_cntl = RREG32(mec_int_cntl_reg);
4645		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4646		WREG32(mec_int_cntl_reg, mec_int_cntl);
4647		break;
4648	case AMDGPU_IRQ_STATE_ENABLE:
4649		mec_int_cntl = RREG32(mec_int_cntl_reg);
4650		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4651		WREG32(mec_int_cntl_reg, mec_int_cntl);
4652		break;
4653	default:
4654		break;
4655	}
4656}
4657
4658static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4659					     struct amdgpu_irq_src *src,
4660					     unsigned type,
4661					     enum amdgpu_interrupt_state state)
4662{
4663	u32 cp_int_cntl;
4664
4665	switch (state) {
4666	case AMDGPU_IRQ_STATE_DISABLE:
4667		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4668		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4669		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4670		break;
4671	case AMDGPU_IRQ_STATE_ENABLE:
4672		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4673		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4674		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4675		break;
4676	default:
4677		break;
4678	}
4679
4680	return 0;
4681}
4682
4683static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4684					      struct amdgpu_irq_src *src,
4685					      unsigned type,
4686					      enum amdgpu_interrupt_state state)
4687{
4688	u32 cp_int_cntl;
4689
4690	switch (state) {
4691	case AMDGPU_IRQ_STATE_DISABLE:
4692		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4693		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4694		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4695		break;
4696	case AMDGPU_IRQ_STATE_ENABLE:
4697		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4698		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4699		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4700		break;
4701	default:
4702		break;
4703	}
4704
4705	return 0;
4706}
4707
4708static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4709					    struct amdgpu_irq_src *src,
4710					    unsigned type,
4711					    enum amdgpu_interrupt_state state)
4712{
4713	switch (type) {
4714	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4715		gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4716		break;
4717	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4718		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4719		break;
4720	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4721		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4722		break;
4723	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4724		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4725		break;
4726	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4727		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4728		break;
4729	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4730		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4731		break;
4732	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4733		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4734		break;
4735	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4736		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4737		break;
4738	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4739		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4740		break;
4741	default:
4742		break;
4743	}
4744	return 0;
4745}
4746
4747static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4748			    struct amdgpu_irq_src *source,
4749			    struct amdgpu_iv_entry *entry)
4750{
4751	u8 me_id, pipe_id;
4752	struct amdgpu_ring *ring;
4753	int i;
4754
4755	DRM_DEBUG("IH: CP EOP\n");
4756	me_id = (entry->ring_id & 0x0c) >> 2;
4757	pipe_id = (entry->ring_id & 0x03) >> 0;
4758	switch (me_id) {
4759	case 0:
4760		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4761		break;
4762	case 1:
4763	case 2:
4764		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4765			ring = &adev->gfx.compute_ring[i];
4766			if ((ring->me == me_id) && (ring->pipe == pipe_id))
4767				amdgpu_fence_process(ring);
4768		}
4769		break;
4770	}
4771	return 0;
4772}
4773
4774static void gfx_v7_0_fault(struct amdgpu_device *adev,
4775			   struct amdgpu_iv_entry *entry)
4776{
4777	struct amdgpu_ring *ring;
4778	u8 me_id, pipe_id;
4779	int i;
4780
4781	me_id = (entry->ring_id & 0x0c) >> 2;
4782	pipe_id = (entry->ring_id & 0x03) >> 0;
4783	switch (me_id) {
4784	case 0:
4785		drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4786		break;
4787	case 1:
4788	case 2:
4789		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4790			ring = &adev->gfx.compute_ring[i];
4791			if ((ring->me == me_id) && (ring->pipe == pipe_id))
4792				drm_sched_fault(&ring->sched);
4793		}
4794		break;
4795	}
4796}
4797
4798static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4799				 struct amdgpu_irq_src *source,
4800				 struct amdgpu_iv_entry *entry)
4801{
4802	DRM_ERROR("Illegal register access in command stream\n");
4803	gfx_v7_0_fault(adev, entry);
4804	return 0;
4805}
4806
4807static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4808				  struct amdgpu_irq_src *source,
4809				  struct amdgpu_iv_entry *entry)
4810{
4811	DRM_ERROR("Illegal instruction in command stream\n");
4812	// XXX soft reset the gfx block only
4813	gfx_v7_0_fault(adev, entry);
4814	return 0;
4815}
4816
4817static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4818					  enum amd_clockgating_state state)
4819{
4820	bool gate = false;
4821	struct amdgpu_device *adev = ip_block->adev;
4822
4823	if (state == AMD_CG_STATE_GATE)
4824		gate = true;
4825
4826	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4827	/* order matters! */
4828	if (gate) {
4829		gfx_v7_0_enable_mgcg(adev, true);
4830		gfx_v7_0_enable_cgcg(adev, true);
4831	} else {
4832		gfx_v7_0_enable_cgcg(adev, false);
4833		gfx_v7_0_enable_mgcg(adev, false);
4834	}
4835	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4836
4837	return 0;
4838}
4839
4840static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4841					  enum amd_powergating_state state)
4842{
4843	bool gate = false;
4844	struct amdgpu_device *adev = ip_block->adev;
4845
4846	if (state == AMD_PG_STATE_GATE)
4847		gate = true;
4848
4849	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4850			      AMD_PG_SUPPORT_GFX_SMG |
4851			      AMD_PG_SUPPORT_GFX_DMG |
4852			      AMD_PG_SUPPORT_CP |
4853			      AMD_PG_SUPPORT_GDS |
4854			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
4855		gfx_v7_0_update_gfx_pg(adev, gate);
4856		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4857			gfx_v7_0_enable_cp_pg(adev, gate);
4858			gfx_v7_0_enable_gds_pg(adev, gate);
4859		}
4860	}
4861
4862	return 0;
4863}
4864
4865static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring)
4866{
4867	amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
4868	amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
4869			  PACKET3_TC_ACTION_ENA |
4870			  PACKET3_SH_KCACHE_ACTION_ENA |
4871			  PACKET3_SH_ICACHE_ACTION_ENA);  /* CP_COHER_CNTL */
4872	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
4873	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE */
4874	amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
4875}
4876
4877static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
4878{
4879	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
4880	amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
4881			  PACKET3_TC_ACTION_ENA |
4882			  PACKET3_SH_KCACHE_ACTION_ENA |
4883			  PACKET3_SH_ICACHE_ACTION_ENA);  /* CP_COHER_CNTL */
4884	amdgpu_ring_write(ring, 0xffffffff);	/* CP_COHER_SIZE */
4885	amdgpu_ring_write(ring, 0xff);		/* CP_COHER_SIZE_HI */
4886	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE */
4887	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE_HI */
4888	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */
4889}
4890
4891static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4892	.name = "gfx_v7_0",
4893	.early_init = gfx_v7_0_early_init,
4894	.late_init = gfx_v7_0_late_init,
4895	.sw_init = gfx_v7_0_sw_init,
4896	.sw_fini = gfx_v7_0_sw_fini,
4897	.hw_init = gfx_v7_0_hw_init,
4898	.hw_fini = gfx_v7_0_hw_fini,
4899	.suspend = gfx_v7_0_suspend,
4900	.resume = gfx_v7_0_resume,
4901	.is_idle = gfx_v7_0_is_idle,
4902	.wait_for_idle = gfx_v7_0_wait_for_idle,
4903	.soft_reset = gfx_v7_0_soft_reset,
4904	.set_clockgating_state = gfx_v7_0_set_clockgating_state,
4905	.set_powergating_state = gfx_v7_0_set_powergating_state,
4906};
4907
4908static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4909	.type = AMDGPU_RING_TYPE_GFX,
4910	.align_mask = 0xff,
4911	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
4912	.support_64bit_ptrs = false,
4913	.get_rptr = gfx_v7_0_ring_get_rptr,
4914	.get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4915	.set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4916	.emit_frame_size =
4917		20 + /* gfx_v7_0_ring_emit_gds_switch */
4918		7 + /* gfx_v7_0_ring_emit_hdp_flush */
4919		5 + /* hdp invalidate */
4920		12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
4921		7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
4922		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
4923		3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
4924		5, /* SURFACE_SYNC */
4925	.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
4926	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4927	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4928	.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4929	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4930	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4931	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4932	.test_ring = gfx_v7_0_ring_test_ring,
4933	.test_ib = gfx_v7_0_ring_test_ib,
4934	.insert_nop = amdgpu_ring_insert_nop,
4935	.pad_ib = amdgpu_ring_generic_pad_ib,
4936	.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
4937	.emit_wreg = gfx_v7_0_ring_emit_wreg,
4938	.soft_recovery = gfx_v7_0_ring_soft_recovery,
4939	.emit_mem_sync = gfx_v7_0_emit_mem_sync,
4940};
4941
4942static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4943	.type = AMDGPU_RING_TYPE_COMPUTE,
4944	.align_mask = 0xff,
4945	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
4946	.support_64bit_ptrs = false,
4947	.get_rptr = gfx_v7_0_ring_get_rptr,
4948	.get_wptr = gfx_v7_0_ring_get_wptr_compute,
4949	.set_wptr = gfx_v7_0_ring_set_wptr_compute,
4950	.emit_frame_size =
4951		20 + /* gfx_v7_0_ring_emit_gds_switch */
4952		7 + /* gfx_v7_0_ring_emit_hdp_flush */
4953		5 + /* hdp invalidate */
4954		7 + /* gfx_v7_0_ring_emit_pipeline_sync */
4955		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
4956		7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
4957		7, /* gfx_v7_0_emit_mem_sync_compute */
4958	.emit_ib_size =	7, /* gfx_v7_0_ring_emit_ib_compute */
4959	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
4960	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
4961	.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4962	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4963	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4964	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4965	.test_ring = gfx_v7_0_ring_test_ring,
4966	.test_ib = gfx_v7_0_ring_test_ib,
4967	.insert_nop = amdgpu_ring_insert_nop,
4968	.pad_ib = amdgpu_ring_generic_pad_ib,
4969	.emit_wreg = gfx_v7_0_ring_emit_wreg,
4970	.soft_recovery = gfx_v7_0_ring_soft_recovery,
4971	.emit_mem_sync = gfx_v7_0_emit_mem_sync_compute,
4972};
4973
4974static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4975{
4976	int i;
4977
4978	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4979		adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4980	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4981		adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
4982}
4983
4984static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
4985	.set = gfx_v7_0_set_eop_interrupt_state,
4986	.process = gfx_v7_0_eop_irq,
4987};
4988
4989static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
4990	.set = gfx_v7_0_set_priv_reg_fault_state,
4991	.process = gfx_v7_0_priv_reg_irq,
4992};
4993
4994static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
4995	.set = gfx_v7_0_set_priv_inst_fault_state,
4996	.process = gfx_v7_0_priv_inst_irq,
4997};
4998
4999static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5000{
5001	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5002	adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5003
5004	adev->gfx.priv_reg_irq.num_types = 1;
5005	adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5006
5007	adev->gfx.priv_inst_irq.num_types = 1;
5008	adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5009}
5010
5011static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5012{
5013	/* init asci gds info */
5014	adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
5015	adev->gds.gws_size = 64;
5016	adev->gds.oa_size = 16;
5017	adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
5018}
5019
5020
5021static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5022{
5023	int i, j, k, counter, active_cu_number = 0;
5024	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5025	struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5026	unsigned disable_masks[4 * 2];
5027	u32 ao_cu_num;
5028
5029	if (adev->flags & AMD_IS_APU)
5030		ao_cu_num = 2;
5031	else
5032		ao_cu_num = adev->gfx.config.max_cu_per_sh;
5033
5034	memset(cu_info, 0, sizeof(*cu_info));
5035
5036	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5037
5038	mutex_lock(&adev->grbm_idx_mutex);
5039	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5040		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5041			mask = 1;
5042			ao_bitmap = 0;
5043			counter = 0;
5044			gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5045			if (i < 4 && j < 2)
5046				gfx_v7_0_set_user_cu_inactive_bitmap(
5047					adev, disable_masks[i * 2 + j]);
5048			bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5049			cu_info->bitmap[0][i][j] = bitmap;
5050
5051			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5052				if (bitmap & mask) {
5053					if (counter < ao_cu_num)
5054						ao_bitmap |= mask;
5055					counter++;
5056				}
5057				mask <<= 1;
5058			}
5059			active_cu_number += counter;
5060			if (i < 2 && j < 2)
5061				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5062			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5063		}
5064	}
5065	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5066	mutex_unlock(&adev->grbm_idx_mutex);
5067
5068	cu_info->number = active_cu_number;
5069	cu_info->ao_cu_mask = ao_cu_mask;
5070	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5071	cu_info->max_waves_per_simd = 10;
5072	cu_info->max_scratch_slots_per_cu = 32;
5073	cu_info->wave_front_size = 64;
5074	cu_info->lds_size = 64;
5075}
5076
5077const struct amdgpu_ip_block_version gfx_v7_1_ip_block = {
5078	.type = AMD_IP_BLOCK_TYPE_GFX,
5079	.major = 7,
5080	.minor = 1,
5081	.rev = 0,
5082	.funcs = &gfx_v7_0_ip_funcs,
5083};
5084
5085const struct amdgpu_ip_block_version gfx_v7_2_ip_block = {
5086	.type = AMD_IP_BLOCK_TYPE_GFX,
5087	.major = 7,
5088	.minor = 2,
5089	.rev = 0,
5090	.funcs = &gfx_v7_0_ip_funcs,
5091};
5092
5093const struct amdgpu_ip_block_version gfx_v7_3_ip_block = {
5094	.type = AMD_IP_BLOCK_TYPE_GFX,
5095	.major = 7,
5096	.minor = 3,
5097	.rev = 0,
5098	.funcs = &gfx_v7_0_ip_funcs,
5099};