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gfx_v10_0.c

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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c C 
    1/*
    2 * Copyright 2019 Advanced Micro Devices, Inc.
    3 *
    4 * Permission is hereby granted, free of charge, to any person obtaining a
    5 * copy of this software and associated documentation files (the "Software"),
    6 * to deal in the Software without restriction, including without limitation
    7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8 * and/or sell copies of the Software, and to permit persons to whom the
    9 * Software is furnished to do so, subject to the following conditions:
   10 *
   11 * The above copyright notice and this permission notice shall be included in
   12 * all copies or substantial portions of the Software.
   13 *
   14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
   18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
   19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
   20 * OTHER DEALINGS IN THE SOFTWARE.
   21 *
   22 */
   23
   24#include <linux/delay.h>
   25#include <linux/kernel.h>
   26#include <linux/firmware.h>
   27#include <linux/module.h>
   28#include <linux/pci.h>
   29#include "amdgpu.h"
   30#include "amdgpu_gfx.h"
   31#include "amdgpu_psp.h"
   32#include "nv.h"
   33#include "nvd.h"
   34
   35#include "gc/gc_10_1_0_offset.h"
   36#include "gc/gc_10_1_0_sh_mask.h"
   37#include "smuio/smuio_11_0_0_offset.h"
   38#include "smuio/smuio_11_0_0_sh_mask.h"
   39#include "navi10_enum.h"
   40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
   41
   42#include "soc15.h"
   43#include "soc15_common.h"
   44#include "clearstate_gfx10.h"
   45#include "v10_structs.h"
   46#include "gfx_v10_0.h"
   47#include "gfx_v10_0_cleaner_shader.h"
   48#include "nbio_v2_3.h"
   49
   50/*
   51 * Navi10 has two graphic rings to share each graphic pipe.
   52 * 1. Primary ring
   53 * 2. Async ring
   54 */
   55#define GFX10_NUM_GFX_RINGS_NV1X	1
   56#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
   57#define GFX10_MEC_HPD_SIZE	2048
   58
   59#define F32_CE_PROGRAM_RAM_SIZE		65536
   60#define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
   61
   62#define mmCGTT_GS_NGG_CLK_CTRL	0x5087
   63#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
   64#define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
   65#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
   66#define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
   67#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
   68
   69#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
   70#define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
   71
   72#define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
   73#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
   74#define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
   75#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
   76
   77#define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
   78#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
   79#define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
   80#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
   81#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
   82#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
   83#define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
   84#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
   85#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
   86#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
   87#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
   88#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
   89#define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
   90#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
   91#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
   92#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
   93#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
   94#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
   95#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
   96#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
   97#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
   98#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
   99#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
  100#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
  101#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
  102#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
  103#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
  104
  105#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
  106#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
  107#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
  108#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
  109
  110#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
  111#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
  112#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
  113#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
  114
  115#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
  116#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
  117#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
  118#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
  119
  120#define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
  121#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
  122#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
  123#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
  124#define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
  125#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
  126#define mmVGT_TF_RING_SIZE_Vangogh               0x224e
  127#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
  128#define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
  129#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
  130#define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
  131#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
  132#define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
  133#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
  134#define mmSPI_CONFIG_CNTL_Vangogh                0x2440
  135#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
  136#define mmGCR_GENERAL_CNTL_Vangogh               0x1580
  137#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
  138#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
  139
  140#define mmCP_HYP_PFP_UCODE_ADDR			0x5814
  141#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
  142#define mmCP_HYP_PFP_UCODE_DATA			0x5815
  143#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
  144#define mmCP_HYP_CE_UCODE_ADDR			0x5818
  145#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
  146#define mmCP_HYP_CE_UCODE_DATA			0x5819
  147#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
  148#define mmCP_HYP_ME_UCODE_ADDR			0x5816
  149#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
  150#define mmCP_HYP_ME_UCODE_DATA			0x5817
  151#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
  152
  153#define mmCPG_PSP_DEBUG				0x5c10
  154#define mmCPG_PSP_DEBUG_BASE_IDX		1
  155#define mmCPC_PSP_DEBUG				0x5c11
  156#define mmCPC_PSP_DEBUG_BASE_IDX		1
  157#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
  158#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
  159
  160//CC_GC_SA_UNIT_DISABLE
  161#define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
  162#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
  163#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
  164#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
  165//GC_USER_SA_UNIT_DISABLE
  166#define mmGC_USER_SA_UNIT_DISABLE               0x0fea
  167#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
  168#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
  169#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
  170//PA_SC_ENHANCE_3
  171#define mmPA_SC_ENHANCE_3                       0x1085
  172#define mmPA_SC_ENHANCE_3_BASE_IDX              0
  173#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
  174#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
  175
  176#define mmCGTT_SPI_CS_CLK_CTRL			0x507c
  177#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
  178
  179#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid		0x16f3
  180#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
  181#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
  182#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
  183
  184#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
  185#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
  186
  187#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
  188#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
  189
  190MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  191MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  192MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  193MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  194MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  195MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  196
  197MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
  198MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
  199MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
  200MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
  201MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
  202MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  203MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  204MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  205MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  206MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  207MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  208
  209MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  210MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  211MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  212MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  213MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  214MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  215
  216MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
  217MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
  218MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
  219MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
  220MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
  221MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
  222
  223MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
  224MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
  225MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
  226MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
  227MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
  228MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
  229
  230MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
  231MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
  232MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
  233MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
  234MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
  235MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
  236
  237MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
  238MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
  239MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
  240MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
  241MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
  242MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
  243
  244MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
  245MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
  246MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
  247MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
  248MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
  249MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
  250
  251MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
  252MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
  253MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
  254MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
  255MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
  256MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
  257
  258MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
  259MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
  260MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
  261MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
  262MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
  263MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
  264
  265MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
  266MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
  267MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
  268MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
  269MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
  270MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
  271
  272MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
  273MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
  274MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
  275MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
  276MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
  277MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
  278
  279static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
  280	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
  281	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
  282	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
  283	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
  284	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
  285	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
  286	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
  287	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
  288	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
  289	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
  290	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
  291	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
  292	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
  293	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
  294	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
  295	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
  296	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
  297	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
  298	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
  299	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
  300	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
  301	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
  302	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
  303	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
  304	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
  305	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
  306	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
  307	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
  308	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
  309	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
  310	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
  311	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
  312	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
  313	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
  314	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
  315	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
  316	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
  317	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
  318	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
  319	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
  320	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
  321	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
  322	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
  323	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
  324	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
  325	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
  326	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
  327	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
  328	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
  329	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
  330	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
  331	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
  332	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
  333	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
  334	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
  335	SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
  336	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
  337	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
  338	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
  339	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
  340	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
  341	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
  342	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
  343	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
  344	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
  345	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
  346	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
  347	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
  348	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
  349	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
  350	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
  351	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
  352	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
  353	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
  354	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
  355	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
  356	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
  357	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
  358	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
  359	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
  360	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
  361	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
  362	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
  363	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
  364	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
  365	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
  366	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
  367	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
  368	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
  369	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
  370	/* cp header registers */
  371	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
  372	/* SE status registers */
  373	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
  374	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
  375	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
  376	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
  377};
  378
  379static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
  380	/* compute registers */
  381	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
  382	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
  383	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
  384	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
  385	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
  386	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
  387	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
  388	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
  389	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
  390	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
  391	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
  392	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
  393	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
  394	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
  395	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
  396	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
  397	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
  398	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
  399	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
  400	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
  401	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
  402	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
  403	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
  404	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
  405	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
  406	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
  407	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
  408	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
  409	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
  410	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
  411	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
  412	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
  413	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
  414	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
  415	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
  416	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
  417	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
  418	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
  419	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),
  420	/* cp header registers */
  421	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  422	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  423	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  424	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  425	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  426	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  427	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  428	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
  429};
  430
  431static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
  432	/* gfx queue registers */
  433	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
  434	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
  435	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
  436	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
  437	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
  438	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
  439	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
  440	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
  441	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
  442	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
  443	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
  444	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
  445	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
  446	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
  447	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
  448	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
  449	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
  450	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
  451	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
  452	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
  453	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
  454	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
  455	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),
  456	/* gfx header registers */
  457	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  458	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  459	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  460	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  461	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  462	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  463	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  464	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
  465	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  466	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  467	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  468	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  469	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  470	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  471	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  472	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
  473	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  474	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  475	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  476	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  477	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  478	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  479	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  480	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
  481};
  482
  483static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
  484	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  485	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  486	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
  487	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  488	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  489	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
  490	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
  491	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
  492	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
  493	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
  494	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
  495	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
  496	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
  497	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
  498	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
  499	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
  500	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
  501	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
  502	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
  503	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
  504	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
  505	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
  506	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
  507	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
  508	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
  509	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
  510	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
  511	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
  512	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
  513	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
  514	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
  515	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
  516	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
  517	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
  518	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
  519	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
  520	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
  521	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
  522	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
  523	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
  524};
  525
  526static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
  527	/* Pending on emulation bring up */
  528};
  529
  530static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
  531	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
  532	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  533	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
  534	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  535	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  536	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  537	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
  538	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  539	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  540	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  541	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
  542	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  543	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  544	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  545	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
  546	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  547	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
  548	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  549	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
  550	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  551	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  552	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  553	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
  554	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  555	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  556	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  557	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
  558	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  559	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  560	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  561	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
  562	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  563	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  564	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  565	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
  566	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  567	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  568	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  569	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
  570	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  571	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  572	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  573	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
  574	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  575	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
  576	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  577	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
  578	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  579	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  580	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  581	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
  582	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  583	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
  584	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  585	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
  586	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  587	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
  588	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  589	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
  590	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  591	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
  592	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  593	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
  594	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  595	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
  596	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  597	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
  598	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  599	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
  600	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  601	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
  602	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  603	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
  604	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  605	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
  606	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  607	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
  608	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  609	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
  610	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  611	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  612	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  613	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
  614	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  615	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
  616	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  617	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
  618	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  619	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  620	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  621	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
  622	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  623	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  624	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  625	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
  626	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  627	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
  628	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  629	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
  630	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  631	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
  632	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  633	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
  634	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  635	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
  636	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  637	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
  638	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  639	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
  640	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  641	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
  642	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  643	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
  644	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  645	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
  646	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  647	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
  648	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  649	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
  650	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  651	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
  652	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  653	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
  654	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  655	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
  656	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  657	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
  658	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  659	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  660	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  661	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
  662	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  663	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
  664	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  665	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
  666	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  667	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
  668	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  669	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
  670	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  671	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
  672	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  673	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
  674	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  675	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
  676	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  677	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
  678	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  679	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  680	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  681	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
  682	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  683	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
  684	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  685	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
  686	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  687	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
  688	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  689	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
  690	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  691	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  692	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  693	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
  694	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  695	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  696	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  697	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
  698	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  699	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  700	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  701	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
  702	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  703	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
  704	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  705	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
  706	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  707	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
  708	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  709	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
  710	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  711	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  712	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  713	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
  714	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  715	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
  716	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  717	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
  718	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  719	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
  720	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  721	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
  722	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  723	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
  724	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  725	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
  726	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  727	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  728	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  729	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
  730	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  731	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
  732	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  733	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
  734	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  735	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
  736	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  737	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
  738	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  739	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  740	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  741	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
  742	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  743	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
  744	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  745	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
  746	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  747	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
  748	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  749	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
  750	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  751	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
  752	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  753	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
  754	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  755	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  756	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  757	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
  758	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  759	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
  760	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  761	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
  762	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  763	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
  764	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  765	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
  766	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  767	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
  768	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  769	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
  770	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  771	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
  772	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  773	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
  774	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  775	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  776	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  777	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
  778	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  779	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  780	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  781	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
  782	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  783	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  784	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  785	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
  786	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  787	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  788	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  789	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
  790	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  791	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  792	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  793	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
  794	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  795	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  796	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  797	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
  798	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  799	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
  800	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  801	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
  802	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  803	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
  804	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  805	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
  806	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  807	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  808	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  809	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
  810	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  811	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  812	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  813	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
  814	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  815	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  816	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  817	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
  818	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  819	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  820	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  821	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
  822	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  823	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
  824	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  825	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
  826	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  827	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
  828	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  829	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
  830	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  831	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  832	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  833	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
  834	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  835	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  836	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  837	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
  838	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  839	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  840	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  841	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
  842	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  843	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  844	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  845	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
  846	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  847	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  848	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  849	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
  850	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  851	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  852	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  853	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
  854	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  855	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  856	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  857	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
  858	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  859	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
  860	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  861	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
  862	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  863	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
  864	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  865	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
  866	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  867	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
  868	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  869	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
  870	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  871	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  872	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  873	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
  874	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  875	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  876	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  877	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
  878	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  879	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  880	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  881	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
  882	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  883	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
  884	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  885	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
  886	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  887	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
  888	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  889	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
  890	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  891	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
  892	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  893	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
  894	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  895	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  896	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  897	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
  898	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  899	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
  900	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  901	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
  902	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  903	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
  904	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  905	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
  906	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  907	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
  908	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  909	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
  910	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  911	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  912	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  913	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
  914	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  915	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  916	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  917	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
  918	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  919	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  920	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  921	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
  922	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  923	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
  924	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  925	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
  926	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  927	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
  928	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  929	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
  930	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  931	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
  932	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  933	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
  934	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  935	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  936	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  937	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
  938	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  939	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  940	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  941	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
  942	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  943	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  944	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  945	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
  946	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  947	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
  948	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  949	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
  950	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  951	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
  952	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  953	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
  954	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  955	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
  956	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  957	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
  958	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  959	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
  960	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  961	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
  962	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  963	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
  964	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  965	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
  966	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  967	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  968	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  969	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
  970	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  971	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  972	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  973	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
  974	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  975	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
  976	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  977	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
  978	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  979	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
  980	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  981	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
  982	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  983	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  984	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  985	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
  986	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  987	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
  988	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  989	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
  990	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  991	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
  992	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  993	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
  994	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
  995	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
  996	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  997	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
  998	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
  999	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1000	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1001	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 1002	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1003	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1004	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1005	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 1006	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1007	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1008	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1009	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 1010	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1011	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1012	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1013	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 1014	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1015	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1016	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1017	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 1018	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1019	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1020	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1021	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 1022	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1023	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1024	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1025	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 1026	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1027	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1028	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1029	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 1030	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1031	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1032	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1033	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 1034	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1035	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1036	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1037	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 1038	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1039	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1040	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1041	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 1042	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1043	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1044	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1045	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 1046	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1047	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1048	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1049	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 1050	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1051	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1052	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1053	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 1054	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1055	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1056	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1057	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 1058	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1059	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1060	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1061	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 1062	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1063	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1064	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1065	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 1066	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1067	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1068	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1069	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 1070	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1071	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1072	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1073	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 1074	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1075	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1076	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1077	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 1078	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1079	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1080	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1081	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 1082	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1083	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1084	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1085	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 1086	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1087	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1088	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1089	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 1090	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1091	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1092	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1093	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 1094	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1095	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1096	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1097	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 1098	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1099	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1100	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1101	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 1102	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1103	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1104	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1105	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 1106	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1107	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1108	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1109	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 1110	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1111	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1112	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1113	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 1114	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1115	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1116	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1117	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 1118	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1119	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 1120	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1121	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 1122	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1123	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 1124	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1125	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 1126	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1127	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1128	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1129	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 1130	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1131	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1132	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1133	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 1134	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1135	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1136	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1137	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 1138	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1139	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1140	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1141	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 1142	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1143	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 1144	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1145	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 1146	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1147	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 1148	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1149	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 1150	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1151	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1152	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1153	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 1154	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1155	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1156	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1157	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 1158	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1159	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1160	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1161	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 1162	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1163	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1164	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1165	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 1166	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1167	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1168	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1169	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 1170	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1171	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1172	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1173	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 1174	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1175	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 1176	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1177	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 1178	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1179	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 1180	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1181	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 1182	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1183	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1184	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1185	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 1186	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1187	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1188	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1189	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 1190	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1191	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1192	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1193	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 1194	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1195	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1196	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1197	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 1198	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1199	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1200	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1201	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 1202	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1203	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1204	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1205	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 1206	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1207	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1208	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1209	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 1210	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1211	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1212	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1213	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 1214	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1215	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1216	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1217	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 1218	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1219	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1220	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1221	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 1222	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1223	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1224	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1225	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 1226	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1227	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1228	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1229	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 1230	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1231	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1232	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1233	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 1234	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1235	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1236	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1237	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 1238	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1239	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1240	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1241	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 1242	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1243	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1244	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1245	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 1246	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1247	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1248	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1249	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 1250	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1251	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 1252	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1253	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 1254	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1255	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 1256	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1257	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 1258	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1259	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 1260	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1261	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 1262	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1263	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1264	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1265	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 1266	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1267	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1268	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1269	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 1270	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1271	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1272	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1273	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 1274	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1275	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1276	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1277	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 1278	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1279	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1280	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1281	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 1282	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1283	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1284	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1285	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 1286	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1287	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1288	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1289	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 1290	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1291	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1292	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1293	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 1294	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1295	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 1296	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1297	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 1298	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1299	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 1300	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1301	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 1302	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1303	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 1304	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1305	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 1306	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1307	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 1308	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1309	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 1310	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1311	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1312	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1313	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 1314	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1315	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1316	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1317	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 1318	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1319	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1320	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1321	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 1322	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1323	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1324	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1325	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 1326	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1327	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1328	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1329	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 1330	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1331	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1332	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1333	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 1334	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1335	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1336	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1337	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 1338	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1339	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1340	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1341	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 1342	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1343	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1344	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1345	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 1346	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1347	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1348	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1349	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 1350	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1351	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1352	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1353	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 1354	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1355	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1356	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1357	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 1358	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1359	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1360	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1361	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 1362	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1363	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1364	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1365	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 1366	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1367	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1368	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1369	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 1370	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1371	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1372	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1373	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 1374	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1375	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1376	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1377	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 1378	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1379	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1380	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1381	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 1382	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1383	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1384	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1385	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 1386	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1387	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1388	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1389	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
 1390	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1391	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1392	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1393	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
 1394	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1395	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1396	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1397	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
 1398	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1399	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 1400	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1401	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
 1402	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1403	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 1404	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1405	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
 1406	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1407	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1408	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1409	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
 1410	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1411	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1412	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1413	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
 1414	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1415	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
 1416	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1417	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
 1418	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1419	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
 1420	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1421	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
 1422	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1423	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 1424	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1425	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
 1426	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1427	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 1428	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1429	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
 1430	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1431	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1432	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1433	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
 1434	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1435	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 1436	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1437	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
 1438	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1439	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1440	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1441	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
 1442	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1443	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1444	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1445	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
 1446	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1447	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 1448	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1449	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
 1450	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1451	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 1452	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1453	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
 1454	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1455	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 1456	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1457	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
 1458	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1459	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 1460	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1461	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
 1462	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1463	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 1464	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1465	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
 1466	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1467	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 1468	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1469	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
 1470	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1471	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1472	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1473	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
 1474	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1475	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1476	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1477	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
 1478	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1479	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 1480	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1481	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
 1482	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1483	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 1484	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1485	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
 1486	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1487	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 1488	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1489	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
 1490	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1491	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 1492	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1493	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
 1494	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1495	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1496	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1497	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
 1498	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1499	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1500	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1501	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
 1502	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1503	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1504	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1505	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
 1506	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1507	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1508	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1509	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
 1510	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1511	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 1512	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1513	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
 1514	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1515	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 1516	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1517	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
 1518	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1519	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1520	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1521	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
 1522	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1523	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1524	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1525	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
 1526	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1527	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1528	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1529	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
 1530	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1531	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1532	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1533	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
 1534	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1535	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1536	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1537	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
 1538	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1539	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1540	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1541	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 1542	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1543	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 1544	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1545	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 1546	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1547	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1548	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1549	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 1550	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1551	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 1552	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1553	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 1554	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1555	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 1556	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1557	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 1558	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1559	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
 1560	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1561	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 1562	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1563	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
 1564	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1565	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 1566	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1567	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 1568	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1569	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
 1570	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1571	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
 1572	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1573	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
 1574	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1575	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
 1576	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1577	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
 1578	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 1579	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
 1580	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1581	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
 1582	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
 1583};
 1584
 1585static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
 1586	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 1587	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1588	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 1589	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 1590	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 1591	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 1592	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1593	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1594	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 1595	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 1596	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 1597	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 1598	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 1599	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 1600	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 1601	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 1602	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 1603	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 1604	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 1605	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 1606	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 1607	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 1608	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 1609	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 1610	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 1611	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 1612	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 1613	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 1614	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 1615	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 1616	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 1617	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
 1618	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 1619	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 1620	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 1621	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 1622	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 1623	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
 1624};
 1625
 1626static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
 1627	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 1628	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1629	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 1630	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
 1631	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 1632	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 1633	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1634	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 1635	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 1636	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 1637	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 1638	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 1639	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 1640	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 1641	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 1642	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 1643	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 1644	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
 1645	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 1646	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 1647	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 1648	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 1649	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 1650	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 1651	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 1652	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 1653	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 1654	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 1655	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 1656	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 1657	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 1658	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 1659	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 1660	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 1661	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 1662	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 1663	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 1664	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 1665	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 1666	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 1667	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 1668	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
 1669};
 1670
 1671static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
 1672	/* Pending on emulation bring up */
 1673};
 1674
 1675static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
 1676	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
 1677	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1678	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 1679	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1680	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1681	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1682	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 1683	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1684	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 1685	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1686	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 1687	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1688	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 1689	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1690	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 1691	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1692	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1693	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1694	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 1695	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1696	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1697	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1698	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 1699	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1700	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1701	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1702	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 1703	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1704	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1705	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1706	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 1707	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1708	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1709	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1710	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 1711	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1712	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1713	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1714	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 1715	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1716	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1717	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1718	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 1719	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1720	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1721	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1722	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 1723	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1724	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1725	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1726	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 1727	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1728	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
 1729	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1730	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 1731	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1732	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 1733	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1734	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 1735	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1736	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1737	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1738	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 1739	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1740	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1741	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1742	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 1743	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1744	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1745	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1746	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 1747	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1748	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1749	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1750	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 1751	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1752	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1753	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1754	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 1755	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1756	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 1757	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1758	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 1759	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1760	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1761	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1762	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 1763	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1764	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1765	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1766	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 1767	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1768	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1769	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1770	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 1771	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1772	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1773	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1774	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 1775	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1776	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1777	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1778	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 1779	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1780	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 1781	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1782	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 1783	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1784	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1785	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1786	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 1787	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1788	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 1789	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1790	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 1791	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1792	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1793	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1794	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 1795	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1796	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1797	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1798	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 1799	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1800	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1801	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1802	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 1803	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1804	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 1805	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1806	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 1807	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1808	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 1809	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1810	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 1811	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1812	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 1813	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1814	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 1815	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1816	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 1817	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1818	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 1819	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1820	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1821	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1822	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 1823	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1824	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1825	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1826	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 1827	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1828	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1829	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1830	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 1831	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1832	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1833	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1834	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 1835	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1836	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 1837	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1838	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 1839	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1840	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1841	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1842	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 1843	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1844	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1845	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1846	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 1847	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1848	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 1849	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1850	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 1851	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1852	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 1853	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1854	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 1855	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1856	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 1857	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1858	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 1859	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1860	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1861	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1862	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 1863	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1864	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1865	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1866	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 1867	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1868	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1869	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1870	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 1871	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1872	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1873	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1874	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 1875	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1876	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
 1877	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1878	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 1879	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1880	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 1881	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1882	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 1883	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1884	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 1885	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1886	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 1887	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1888	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1889	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1890	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 1891	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1892	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
 1893	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1894	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 1895	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1896	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 1897	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1898	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 1899	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1900	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1901	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1902	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 1903	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1904	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1905	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1906	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 1907	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1908	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1909	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1910	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 1911	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1912	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1913	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1914	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 1915	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1916	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1917	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1918	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 1919	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1920	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1921	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1922	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 1923	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1924	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1925	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1926	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 1927	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1928	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1929	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1930	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 1931	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1932	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 1933	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1934	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 1935	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1936	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 1937	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1938	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 1939	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1940	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1941	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1942	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 1943	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1944	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 1945	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1946	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 1947	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1948	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1949	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1950	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 1951	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1952	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1953	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1954	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 1955	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1956	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 1957	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1958	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 1959	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1960	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 1961	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1962	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 1963	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1964	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 1965	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1966	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 1967	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1968	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 1969	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1970	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 1971	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1972	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 1973	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1974	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 1975	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1976	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1977	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1978	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 1979	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1980	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1981	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1982	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 1983	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1984	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1985	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1986	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 1987	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1988	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 1989	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1990	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 1991	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1992	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 1993	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1994	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 1995	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1996	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 1997	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 1998	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 1999	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2000	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2001	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2002	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 2003	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2004	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2005	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2006	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 2007	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2008	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2009	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2010	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 2011	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2012	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2013	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2014	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 2015	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2016	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2017	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2018	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 2019	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2020	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2021	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2022	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 2023	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2024	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2025	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2026	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 2027	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2028	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2029	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2030	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 2031	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2032	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2033	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2034	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 2035	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2036	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2037	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2038	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
 2039	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2040	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2041	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2042	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 2043	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2044	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2045	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2046	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 2047	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2048	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2049	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2050	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 2051	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2052	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2053	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2054	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 2055	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2056	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2057	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2058	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 2059	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2060	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2061	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2062	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 2063	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2064	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2065	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2066	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 2067	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2068	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2069	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2070	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 2071	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2072	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2073	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2074	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 2075	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2076	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 2077	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2078	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 2079	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2080	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2081	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2082	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 2083	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2084	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2085	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2086	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 2087	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2088	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2089	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2090	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 2091	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2092	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2093	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2094	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 2095	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2096	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
 2097	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2098	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 2099	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2100	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2101	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2102	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 2103	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2104	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2105	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2106	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 2107	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2108	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2109	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2110	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 2111	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2112	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2113	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2114	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 2115	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2116	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2117	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2118	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 2119	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2120	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2121	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2122	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 2123	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2124	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2125	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2126	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 2127	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2128	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2129	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2130	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 2131	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2132	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2133	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2134	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 2135	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2136	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2137	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2138	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
 2139	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2140	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2141	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2142	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
 2143	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2144	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2145	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2146	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
 2147	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2148	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2149	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2150	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
 2151	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2152	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2153	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2154	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
 2155	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2156	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2157	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2158	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
 2159	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2160	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2161	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2162	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
 2163	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2164	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2165	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2166	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
 2167	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2168	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2169	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2170	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
 2171	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2172	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 2173	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2174	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
 2175	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2176	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2177	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2178	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
 2179	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2180	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 2181	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2182	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
 2183	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2184	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2185	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2186	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
 2187	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2188	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 2189	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2190	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
 2191	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2192	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2193	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2194	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
 2195	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2196	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2197	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2198	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
 2199	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2200	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2201	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2202	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
 2203	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2204	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2205	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2206	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
 2207	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2208	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2209	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2210	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
 2211	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2212	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2213	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2214	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
 2215	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2216	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2217	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2218	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
 2219	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2220	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2221	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2222	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
 2223	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2224	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2225	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2226	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
 2227	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2228	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2229	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2230	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
 2231	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2232	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2233	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2234	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
 2235	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2236	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2237	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2238	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
 2239	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2240	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2241	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2242	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
 2243	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2244	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2245	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2246	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
 2247	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2248	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2249	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2250	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
 2251	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2252	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2253	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2254	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
 2255	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2256	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2257	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2258	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
 2259	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2260	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2261	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2262	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 2263	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2264	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2265	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2266	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 2267	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2268	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2269	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2270	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 2271	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2272	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
 2273	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2274	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 2275	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2276	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
 2277	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2278	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 2279	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2280	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2281	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2282	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
 2283	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2284	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
 2285	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2286	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
 2287	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2288	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
 2289	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2290	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
 2291	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2292	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
 2293	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2294	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
 2295	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
 2296};
 2297
 2298static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
 2299	/* Pending on emulation bring up */
 2300};
 2301
 2302static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
 2303	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
 2304	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2305	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 2306	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2307	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 2308	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2309	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 2310	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2311	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 2312	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2313	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 2314	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2315	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 2316	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2317	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 2318	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2319	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2320	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2321	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 2322	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2323	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2324	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2325	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 2326	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2327	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2328	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2329	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 2330	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2331	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2332	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2333	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 2334	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2335	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2336	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2337	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 2338	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2339	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2340	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2341	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 2342	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2343	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2344	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2345	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 2346	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2347	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2348	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2349	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 2350	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2351	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2352	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2353	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 2354	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2355	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2356	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2357	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 2358	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2359	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2360	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2361	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 2362	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2363	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2364	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2365	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 2366	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2367	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 2368	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2369	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 2370	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2371	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 2372	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2373	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 2374	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2375	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 2376	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2377	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 2378	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2379	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 2380	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2381	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 2382	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2383	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2384	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2385	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 2386	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2387	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2388	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2389	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 2390	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2391	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2392	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2393	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 2394	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2395	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2396	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2397	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 2398	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2399	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
 2400	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2401	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 2402	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2403	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
 2404	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2405	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 2406	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2407	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 2408	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2409	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 2410	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2411	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2412	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2413	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 2414	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2415	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
 2416	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2417	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 2418	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2419	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2420	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2421	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 2422	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2423	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2424	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2425	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 2426	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2427	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2428	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2429	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 2430	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2431	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 2432	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2433	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 2434	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2435	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2436	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2437	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 2438	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2439	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 2440	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2441	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 2442	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2443	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2444	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2445	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 2446	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2447	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2448	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2449	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 2450	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2451	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2452	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2453	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 2454	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2455	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2456	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2457	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 2458	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2459	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2460	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2461	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 2462	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2463	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2464	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2465	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 2466	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2467	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 2468	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2469	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 2470	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2471	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2472	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2473	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 2474	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2475	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 2476	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2477	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 2478	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2479	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2480	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2481	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 2482	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2483	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2484	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2485	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 2486	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2487	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2488	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2489	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 2490	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2491	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2492	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2493	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 2494	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2495	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 2496	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2497	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 2498	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2499	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2500	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2501	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 2502	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2503	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2504	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2505	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 2506	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2507	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 2508	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2509	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 2510	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2511	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2512	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2513	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 2514	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2515	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 2516	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2517	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 2518	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2519	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 2520	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2521	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 2522	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2523	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 2524	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2525	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 2526	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2527	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2528	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2529	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 2530	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2531	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 2532	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2533	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 2534	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2535	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 2536	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2537	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 2538	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2539	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2540	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2541	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 2542	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2543	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2544	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2545	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 2546	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2547	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2548	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2549	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 2550	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2551	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2552	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2553	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 2554	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2555	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2556	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2557	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 2558	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2559	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2560	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2561	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 2562	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2563	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 2564	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2565	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 2566	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2567	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 2568	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2569	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 2570	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2571	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2572	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2573	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 2574	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2575	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2576	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2577	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 2578	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2579	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2580	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2581	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 2582	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2583	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2584	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2585	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 2586	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2587	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2588	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2589	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 2590	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2591	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2592	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2593	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 2594	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2595	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2596	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2597	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 2598	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2599	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 2600	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2601	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 2602	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2603	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2604	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2605	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 2606	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2607	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2608	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2609	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 2610	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2611	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2612	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2613	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 2614	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2615	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2616	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2617	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 2618	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2619	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2620	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2621	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 2622	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2623	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2624	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2625	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 2626	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2627	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2628	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2629	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 2630	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2631	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2632	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2633	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 2634	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2635	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2636	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2637	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 2638	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2639	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2640	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2641	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 2642	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2643	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2644	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2645	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 2646	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2647	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2648	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2649	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 2650	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2651	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2652	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2653	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 2654	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2655	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2656	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2657	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 2658	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2659	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2660	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2661	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 2662	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2663	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2664	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2665	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 2666	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2667	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2668	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2669	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 2670	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2671	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 2672	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2673	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 2674	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2675	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 2676	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2677	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 2678	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2679	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 2680	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2681	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 2682	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2683	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2684	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2685	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 2686	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2687	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2688	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2689	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 2690	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2691	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2692	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2693	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 2694	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2695	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2696	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2697	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 2698	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2699	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2700	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2701	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 2702	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2703	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2704	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2705	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 2706	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2707	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2708	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2709	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 2710	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2711	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2712	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2713	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 2714	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2715	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2716	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2717	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 2718	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2719	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2720	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2721	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 2722	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2723	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2724	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2725	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 2726	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2727	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2728	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2729	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 2730	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2731	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2732	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2733	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 2734	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2735	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2736	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2737	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 2738	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2739	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2740	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2741	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 2742	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2743	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2744	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2745	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 2746	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2747	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2748	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2749	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 2750	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2751	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2752	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2753	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 2754	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2755	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2756	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2757	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 2758	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2759	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2760	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2761	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 2762	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2763	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2764	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2765	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 2766	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2767	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2768	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2769	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 2770	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2771	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2772	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2773	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 2774	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2775	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2776	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2777	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 2778	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2779	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 2780	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2781	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 2782	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2783	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 2784	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2785	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 2786	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2787	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2788	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2789	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 2790	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2791	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2792	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2793	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 2794	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2795	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2796	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2797	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 2798	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2799	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2800	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2801	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 2802	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2803	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2804	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2805	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 2806	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2807	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 2808	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2809	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 2810	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2811	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 2812	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2813	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 2814	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2815	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 2816	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2817	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 2818	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2819	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2820	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2821	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 2822	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2823	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 2824	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2825	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 2826	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2827	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2828	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2829	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 2830	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2831	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2832	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2833	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 2834	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2835	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2836	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2837	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 2838	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2839	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2840	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2841	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 2842	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2843	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2844	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2845	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 2846	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2847	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2848	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2849	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 2850	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2851	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2852	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2853	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 2854	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2855	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2856	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2857	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 2858	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2859	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2860	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2861	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 2862	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2863	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2864	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2865	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 2866	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2867	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2868	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2869	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 2870	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2871	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 2872	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2873	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 2874	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2875	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2876	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2877	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 2878	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2879	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2880	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2881	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 2882	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2883	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2884	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2885	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 2886	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2887	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2888	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2889	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 2890	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2891	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2892	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2893	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 2894	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2895	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 2896	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2897	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 2898	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2899	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2900	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2901	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 2902	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2903	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 2904	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2905	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 2906	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2907	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2908	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2909	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 2910	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2911	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2912	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2913	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 2914	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2915	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2916	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2917	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 2918	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2919	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 2920	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2921	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 2922	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2923	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2924	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2925	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 2926	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2927	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2928	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2929	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 2930	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2931	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2932	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2933	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 2934	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2935	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 2936	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2937	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 2938	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2939	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2940	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2941	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 2942	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2943	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2944	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2945	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 2946	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2947	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2948	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2949	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 2950	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2951	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2952	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2953	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 2954	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2955	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2956	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2957	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 2958	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2959	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 2960	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2961	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 2962	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2963	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 2964	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2965	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 2966	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2967	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 2968	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2969	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 2970	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2971	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2972	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2973	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 2974	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2975	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 2976	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2977	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 2978	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2979	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2980	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2981	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 2982	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2983	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 2984	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2985	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 2986	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2987	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2988	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2989	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 2990	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2991	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 2992	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2993	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 2994	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 2995	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 2996	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2997	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 2998	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 2999	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3000	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3001	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 3002	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3003	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3004	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3005	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 3006	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3007	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3008	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3009	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 3010	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3011	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3012	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3013	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 3014	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3015	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3016	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3017	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 3018	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3019	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3020	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3021	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 3022	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3023	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3024	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3025	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 3026	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3027	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3028	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3029	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 3030	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3031	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3032	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3033	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 3034	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3035	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3036	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3037	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 3038	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3039	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
 3040	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3041	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 3042	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3043	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 3044	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3045	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 3046	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3047	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 3048	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3049	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 3050	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3051	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3052	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3053	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 3054	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3055	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3056	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3057	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 3058	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3059	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3060	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3061	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 3062	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3063	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 3064	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3065	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 3066	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3067	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 3068	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3069	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 3070	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3071	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 3072	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3073	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 3074	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3075	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3076	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3077	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 3078	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3079	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3080	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3081	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 3082	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3083	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3084	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3085	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 3086	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3087	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3088	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3089	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 3090	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3091	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3092	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3093	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 3094	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3095	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3096	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3097	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 3098	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3099	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3100	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3101	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 3102	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3103	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3104	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3105	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 3106	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3107	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3108	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3109	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 3110	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3111	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 3112	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3113	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 3114	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3115	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 3116	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3117	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 3118	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3119	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 3120	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3121	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 3122	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3123	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3124	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3125	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 3126	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3127	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3128	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3129	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 3130	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3131	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 3132	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3133	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 3134	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3135	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 3136	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3137	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 3138	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3139	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3140	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3141	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 3142	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3143	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3144	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3145	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 3146	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3147	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 3148	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3149	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 3150	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3151	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 3152	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3153	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 3154	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3155	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3156	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3157	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 3158	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3159	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3160	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3161	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
 3162	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3163	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 3164	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3165	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
 3166	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3167	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 3168	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3169	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
 3170	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3171	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3172	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3173	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
 3174	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3175	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3176	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3177	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
 3178	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3179	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 3180	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3181	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
 3182	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3183	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 3184	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3185	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
 3186	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3187	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 3188	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3189	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
 3190	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3191	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 3192	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3193	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
 3194	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3195	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 3196	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3197	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
 3198	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3199	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 3200	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3201	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
 3202	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3203	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3204	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3205	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
 3206	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3207	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3208	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3209	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
 3210	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3211	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 3212	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3213	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
 3214	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3215	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 3216	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3217	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
 3218	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3219	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3220	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3221	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
 3222	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3223	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3224	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3225	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
 3226	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3227	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3228	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3229	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
 3230	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3231	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3232	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3233	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
 3234	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3235	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3236	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3237	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
 3238	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3239	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3240	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3241	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
 3242	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3243	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3244	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3245	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
 3246	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3247	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3248	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3249	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
 3250	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3251	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3252	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3253	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
 3254	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3255	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 3256	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3257	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
 3258	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3259	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3260	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3261	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
 3262	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3263	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3264	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3265	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
 3266	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3267	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3268	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3269	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
 3270	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3271	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3272	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3273	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
 3274	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3275	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3276	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3277	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
 3278	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3279	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 3280	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3281	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
 3282	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3283	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 3284	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3285	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
 3286	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3287	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 3288	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3289	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
 3290	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3291	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 3292	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3293	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
 3294	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3295	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 3296	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3297	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
 3298	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3299	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3300	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3301	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
 3302	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3303	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 3304	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3305	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
 3306	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3307	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 3308	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3309	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
 3310	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3311	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 3312	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3313	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 3314	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3315	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 3316	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3317	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 3318	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3319	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 3320	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3321	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 3322	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3323	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 3324	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3325	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 3326	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3327	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 3328	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3329	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 3330	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3331	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
 3332	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3333	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 3334	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3335	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
 3336	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3337	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 3338	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3339	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 3340	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3341	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
 3342	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3343	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
 3344	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3345	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
 3346	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3347	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
 3348	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3349	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
 3350	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 3351	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
 3352	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 3353	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
 3354	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
 3355};
 3356
 3357static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
 3358	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
 3359	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3360	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
 3361	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
 3362	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
 3363	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3364	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3365	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
 3366	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
 3367	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
 3368	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
 3369	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
 3370	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
 3371	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
 3372	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3373	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3374	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3375	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
 3376	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
 3377	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3378	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3379	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
 3380	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
 3381	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
 3382	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
 3383	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
 3384	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
 3385	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
 3386	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
 3387	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
 3388	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
 3389	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
 3390	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
 3391	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
 3392	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
 3393	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
 3394	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
 3395	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 3396	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 3397	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
 3398	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 3399	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3400	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
 3401};
 3402
 3403static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
 3404	/* Pending on emulation bring up */
 3405};
 3406
 3407static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
 3408	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3409	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3410	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
 3411	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
 3412	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
 3413	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3414	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3415	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
 3416	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
 3417	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
 3418	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
 3419	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
 3420	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3421	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3422	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3423	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3424	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3425	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3426	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
 3427	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
 3428	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
 3429	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
 3430	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
 3431	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
 3432	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
 3433	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
 3434	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
 3435	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
 3436	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
 3437	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
 3438	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
 3439	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
 3440	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
 3441	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
 3442	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
 3443	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 3444	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 3445	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
 3446	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3447	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
 3448	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
 3449
 3450	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
 3451	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
 3452};
 3453
 3454static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
 3455	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
 3456	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
 3457	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
 3458	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 3459	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3460	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
 3461	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
 3462	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
 3463	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
 3464	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
 3465	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
 3466	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3467	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3468	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3469	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3470	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3471	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3472	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
 3473	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
 3474	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
 3475	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 3476	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3477	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
 3478	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 3479
 3480	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
 3481	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
 3482};
 3483
 3484static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
 3485	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3486	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
 3487	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
 3488	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3489	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3490	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
 3491	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
 3492	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
 3493	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
 3494	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
 3495	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3496	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3497	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3498	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3499	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
 3500	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3501	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3502	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
 3503	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3504	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
 3505};
 3506
 3507static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
 3508	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
 3509	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
 3510	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
 3511	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
 3512	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
 3513	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
 3514	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
 3515	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
 3516	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3517	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3518	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
 3519	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
 3520	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
 3521	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3522	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 3523	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
 3524	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
 3525	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
 3526	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
 3527	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
 3528	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
 3529	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
 3530	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
 3531	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
 3532	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
 3533	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
 3534	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
 3535	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
 3536	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
 3537	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 3538	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 3539	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
 3540	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 3541	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
 3542	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
 3543	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
 3544};
 3545
 3546static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
 3547	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
 3548	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
 3549	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
 3550	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
 3551	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3552	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3553	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
 3554	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3555	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3556	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3557	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3558	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
 3559	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3560	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
 3561	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
 3562	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
 3563	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
 3564	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
 3565	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
 3566	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
 3567	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
 3568	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
 3569	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
 3570	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
 3571	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
 3572	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
 3573	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
 3574	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 3575	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 3576	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
 3577	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3578	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
 3579};
 3580
 3581static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
 3582	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
 3583	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
 3584	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 3585	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
 3586	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
 3587	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
 3588	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
 3589	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
 3590	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
 3591	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 3592	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 3593	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 3594	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 3595	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
 3596	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
 3597	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
 3598	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
 3599	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
 3600	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
 3601	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
 3602	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
 3603	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3604	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 3605	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 3606	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
 3607	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
 3608	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
 3609	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
 3610	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
 3611	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
 3612	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 3613	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 3614	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
 3615	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
 3616};
 3617
 3618static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
 3619	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3620	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
 3621	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
 3622	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3623	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3624	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
 3625	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
 3626	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
 3627	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
 3628	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
 3629	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3630	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 3631	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3632	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3633	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
 3634	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
 3635	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3636	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
 3637	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
 3638	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
 3639	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3640	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
 3641};
 3642
 3643static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
 3644	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 3645	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
 3646	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
 3647	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 3648	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 3649	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
 3650	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
 3651	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
 3652	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
 3653	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
 3654	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
 3655	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
 3656	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
 3657	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
 3658	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
 3659	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
 3660	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 3661	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
 3662	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
 3663	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
 3664	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 3665	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
 3666};
 3667
 3668#define DEFAULT_SH_MEM_CONFIG \
 3669	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 3670	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 3671	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
 3672	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 3673
 3674/* TODO: pending on golden setting value of gb address config */
 3675#define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
 3676
 3677static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 3678static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 3679static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 3680static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 3681static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
 3682static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 3683				 struct amdgpu_cu_info *cu_info);
 3684static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 3685static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 3686				   u32 sh_num, u32 instance, int xcc_id);
 3687static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 3688
 3689static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
 3690static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
 3691static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
 3692static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 3693static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 3694static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 3695static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 3696static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
 3697static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
 3698static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
 3699static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 3700					   uint16_t pasid, uint32_t flush_type,
 3701					   bool all_hub, uint8_t dst_sel);
 3702static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
 3703					       unsigned int vmid);
 3704
 3705static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
 3706					  enum amd_powergating_state state);
 3707static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 3708{
 3709	struct amdgpu_device *adev = kiq_ring->adev;
 3710	u64 shader_mc_addr;
 3711
 3712	/* Cleaner shader MC address */
 3713	shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
 3714
 3715	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 3716	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 3717			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
 3718	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
 3719	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
 3720	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
 3721	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
 3722	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
 3723	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
 3724}
 3725
 3726static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 3727				 struct amdgpu_ring *ring)
 3728{
 3729	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 3730	uint64_t wptr_addr = ring->wptr_gpu_addr;
 3731	uint32_t eng_sel = 0;
 3732
 3733	switch (ring->funcs->type) {
 3734	case AMDGPU_RING_TYPE_COMPUTE:
 3735		eng_sel = 0;
 3736		break;
 3737	case AMDGPU_RING_TYPE_GFX:
 3738		eng_sel = 4;
 3739		break;
 3740	case AMDGPU_RING_TYPE_MES:
 3741		eng_sel = 5;
 3742		break;
 3743	default:
 3744		WARN_ON(1);
 3745	}
 3746
 3747	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 3748	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 3749	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 3750			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 3751			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 3752			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 3753			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 3754			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 3755			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 3756			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 3757			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 3758			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 3759	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 3760	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 3761	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 3762	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 3763	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 3764}
 3765
 3766static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 3767				   struct amdgpu_ring *ring,
 3768				   enum amdgpu_unmap_queues_action action,
 3769				   u64 gpu_addr, u64 seq)
 3770{
 3771	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 3772
 3773	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 3774	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 3775			  PACKET3_UNMAP_QUEUES_ACTION(action) |
 3776			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 3777			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 3778			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 3779	amdgpu_ring_write(kiq_ring,
 3780		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 3781
 3782	if (action == PREEMPT_QUEUES_NO_UNMAP) {
 3783		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 3784		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 3785		amdgpu_ring_write(kiq_ring, seq);
 3786	} else {
 3787		amdgpu_ring_write(kiq_ring, 0);
 3788		amdgpu_ring_write(kiq_ring, 0);
 3789		amdgpu_ring_write(kiq_ring, 0);
 3790	}
 3791}
 3792
 3793static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 3794				   struct amdgpu_ring *ring,
 3795				   u64 addr,
 3796				   u64 seq)
 3797{
 3798	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 3799
 3800	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 3801	amdgpu_ring_write(kiq_ring,
 3802			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 3803			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 3804			  PACKET3_QUERY_STATUS_COMMAND(2));
 3805	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 3806			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 3807			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 3808	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 3809	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 3810	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 3811	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 3812}
 3813
 3814static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 3815				uint16_t pasid, uint32_t flush_type,
 3816				bool all_hub)
 3817{
 3818	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 3819}
 3820
 3821static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
 3822					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
 3823					uint32_t xcc_id, uint32_t vmid)
 3824{
 3825	struct amdgpu_device *adev = kiq_ring->adev;
 3826	unsigned i;
 3827	uint32_t tmp;
 3828
 3829	/* enter save mode */
 3830	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
 3831	mutex_lock(&adev->srbm_mutex);
 3832	nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
 3833
 3834	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
 3835		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
 3836		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
 3837		/* wait till dequeue take effects */
 3838		for (i = 0; i < adev->usec_timeout; i++) {
 3839			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
 3840				break;
 3841			udelay(1);
 3842		}
 3843		if (i >= adev->usec_timeout)
 3844			dev_err(adev->dev, "fail to wait on hqd deactive\n");
 3845	} else if (queue_type == AMDGPU_RING_TYPE_GFX) {
 3846		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
 3847			     (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
 3848		tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
 3849		if (pipe_id == 0)
 3850			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
 3851		else
 3852			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
 3853		WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
 3854
 3855		/* wait till dequeue take effects */
 3856		for (i = 0; i < adev->usec_timeout; i++) {
 3857			if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))
 3858				break;
 3859			udelay(1);
 3860		}
 3861		if (i >= adev->usec_timeout)
 3862			dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
 3863	} else {
 3864		dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
 3865	}
 3866
 3867	nv_grbm_select(adev, 0, 0, 0, 0);
 3868	mutex_unlock(&adev->srbm_mutex);
 3869	/* exit safe mode */
 3870	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 3871}
 3872
 3873static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
 3874	.kiq_set_resources = gfx10_kiq_set_resources,
 3875	.kiq_map_queues = gfx10_kiq_map_queues,
 3876	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
 3877	.kiq_query_status = gfx10_kiq_query_status,
 3878	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
 3879	.kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
 3880	.set_resources_size = 8,
 3881	.map_queues_size = 7,
 3882	.unmap_queues_size = 6,
 3883	.query_status_size = 7,
 3884	.invalidate_tlbs_size = 2,
 3885};
 3886
 3887static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 3888{
 3889	adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
 3890}
 3891
 3892static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
 3893{
 3894	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 3895	case IP_VERSION(10, 1, 10):
 3896		soc15_program_register_sequence(adev,
 3897						golden_settings_gc_rlc_spm_10_0_nv10,
 3898						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
 3899		break;
 3900	case IP_VERSION(10, 1, 1):
 3901		soc15_program_register_sequence(adev,
 3902						golden_settings_gc_rlc_spm_10_1_nv14,
 3903						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
 3904		break;
 3905	case IP_VERSION(10, 1, 2):
 3906		soc15_program_register_sequence(adev,
 3907						golden_settings_gc_rlc_spm_10_1_2_nv12,
 3908						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
 3909		break;
 3910	default:
 3911		break;
 3912	}
 3913}
 3914
 3915static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 3916{
 3917	if (amdgpu_sriov_vf(adev))
 3918		return;
 3919
 3920	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 3921	case IP_VERSION(10, 1, 10):
 3922		soc15_program_register_sequence(adev,
 3923						golden_settings_gc_10_1,
 3924						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
 3925		soc15_program_register_sequence(adev,
 3926						golden_settings_gc_10_0_nv10,
 3927						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
 3928		break;
 3929	case IP_VERSION(10, 1, 1):
 3930		soc15_program_register_sequence(adev,
 3931						golden_settings_gc_10_1_1,
 3932						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 3933		soc15_program_register_sequence(adev,
 3934						golden_settings_gc_10_1_nv14,
 3935						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 3936		break;
 3937	case IP_VERSION(10, 1, 2):
 3938		soc15_program_register_sequence(adev,
 3939						golden_settings_gc_10_1_2,
 3940						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 3941		soc15_program_register_sequence(adev,
 3942						golden_settings_gc_10_1_2_nv12,
 3943						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 3944		break;
 3945	case IP_VERSION(10, 3, 0):
 3946		soc15_program_register_sequence(adev,
 3947						golden_settings_gc_10_3,
 3948						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
 3949		soc15_program_register_sequence(adev,
 3950						golden_settings_gc_10_3_sienna_cichlid,
 3951						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
 3952		break;
 3953	case IP_VERSION(10, 3, 2):
 3954		soc15_program_register_sequence(adev,
 3955						golden_settings_gc_10_3_2,
 3956						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
 3957		break;
 3958	case IP_VERSION(10, 3, 1):
 3959		soc15_program_register_sequence(adev,
 3960						golden_settings_gc_10_3_vangogh,
 3961						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
 3962		break;
 3963	case IP_VERSION(10, 3, 3):
 3964		soc15_program_register_sequence(adev,
 3965						golden_settings_gc_10_3_3,
 3966						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
 3967		break;
 3968	case IP_VERSION(10, 3, 4):
 3969		soc15_program_register_sequence(adev,
 3970						golden_settings_gc_10_3_4,
 3971						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
 3972		break;
 3973	case IP_VERSION(10, 3, 5):
 3974		soc15_program_register_sequence(adev,
 3975						golden_settings_gc_10_3_5,
 3976						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
 3977		break;
 3978	case IP_VERSION(10, 1, 3):
 3979	case IP_VERSION(10, 1, 4):
 3980		soc15_program_register_sequence(adev,
 3981						golden_settings_gc_10_0_cyan_skillfish,
 3982						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
 3983		break;
 3984	case IP_VERSION(10, 3, 6):
 3985		soc15_program_register_sequence(adev,
 3986						golden_settings_gc_10_3_6,
 3987						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
 3988		break;
 3989	case IP_VERSION(10, 3, 7):
 3990		soc15_program_register_sequence(adev,
 3991						golden_settings_gc_10_3_7,
 3992						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
 3993		break;
 3994	default:
 3995		break;
 3996	}
 3997	gfx_v10_0_init_spm_golden_registers(adev);
 3998}
 3999
 4000static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 4001				       bool wc, uint32_t reg, uint32_t val)
 4002{
 4003	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 4004	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 4005			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 4006	amdgpu_ring_write(ring, reg);
 4007	amdgpu_ring_write(ring, 0);
 4008	amdgpu_ring_write(ring, val);
 4009}
 4010
 4011static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 4012				  int mem_space, int opt, uint32_t addr0,
 4013				  uint32_t addr1, uint32_t ref, uint32_t mask,
 4014				  uint32_t inv)
 4015{
 4016	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 4017	amdgpu_ring_write(ring,
 4018			  /* memory (1) or register (0) */
 4019			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 4020			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
 4021			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 4022			   WAIT_REG_MEM_ENGINE(eng_sel)));
 4023
 4024	if (mem_space)
 4025		BUG_ON(addr0 & 0x3); /* Dword align */
 4026	amdgpu_ring_write(ring, addr0);
 4027	amdgpu_ring_write(ring, addr1);
 4028	amdgpu_ring_write(ring, ref);
 4029	amdgpu_ring_write(ring, mask);
 4030	amdgpu_ring_write(ring, inv); /* poll interval */
 4031}
 4032
 4033static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 4034{
 4035	struct amdgpu_device *adev = ring->adev;
 4036	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 4037	uint32_t tmp = 0;
 4038	unsigned int i;
 4039	int r;
 4040
 4041	WREG32(scratch, 0xCAFEDEAD);
 4042	r = amdgpu_ring_alloc(ring, 3);
 4043	if (r) {
 4044		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 4045			  ring->idx, r);
 4046		return r;
 4047	}
 4048
 4049	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 4050	amdgpu_ring_write(ring, scratch -
 4051			  PACKET3_SET_UCONFIG_REG_START);
 4052	amdgpu_ring_write(ring, 0xDEADBEEF);
 4053	amdgpu_ring_commit(ring);
 4054
 4055	for (i = 0; i < adev->usec_timeout; i++) {
 4056		tmp = RREG32(scratch);
 4057		if (tmp == 0xDEADBEEF)
 4058			break;
 4059		if (amdgpu_emu_mode == 1)
 4060			msleep(1);
 4061		else
 4062			udelay(1);
 4063	}
 4064
 4065	if (i >= adev->usec_timeout)
 4066		r = -ETIMEDOUT;
 4067
 4068	return r;
 4069}
 4070
 4071static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 4072{
 4073	struct amdgpu_device *adev = ring->adev;
 4074	struct amdgpu_ib ib;
 4075	struct dma_fence *f = NULL;
 4076	unsigned int index;
 4077	uint64_t gpu_addr;
 4078	uint32_t *cpu_ptr;
 4079	long r;
 4080
 4081	memset(&ib, 0, sizeof(ib));
 4082
 4083	r = amdgpu_device_wb_get(adev, &index);
 4084	if (r)
 4085		return r;
 4086
 4087	gpu_addr = adev->wb.gpu_addr + (index * 4);
 4088	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 4089	cpu_ptr = &adev->wb.wb[index];
 4090
 4091	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 4092	if (r) {
 4093		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 4094		goto err1;
 4095	}
 4096
 4097	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 4098	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 4099	ib.ptr[2] = lower_32_bits(gpu_addr);
 4100	ib.ptr[3] = upper_32_bits(gpu_addr);
 4101	ib.ptr[4] = 0xDEADBEEF;
 4102	ib.length_dw = 5;
 4103
 4104	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 4105	if (r)
 4106		goto err2;
 4107
 4108	r = dma_fence_wait_timeout(f, false, timeout);
 4109	if (r == 0) {
 4110		r = -ETIMEDOUT;
 4111		goto err2;
 4112	} else if (r < 0) {
 4113		goto err2;
 4114	}
 4115
 4116	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 4117		r = 0;
 4118	else
 4119		r = -EINVAL;
 4120err2:
 4121	amdgpu_ib_free(&ib, NULL);
 4122	dma_fence_put(f);
 4123err1:
 4124	amdgpu_device_wb_free(adev, index);
 4125	return r;
 4126}
 4127
 4128static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
 4129{
 4130	amdgpu_ucode_release(&adev->gfx.pfp_fw);
 4131	amdgpu_ucode_release(&adev->gfx.me_fw);
 4132	amdgpu_ucode_release(&adev->gfx.ce_fw);
 4133	amdgpu_ucode_release(&adev->gfx.rlc_fw);
 4134	amdgpu_ucode_release(&adev->gfx.mec_fw);
 4135	amdgpu_ucode_release(&adev->gfx.mec2_fw);
 4136
 4137	kfree(adev->gfx.rlc.register_list_format);
 4138}
 4139
 4140static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 4141{
 4142	adev->gfx.cp_fw_write_wait = false;
 4143
 4144	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4145	case IP_VERSION(10, 1, 10):
 4146	case IP_VERSION(10, 1, 2):
 4147	case IP_VERSION(10, 1, 1):
 4148	case IP_VERSION(10, 1, 3):
 4149	case IP_VERSION(10, 1, 4):
 4150		if ((adev->gfx.me_fw_version >= 0x00000046) &&
 4151		    (adev->gfx.me_feature_version >= 27) &&
 4152		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
 4153		    (adev->gfx.pfp_feature_version >= 27) &&
 4154		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
 4155		    (adev->gfx.mec_feature_version >= 27))
 4156			adev->gfx.cp_fw_write_wait = true;
 4157		break;
 4158	case IP_VERSION(10, 3, 0):
 4159	case IP_VERSION(10, 3, 2):
 4160	case IP_VERSION(10, 3, 1):
 4161	case IP_VERSION(10, 3, 4):
 4162	case IP_VERSION(10, 3, 5):
 4163	case IP_VERSION(10, 3, 6):
 4164	case IP_VERSION(10, 3, 3):
 4165	case IP_VERSION(10, 3, 7):
 4166		adev->gfx.cp_fw_write_wait = true;
 4167		break;
 4168	default:
 4169		break;
 4170	}
 4171
 4172	if (!adev->gfx.cp_fw_write_wait)
 4173		DRM_WARN_ONCE("CP firmware version too old, please update!");
 4174}
 4175
 4176static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
 4177{
 4178	bool ret = false;
 4179
 4180	switch (adev->pdev->revision) {
 4181	case 0xc2:
 4182	case 0xc3:
 4183		ret = true;
 4184		break;
 4185	default:
 4186		ret = false;
 4187		break;
 4188	}
 4189
 4190	return ret;
 4191}
 4192
 4193static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 4194{
 4195	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4196	case IP_VERSION(10, 1, 10):
 4197		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
 4198			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 4199		break;
 4200	default:
 4201		break;
 4202	}
 4203}
 4204
 4205static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 4206{
 4207	char fw_name[53];
 4208	char ucode_prefix[30];
 4209	const char *wks = "";
 4210	int err;
 4211	const struct rlc_firmware_header_v2_0 *rlc_hdr;
 4212	uint16_t version_major;
 4213	uint16_t version_minor;
 4214
 4215	DRM_DEBUG("\n");
 4216
 4217	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
 4218	    (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
 4219		wks = "_wks";
 4220	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 4221
 4222	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
 4223				   AMDGPU_UCODE_REQUIRED,
 4224				   "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
 4225	if (err)
 4226		goto out;
 4227	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 4228
 4229	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
 4230				   AMDGPU_UCODE_REQUIRED,
 4231				   "amdgpu/%s_me%s.bin", ucode_prefix, wks);
 4232	if (err)
 4233		goto out;
 4234	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 4235
 4236	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
 4237				   AMDGPU_UCODE_REQUIRED,
 4238				   "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
 4239	if (err)
 4240		goto out;
 4241	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
 4242
 4243	if (!amdgpu_sriov_vf(adev)) {
 4244		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 4245		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 4246		if (err)
 4247			goto out;
 4248
 4249		/* don't validate this firmware. There are apparently firmwares
 4250		 * in the wild with incorrect size in the header
 4251		 */
 4252		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 4253		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 4254		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 4255		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 4256		if (err)
 4257			goto out;
 4258	}
 4259
 4260	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
 4261				   AMDGPU_UCODE_REQUIRED,
 4262				   "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
 4263	if (err)
 4264		goto out;
 4265	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 4266	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 4267
 4268	err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
 4269				   AMDGPU_UCODE_REQUIRED,
 4270				   "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
 4271	if (!err) {
 4272		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
 4273		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
 4274	} else {
 4275		err = 0;
 4276		adev->gfx.mec2_fw = NULL;
 4277	}
 4278
 4279	gfx_v10_0_check_fw_write_wait(adev);
 4280out:
 4281	if (err) {
 4282		amdgpu_ucode_release(&adev->gfx.pfp_fw);
 4283		amdgpu_ucode_release(&adev->gfx.me_fw);
 4284		amdgpu_ucode_release(&adev->gfx.ce_fw);
 4285		amdgpu_ucode_release(&adev->gfx.rlc_fw);
 4286		amdgpu_ucode_release(&adev->gfx.mec_fw);
 4287		amdgpu_ucode_release(&adev->gfx.mec2_fw);
 4288	}
 4289
 4290	gfx_v10_0_check_gfxoff_flag(adev);
 4291
 4292	return err;
 4293}
 4294
 4295static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
 4296{
 4297	u32 count = 0;
 4298	const struct cs_section_def *sect = NULL;
 4299	const struct cs_extent_def *ext = NULL;
 4300
 4301	/* begin clear state */
 4302	count += 2;
 4303	/* context control state */
 4304	count += 3;
 4305
 4306	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 4307		for (ext = sect->section; ext->extent != NULL; ++ext) {
 4308			if (sect->id == SECT_CONTEXT)
 4309				count += 2 + ext->reg_count;
 4310			else
 4311				return 0;
 4312		}
 4313	}
 4314
 4315	/* set PA_SC_TILE_STEERING_OVERRIDE */
 4316	count += 3;
 4317	/* end clear state */
 4318	count += 2;
 4319	/* clear state */
 4320	count += 2;
 4321
 4322	return count;
 4323}
 4324
 4325static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
 4326{
 4327	u32 count = 0;
 4328	int ctx_reg_offset;
 4329
 4330	if (adev->gfx.rlc.cs_data == NULL)
 4331		return;
 4332	if (buffer == NULL)
 4333		return;
 4334
 4335	count = amdgpu_gfx_csb_preamble_start(buffer);
 4336	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);
 4337
 4338	ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 4339	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 4340	buffer[count++] = cpu_to_le32(ctx_reg_offset);
 4341	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 4342
 4343	amdgpu_gfx_csb_preamble_end(buffer, count);
 4344}
 4345
 4346static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
 4347{
 4348	/* clear state block */
 4349	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 4350			&adev->gfx.rlc.clear_state_gpu_addr,
 4351			(void **)&adev->gfx.rlc.cs_ptr);
 4352
 4353	/* jump table block */
 4354	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 4355			&adev->gfx.rlc.cp_table_gpu_addr,
 4356			(void **)&adev->gfx.rlc.cp_table_ptr);
 4357}
 4358
 4359static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 4360{
 4361	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 4362
 4363	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
 4364	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 4365	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
 4366	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
 4367	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
 4368	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
 4369	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
 4370	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4371	case IP_VERSION(10, 3, 0):
 4372		reg_access_ctrl->spare_int =
 4373			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
 4374		break;
 4375	default:
 4376		reg_access_ctrl->spare_int =
 4377			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
 4378		break;
 4379	}
 4380	adev->gfx.rlc.rlcg_reg_access_supported = true;
 4381}
 4382
 4383static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
 4384{
 4385	const struct cs_section_def *cs_data;
 4386	int r;
 4387
 4388	adev->gfx.rlc.cs_data = gfx10_cs_data;
 4389
 4390	cs_data = adev->gfx.rlc.cs_data;
 4391
 4392	if (cs_data) {
 4393		/* init clear state block */
 4394		r = amdgpu_gfx_rlc_init_csb(adev);
 4395		if (r)
 4396			return r;
 4397	}
 4398
 4399	return 0;
 4400}
 4401
 4402static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
 4403{
 4404	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 4405	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 4406}
 4407
 4408static void gfx_v10_0_me_init(struct amdgpu_device *adev)
 4409{
 4410	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 4411
 4412	amdgpu_gfx_graphics_queue_acquire(adev);
 4413}
 4414
 4415static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
 4416{
 4417	int r;
 4418	u32 *hpd;
 4419	const __le32 *fw_data = NULL;
 4420	unsigned int fw_size;
 4421	u32 *fw = NULL;
 4422	size_t mec_hpd_size;
 4423
 4424	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
 4425
 4426	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 4427
 4428	/* take ownership of the relevant compute queues */
 4429	amdgpu_gfx_compute_queue_acquire(adev);
 4430	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
 4431
 4432	if (mec_hpd_size) {
 4433		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 4434					      AMDGPU_GEM_DOMAIN_GTT,
 4435					      &adev->gfx.mec.hpd_eop_obj,
 4436					      &adev->gfx.mec.hpd_eop_gpu_addr,
 4437					      (void **)&hpd);
 4438		if (r) {
 4439			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 4440			gfx_v10_0_mec_fini(adev);
 4441			return r;
 4442		}
 4443
 4444		memset(hpd, 0, mec_hpd_size);
 4445
 4446		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 4447		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 4448	}
 4449
 4450	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 4451		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 4452
 4453		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
 4454			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 4455		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
 4456
 4457		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
 4458					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 4459					      &adev->gfx.mec.mec_fw_obj,
 4460					      &adev->gfx.mec.mec_fw_gpu_addr,
 4461					      (void **)&fw);
 4462		if (r) {
 4463			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
 4464			gfx_v10_0_mec_fini(adev);
 4465			return r;
 4466		}
 4467
 4468		memcpy(fw, fw_data, fw_size);
 4469
 4470		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 4471		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 4472	}
 4473
 4474	return 0;
 4475}
 4476
 4477static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 4478{
 4479	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
 4480		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 4481		(address << SQ_IND_INDEX__INDEX__SHIFT));
 4482	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
 4483}
 4484
 4485static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 4486			   uint32_t thread, uint32_t regno,
 4487			   uint32_t num, uint32_t *out)
 4488{
 4489	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
 4490		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 4491		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
 4492		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 4493		(SQ_IND_INDEX__AUTO_INCR_MASK));
 4494	while (num--)
 4495		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
 4496}
 4497
 4498static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 4499{
 4500	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
 4501	 * field when performing a select_se_sh so it should be
 4502	 * zero here
 4503	 */
 4504	WARN_ON(simd != 0);
 4505
 4506	/* type 2 wave data */
 4507	dst[(*no_fields)++] = 2;
 4508	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 4509	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 4510	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 4511	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 4512	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 4513	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 4514	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 4515	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
 4516	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 4517	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 4518	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 4519	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 4520	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 4521	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 4522	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 4523	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 4524}
 4525
 4526static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 4527				     uint32_t wave, uint32_t start,
 4528				     uint32_t size, uint32_t *dst)
 4529{
 4530	WARN_ON(simd != 0);
 4531
 4532	wave_read_regs(
 4533		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 4534		dst);
 4535}
 4536
 4537static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 4538				      uint32_t wave, uint32_t thread,
 4539				      uint32_t start, uint32_t size,
 4540				      uint32_t *dst)
 4541{
 4542	wave_read_regs(
 4543		adev, wave, thread,
 4544		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 4545}
 4546
 4547static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
 4548				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 4549{
 4550	nv_grbm_select(adev, me, pipe, q, vm);
 4551}
 4552
 4553static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
 4554					  bool enable)
 4555{
 4556	uint32_t data, def;
 4557
 4558	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
 4559
 4560	if (enable)
 4561		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
 4562	else
 4563		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
 4564
 4565	if (data != def)
 4566		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
 4567}
 4568
 4569static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
 4570	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
 4571	.select_se_sh = &gfx_v10_0_select_se_sh,
 4572	.read_wave_data = &gfx_v10_0_read_wave_data,
 4573	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
 4574	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
 4575	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
 4576	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
 4577	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
 4578};
 4579
 4580static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 4581{
 4582	u32 gb_addr_config;
 4583
 4584	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4585	case IP_VERSION(10, 1, 10):
 4586	case IP_VERSION(10, 1, 1):
 4587	case IP_VERSION(10, 1, 2):
 4588		adev->gfx.config.max_hw_contexts = 8;
 4589		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 4590		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 4591		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 4592		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 4593		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
 4594		break;
 4595	case IP_VERSION(10, 3, 0):
 4596	case IP_VERSION(10, 3, 2):
 4597	case IP_VERSION(10, 3, 1):
 4598	case IP_VERSION(10, 3, 4):
 4599	case IP_VERSION(10, 3, 5):
 4600	case IP_VERSION(10, 3, 6):
 4601	case IP_VERSION(10, 3, 3):
 4602	case IP_VERSION(10, 3, 7):
 4603		adev->gfx.config.max_hw_contexts = 8;
 4604		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 4605		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 4606		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 4607		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 4608		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
 4609		adev->gfx.config.gb_addr_config_fields.num_pkrs =
 4610			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
 4611		break;
 4612	case IP_VERSION(10, 1, 3):
 4613	case IP_VERSION(10, 1, 4):
 4614		adev->gfx.config.max_hw_contexts = 8;
 4615		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 4616		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 4617		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 4618		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 4619		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
 4620		break;
 4621	default:
 4622		BUG();
 4623		break;
 4624	}
 4625
 4626	adev->gfx.config.gb_addr_config = gb_addr_config;
 4627
 4628	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
 4629			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
 4630				      GB_ADDR_CONFIG, NUM_PIPES);
 4631
 4632	adev->gfx.config.max_tile_pipes =
 4633		adev->gfx.config.gb_addr_config_fields.num_pipes;
 4634
 4635	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
 4636			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
 4637				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
 4638	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
 4639			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
 4640				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
 4641	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
 4642			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
 4643				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
 4644	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
 4645			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
 4646				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
 4647}
 4648
 4649static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 4650				   int me, int pipe, int queue)
 4651{
 4652	struct amdgpu_ring *ring;
 4653	unsigned int irq_type;
 4654	unsigned int hw_prio;
 4655
 4656	ring = &adev->gfx.gfx_ring[ring_id];
 4657
 4658	ring->me = me;
 4659	ring->pipe = pipe;
 4660	ring->queue = queue;
 4661
 4662	ring->ring_obj = NULL;
 4663	ring->use_doorbell = true;
 4664
 4665	if (!ring_id)
 4666		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 4667	else
 4668		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 4669	ring->vm_hub = AMDGPU_GFXHUB(0);
 4670	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 4671
 4672	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 4673	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
 4674			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 4675	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 4676				hw_prio, NULL);
 4677}
 4678
 4679static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 4680				       int mec, int pipe, int queue)
 4681{
 4682	unsigned int irq_type;
 4683	struct amdgpu_ring *ring;
 4684	unsigned int hw_prio;
 4685
 4686	ring = &adev->gfx.compute_ring[ring_id];
 4687
 4688	/* mec0 is me1 */
 4689	ring->me = mec + 1;
 4690	ring->pipe = pipe;
 4691	ring->queue = queue;
 4692
 4693	ring->ring_obj = NULL;
 4694	ring->use_doorbell = true;
 4695	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 4696	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 4697				+ (ring_id * GFX10_MEC_HPD_SIZE);
 4698	ring->vm_hub = AMDGPU_GFXHUB(0);
 4699	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 4700
 4701	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 4702		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 4703		+ ring->pipe;
 4704	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 4705			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
 4706	/* type-2 packets are deprecated on MEC, use type-3 instead */
 4707	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 4708			     hw_prio, NULL);
 4709}
 4710
 4711static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 4712{
 4713	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 4714	uint32_t *ptr;
 4715	uint32_t inst;
 4716
 4717	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
 4718	if (!ptr) {
 4719		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
 4720		adev->gfx.ip_dump_core = NULL;
 4721	} else {
 4722		adev->gfx.ip_dump_core = ptr;
 4723	}
 4724
 4725	/* Allocate memory for compute queue registers for all the instances */
 4726	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
 4727	inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
 4728		adev->gfx.mec.num_queue_per_pipe;
 4729
 4730	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
 4731	if (!ptr) {
 4732		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
 4733		adev->gfx.ip_dump_compute_queues = NULL;
 4734	} else {
 4735		adev->gfx.ip_dump_compute_queues = ptr;
 4736	}
 4737
 4738	/* Allocate memory for gfx queue registers for all the instances */
 4739	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
 4740	inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
 4741		adev->gfx.me.num_queue_per_pipe;
 4742
 4743	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
 4744	if (!ptr) {
 4745		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
 4746		adev->gfx.ip_dump_gfx_queues = NULL;
 4747	} else {
 4748		adev->gfx.ip_dump_gfx_queues = ptr;
 4749	}
 4750}
 4751
 4752static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
 4753{
 4754	int i, j, k, r, ring_id = 0;
 4755	int xcc_id = 0;
 4756	struct amdgpu_device *adev = ip_block->adev;
 4757	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
 4758
 4759	INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
 4760
 4761	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4762	case IP_VERSION(10, 1, 10):
 4763	case IP_VERSION(10, 1, 1):
 4764	case IP_VERSION(10, 1, 2):
 4765	case IP_VERSION(10, 1, 3):
 4766	case IP_VERSION(10, 1, 4):
 4767		adev->gfx.me.num_me = 1;
 4768		adev->gfx.me.num_pipe_per_me = 1;
 4769		adev->gfx.me.num_queue_per_pipe = 8;
 4770		adev->gfx.mec.num_mec = 2;
 4771		adev->gfx.mec.num_pipe_per_mec = 4;
 4772		adev->gfx.mec.num_queue_per_pipe = 8;
 4773		break;
 4774	case IP_VERSION(10, 3, 0):
 4775	case IP_VERSION(10, 3, 2):
 4776	case IP_VERSION(10, 3, 1):
 4777	case IP_VERSION(10, 3, 4):
 4778	case IP_VERSION(10, 3, 5):
 4779	case IP_VERSION(10, 3, 6):
 4780	case IP_VERSION(10, 3, 3):
 4781	case IP_VERSION(10, 3, 7):
 4782		adev->gfx.me.num_me = 1;
 4783		adev->gfx.me.num_pipe_per_me = 2;
 4784		adev->gfx.me.num_queue_per_pipe = 2;
 4785		adev->gfx.mec.num_mec = 2;
 4786		adev->gfx.mec.num_pipe_per_mec = 4;
 4787		adev->gfx.mec.num_queue_per_pipe = 4;
 4788		break;
 4789	default:
 4790		adev->gfx.me.num_me = 1;
 4791		adev->gfx.me.num_pipe_per_me = 1;
 4792		adev->gfx.me.num_queue_per_pipe = 1;
 4793		adev->gfx.mec.num_mec = 1;
 4794		adev->gfx.mec.num_pipe_per_mec = 4;
 4795		adev->gfx.mec.num_queue_per_pipe = 8;
 4796		break;
 4797	}
 4798	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 4799	case IP_VERSION(10, 1, 10):
 4800	case IP_VERSION(10, 1, 1):
 4801	case IP_VERSION(10, 1, 2):
 4802		adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;
 4803		adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);
 4804		if (adev->gfx.me_fw_version >= 101 &&
 4805		    adev->gfx.pfp_fw_version  >= 158 &&
 4806		    adev->gfx.mec_fw_version >= 151) {
 4807			adev->gfx.enable_cleaner_shader = true;
 4808			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
 4809			if (r) {
 4810				adev->gfx.enable_cleaner_shader = false;
 4811				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
 4812			}
 4813		}
 4814		break;
 4815	case IP_VERSION(10, 3, 0):
 4816	case IP_VERSION(10, 3, 1):
 4817	case IP_VERSION(10, 3, 2):
 4818	case IP_VERSION(10, 3, 3):
 4819	case IP_VERSION(10, 3, 4):
 4820	case IP_VERSION(10, 3, 5):
 4821		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
 4822		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
 4823		if (adev->gfx.me_fw_version >= 64 &&
 4824		    adev->gfx.pfp_fw_version >= 100 &&
 4825		    adev->gfx.mec_fw_version >= 122) {
 4826			adev->gfx.enable_cleaner_shader = true;
 4827			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
 4828			if (r) {
 4829				adev->gfx.enable_cleaner_shader = false;
 4830				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
 4831			}
 4832		}
 4833		break;
 4834	case IP_VERSION(10, 3, 6):
 4835		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
 4836		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
 4837		if (adev->gfx.me_fw_version >= 14 &&
 4838		    adev->gfx.pfp_fw_version >= 17 &&
 4839		    adev->gfx.mec_fw_version >= 24) {
 4840			adev->gfx.enable_cleaner_shader = true;
 4841			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
 4842			if (r) {
 4843				adev->gfx.enable_cleaner_shader = false;
 4844				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
 4845			}
 4846		}
 4847		break;
 4848	case IP_VERSION(10, 3, 7):
 4849		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
 4850		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
 4851		if (adev->gfx.me_fw_version >= 4 &&
 4852		    adev->gfx.pfp_fw_version >= 9 &&
 4853		    adev->gfx.mec_fw_version >= 12) {
 4854			adev->gfx.enable_cleaner_shader = true;
 4855			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
 4856			if (r) {
 4857				adev->gfx.enable_cleaner_shader = false;
 4858				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
 4859			}
 4860		}
 4861		break;
 4862	default:
 4863		adev->gfx.enable_cleaner_shader = false;
 4864		break;
 4865	}
 4866
 4867	/* KIQ event */
 4868	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
 4869			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
 4870			      &adev->gfx.kiq[0].irq);
 4871	if (r)
 4872		return r;
 4873
 4874	/* EOP Event */
 4875	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
 4876			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
 4877			      &adev->gfx.eop_irq);
 4878	if (r)
 4879		return r;
 4880
 4881	/* Bad opcode Event */
 4882	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
 4883			      GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
 4884			      &adev->gfx.bad_op_irq);
 4885	if (r)
 4886		return r;
 4887
 4888	/* Privileged reg */
 4889	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
 4890			      &adev->gfx.priv_reg_irq);
 4891	if (r)
 4892		return r;
 4893
 4894	/* Privileged inst */
 4895	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
 4896			      &adev->gfx.priv_inst_irq);
 4897	if (r)
 4898		return r;
 4899
 4900	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 4901
 4902	gfx_v10_0_me_init(adev);
 4903
 4904	if (adev->gfx.rlc.funcs) {
 4905		if (adev->gfx.rlc.funcs->init) {
 4906			r = adev->gfx.rlc.funcs->init(adev);
 4907			if (r) {
 4908				dev_err(adev->dev, "Failed to init rlc BOs!\n");
 4909				return r;
 4910			}
 4911		}
 4912	}
 4913
 4914	r = gfx_v10_0_mec_init(adev);
 4915	if (r) {
 4916		DRM_ERROR("Failed to init MEC BOs!\n");
 4917		return r;
 4918	}
 4919
 4920	/* set up the gfx ring */
 4921	for (i = 0; i < adev->gfx.me.num_me; i++) {
 4922		for (j = 0; j < num_queue_per_pipe; j++) {
 4923			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
 4924				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
 4925					continue;
 4926
 4927				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
 4928							    i, k, j);
 4929				if (r)
 4930					return r;
 4931				ring_id++;
 4932			}
 4933		}
 4934	}
 4935
 4936	ring_id = 0;
 4937	/* set up the compute queues - allocate horizontally across pipes */
 4938	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
 4939		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
 4940			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
 4941				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
 4942								     k, j))
 4943					continue;
 4944
 4945				r = gfx_v10_0_compute_ring_init(adev, ring_id,
 4946								i, k, j);
 4947				if (r)
 4948					return r;
 4949
 4950				ring_id++;
 4951			}
 4952		}
 4953	}
 4954
 4955	adev->gfx.gfx_supported_reset =
 4956		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
 4957	adev->gfx.compute_supported_reset =
 4958		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
 4959	if (!amdgpu_sriov_vf(adev) &&
 4960	    !adev->debug_disable_gpu_ring_reset) {
 4961		adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 4962		adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 4963	}
 4964
 4965	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
 4966	if (r) {
 4967		DRM_ERROR("Failed to init KIQ BOs!\n");
 4968		return r;
 4969	}
 4970
 4971	r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
 4972	if (r)
 4973		return r;
 4974
 4975	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
 4976	if (r)
 4977		return r;
 4978
 4979	/* allocate visible FB for rlc auto-loading fw */
 4980	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
 4981		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
 4982		if (r)
 4983			return r;
 4984	}
 4985
 4986	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
 4987
 4988	gfx_v10_0_gpu_early_init(adev);
 4989
 4990	gfx_v10_0_alloc_ip_dump(adev);
 4991
 4992	r = amdgpu_gfx_sysfs_init(adev);
 4993	if (r)
 4994		return r;
 4995
 4996	return 0;
 4997}
 4998
 4999static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
 5000{
 5001	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
 5002			      &adev->gfx.pfp.pfp_fw_gpu_addr,
 5003			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
 5004}
 5005
 5006static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
 5007{
 5008	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
 5009			      &adev->gfx.ce.ce_fw_gpu_addr,
 5010			      (void **)&adev->gfx.ce.ce_fw_ptr);
 5011}
 5012
 5013static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
 5014{
 5015	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
 5016			      &adev->gfx.me.me_fw_gpu_addr,
 5017			      (void **)&adev->gfx.me.me_fw_ptr);
 5018}
 5019
 5020static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
 5021{
 5022	int i;
 5023	struct amdgpu_device *adev = ip_block->adev;
 5024
 5025	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 5026		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
 5027	for (i = 0; i < adev->gfx.num_compute_rings; i++)
 5028		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 5029
 5030	amdgpu_gfx_mqd_sw_fini(adev, 0);
 5031
 5032	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
 5033	amdgpu_gfx_kiq_fini(adev, 0);
 5034
 5035	amdgpu_gfx_cleaner_shader_sw_fini(adev);
 5036
 5037	gfx_v10_0_pfp_fini(adev);
 5038	gfx_v10_0_ce_fini(adev);
 5039	gfx_v10_0_me_fini(adev);
 5040	gfx_v10_0_rlc_fini(adev);
 5041	gfx_v10_0_mec_fini(adev);
 5042
 5043	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 5044		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
 5045
 5046	gfx_v10_0_free_microcode(adev);
 5047	amdgpu_gfx_sysfs_fini(adev);
 5048
 5049	kfree(adev->gfx.ip_dump_core);
 5050	kfree(adev->gfx.ip_dump_compute_queues);
 5051	kfree(adev->gfx.ip_dump_gfx_queues);
 5052
 5053	return 0;
 5054}
 5055
 5056static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 5057				   u32 sh_num, u32 instance, int xcc_id)
 5058{
 5059	u32 data;
 5060
 5061	if (instance == 0xffffffff)
 5062		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 5063				     INSTANCE_BROADCAST_WRITES, 1);
 5064	else
 5065		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
 5066				     instance);
 5067
 5068	if (se_num == 0xffffffff)
 5069		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
 5070				     1);
 5071	else
 5072		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
 5073
 5074	if (sh_num == 0xffffffff)
 5075		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
 5076				     1);
 5077	else
 5078		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
 5079
 5080	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 5081}
 5082
 5083static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 5084{
 5085	u32 data, mask;
 5086
 5087	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
 5088	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
 5089
 5090	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
 5091	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
 5092
 5093	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
 5094					 adev->gfx.config.max_sh_per_se);
 5095
 5096	return (~data) & mask;
 5097}
 5098
 5099static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
 5100{
 5101	int i, j;
 5102	u32 data;
 5103	u32 active_rbs = 0;
 5104	u32 bitmap;
 5105	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
 5106					adev->gfx.config.max_sh_per_se;
 5107
 5108	mutex_lock(&adev->grbm_idx_mutex);
 5109	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 5110		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 5111			bitmap = i * adev->gfx.config.max_sh_per_se + j;
 5112			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
 5113			      IP_VERSION(10, 3, 0)) ||
 5114			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
 5115			      IP_VERSION(10, 3, 3)) ||
 5116			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
 5117			      IP_VERSION(10, 3, 6))) &&
 5118			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
 5119				continue;
 5120			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
 5121			data = gfx_v10_0_get_rb_active_bitmap(adev);
 5122			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
 5123					       rb_bitmap_width_per_sh);
 5124		}
 5125	}
 5126	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 5127	mutex_unlock(&adev->grbm_idx_mutex);
 5128
 5129	adev->gfx.config.backend_enable_mask = active_rbs;
 5130	adev->gfx.config.num_rbs = hweight32(active_rbs);
 5131}
 5132
 5133static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
 5134{
 5135	uint32_t num_sc;
 5136	uint32_t enabled_rb_per_sh;
 5137	uint32_t active_rb_bitmap;
 5138	uint32_t num_rb_per_sc;
 5139	uint32_t num_packer_per_sc;
 5140	uint32_t pa_sc_tile_steering_override;
 5141
 5142	/* for ASICs that integrates GFX v10.3
 5143	 * pa_sc_tile_steering_override should be set to 0
 5144	 */
 5145	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
 5146		return 0;
 5147
 5148	/* init num_sc */
 5149	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
 5150			adev->gfx.config.num_sc_per_sh;
 5151	/* init num_rb_per_sc */
 5152	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
 5153	enabled_rb_per_sh = hweight32(active_rb_bitmap);
 5154	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
 5155	/* init num_packer_per_sc */
 5156	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
 5157
 5158	pa_sc_tile_steering_override = 0;
 5159	pa_sc_tile_steering_override |=
 5160		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
 5161		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
 5162	pa_sc_tile_steering_override |=
 5163		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
 5164		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
 5165	pa_sc_tile_steering_override |=
 5166		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
 5167		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
 5168
 5169	return pa_sc_tile_steering_override;
 5170}
 5171
 5172#define DEFAULT_SH_MEM_BASES	(0x6000)
 5173
 5174static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
 5175				uint32_t first_vmid,
 5176				uint32_t last_vmid)
 5177{
 5178	uint32_t data;
 5179	uint32_t trap_config_vmid_mask = 0;
 5180	int i;
 5181
 5182	/* Calculate trap config vmid mask */
 5183	for (i = first_vmid; i < last_vmid; i++)
 5184		trap_config_vmid_mask |= (1 << i);
 5185
 5186	data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
 5187			VMID_SEL, trap_config_vmid_mask);
 5188	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
 5189			TRAP_EN, 1);
 5190	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
 5191	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
 5192
 5193	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
 5194	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
 5195}
 5196
 5197static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
 5198{
 5199	int i;
 5200	uint32_t sh_mem_bases;
 5201
 5202	/*
 5203	 * Configure apertures:
 5204	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 5205	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 5206	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 5207	 */
 5208	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 5209
 5210	mutex_lock(&adev->srbm_mutex);
 5211	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 5212		nv_grbm_select(adev, 0, 0, 0, i);
 5213		/* CP and shaders */
 5214		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
 5215		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
 5216	}
 5217	nv_grbm_select(adev, 0, 0, 0, 0);
 5218	mutex_unlock(&adev->srbm_mutex);
 5219
 5220	/*
 5221	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
 5222	 * access. These should be enabled by FW for target VMIDs.
 5223	 */
 5224	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 5225		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
 5226		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
 5227		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
 5228		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
 5229	}
 5230
 5231	gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
 5232					AMDGPU_NUM_VMID);
 5233}
 5234
 5235static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
 5236{
 5237	int vmid;
 5238
 5239	/*
 5240	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 5241	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
 5242	 * the driver can enable them for graphics. VMID0 should maintain
 5243	 * access so that HWS firmware can save/restore entries.
 5244	 */
 5245	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 5246		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
 5247		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
 5248		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
 5249		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
 5250	}
 5251}
 5252
 5253
 5254static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
 5255{
 5256	int i, j, k;
 5257	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
 5258	u32 tmp, wgp_active_bitmap = 0;
 5259	u32 gcrd_targets_disable_tcp = 0;
 5260	u32 utcl_invreq_disable = 0;
 5261	/*
 5262	 * GCRD_TARGETS_DISABLE field contains
 5263	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
 5264	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
 5265	 */
 5266	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
 5267		2 * max_wgp_per_sh + /* TCP */
 5268		max_wgp_per_sh + /* SQC */
 5269		4); /* GL1C */
 5270	/*
 5271	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
 5272	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
 5273	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
 5274	 */
 5275	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
 5276		2 * max_wgp_per_sh + /* TCP */
 5277		2 * max_wgp_per_sh + /* SQC */
 5278		4 + /* RMI */
 5279		1); /* SQG */
 5280
 5281	mutex_lock(&adev->grbm_idx_mutex);
 5282	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 5283		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 5284			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
 5285			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
 5286			/*
 5287			 * Set corresponding TCP bits for the inactive WGPs in
 5288			 * GCRD_SA_TARGETS_DISABLE
 5289			 */
 5290			gcrd_targets_disable_tcp = 0;
 5291			/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
 5292			utcl_invreq_disable = 0;
 5293
 5294			for (k = 0; k < max_wgp_per_sh; k++) {
 5295				if (!(wgp_active_bitmap & (1 << k))) {
 5296					gcrd_targets_disable_tcp |= 3 << (2 * k);
 5297					gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
 5298					utcl_invreq_disable |= (3 << (2 * k)) |
 5299						(3 << (2 * (max_wgp_per_sh + k)));
 5300				}
 5301			}
 5302
 5303			tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
 5304			/* only override TCP & SQC bits */
 5305			tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
 5306			tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
 5307			WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
 5308
 5309			tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
 5310			/* only override TCP & SQC bits */
 5311			tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
 5312			tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
 5313			WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
 5314		}
 5315	}
 5316
 5317	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 5318	mutex_unlock(&adev->grbm_idx_mutex);
 5319}
 5320
 5321static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
 5322{
 5323	/* TCCs are global (not instanced). */
 5324	uint32_t tcc_disable;
 5325
 5326	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
 5327		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
 5328			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
 5329	} else {
 5330		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
 5331			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
 5332	}
 5333
 5334	adev->gfx.config.tcc_disabled_mask =
 5335		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
 5336		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
 5337}
 5338
 5339static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
 5340{
 5341	u32 tmp;
 5342	int i;
 5343
 5344	if (!amdgpu_sriov_vf(adev))
 5345		WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
 5346
 5347	gfx_v10_0_setup_rb(adev);
 5348	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
 5349	gfx_v10_0_get_tcc_info(adev);
 5350	adev->gfx.config.pa_sc_tile_steering_override =
 5351		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
 5352
 5353	/* XXX SH_MEM regs */
 5354	/* where to put LDS, scratch, GPUVM in FSA64 space */
 5355	mutex_lock(&adev->srbm_mutex);
 5356	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
 5357		nv_grbm_select(adev, 0, 0, 0, i);
 5358		/* CP and shaders */
 5359		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
 5360		if (i != 0) {
 5361			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
 5362				(adev->gmc.private_aperture_start >> 48));
 5363			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
 5364				(adev->gmc.shared_aperture_start >> 48));
 5365			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
 5366		}
 5367	}
 5368	nv_grbm_select(adev, 0, 0, 0, 0);
 5369
 5370	mutex_unlock(&adev->srbm_mutex);
 5371
 5372	gfx_v10_0_init_compute_vmid(adev);
 5373	gfx_v10_0_init_gds_vmid(adev);
 5374
 5375}
 5376
 5377static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
 5378				      int me, int pipe)
 5379{
 5380	if (me != 0)
 5381		return 0;
 5382
 5383	switch (pipe) {
 5384	case 0:
 5385		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
 5386	case 1:
 5387		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
 5388	default:
 5389		return 0;
 5390	}
 5391}
 5392
 5393static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
 5394				      int me, int pipe)
 5395{
 5396	/*
 5397	 * amdgpu controls only the first MEC. That's why this function only
 5398	 * handles the setting of interrupts for this specific MEC. All other
 5399	 * pipes' interrupts are set by amdkfd.
 5400	 */
 5401	if (me != 1)
 5402		return 0;
 5403
 5404	switch (pipe) {
 5405	case 0:
 5406		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
 5407	case 1:
 5408		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
 5409	case 2:
 5410		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
 5411	case 3:
 5412		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
 5413	default:
 5414		return 0;
 5415	}
 5416}
 5417
 5418static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
 5419					       bool enable)
 5420{
 5421	u32 tmp, cp_int_cntl_reg;
 5422	int i, j;
 5423
 5424	if (amdgpu_sriov_vf(adev))
 5425		return;
 5426
 5427	for (i = 0; i < adev->gfx.me.num_me; i++) {
 5428		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 5429			cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
 5430
 5431			if (cp_int_cntl_reg) {
 5432				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 5433				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
 5434						    enable ? 1 : 0);
 5435				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
 5436						    enable ? 1 : 0);
 5437				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
 5438						    enable ? 1 : 0);
 5439				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
 5440						    enable ? 1 : 0);
 5441				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
 5442			}
 5443		}
 5444	}
 5445}
 5446
 5447static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
 5448{
 5449	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
 5450
 5451	/* csib */
 5452	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
 5453		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
 5454				adev->gfx.rlc.clear_state_gpu_addr >> 32);
 5455		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
 5456				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
 5457		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
 5458	} else {
 5459		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
 5460				adev->gfx.rlc.clear_state_gpu_addr >> 32);
 5461		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
 5462				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
 5463		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
 5464	}
 5465	return 0;
 5466}
 5467
 5468static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
 5469{
 5470	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
 5471
 5472	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
 5473	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
 5474}
 5475
 5476static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
 5477{
 5478	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
 5479	udelay(50);
 5480	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
 5481	udelay(50);
 5482}
 5483
 5484static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
 5485					     bool enable)
 5486{
 5487	uint32_t rlc_pg_cntl;
 5488
 5489	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
 5490
 5491	if (!enable) {
 5492		/* RLC_PG_CNTL[23] = 0 (default)
 5493		 * RLC will wait for handshake acks with SMU
 5494		 * GFXOFF will be enabled
 5495		 * RLC_PG_CNTL[23] = 1
 5496		 * RLC will not issue any message to SMU
 5497		 * hence no handshake between SMU & RLC
 5498		 * GFXOFF will be disabled
 5499		 */
 5500		rlc_pg_cntl |= 0x800000;
 5501	} else
 5502		rlc_pg_cntl &= ~0x800000;
 5503	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
 5504}
 5505
 5506static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
 5507{
 5508	/*
 5509	 * TODO: enable rlc & smu handshake until smu
 5510	 * and gfxoff feature works as expected
 5511	 */
 5512	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
 5513		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
 5514
 5515	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
 5516	udelay(50);
 5517}
 5518
 5519static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
 5520{
 5521	uint32_t tmp;
 5522
 5523	/* enable Save Restore Machine */
 5524	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
 5525	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
 5526	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
 5527	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
 5528}
 5529
 5530static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
 5531{
 5532	const struct rlc_firmware_header_v2_0 *hdr;
 5533	const __le32 *fw_data;
 5534	unsigned int i, fw_size;
 5535
 5536	if (!adev->gfx.rlc_fw)
 5537		return -EINVAL;
 5538
 5539	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 5540	amdgpu_ucode_print_rlc_hdr(&hdr->header);
 5541
 5542	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
 5543			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 5544	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 5545
 5546	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
 5547		     RLCG_UCODE_LOADING_START_ADDRESS);
 5548
 5549	for (i = 0; i < fw_size; i++)
 5550		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
 5551			     le32_to_cpup(fw_data++));
 5552
 5553	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
 5554
 5555	return 0;
 5556}
 5557
 5558static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
 5559{
 5560	int r;
 5561
 5562	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 5563		adev->psp.autoload_supported) {
 5564
 5565		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
 5566		if (r)
 5567			return r;
 5568
 5569		gfx_v10_0_init_csb(adev);
 5570
 5571		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
 5572
 5573		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
 5574			gfx_v10_0_rlc_enable_srm(adev);
 5575	} else {
 5576		if (amdgpu_sriov_vf(adev)) {
 5577			gfx_v10_0_init_csb(adev);
 5578			return 0;
 5579		}
 5580
 5581		adev->gfx.rlc.funcs->stop(adev);
 5582
 5583		/* disable CG */
 5584		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
 5585
 5586		/* disable PG */
 5587		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
 5588
 5589		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 5590			/* legacy rlc firmware loading */
 5591			r = gfx_v10_0_rlc_load_microcode(adev);
 5592			if (r)
 5593				return r;
 5594		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
 5595			/* rlc backdoor autoload firmware */
 5596			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
 5597			if (r)
 5598				return r;
 5599		}
 5600
 5601		gfx_v10_0_init_csb(adev);
 5602
 5603		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
 5604
 5605		adev->gfx.rlc.funcs->start(adev);
 5606
 5607		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
 5608			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
 5609			if (r)
 5610				return r;
 5611		}
 5612	}
 5613
 5614	return 0;
 5615}
 5616
 5617static struct {
 5618	FIRMWARE_ID	id;
 5619	unsigned int	offset;
 5620	unsigned int	size;
 5621} rlc_autoload_info[FIRMWARE_ID_MAX];
 5622
 5623static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
 5624{
 5625	int ret;
 5626	RLC_TABLE_OF_CONTENT *rlc_toc;
 5627
 5628	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
 5629					AMDGPU_GEM_DOMAIN_GTT,
 5630					&adev->gfx.rlc.rlc_toc_bo,
 5631					&adev->gfx.rlc.rlc_toc_gpu_addr,
 5632					(void **)&adev->gfx.rlc.rlc_toc_buf);
 5633	if (ret) {
 5634		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
 5635		return ret;
 5636	}
 5637
 5638	/* Copy toc from psp sos fw to rlc toc buffer */
 5639	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
 5640
 5641	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
 5642	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
 5643		(rlc_toc->id < FIRMWARE_ID_MAX)) {
 5644		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
 5645		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
 5646			/* Offset needs 4KB alignment */
 5647			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
 5648		}
 5649
 5650		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
 5651		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
 5652		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
 5653
 5654		rlc_toc++;
 5655	}
 5656
 5657	return 0;
 5658}
 5659
 5660static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
 5661{
 5662	uint32_t total_size = 0;
 5663	FIRMWARE_ID id;
 5664	int ret;
 5665
 5666	ret = gfx_v10_0_parse_rlc_toc(adev);
 5667	if (ret) {
 5668		dev_err(adev->dev, "failed to parse rlc toc\n");
 5669		return 0;
 5670	}
 5671
 5672	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
 5673		total_size += rlc_autoload_info[id].size;
 5674
 5675	/* In case the offset in rlc toc ucode is aligned */
 5676	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
 5677		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
 5678				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
 5679
 5680	return total_size;
 5681}
 5682
 5683static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
 5684{
 5685	int r;
 5686	uint32_t total_size;
 5687
 5688	total_size = gfx_v10_0_calc_toc_total_size(adev);
 5689
 5690	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
 5691				      AMDGPU_GEM_DOMAIN_GTT,
 5692				      &adev->gfx.rlc.rlc_autoload_bo,
 5693				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
 5694				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 5695	if (r) {
 5696		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
 5697		return r;
 5698	}
 5699
 5700	return 0;
 5701}
 5702
 5703static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
 5704{
 5705	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
 5706			      &adev->gfx.rlc.rlc_toc_gpu_addr,
 5707			      (void **)&adev->gfx.rlc.rlc_toc_buf);
 5708	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
 5709			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
 5710			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 5711}
 5712
 5713static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
 5714						       FIRMWARE_ID id,
 5715						       const void *fw_data,
 5716						       uint32_t fw_size)
 5717{
 5718	uint32_t toc_offset;
 5719	uint32_t toc_fw_size;
 5720	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
 5721
 5722	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
 5723		return;
 5724
 5725	toc_offset = rlc_autoload_info[id].offset;
 5726	toc_fw_size = rlc_autoload_info[id].size;
 5727
 5728	if (fw_size == 0)
 5729		fw_size = toc_fw_size;
 5730
 5731	if (fw_size > toc_fw_size)
 5732		fw_size = toc_fw_size;
 5733
 5734	memcpy(ptr + toc_offset, fw_data, fw_size);
 5735
 5736	if (fw_size < toc_fw_size)
 5737		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
 5738}
 5739
 5740static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
 5741{
 5742	void *data;
 5743	uint32_t size;
 5744
 5745	data = adev->gfx.rlc.rlc_toc_buf;
 5746	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
 5747
 5748	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5749						   FIRMWARE_ID_RLC_TOC,
 5750						   data, size);
 5751}
 5752
 5753static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
 5754{
 5755	const __le32 *fw_data;
 5756	uint32_t fw_size;
 5757	const struct gfx_firmware_header_v1_0 *cp_hdr;
 5758	const struct rlc_firmware_header_v2_0 *rlc_hdr;
 5759
 5760	/* pfp ucode */
 5761	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 5762		adev->gfx.pfp_fw->data;
 5763	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
 5764		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
 5765	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 5766	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5767						   FIRMWARE_ID_CP_PFP,
 5768						   fw_data, fw_size);
 5769
 5770	/* ce ucode */
 5771	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 5772		adev->gfx.ce_fw->data;
 5773	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
 5774		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
 5775	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 5776	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5777						   FIRMWARE_ID_CP_CE,
 5778						   fw_data, fw_size);
 5779
 5780	/* me ucode */
 5781	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 5782		adev->gfx.me_fw->data;
 5783	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
 5784		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
 5785	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 5786	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5787						   FIRMWARE_ID_CP_ME,
 5788						   fw_data, fw_size);
 5789
 5790	/* rlc ucode */
 5791	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
 5792		adev->gfx.rlc_fw->data;
 5793	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
 5794		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
 5795	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
 5796	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5797						   FIRMWARE_ID_RLC_G_UCODE,
 5798						   fw_data, fw_size);
 5799
 5800	/* mec1 ucode */
 5801	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 5802		adev->gfx.mec_fw->data;
 5803	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
 5804		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
 5805	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
 5806		cp_hdr->jt_size * 4;
 5807	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5808						   FIRMWARE_ID_CP_MEC,
 5809						   fw_data, fw_size);
 5810	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
 5811}
 5812
 5813/* Temporarily put sdma part here */
 5814static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
 5815{
 5816	const __le32 *fw_data;
 5817	uint32_t fw_size;
 5818	const struct sdma_firmware_header_v1_0 *sdma_hdr;
 5819	int i;
 5820
 5821	for (i = 0; i < adev->sdma.num_instances; i++) {
 5822		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
 5823			adev->sdma.instance[i].fw->data;
 5824		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
 5825			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
 5826		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
 5827
 5828		if (i == 0) {
 5829			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5830				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
 5831			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5832				FIRMWARE_ID_SDMA0_JT,
 5833				(uint32_t *)fw_data +
 5834				sdma_hdr->jt_offset,
 5835				sdma_hdr->jt_size * 4);
 5836		} else if (i == 1) {
 5837			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5838				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
 5839			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
 5840				FIRMWARE_ID_SDMA1_JT,
 5841				(uint32_t *)fw_data +
 5842				sdma_hdr->jt_offset,
 5843				sdma_hdr->jt_size * 4);
 5844		}
 5845	}
 5846}
 5847
 5848static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
 5849{
 5850	uint32_t rlc_g_offset, rlc_g_size, tmp;
 5851	uint64_t gpu_addr;
 5852
 5853	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
 5854	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
 5855	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
 5856
 5857	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
 5858	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
 5859	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
 5860
 5861	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
 5862	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
 5863	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
 5864
 5865	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
 5866	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
 5867		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
 5868		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
 5869		return -EINVAL;
 5870	}
 5871
 5872	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
 5873	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
 5874		DRM_ERROR("RLC ROM should halt itself\n");
 5875		return -EINVAL;
 5876	}
 5877
 5878	return 0;
 5879}
 5880
 5881static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
 5882{
 5883	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 5884	uint32_t tmp;
 5885	int i;
 5886	uint64_t addr;
 5887
 5888	/* Trigger an invalidation of the L1 instruction caches */
 5889	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
 5890	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 5891	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
 5892
 5893	/* Wait for invalidation complete */
 5894	for (i = 0; i < usec_timeout; i++) {
 5895		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
 5896		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
 5897			INVALIDATE_CACHE_COMPLETE))
 5898			break;
 5899		udelay(1);
 5900	}
 5901
 5902	if (i >= usec_timeout) {
 5903		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 5904		return -EINVAL;
 5905	}
 5906
 5907	/* Program me ucode address into intruction cache address register */
 5908	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
 5909		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
 5910	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
 5911			lower_32_bits(addr) & 0xFFFFF000);
 5912	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
 5913			upper_32_bits(addr));
 5914
 5915	return 0;
 5916}
 5917
 5918static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
 5919{
 5920	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 5921	uint32_t tmp;
 5922	int i;
 5923	uint64_t addr;
 5924
 5925	/* Trigger an invalidation of the L1 instruction caches */
 5926	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
 5927	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 5928	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
 5929
 5930	/* Wait for invalidation complete */
 5931	for (i = 0; i < usec_timeout; i++) {
 5932		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
 5933		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
 5934			INVALIDATE_CACHE_COMPLETE))
 5935			break;
 5936		udelay(1);
 5937	}
 5938
 5939	if (i >= usec_timeout) {
 5940		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 5941		return -EINVAL;
 5942	}
 5943
 5944	/* Program ce ucode address into intruction cache address register */
 5945	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
 5946		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
 5947	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
 5948			lower_32_bits(addr) & 0xFFFFF000);
 5949	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
 5950			upper_32_bits(addr));
 5951
 5952	return 0;
 5953}
 5954
 5955static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
 5956{
 5957	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 5958	uint32_t tmp;
 5959	int i;
 5960	uint64_t addr;
 5961
 5962	/* Trigger an invalidation of the L1 instruction caches */
 5963	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
 5964	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 5965	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
 5966
 5967	/* Wait for invalidation complete */
 5968	for (i = 0; i < usec_timeout; i++) {
 5969		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
 5970		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
 5971			INVALIDATE_CACHE_COMPLETE))
 5972			break;
 5973		udelay(1);
 5974	}
 5975
 5976	if (i >= usec_timeout) {
 5977		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 5978		return -EINVAL;
 5979	}
 5980
 5981	/* Program pfp ucode address into intruction cache address register */
 5982	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
 5983		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
 5984	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
 5985			lower_32_bits(addr) & 0xFFFFF000);
 5986	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
 5987			upper_32_bits(addr));
 5988
 5989	return 0;
 5990}
 5991
 5992static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
 5993{
 5994	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 5995	uint32_t tmp;
 5996	int i;
 5997	uint64_t addr;
 5998
 5999	/* Trigger an invalidation of the L1 instruction caches */
 6000	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
 6001	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 6002	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
 6003
 6004	/* Wait for invalidation complete */
 6005	for (i = 0; i < usec_timeout; i++) {
 6006		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
 6007		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
 6008			INVALIDATE_CACHE_COMPLETE))
 6009			break;
 6010		udelay(1);
 6011	}
 6012
 6013	if (i >= usec_timeout) {
 6014		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 6015		return -EINVAL;
 6016	}
 6017
 6018	/* Program mec1 ucode address into intruction cache address register */
 6019	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
 6020		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
 6021	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
 6022			lower_32_bits(addr) & 0xFFFFF000);
 6023	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
 6024			upper_32_bits(addr));
 6025
 6026	return 0;
 6027}
 6028
 6029static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
 6030{
 6031	uint32_t cp_status;
 6032	uint32_t bootload_status;
 6033	int i, r;
 6034
 6035	for (i = 0; i < adev->usec_timeout; i++) {
 6036		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
 6037		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
 6038		if ((cp_status == 0) &&
 6039		    (REG_GET_FIELD(bootload_status,
 6040			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
 6041			break;
 6042		}
 6043		udelay(1);
 6044	}
 6045
 6046	if (i >= adev->usec_timeout) {
 6047		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
 6048		return -ETIMEDOUT;
 6049	}
 6050
 6051	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
 6052		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
 6053		if (r)
 6054			return r;
 6055
 6056		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
 6057		if (r)
 6058			return r;
 6059
 6060		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
 6061		if (r)
 6062			return r;
 6063
 6064		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
 6065		if (r)
 6066			return r;
 6067	}
 6068
 6069	return 0;
 6070}
 6071
 6072static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
 6073{
 6074	int i;
 6075	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
 6076
 6077	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
 6078	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
 6079	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
 6080
 6081	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
 6082		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
 6083	else
 6084		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
 6085
 6086	if (amdgpu_in_reset(adev) && !enable)
 6087		return 0;
 6088
 6089	for (i = 0; i < adev->usec_timeout; i++) {
 6090		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
 6091			break;
 6092		udelay(1);
 6093	}
 6094
 6095	if (i >= adev->usec_timeout)
 6096		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
 6097
 6098	return 0;
 6099}
 6100
 6101static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
 6102{
 6103	int r;
 6104	const struct gfx_firmware_header_v1_0 *pfp_hdr;
 6105	const __le32 *fw_data;
 6106	unsigned int i, fw_size;
 6107	uint32_t tmp;
 6108	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 6109
 6110	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
 6111		adev->gfx.pfp_fw->data;
 6112
 6113	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
 6114
 6115	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
 6116		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
 6117	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
 6118
 6119	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
 6120				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 6121				      &adev->gfx.pfp.pfp_fw_obj,
 6122				      &adev->gfx.pfp.pfp_fw_gpu_addr,
 6123				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
 6124	if (r) {
 6125		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
 6126		gfx_v10_0_pfp_fini(adev);
 6127		return r;
 6128	}
 6129
 6130	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
 6131
 6132	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
 6133	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
 6134
 6135	/* Trigger an invalidation of the L1 instruction caches */
 6136	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
 6137	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 6138	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
 6139
 6140	/* Wait for invalidation complete */
 6141	for (i = 0; i < usec_timeout; i++) {
 6142		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
 6143		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
 6144			INVALIDATE_CACHE_COMPLETE))
 6145			break;
 6146		udelay(1);
 6147	}
 6148
 6149	if (i >= usec_timeout) {
 6150		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 6151		return -EINVAL;
 6152	}
 6153
 6154	if (amdgpu_emu_mode == 1)
 6155		amdgpu_device_flush_hdp(adev, NULL);
 6156
 6157	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
 6158	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
 6159	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
 6160	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
 6161	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
 6162	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
 6163	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
 6164		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
 6165	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
 6166		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
 6167
 6168	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
 6169
 6170	for (i = 0; i < pfp_hdr->jt_size; i++)
 6171		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
 6172			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
 6173
 6174	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
 6175
 6176	return 0;
 6177}
 6178
 6179static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
 6180{
 6181	int r;
 6182	const struct gfx_firmware_header_v1_0 *ce_hdr;
 6183	const __le32 *fw_data;
 6184	unsigned int i, fw_size;
 6185	uint32_t tmp;
 6186	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 6187
 6188	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
 6189		adev->gfx.ce_fw->data;
 6190
 6191	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
 6192
 6193	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
 6194		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
 6195	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
 6196
 6197	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
 6198				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 6199				      &adev->gfx.ce.ce_fw_obj,
 6200				      &adev->gfx.ce.ce_fw_gpu_addr,
 6201				      (void **)&adev->gfx.ce.ce_fw_ptr);
 6202	if (r) {
 6203		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
 6204		gfx_v10_0_ce_fini(adev);
 6205		return r;
 6206	}
 6207
 6208	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
 6209
 6210	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
 6211	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
 6212
 6213	/* Trigger an invalidation of the L1 instruction caches */
 6214	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
 6215	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 6216	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
 6217
 6218	/* Wait for invalidation complete */
 6219	for (i = 0; i < usec_timeout; i++) {
 6220		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
 6221		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
 6222			INVALIDATE_CACHE_COMPLETE))
 6223			break;
 6224		udelay(1);
 6225	}
 6226
 6227	if (i >= usec_timeout) {
 6228		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 6229		return -EINVAL;
 6230	}
 6231
 6232	if (amdgpu_emu_mode == 1)
 6233		amdgpu_device_flush_hdp(adev, NULL);
 6234
 6235	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
 6236	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
 6237	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
 6238	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
 6239	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
 6240	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
 6241		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
 6242	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
 6243		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
 6244
 6245	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
 6246
 6247	for (i = 0; i < ce_hdr->jt_size; i++)
 6248		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
 6249			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
 6250
 6251	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
 6252
 6253	return 0;
 6254}
 6255
 6256static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
 6257{
 6258	int r;
 6259	const struct gfx_firmware_header_v1_0 *me_hdr;
 6260	const __le32 *fw_data;
 6261	unsigned int i, fw_size;
 6262	uint32_t tmp;
 6263	uint32_t usec_timeout = 50000;  /* wait for 50ms */
 6264
 6265	me_hdr = (const struct gfx_firmware_header_v1_0 *)
 6266		adev->gfx.me_fw->data;
 6267
 6268	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
 6269
 6270	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
 6271		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
 6272	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
 6273
 6274	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
 6275				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 6276				      &adev->gfx.me.me_fw_obj,
 6277				      &adev->gfx.me.me_fw_gpu_addr,
 6278				      (void **)&adev->gfx.me.me_fw_ptr);
 6279	if (r) {
 6280		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
 6281		gfx_v10_0_me_fini(adev);
 6282		return r;
 6283	}
 6284
 6285	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
 6286
 6287	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
 6288	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
 6289
 6290	/* Trigger an invalidation of the L1 instruction caches */
 6291	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
 6292	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 6293	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
 6294
 6295	/* Wait for invalidation complete */
 6296	for (i = 0; i < usec_timeout; i++) {
 6297		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
 6298		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
 6299			INVALIDATE_CACHE_COMPLETE))
 6300			break;
 6301		udelay(1);
 6302	}
 6303
 6304	if (i >= usec_timeout) {
 6305		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 6306		return -EINVAL;
 6307	}
 6308
 6309	if (amdgpu_emu_mode == 1)
 6310		amdgpu_device_flush_hdp(adev, NULL);
 6311
 6312	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
 6313	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
 6314	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
 6315	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
 6316	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
 6317	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
 6318		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
 6319	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
 6320		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
 6321
 6322	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
 6323
 6324	for (i = 0; i < me_hdr->jt_size; i++)
 6325		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
 6326			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
 6327
 6328	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
 6329
 6330	return 0;
 6331}
 6332
 6333static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
 6334{
 6335	int r;
 6336
 6337	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
 6338		return -EINVAL;
 6339
 6340	gfx_v10_0_cp_gfx_enable(adev, false);
 6341
 6342	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
 6343	if (r) {
 6344		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
 6345		return r;
 6346	}
 6347
 6348	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
 6349	if (r) {
 6350		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
 6351		return r;
 6352	}
 6353
 6354	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
 6355	if (r) {
 6356		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
 6357		return r;
 6358	}
 6359
 6360	return 0;
 6361}
 6362
 6363static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
 6364{
 6365	struct amdgpu_ring *ring;
 6366	const struct cs_section_def *sect = NULL;
 6367	const struct cs_extent_def *ext = NULL;
 6368	int r, i;
 6369	int ctx_reg_offset;
 6370
 6371	/* init the CP */
 6372	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
 6373		     adev->gfx.config.max_hw_contexts - 1);
 6374	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
 6375
 6376	gfx_v10_0_cp_gfx_enable(adev, true);
 6377
 6378	ring = &adev->gfx.gfx_ring[0];
 6379	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
 6380	if (r) {
 6381		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
 6382		return r;
 6383	}
 6384
 6385	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 6386	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 6387
 6388	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 6389	amdgpu_ring_write(ring, 0x80000000);
 6390	amdgpu_ring_write(ring, 0x80000000);
 6391
 6392	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 6393		for (ext = sect->section; ext->extent != NULL; ++ext) {
 6394			if (sect->id == SECT_CONTEXT) {
 6395				amdgpu_ring_write(ring,
 6396						  PACKET3(PACKET3_SET_CONTEXT_REG,
 6397							  ext->reg_count));
 6398				amdgpu_ring_write(ring, ext->reg_index -
 6399						  PACKET3_SET_CONTEXT_REG_START);
 6400				for (i = 0; i < ext->reg_count; i++)
 6401					amdgpu_ring_write(ring, ext->extent[i]);
 6402			}
 6403		}
 6404	}
 6405
 6406	ctx_reg_offset =
 6407		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 6408	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 6409	amdgpu_ring_write(ring, ctx_reg_offset);
 6410	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
 6411
 6412	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 6413	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
 6414
 6415	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
 6416	amdgpu_ring_write(ring, 0);
 6417
 6418	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
 6419	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
 6420	amdgpu_ring_write(ring, 0x8000);
 6421	amdgpu_ring_write(ring, 0x8000);
 6422
 6423	amdgpu_ring_commit(ring);
 6424
 6425	/* submit cs packet to copy state 0 to next available state */
 6426	if (adev->gfx.num_gfx_rings > 1) {
 6427		/* maximum supported gfx ring is 2 */
 6428		ring = &adev->gfx.gfx_ring[1];
 6429		r = amdgpu_ring_alloc(ring, 2);
 6430		if (r) {
 6431			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
 6432			return r;
 6433		}
 6434
 6435		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
 6436		amdgpu_ring_write(ring, 0);
 6437
 6438		amdgpu_ring_commit(ring);
 6439	}
 6440	return 0;
 6441}
 6442
 6443static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
 6444					 CP_PIPE_ID pipe)
 6445{
 6446	u32 tmp;
 6447
 6448	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
 6449	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
 6450
 6451	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
 6452}
 6453
 6454static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
 6455					  struct amdgpu_ring *ring)
 6456{
 6457	u32 tmp;
 6458
 6459	if (!amdgpu_async_gfx_ring) {
 6460		tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
 6461		if (ring->use_doorbell) {
 6462			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6463						DOORBELL_OFFSET, ring->doorbell_index);
 6464			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6465						DOORBELL_EN, 1);
 6466		} else {
 6467			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6468						DOORBELL_EN, 0);
 6469		}
 6470		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
 6471	}
 6472	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 6473	case IP_VERSION(10, 3, 0):
 6474	case IP_VERSION(10, 3, 2):
 6475	case IP_VERSION(10, 3, 1):
 6476	case IP_VERSION(10, 3, 4):
 6477	case IP_VERSION(10, 3, 5):
 6478	case IP_VERSION(10, 3, 6):
 6479	case IP_VERSION(10, 3, 3):
 6480	case IP_VERSION(10, 3, 7):
 6481		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
 6482				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
 6483		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
 6484
 6485		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
 6486			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
 6487		break;
 6488	default:
 6489		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
 6490				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
 6491		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
 6492
 6493		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
 6494			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
 6495		break;
 6496	}
 6497}
 6498
 6499static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
 6500{
 6501	struct amdgpu_ring *ring;
 6502	u32 tmp;
 6503	u32 rb_bufsz;
 6504	u64 rb_addr, rptr_addr, wptr_gpu_addr;
 6505
 6506	/* Set the write pointer delay */
 6507	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
 6508
 6509	/* set the RB to use vmid 0 */
 6510	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
 6511
 6512	/* Init gfx ring 0 for pipe 0 */
 6513	mutex_lock(&adev->srbm_mutex);
 6514	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
 6515
 6516	/* Set ring buffer size */
 6517	ring = &adev->gfx.gfx_ring[0];
 6518	rb_bufsz = order_base_2(ring->ring_size / 8);
 6519	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
 6520	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
 6521#ifdef __BIG_ENDIAN
 6522	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
 6523#endif
 6524	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
 6525
 6526	/* Initialize the ring buffer's write pointers */
 6527	ring->wptr = 0;
 6528	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 6529	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
 6530
 6531	/* set the wb address whether it's enabled or not */
 6532	rptr_addr = ring->rptr_gpu_addr;
 6533	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
 6534	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
 6535		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
 6536
 6537	wptr_gpu_addr = ring->wptr_gpu_addr;
 6538	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
 6539		     lower_32_bits(wptr_gpu_addr));
 6540	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
 6541		     upper_32_bits(wptr_gpu_addr));
 6542
 6543	mdelay(1);
 6544	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
 6545
 6546	rb_addr = ring->gpu_addr >> 8;
 6547	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
 6548	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
 6549
 6550	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
 6551
 6552	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
 6553	mutex_unlock(&adev->srbm_mutex);
 6554
 6555	/* Init gfx ring 1 for pipe 1 */
 6556	if (adev->gfx.num_gfx_rings > 1) {
 6557		mutex_lock(&adev->srbm_mutex);
 6558		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
 6559		/* maximum supported gfx ring is 2 */
 6560		ring = &adev->gfx.gfx_ring[1];
 6561		rb_bufsz = order_base_2(ring->ring_size / 8);
 6562		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
 6563		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
 6564		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
 6565		/* Initialize the ring buffer's write pointers */
 6566		ring->wptr = 0;
 6567		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
 6568		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
 6569		/* Set the wb address whether it's enabled or not */
 6570		rptr_addr = ring->rptr_gpu_addr;
 6571		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
 6572		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
 6573			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
 6574		wptr_gpu_addr = ring->wptr_gpu_addr;
 6575		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
 6576			     lower_32_bits(wptr_gpu_addr));
 6577		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
 6578			     upper_32_bits(wptr_gpu_addr));
 6579
 6580		mdelay(1);
 6581		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
 6582
 6583		rb_addr = ring->gpu_addr >> 8;
 6584		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
 6585		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
 6586		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
 6587
 6588		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
 6589		mutex_unlock(&adev->srbm_mutex);
 6590	}
 6591	/* Switch to pipe 0 */
 6592	mutex_lock(&adev->srbm_mutex);
 6593	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
 6594	mutex_unlock(&adev->srbm_mutex);
 6595
 6596	/* start the ring */
 6597	gfx_v10_0_cp_gfx_start(adev);
 6598
 6599	return 0;
 6600}
 6601
 6602static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 6603{
 6604	if (enable) {
 6605		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 6606		case IP_VERSION(10, 3, 0):
 6607		case IP_VERSION(10, 3, 2):
 6608		case IP_VERSION(10, 3, 1):
 6609		case IP_VERSION(10, 3, 4):
 6610		case IP_VERSION(10, 3, 5):
 6611		case IP_VERSION(10, 3, 6):
 6612		case IP_VERSION(10, 3, 3):
 6613		case IP_VERSION(10, 3, 7):
 6614			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
 6615			break;
 6616		default:
 6617			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
 6618			break;
 6619		}
 6620	} else {
 6621		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 6622		case IP_VERSION(10, 3, 0):
 6623		case IP_VERSION(10, 3, 2):
 6624		case IP_VERSION(10, 3, 1):
 6625		case IP_VERSION(10, 3, 4):
 6626		case IP_VERSION(10, 3, 5):
 6627		case IP_VERSION(10, 3, 6):
 6628		case IP_VERSION(10, 3, 3):
 6629		case IP_VERSION(10, 3, 7):
 6630			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
 6631				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
 6632				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
 6633			break;
 6634		default:
 6635			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
 6636				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
 6637				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
 6638			break;
 6639		}
 6640		adev->gfx.kiq[0].ring.sched.ready = false;
 6641	}
 6642	udelay(50);
 6643}
 6644
 6645static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 6646{
 6647	const struct gfx_firmware_header_v1_0 *mec_hdr;
 6648	const __le32 *fw_data;
 6649	unsigned int i;
 6650	u32 tmp;
 6651	u32 usec_timeout = 50000; /* Wait for 50 ms */
 6652
 6653	if (!adev->gfx.mec_fw)
 6654		return -EINVAL;
 6655
 6656	gfx_v10_0_cp_compute_enable(adev, false);
 6657
 6658	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 6659	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
 6660
 6661	fw_data = (const __le32 *)
 6662		(adev->gfx.mec_fw->data +
 6663		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 6664
 6665	/* Trigger an invalidation of the L1 instruction caches */
 6666	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
 6667	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 6668	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
 6669
 6670	/* Wait for invalidation complete */
 6671	for (i = 0; i < usec_timeout; i++) {
 6672		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
 6673		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
 6674				       INVALIDATE_CACHE_COMPLETE))
 6675			break;
 6676		udelay(1);
 6677	}
 6678
 6679	if (i >= usec_timeout) {
 6680		dev_err(adev->dev, "failed to invalidate instruction cache\n");
 6681		return -EINVAL;
 6682	}
 6683
 6684	if (amdgpu_emu_mode == 1)
 6685		amdgpu_device_flush_hdp(adev, NULL);
 6686
 6687	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
 6688	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
 6689	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
 6690	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
 6691	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
 6692
 6693	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
 6694		     0xFFFFF000);
 6695	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
 6696		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
 6697
 6698	/* MEC1 */
 6699	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
 6700
 6701	for (i = 0; i < mec_hdr->jt_size; i++)
 6702		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
 6703			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
 6704
 6705	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
 6706
 6707	/*
 6708	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
 6709	 * different microcode than MEC1.
 6710	 */
 6711
 6712	return 0;
 6713}
 6714
 6715static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 6716{
 6717	uint32_t tmp;
 6718	struct amdgpu_device *adev = ring->adev;
 6719
 6720	/* tell RLC which is KIQ queue */
 6721	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 6722	case IP_VERSION(10, 3, 0):
 6723	case IP_VERSION(10, 3, 2):
 6724	case IP_VERSION(10, 3, 1):
 6725	case IP_VERSION(10, 3, 4):
 6726	case IP_VERSION(10, 3, 5):
 6727	case IP_VERSION(10, 3, 6):
 6728	case IP_VERSION(10, 3, 3):
 6729	case IP_VERSION(10, 3, 7):
 6730		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
 6731		tmp &= 0xffffff00;
 6732		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
 6733		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
 6734		break;
 6735	default:
 6736		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
 6737		tmp &= 0xffffff00;
 6738		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
 6739		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
 6740		break;
 6741	}
 6742}
 6743
 6744static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
 6745					   struct v10_gfx_mqd *mqd,
 6746					   struct amdgpu_mqd_prop *prop)
 6747{
 6748	bool priority = 0;
 6749	u32 tmp;
 6750
 6751	/* set up default queue priority level
 6752	 * 0x0 = low priority, 0x1 = high priority
 6753	 */
 6754	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
 6755		priority = 1;
 6756
 6757	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
 6758	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
 6759	mqd->cp_gfx_hqd_queue_priority = tmp;
 6760}
 6761
 6762static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
 6763				  struct amdgpu_mqd_prop *prop)
 6764{
 6765	struct v10_gfx_mqd *mqd = m;
 6766	uint64_t hqd_gpu_addr, wb_gpu_addr;
 6767	uint32_t tmp;
 6768	uint32_t rb_bufsz;
 6769
 6770	/* set up gfx hqd wptr */
 6771	mqd->cp_gfx_hqd_wptr = 0;
 6772	mqd->cp_gfx_hqd_wptr_hi = 0;
 6773
 6774	/* set the pointer to the MQD */
 6775	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
 6776	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
 6777
 6778	/* set up mqd control */
 6779	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
 6780	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
 6781	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
 6782	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
 6783	mqd->cp_gfx_mqd_control = tmp;
 6784
 6785	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
 6786	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
 6787	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
 6788	mqd->cp_gfx_hqd_vmid = 0;
 6789
 6790	/* set up gfx queue priority */
 6791	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
 6792
 6793	/* set up time quantum */
 6794	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
 6795	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
 6796	mqd->cp_gfx_hqd_quantum = tmp;
 6797
 6798	/* set up gfx hqd base. this is similar as CP_RB_BASE */
 6799	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
 6800	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
 6801	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
 6802
 6803	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
 6804	wb_gpu_addr = prop->rptr_gpu_addr;
 6805	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
 6806	mqd->cp_gfx_hqd_rptr_addr_hi =
 6807		upper_32_bits(wb_gpu_addr) & 0xffff;
 6808
 6809	/* set up rb_wptr_poll addr */
 6810	wb_gpu_addr = prop->wptr_gpu_addr;
 6811	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
 6812	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 6813
 6814	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
 6815	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
 6816	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
 6817	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
 6818	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
 6819#ifdef __BIG_ENDIAN
 6820	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
 6821#endif
 6822	mqd->cp_gfx_hqd_cntl = tmp;
 6823
 6824	/* set up cp_doorbell_control */
 6825	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
 6826	if (prop->use_doorbell) {
 6827		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6828				    DOORBELL_OFFSET, prop->doorbell_index);
 6829		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6830				    DOORBELL_EN, 1);
 6831	} else
 6832		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
 6833				    DOORBELL_EN, 0);
 6834	mqd->cp_rb_doorbell_control = tmp;
 6835
 6836	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 6837	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
 6838
 6839	/* active the queue */
 6840	mqd->cp_gfx_hqd_active = 1;
 6841
 6842	return 0;
 6843}
 6844
 6845static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
 6846{
 6847	struct amdgpu_device *adev = ring->adev;
 6848	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
 6849	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
 6850
 6851	if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
 6852		memset((void *)mqd, 0, sizeof(*mqd));
 6853		mutex_lock(&adev->srbm_mutex);
 6854		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 6855		amdgpu_ring_init_mqd(ring);
 6856
 6857		/*
 6858		 * if there are 2 gfx rings, set the lower doorbell
 6859		 * range of the first ring, otherwise the range of
 6860		 * the second ring will override the first ring
 6861		 */
 6862		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
 6863			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
 6864
 6865		nv_grbm_select(adev, 0, 0, 0, 0);
 6866		mutex_unlock(&adev->srbm_mutex);
 6867		if (adev->gfx.me.mqd_backup[mqd_idx])
 6868			memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
 6869	} else {
 6870		mutex_lock(&adev->srbm_mutex);
 6871		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 6872		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
 6873			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
 6874
 6875		nv_grbm_select(adev, 0, 0, 0, 0);
 6876		mutex_unlock(&adev->srbm_mutex);
 6877		/* restore mqd with the backup copy */
 6878		if (adev->gfx.me.mqd_backup[mqd_idx])
 6879			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
 6880		/* reset the ring */
 6881		ring->wptr = 0;
 6882		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
 6883		amdgpu_ring_clear_ring(ring);
 6884	}
 6885
 6886	return 0;
 6887}
 6888
 6889static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
 6890{
 6891	int r, i;
 6892
 6893	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 6894		r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
 6895		if (r)
 6896			return r;
 6897	}
 6898
 6899	r = amdgpu_gfx_enable_kgq(adev, 0);
 6900	if (r)
 6901		return r;
 6902
 6903	return gfx_v10_0_cp_gfx_start(adev);
 6904}
 6905
 6906static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 6907				      struct amdgpu_mqd_prop *prop)
 6908{
 6909	struct v10_compute_mqd *mqd = m;
 6910	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 6911	uint32_t tmp;
 6912
 6913	mqd->header = 0xC0310800;
 6914	mqd->compute_pipelinestat_enable = 0x00000001;
 6915	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 6916	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 6917	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 6918	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 6919	mqd->compute_misc_reserved = 0x00000003;
 6920
 6921	eop_base_addr = prop->eop_gpu_addr >> 8;
 6922	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
 6923	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 6924
 6925	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 6926	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
 6927	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 6928			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
 6929
 6930	mqd->cp_hqd_eop_control = tmp;
 6931
 6932	/* enable doorbell? */
 6933	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
 6934
 6935	if (prop->use_doorbell) {
 6936		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 6937				    DOORBELL_OFFSET, prop->doorbell_index);
 6938		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 6939				    DOORBELL_EN, 1);
 6940		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 6941				    DOORBELL_SOURCE, 0);
 6942		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 6943				    DOORBELL_HIT, 0);
 6944	} else {
 6945		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 6946				    DOORBELL_EN, 0);
 6947	}
 6948
 6949	mqd->cp_hqd_pq_doorbell_control = tmp;
 6950
 6951	/* disable the queue if it's active */
 6952	mqd->cp_hqd_dequeue_request = 0;
 6953	mqd->cp_hqd_pq_rptr = 0;
 6954	mqd->cp_hqd_pq_wptr_lo = 0;
 6955	mqd->cp_hqd_pq_wptr_hi = 0;
 6956
 6957	/* set the pointer to the MQD */
 6958	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
 6959	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
 6960
 6961	/* set MQD vmid to 0 */
 6962	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
 6963	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 6964	mqd->cp_mqd_control = tmp;
 6965
 6966	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 6967	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
 6968	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
 6969	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 6970
 6971	/* set up the HQD, this is similar to CP_RB0_CNTL */
 6972	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
 6973	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 6974			    (order_base_2(prop->queue_size / 4) - 1));
 6975	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 6976			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
 6977#ifdef __BIG_ENDIAN
 6978	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
 6979#endif
 6980	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 6981	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
 6982			    prop->allow_tunneling);
 6983	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 6984	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 6985	mqd->cp_hqd_pq_control = tmp;
 6986
 6987	/* set the wb address whether it's enabled or not */
 6988	wb_gpu_addr = prop->rptr_gpu_addr;
 6989	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 6990	mqd->cp_hqd_pq_rptr_report_addr_hi =
 6991		upper_32_bits(wb_gpu_addr) & 0xffff;
 6992
 6993	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 6994	wb_gpu_addr = prop->wptr_gpu_addr;
 6995	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
 6996	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 6997
 6998	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 6999	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
 7000
 7001	/* set the vmid for the queue */
 7002	mqd->cp_hqd_vmid = 0;
 7003
 7004	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
 7005	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
 7006	mqd->cp_hqd_persistent_state = tmp;
 7007
 7008	/* set MIN_IB_AVAIL_SIZE */
 7009	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
 7010	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
 7011	mqd->cp_hqd_ib_control = tmp;
 7012
 7013	/* set static priority for a compute queue/ring */
 7014	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
 7015	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
 7016
 7017	mqd->cp_hqd_active = prop->hqd_active;
 7018
 7019	return 0;
 7020}
 7021
 7022static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
 7023{
 7024	struct amdgpu_device *adev = ring->adev;
 7025	struct v10_compute_mqd *mqd = ring->mqd_ptr;
 7026	int j;
 7027
 7028	/* inactivate the queue */
 7029	if (amdgpu_sriov_vf(adev))
 7030		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
 7031
 7032	/* disable wptr polling */
 7033	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
 7034
 7035	/* disable the queue if it's active */
 7036	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
 7037		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
 7038		for (j = 0; j < adev->usec_timeout; j++) {
 7039			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
 7040				break;
 7041			udelay(1);
 7042		}
 7043		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
 7044		       mqd->cp_hqd_dequeue_request);
 7045		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
 7046		       mqd->cp_hqd_pq_rptr);
 7047		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
 7048		       mqd->cp_hqd_pq_wptr_lo);
 7049		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
 7050		       mqd->cp_hqd_pq_wptr_hi);
 7051	}
 7052
 7053	/* disable doorbells */
 7054	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
 7055
 7056	/* write the EOP addr */
 7057	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
 7058	       mqd->cp_hqd_eop_base_addr_lo);
 7059	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
 7060	       mqd->cp_hqd_eop_base_addr_hi);
 7061
 7062	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 7063	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
 7064	       mqd->cp_hqd_eop_control);
 7065
 7066	/* set the pointer to the MQD */
 7067	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
 7068	       mqd->cp_mqd_base_addr_lo);
 7069	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
 7070	       mqd->cp_mqd_base_addr_hi);
 7071
 7072	/* set MQD vmid to 0 */
 7073	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
 7074	       mqd->cp_mqd_control);
 7075
 7076	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 7077	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
 7078	       mqd->cp_hqd_pq_base_lo);
 7079	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
 7080	       mqd->cp_hqd_pq_base_hi);
 7081
 7082	/* set up the HQD, this is similar to CP_RB0_CNTL */
 7083	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
 7084	       mqd->cp_hqd_pq_control);
 7085
 7086	/* set the wb address whether it's enabled or not */
 7087	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
 7088		mqd->cp_hqd_pq_rptr_report_addr_lo);
 7089	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 7090		mqd->cp_hqd_pq_rptr_report_addr_hi);
 7091
 7092	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 7093	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
 7094	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
 7095	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 7096	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
 7097
 7098	/* enable the doorbell if requested */
 7099	if (ring->use_doorbell) {
 7100		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
 7101			(adev->doorbell_index.kiq * 2) << 2);
 7102		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
 7103			(adev->doorbell_index.userqueue_end * 2) << 2);
 7104	}
 7105
 7106	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
 7107	       mqd->cp_hqd_pq_doorbell_control);
 7108
 7109	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 7110	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
 7111	       mqd->cp_hqd_pq_wptr_lo);
 7112	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
 7113	       mqd->cp_hqd_pq_wptr_hi);
 7114
 7115	/* set the vmid for the queue */
 7116	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
 7117
 7118	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
 7119	       mqd->cp_hqd_persistent_state);
 7120
 7121	/* activate the queue */
 7122	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
 7123	       mqd->cp_hqd_active);
 7124
 7125	if (ring->use_doorbell)
 7126		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
 7127
 7128	return 0;
 7129}
 7130
 7131static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
 7132{
 7133	struct amdgpu_device *adev = ring->adev;
 7134	struct v10_compute_mqd *mqd = ring->mqd_ptr;
 7135
 7136	gfx_v10_0_kiq_setting(ring);
 7137
 7138	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
 7139		/* reset MQD to a clean status */
 7140		if (adev->gfx.kiq[0].mqd_backup)
 7141			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
 7142
 7143		/* reset ring buffer */
 7144		ring->wptr = 0;
 7145		amdgpu_ring_clear_ring(ring);
 7146
 7147		mutex_lock(&adev->srbm_mutex);
 7148		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 7149		gfx_v10_0_kiq_init_register(ring);
 7150		nv_grbm_select(adev, 0, 0, 0, 0);
 7151		mutex_unlock(&adev->srbm_mutex);
 7152	} else {
 7153		memset((void *)mqd, 0, sizeof(*mqd));
 7154		if (amdgpu_sriov_vf(adev) && adev->in_suspend)
 7155			amdgpu_ring_clear_ring(ring);
 7156		mutex_lock(&adev->srbm_mutex);
 7157		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 7158		amdgpu_ring_init_mqd(ring);
 7159		gfx_v10_0_kiq_init_register(ring);
 7160		nv_grbm_select(adev, 0, 0, 0, 0);
 7161		mutex_unlock(&adev->srbm_mutex);
 7162
 7163		if (adev->gfx.kiq[0].mqd_backup)
 7164			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
 7165	}
 7166
 7167	return 0;
 7168}
 7169
 7170static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
 7171{
 7172	struct amdgpu_device *adev = ring->adev;
 7173	struct v10_compute_mqd *mqd = ring->mqd_ptr;
 7174	int mqd_idx = ring - &adev->gfx.compute_ring[0];
 7175
 7176	if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
 7177		memset((void *)mqd, 0, sizeof(*mqd));
 7178		mutex_lock(&adev->srbm_mutex);
 7179		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 7180		amdgpu_ring_init_mqd(ring);
 7181		nv_grbm_select(adev, 0, 0, 0, 0);
 7182		mutex_unlock(&adev->srbm_mutex);
 7183
 7184		if (adev->gfx.mec.mqd_backup[mqd_idx])
 7185			memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
 7186	} else {
 7187		/* restore MQD to a clean status */
 7188		if (adev->gfx.mec.mqd_backup[mqd_idx])
 7189			memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
 7190		/* reset ring buffer */
 7191		ring->wptr = 0;
 7192		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
 7193		amdgpu_ring_clear_ring(ring);
 7194	}
 7195
 7196	return 0;
 7197}
 7198
 7199static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
 7200{
 7201	gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
 7202	return 0;
 7203}
 7204
 7205static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
 7206{
 7207	int i, r;
 7208
 7209	gfx_v10_0_cp_compute_enable(adev, true);
 7210
 7211	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 7212		r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i],
 7213					     false);
 7214		if (r)
 7215			return r;
 7216	}
 7217
 7218	return amdgpu_gfx_enable_kcq(adev, 0);
 7219}
 7220
 7221static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
 7222{
 7223	int r, i;
 7224	struct amdgpu_ring *ring;
 7225
 7226	if (!(adev->flags & AMD_IS_APU))
 7227		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
 7228
 7229	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 7230		/* legacy firmware loading */
 7231		r = gfx_v10_0_cp_gfx_load_microcode(adev);
 7232		if (r)
 7233			return r;
 7234
 7235		r = gfx_v10_0_cp_compute_load_microcode(adev);
 7236		if (r)
 7237			return r;
 7238	}
 7239
 7240	r = gfx_v10_0_kiq_resume(adev);
 7241	if (r)
 7242		return r;
 7243
 7244	r = gfx_v10_0_kcq_resume(adev);
 7245	if (r)
 7246		return r;
 7247
 7248	if (!amdgpu_async_gfx_ring) {
 7249		r = gfx_v10_0_cp_gfx_resume(adev);
 7250		if (r)
 7251			return r;
 7252	} else {
 7253		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
 7254		if (r)
 7255			return r;
 7256	}
 7257
 7258	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 7259		ring = &adev->gfx.gfx_ring[i];
 7260		r = amdgpu_ring_test_helper(ring);
 7261		if (r)
 7262			return r;
 7263	}
 7264
 7265	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 7266		ring = &adev->gfx.compute_ring[i];
 7267		r = amdgpu_ring_test_helper(ring);
 7268		if (r)
 7269			return r;
 7270	}
 7271
 7272	return 0;
 7273}
 7274
 7275static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
 7276{
 7277	gfx_v10_0_cp_gfx_enable(adev, enable);
 7278	gfx_v10_0_cp_compute_enable(adev, enable);
 7279}
 7280
 7281static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 7282{
 7283	uint32_t data, pattern = 0xDEADBEEF;
 7284
 7285	/*
 7286	 * check if mmVGT_ESGS_RING_SIZE_UMD
 7287	 * has been remapped to mmVGT_ESGS_RING_SIZE
 7288	 */
 7289	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7290	case IP_VERSION(10, 3, 0):
 7291	case IP_VERSION(10, 3, 2):
 7292	case IP_VERSION(10, 3, 4):
 7293	case IP_VERSION(10, 3, 5):
 7294		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
 7295		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
 7296		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
 7297
 7298		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
 7299			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
 7300			return true;
 7301		}
 7302		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
 7303		break;
 7304	case IP_VERSION(10, 3, 1):
 7305	case IP_VERSION(10, 3, 3):
 7306	case IP_VERSION(10, 3, 6):
 7307	case IP_VERSION(10, 3, 7):
 7308		return true;
 7309	default:
 7310		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
 7311		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
 7312		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
 7313
 7314		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
 7315			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
 7316			return true;
 7317		}
 7318		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
 7319		break;
 7320	}
 7321
 7322	return false;
 7323}
 7324
 7325static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 7326{
 7327	uint32_t data;
 7328
 7329	if (amdgpu_sriov_vf(adev))
 7330		return;
 7331
 7332	/*
 7333	 * Initialize cam_index to 0
 7334	 * index will auto-inc after each data writing
 7335	 */
 7336	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
 7337
 7338	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7339	case IP_VERSION(10, 3, 0):
 7340	case IP_VERSION(10, 3, 2):
 7341	case IP_VERSION(10, 3, 1):
 7342	case IP_VERSION(10, 3, 4):
 7343	case IP_VERSION(10, 3, 5):
 7344	case IP_VERSION(10, 3, 6):
 7345	case IP_VERSION(10, 3, 3):
 7346	case IP_VERSION(10, 3, 7):
 7347		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
 7348		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
 7349			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7350		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
 7351			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7352		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7353		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7354
 7355		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
 7356		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
 7357			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7358		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
 7359			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7360		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7361		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7362
 7363		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
 7364		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
 7365			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7366		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
 7367			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7368		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7369		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7370
 7371		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
 7372		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
 7373			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7374		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
 7375			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7376		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7377		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7378
 7379		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
 7380		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
 7381			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7382		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
 7383			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7384		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7385		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7386
 7387		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
 7388		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
 7389			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7390		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
 7391			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7392		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7393		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7394
 7395		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
 7396		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
 7397			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7398		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
 7399			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7400		break;
 7401	default:
 7402		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
 7403		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
 7404			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7405		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
 7406			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7407		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7408		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7409
 7410		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
 7411		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
 7412			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7413		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
 7414			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7415		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7416		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7417
 7418		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
 7419		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
 7420			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7421		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
 7422			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7423		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7424		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7425
 7426		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
 7427		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
 7428			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7429		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
 7430			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7431		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7432		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7433
 7434		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
 7435		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
 7436			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7437		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
 7438			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7439		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7440		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7441
 7442		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
 7443		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
 7444			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7445		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
 7446			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7447		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7448		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7449
 7450		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
 7451		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
 7452			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
 7453		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
 7454			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
 7455		break;
 7456	}
 7457
 7458	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
 7459	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 7460}
 7461
 7462static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
 7463{
 7464	uint32_t data;
 7465
 7466	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
 7467	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
 7468	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
 7469
 7470	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
 7471	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
 7472	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
 7473}
 7474
 7475static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
 7476{
 7477	int r;
 7478	struct amdgpu_device *adev = ip_block->adev;
 7479
 7480	if (!amdgpu_emu_mode)
 7481		gfx_v10_0_init_golden_registers(adev);
 7482
 7483	amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
 7484				       adev->gfx.cleaner_shader_ptr);
 7485
 7486	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 7487		/**
 7488		 * For gfx 10, rlc firmware loading relies on smu firmware is
 7489		 * loaded firstly, so in direct type, it has to load smc ucode
 7490		 * here before rlc.
 7491		 */
 7492		r = amdgpu_pm_load_smu_firmware(adev, NULL);
 7493		if (r)
 7494			return r;
 7495		gfx_v10_0_disable_gpa_mode(adev);
 7496	}
 7497
 7498	/* if GRBM CAM not remapped, set up the remapping */
 7499	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
 7500		gfx_v10_0_setup_grbm_cam_remapping(adev);
 7501
 7502	gfx_v10_0_constants_init(adev);
 7503
 7504	r = gfx_v10_0_rlc_resume(adev);
 7505	if (r)
 7506		return r;
 7507
 7508	/*
 7509	 * init golden registers and rlc resume may override some registers,
 7510	 * reconfig them here
 7511	 */
 7512	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
 7513	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
 7514	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
 7515		gfx_v10_0_tcp_harvest(adev);
 7516
 7517	r = gfx_v10_0_cp_resume(adev);
 7518	if (r)
 7519		return r;
 7520
 7521	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
 7522		gfx_v10_3_program_pbb_mode(adev);
 7523
 7524	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
 7525		gfx_v10_3_set_power_brake_sequence(adev);
 7526
 7527	return r;
 7528}
 7529
 7530static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
 7531{
 7532	struct amdgpu_device *adev = ip_block->adev;
 7533
 7534	cancel_delayed_work_sync(&adev->gfx.idle_work);
 7535
 7536	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 7537	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 7538	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
 7539
 7540	/* WA added for Vangogh asic fixing the SMU suspend failure
 7541	 * It needs to set power gating again during gfxoff control
 7542	 * otherwise the gfxoff disallowing will be failed to set.
 7543	 */
 7544	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
 7545		gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
 7546
 7547	if (!adev->no_hw_access) {
 7548		if (amdgpu_async_gfx_ring) {
 7549			if (amdgpu_gfx_disable_kgq(adev, 0))
 7550				DRM_ERROR("KGQ disable failed\n");
 7551		}
 7552
 7553		if (amdgpu_gfx_disable_kcq(adev, 0))
 7554			DRM_ERROR("KCQ disable failed\n");
 7555	}
 7556
 7557	if (amdgpu_sriov_vf(adev)) {
 7558		gfx_v10_0_cp_gfx_enable(adev, false);
 7559		/* Remove the steps of clearing KIQ position.
 7560		 * It causes GFX hang when another Win guest is rendering.
 7561		 */
 7562		return 0;
 7563	}
 7564	gfx_v10_0_cp_enable(adev, false);
 7565	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
 7566
 7567	return 0;
 7568}
 7569
 7570static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
 7571{
 7572	return gfx_v10_0_hw_fini(ip_block);
 7573}
 7574
 7575static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
 7576{
 7577	return gfx_v10_0_hw_init(ip_block);
 7578}
 7579
 7580static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
 7581{
 7582	struct amdgpu_device *adev = ip_block->adev;
 7583
 7584	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
 7585				GRBM_STATUS, GUI_ACTIVE))
 7586		return false;
 7587	else
 7588		return true;
 7589}
 7590
 7591static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 7592{
 7593	unsigned int i;
 7594	u32 tmp;
 7595	struct amdgpu_device *adev = ip_block->adev;
 7596
 7597	for (i = 0; i < adev->usec_timeout; i++) {
 7598		/* read MC_STATUS */
 7599		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
 7600			GRBM_STATUS__GUI_ACTIVE_MASK;
 7601
 7602		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
 7603			return 0;
 7604		udelay(1);
 7605	}
 7606	return -ETIMEDOUT;
 7607}
 7608
 7609static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
 7610{
 7611	u32 grbm_soft_reset = 0;
 7612	u32 tmp;
 7613	struct amdgpu_device *adev = ip_block->adev;
 7614
 7615	/* GRBM_STATUS */
 7616	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
 7617	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
 7618		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
 7619		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
 7620		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
 7621		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
 7622		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 7623						GRBM_SOFT_RESET, SOFT_RESET_CP,
 7624						1);
 7625		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 7626						GRBM_SOFT_RESET, SOFT_RESET_GFX,
 7627						1);
 7628	}
 7629
 7630	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
 7631		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 7632						GRBM_SOFT_RESET, SOFT_RESET_CP,
 7633						1);
 7634	}
 7635
 7636	/* GRBM_STATUS2 */
 7637	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
 7638	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7639	case IP_VERSION(10, 3, 0):
 7640	case IP_VERSION(10, 3, 2):
 7641	case IP_VERSION(10, 3, 1):
 7642	case IP_VERSION(10, 3, 4):
 7643	case IP_VERSION(10, 3, 5):
 7644	case IP_VERSION(10, 3, 6):
 7645	case IP_VERSION(10, 3, 3):
 7646		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
 7647			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 7648							GRBM_SOFT_RESET,
 7649							SOFT_RESET_RLC,
 7650							1);
 7651		break;
 7652	default:
 7653		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
 7654			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 7655							GRBM_SOFT_RESET,
 7656							SOFT_RESET_RLC,
 7657							1);
 7658		break;
 7659	}
 7660
 7661	if (grbm_soft_reset) {
 7662		/* stop the rlc */
 7663		gfx_v10_0_rlc_stop(adev);
 7664
 7665		/* Disable GFX parsing/prefetching */
 7666		gfx_v10_0_cp_gfx_enable(adev, false);
 7667
 7668		/* Disable MEC parsing/prefetching */
 7669		gfx_v10_0_cp_compute_enable(adev, false);
 7670
 7671		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 7672		tmp |= grbm_soft_reset;
 7673		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 7674		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 7675		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 7676
 7677		udelay(50);
 7678
 7679		tmp &= ~grbm_soft_reset;
 7680		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 7681		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 7682
 7683		/* Wait a little for things to settle down */
 7684		udelay(50);
 7685	}
 7686	return 0;
 7687}
 7688
 7689static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 7690{
 7691	uint64_t clock, clock_lo, clock_hi, hi_check;
 7692
 7693	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7694	case IP_VERSION(10, 1, 3):
 7695	case IP_VERSION(10, 1, 4):
 7696		preempt_disable();
 7697		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
 7698		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
 7699		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
 7700		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
 7701		 * roughly every 42 seconds.
 7702		 */
 7703		if (hi_check != clock_hi) {
 7704			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
 7705			clock_hi = hi_check;
 7706		}
 7707		preempt_enable();
 7708		clock = clock_lo | (clock_hi << 32ULL);
 7709		break;
 7710	case IP_VERSION(10, 3, 1):
 7711	case IP_VERSION(10, 3, 3):
 7712	case IP_VERSION(10, 3, 7):
 7713		preempt_disable();
 7714		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
 7715		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
 7716		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
 7717		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
 7718		 * roughly every 42 seconds.
 7719		 */
 7720		if (hi_check != clock_hi) {
 7721			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
 7722			clock_hi = hi_check;
 7723		}
 7724		preempt_enable();
 7725		clock = clock_lo | (clock_hi << 32ULL);
 7726		break;
 7727	case IP_VERSION(10, 3, 6):
 7728		preempt_disable();
 7729		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
 7730		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
 7731		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
 7732		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
 7733		 * roughly every 42 seconds.
 7734		 */
 7735		if (hi_check != clock_hi) {
 7736			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
 7737			clock_hi = hi_check;
 7738		}
 7739		preempt_enable();
 7740		clock = clock_lo | (clock_hi << 32ULL);
 7741		break;
 7742	default:
 7743		preempt_disable();
 7744		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
 7745		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
 7746		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
 7747		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
 7748		 * roughly every 42 seconds.
 7749		 */
 7750		if (hi_check != clock_hi) {
 7751			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
 7752			clock_hi = hi_check;
 7753		}
 7754		preempt_enable();
 7755		clock = clock_lo | (clock_hi << 32ULL);
 7756		break;
 7757	}
 7758	return clock;
 7759}
 7760
 7761static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
 7762					   uint32_t vmid,
 7763					   uint32_t gds_base, uint32_t gds_size,
 7764					   uint32_t gws_base, uint32_t gws_size,
 7765					   uint32_t oa_base, uint32_t oa_size)
 7766{
 7767	struct amdgpu_device *adev = ring->adev;
 7768
 7769	/* GDS Base */
 7770	gfx_v10_0_write_data_to_reg(ring, 0, false,
 7771				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
 7772				    gds_base);
 7773
 7774	/* GDS Size */
 7775	gfx_v10_0_write_data_to_reg(ring, 0, false,
 7776				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
 7777				    gds_size);
 7778
 7779	/* GWS */
 7780	gfx_v10_0_write_data_to_reg(ring, 0, false,
 7781				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
 7782				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
 7783
 7784	/* OA */
 7785	gfx_v10_0_write_data_to_reg(ring, 0, false,
 7786				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
 7787				    (1 << (oa_size + oa_base)) - (1 << oa_base));
 7788}
 7789
 7790static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
 7791{
 7792	struct amdgpu_device *adev = ip_block->adev;
 7793
 7794	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
 7795
 7796	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7797	case IP_VERSION(10, 1, 10):
 7798	case IP_VERSION(10, 1, 1):
 7799	case IP_VERSION(10, 1, 2):
 7800	case IP_VERSION(10, 1, 3):
 7801	case IP_VERSION(10, 1, 4):
 7802		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
 7803		break;
 7804	case IP_VERSION(10, 3, 0):
 7805	case IP_VERSION(10, 3, 2):
 7806	case IP_VERSION(10, 3, 1):
 7807	case IP_VERSION(10, 3, 4):
 7808	case IP_VERSION(10, 3, 5):
 7809	case IP_VERSION(10, 3, 6):
 7810	case IP_VERSION(10, 3, 3):
 7811	case IP_VERSION(10, 3, 7):
 7812		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
 7813		break;
 7814	default:
 7815		break;
 7816	}
 7817
 7818	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
 7819					  AMDGPU_MAX_COMPUTE_RINGS);
 7820
 7821	gfx_v10_0_set_kiq_pm4_funcs(adev);
 7822	gfx_v10_0_set_ring_funcs(adev);
 7823	gfx_v10_0_set_irq_funcs(adev);
 7824	gfx_v10_0_set_gds_init(adev);
 7825	gfx_v10_0_set_rlc_funcs(adev);
 7826	gfx_v10_0_set_mqd_funcs(adev);
 7827
 7828	/* init rlcg reg access ctrl */
 7829	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
 7830
 7831	return gfx_v10_0_init_microcode(adev);
 7832}
 7833
 7834static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
 7835{
 7836	struct amdgpu_device *adev = ip_block->adev;
 7837	int r;
 7838
 7839	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
 7840	if (r)
 7841		return r;
 7842
 7843	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
 7844	if (r)
 7845		return r;
 7846
 7847	r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
 7848	if (r)
 7849		return r;
 7850
 7851	return 0;
 7852}
 7853
 7854static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
 7855{
 7856	uint32_t rlc_cntl;
 7857
 7858	/* if RLC is not enabled, do nothing */
 7859	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
 7860	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
 7861}
 7862
 7863static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 7864{
 7865	uint32_t data;
 7866	unsigned int i;
 7867
 7868	data = RLC_SAFE_MODE__CMD_MASK;
 7869	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
 7870
 7871	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7872	case IP_VERSION(10, 3, 0):
 7873	case IP_VERSION(10, 3, 2):
 7874	case IP_VERSION(10, 3, 1):
 7875	case IP_VERSION(10, 3, 4):
 7876	case IP_VERSION(10, 3, 5):
 7877	case IP_VERSION(10, 3, 6):
 7878	case IP_VERSION(10, 3, 3):
 7879	case IP_VERSION(10, 3, 7):
 7880		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 7881
 7882		/* wait for RLC_SAFE_MODE */
 7883		for (i = 0; i < adev->usec_timeout; i++) {
 7884			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
 7885					   RLC_SAFE_MODE, CMD))
 7886				break;
 7887			udelay(1);
 7888		}
 7889		break;
 7890	default:
 7891		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
 7892
 7893		/* wait for RLC_SAFE_MODE */
 7894		for (i = 0; i < adev->usec_timeout; i++) {
 7895			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
 7896					   RLC_SAFE_MODE, CMD))
 7897				break;
 7898			udelay(1);
 7899		}
 7900		break;
 7901	}
 7902}
 7903
 7904static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 7905{
 7906	uint32_t data;
 7907
 7908	data = RLC_SAFE_MODE__CMD_MASK;
 7909	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 7910	case IP_VERSION(10, 3, 0):
 7911	case IP_VERSION(10, 3, 2):
 7912	case IP_VERSION(10, 3, 1):
 7913	case IP_VERSION(10, 3, 4):
 7914	case IP_VERSION(10, 3, 5):
 7915	case IP_VERSION(10, 3, 6):
 7916	case IP_VERSION(10, 3, 3):
 7917	case IP_VERSION(10, 3, 7):
 7918		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 7919		break;
 7920	default:
 7921		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
 7922		break;
 7923	}
 7924}
 7925
 7926static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 7927						      bool enable)
 7928{
 7929	uint32_t data, def;
 7930
 7931	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
 7932		return;
 7933
 7934	/* It is disabled by HW by default */
 7935	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
 7936		/* 0 - Disable some blocks' MGCG */
 7937		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
 7938		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
 7939		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
 7940		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
 7941
 7942		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
 7943		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 7944		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
 7945			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
 7946			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 7947			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
 7948			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
 7949			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
 7950
 7951		if (def != data)
 7952			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 7953
 7954		/* MGLS is a global flag to control all MGLS in GFX */
 7955		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
 7956			/* 2 - RLC memory Light sleep */
 7957			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
 7958				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
 7959				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
 7960				if (def != data)
 7961					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
 7962			}
 7963			/* 3 - CP memory Light sleep */
 7964			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
 7965				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
 7966				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
 7967				if (def != data)
 7968					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
 7969			}
 7970		}
 7971	} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
 7972		/* 1 - MGCG_OVERRIDE */
 7973		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 7974		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
 7975			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
 7976			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 7977			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
 7978			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
 7979			 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
 7980		if (def != data)
 7981			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 7982
 7983		/* 2 - disable MGLS in CP */
 7984		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
 7985		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
 7986			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
 7987			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
 7988		}
 7989
 7990		/* 3 - disable MGLS in RLC */
 7991		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
 7992		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
 7993			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
 7994			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
 7995		}
 7996
 7997	}
 7998}
 7999
 8000static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
 8001					   bool enable)
 8002{
 8003	uint32_t data, def;
 8004
 8005	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
 8006		return;
 8007
 8008	/* Enable 3D CGCG/CGLS */
 8009	if (enable) {
 8010		/* write cmd to clear cgcg/cgls ov */
 8011		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 8012
 8013		/* unset CGCG override */
 8014		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
 8015			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
 8016
 8017		/* update CGCG and CGLS override bits */
 8018		if (def != data)
 8019			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 8020
 8021		/* enable 3Dcgcg FSM(0x0000363f) */
 8022		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
 8023		data = 0;
 8024
 8025		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
 8026			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
 8027				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
 8028
 8029		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
 8030			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
 8031				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
 8032
 8033		if (def != data)
 8034			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
 8035
 8036		/* set IDLE_POLL_COUNT(0x00900100) */
 8037		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
 8038		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
 8039			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
 8040		if (def != data)
 8041			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
 8042	} else {
 8043		/* Disable CGCG/CGLS */
 8044		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
 8045
 8046		/* disable cgcg, cgls should be disabled */
 8047		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
 8048			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
 8049
 8050		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
 8051			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
 8052
 8053		/* disable cgcg and cgls in FSM */
 8054		if (def != data)
 8055			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
 8056	}
 8057}
 8058
 8059static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
 8060						      bool enable)
 8061{
 8062	uint32_t def, data;
 8063
 8064	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
 8065		return;
 8066
 8067	if (enable) {
 8068		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 8069
 8070		/* unset CGCG override */
 8071		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
 8072			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
 8073
 8074		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
 8075			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
 8076
 8077		/* update CGCG and CGLS override bits */
 8078		if (def != data)
 8079			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 8080
 8081		/* enable cgcg FSM(0x0000363F) */
 8082		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
 8083		data = 0;
 8084
 8085		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
 8086			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
 8087				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
 8088
 8089		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
 8090			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
 8091				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
 8092
 8093		if (def != data)
 8094			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
 8095
 8096		/* set IDLE_POLL_COUNT(0x00900100) */
 8097		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
 8098		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
 8099			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
 8100		if (def != data)
 8101			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
 8102	} else {
 8103		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
 8104
 8105		/* reset CGCG/CGLS bits */
 8106		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
 8107			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
 8108
 8109		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
 8110			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
 8111
 8112		/* disable cgcg and cgls in FSM */
 8113		if (def != data)
 8114			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
 8115	}
 8116}
 8117
 8118static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
 8119						      bool enable)
 8120{
 8121	uint32_t def, data;
 8122
 8123	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
 8124		return;
 8125
 8126	if (enable) {
 8127		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 8128		/* unset FGCG override */
 8129		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
 8130		/* update FGCG override bits */
 8131		if (def != data)
 8132			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 8133
 8134		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
 8135		/* unset RLC SRAM CLK GATER override */
 8136		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
 8137		/* update RLC SRAM CLK GATER override bits */
 8138		if (def != data)
 8139			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
 8140	} else {
 8141		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 8142		/* reset FGCG bits */
 8143		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
 8144		/* disable FGCG*/
 8145		if (def != data)
 8146			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 8147
 8148		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
 8149		/* reset RLC SRAM CLK GATER bits */
 8150		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
 8151		/* disable RLC SRAM CLK*/
 8152		if (def != data)
 8153			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
 8154	}
 8155}
 8156
 8157static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
 8158{
 8159	uint32_t reg_data = 0;
 8160	uint32_t reg_idx = 0;
 8161	uint32_t i;
 8162
 8163	const uint32_t tcp_ctrl_regs[] = {
 8164		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
 8165		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
 8166		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
 8167		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
 8168		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
 8169		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
 8170		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
 8171		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
 8172		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
 8173		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
 8174		mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
 8175		mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
 8176		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
 8177		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
 8178		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
 8179		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
 8180		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
 8181		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
 8182		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
 8183		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
 8184		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
 8185		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
 8186		mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
 8187		mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
 8188	};
 8189
 8190	const uint32_t tcp_ctrl_regs_nv12[] = {
 8191		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
 8192		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
 8193		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
 8194		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
 8195		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
 8196		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
 8197		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
 8198		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
 8199		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
 8200		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
 8201		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
 8202		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
 8203		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
 8204		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
 8205		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
 8206		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
 8207		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
 8208		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
 8209		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
 8210		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
 8211	};
 8212
 8213	const uint32_t sm_ctlr_regs[] = {
 8214		mmCGTS_SA0_QUAD0_SM_CTRL_REG,
 8215		mmCGTS_SA0_QUAD1_SM_CTRL_REG,
 8216		mmCGTS_SA1_QUAD0_SM_CTRL_REG,
 8217		mmCGTS_SA1_QUAD1_SM_CTRL_REG
 8218	};
 8219
 8220	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
 8221		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
 8222			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
 8223				  tcp_ctrl_regs_nv12[i];
 8224			reg_data = RREG32(reg_idx);
 8225			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
 8226			WREG32(reg_idx, reg_data);
 8227		}
 8228	} else {
 8229		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
 8230			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
 8231				  tcp_ctrl_regs[i];
 8232			reg_data = RREG32(reg_idx);
 8233			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
 8234			WREG32(reg_idx, reg_data);
 8235		}
 8236	}
 8237
 8238	for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
 8239		reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
 8240			  sm_ctlr_regs[i];
 8241		reg_data = RREG32(reg_idx);
 8242		reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
 8243		reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
 8244		WREG32(reg_idx, reg_data);
 8245	}
 8246}
 8247
 8248static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 8249					    bool enable)
 8250{
 8251	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 8252
 8253	if (enable) {
 8254		/* enable FGCG firstly*/
 8255		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
 8256		/* CGCG/CGLS should be enabled after MGCG/MGLS
 8257		 * ===  MGCG + MGLS ===
 8258		 */
 8259		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
 8260		/* ===  CGCG /CGLS for GFX 3D Only === */
 8261		gfx_v10_0_update_3d_clock_gating(adev, enable);
 8262		/* ===  CGCG + CGLS === */
 8263		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
 8264
 8265		if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
 8266		     IP_VERSION(10, 1, 10)) ||
 8267		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
 8268		     IP_VERSION(10, 1, 1)) ||
 8269		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
 8270		     IP_VERSION(10, 1, 2)))
 8271			gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
 8272	} else {
 8273		/* CGCG/CGLS should be disabled before MGCG/MGLS
 8274		 * ===  CGCG + CGLS ===
 8275		 */
 8276		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
 8277		/* ===  CGCG /CGLS for GFX 3D Only === */
 8278		gfx_v10_0_update_3d_clock_gating(adev, enable);
 8279		/* ===  MGCG + MGLS === */
 8280		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
 8281		/* disable fgcg at last*/
 8282		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
 8283	}
 8284
 8285	if (adev->cg_flags &
 8286	    (AMD_CG_SUPPORT_GFX_MGCG |
 8287	     AMD_CG_SUPPORT_GFX_CGLS |
 8288	     AMD_CG_SUPPORT_GFX_CGCG |
 8289	     AMD_CG_SUPPORT_GFX_3D_CGCG |
 8290	     AMD_CG_SUPPORT_GFX_3D_CGLS))
 8291		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
 8292
 8293	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 8294
 8295	return 0;
 8296}
 8297
 8298static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
 8299					       unsigned int vmid)
 8300{
 8301	u32 reg, pre_data, data;
 8302
 8303	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
 8304	/* not for *_SOC15 */
 8305	if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
 8306		pre_data = RREG32_NO_KIQ(reg);
 8307	else
 8308		pre_data = RREG32(reg);
 8309
 8310	data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
 8311	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 8312
 8313	if (pre_data != data) {
 8314		if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
 8315			WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 8316		} else
 8317			WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
 8318	}
 8319}
 8320
 8321static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
 8322{
 8323	amdgpu_gfx_off_ctrl(adev, false);
 8324
 8325	gfx_v10_0_update_spm_vmid_internal(adev, vmid);
 8326
 8327	amdgpu_gfx_off_ctrl(adev, true);
 8328}
 8329
 8330static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
 8331					uint32_t offset,
 8332					struct soc15_reg_rlcg *entries, int arr_size)
 8333{
 8334	int i;
 8335	uint32_t reg;
 8336
 8337	if (!entries)
 8338		return false;
 8339
 8340	for (i = 0; i < arr_size; i++) {
 8341		const struct soc15_reg_rlcg *entry;
 8342
 8343		entry = &entries[i];
 8344		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 8345		if (offset == reg)
 8346			return true;
 8347	}
 8348
 8349	return false;
 8350}
 8351
 8352static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
 8353{
 8354	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
 8355}
 8356
 8357static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
 8358{
 8359	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
 8360
 8361	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
 8362		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
 8363	else
 8364		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
 8365
 8366	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
 8367
 8368	/*
 8369	 * CGPG enablement required and the register to program the hysteresis value
 8370	 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
 8371	 * in refclk count. Note that RLC FW is modified to take 16 bits from
 8372	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
 8373	 *
 8374	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
 8375	 * of CGPG enablement starting point.
 8376	 * Power/performance team will optimize it and might give a new value later.
 8377	 */
 8378	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
 8379		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 8380		case IP_VERSION(10, 3, 1):
 8381		case IP_VERSION(10, 3, 3):
 8382		case IP_VERSION(10, 3, 6):
 8383		case IP_VERSION(10, 3, 7):
 8384			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
 8385			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
 8386			break;
 8387		default:
 8388			break;
 8389		}
 8390	}
 8391}
 8392
 8393static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
 8394{
 8395	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 8396
 8397	gfx_v10_cntl_power_gating(adev, enable);
 8398
 8399	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 8400}
 8401
 8402static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
 8403	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
 8404	.set_safe_mode = gfx_v10_0_set_safe_mode,
 8405	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
 8406	.init = gfx_v10_0_rlc_init,
 8407	.get_csb_size = gfx_v10_0_get_csb_size,
 8408	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
 8409	.resume = gfx_v10_0_rlc_resume,
 8410	.stop = gfx_v10_0_rlc_stop,
 8411	.reset = gfx_v10_0_rlc_reset,
 8412	.start = gfx_v10_0_rlc_start,
 8413	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
 8414};
 8415
 8416static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
 8417	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
 8418	.set_safe_mode = gfx_v10_0_set_safe_mode,
 8419	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
 8420	.init = gfx_v10_0_rlc_init,
 8421	.get_csb_size = gfx_v10_0_get_csb_size,
 8422	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
 8423	.resume = gfx_v10_0_rlc_resume,
 8424	.stop = gfx_v10_0_rlc_stop,
 8425	.reset = gfx_v10_0_rlc_reset,
 8426	.start = gfx_v10_0_rlc_start,
 8427	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
 8428	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
 8429};
 8430
 8431static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
 8432					  enum amd_powergating_state state)
 8433{
 8434	struct amdgpu_device *adev = ip_block->adev;
 8435	bool enable = (state == AMD_PG_STATE_GATE);
 8436
 8437	if (amdgpu_sriov_vf(adev))
 8438		return 0;
 8439
 8440	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 8441	case IP_VERSION(10, 1, 10):
 8442	case IP_VERSION(10, 1, 1):
 8443	case IP_VERSION(10, 1, 2):
 8444	case IP_VERSION(10, 3, 0):
 8445	case IP_VERSION(10, 3, 2):
 8446	case IP_VERSION(10, 3, 4):
 8447	case IP_VERSION(10, 3, 5):
 8448		amdgpu_gfx_off_ctrl(adev, enable);
 8449		break;
 8450	case IP_VERSION(10, 3, 1):
 8451	case IP_VERSION(10, 3, 3):
 8452	case IP_VERSION(10, 3, 6):
 8453	case IP_VERSION(10, 3, 7):
 8454		if (!enable)
 8455			amdgpu_gfx_off_ctrl(adev, false);
 8456
 8457		gfx_v10_cntl_pg(adev, enable);
 8458
 8459		if (enable)
 8460			amdgpu_gfx_off_ctrl(adev, true);
 8461
 8462		break;
 8463	default:
 8464		break;
 8465	}
 8466	return 0;
 8467}
 8468
 8469static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 8470					  enum amd_clockgating_state state)
 8471{
 8472	struct amdgpu_device *adev = ip_block->adev;
 8473
 8474	if (amdgpu_sriov_vf(adev))
 8475		return 0;
 8476
 8477	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 8478	case IP_VERSION(10, 1, 10):
 8479	case IP_VERSION(10, 1, 1):
 8480	case IP_VERSION(10, 1, 2):
 8481	case IP_VERSION(10, 3, 0):
 8482	case IP_VERSION(10, 3, 2):
 8483	case IP_VERSION(10, 3, 1):
 8484	case IP_VERSION(10, 3, 4):
 8485	case IP_VERSION(10, 3, 5):
 8486	case IP_VERSION(10, 3, 6):
 8487	case IP_VERSION(10, 3, 3):
 8488	case IP_VERSION(10, 3, 7):
 8489		gfx_v10_0_update_gfx_clock_gating(adev,
 8490						 state == AMD_CG_STATE_GATE);
 8491		break;
 8492	default:
 8493		break;
 8494	}
 8495	return 0;
 8496}
 8497
 8498static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
 8499{
 8500	struct amdgpu_device *adev = ip_block->adev;
 8501	int data;
 8502
 8503	/* AMD_CG_SUPPORT_GFX_FGCG */
 8504	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
 8505	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
 8506		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
 8507
 8508	/* AMD_CG_SUPPORT_GFX_MGCG */
 8509	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
 8510	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
 8511		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
 8512
 8513	/* AMD_CG_SUPPORT_GFX_CGCG */
 8514	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
 8515	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
 8516		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
 8517
 8518	/* AMD_CG_SUPPORT_GFX_CGLS */
 8519	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
 8520		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
 8521
 8522	/* AMD_CG_SUPPORT_GFX_RLC_LS */
 8523	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
 8524	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
 8525		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
 8526
 8527	/* AMD_CG_SUPPORT_GFX_CP_LS */
 8528	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
 8529	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
 8530		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
 8531
 8532	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
 8533	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
 8534	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
 8535		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
 8536
 8537	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
 8538	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
 8539		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
 8540}
 8541
 8542static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
 8543{
 8544	/* gfx10 is 32bit rptr*/
 8545	return *(uint32_t *)ring->rptr_cpu_addr;
 8546}
 8547
 8548static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 8549{
 8550	struct amdgpu_device *adev = ring->adev;
 8551	u64 wptr;
 8552
 8553	/* XXX check if swapping is necessary on BE */
 8554	if (ring->use_doorbell) {
 8555		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
 8556	} else {
 8557		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
 8558		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
 8559	}
 8560
 8561	return wptr;
 8562}
 8563
 8564static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 8565{
 8566	struct amdgpu_device *adev = ring->adev;
 8567
 8568	if (ring->use_doorbell) {
 8569		/* XXX check if swapping is necessary on BE */
 8570		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 8571			     ring->wptr);
 8572		WDOORBELL64(ring->doorbell_index, ring->wptr);
 8573	} else {
 8574		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
 8575			     lower_32_bits(ring->wptr));
 8576		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
 8577			     upper_32_bits(ring->wptr));
 8578	}
 8579}
 8580
 8581static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 8582{
 8583	/* gfx10 hardware is 32bit rptr */
 8584	return *(uint32_t *)ring->rptr_cpu_addr;
 8585}
 8586
 8587static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 8588{
 8589	u64 wptr;
 8590
 8591	/* XXX check if swapping is necessary on BE */
 8592	if (ring->use_doorbell)
 8593		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
 8594	else
 8595		BUG();
 8596	return wptr;
 8597}
 8598
 8599static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 8600{
 8601	struct amdgpu_device *adev = ring->adev;
 8602
 8603	if (ring->use_doorbell) {
 8604		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 8605			     ring->wptr);
 8606		WDOORBELL64(ring->doorbell_index, ring->wptr);
 8607	} else {
 8608		BUG(); /* only DOORBELL method supported on gfx10 now */
 8609	}
 8610}
 8611
 8612static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 8613{
 8614	struct amdgpu_device *adev = ring->adev;
 8615	u32 ref_and_mask, reg_mem_engine;
 8616	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 8617
 8618	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
 8619		switch (ring->me) {
 8620		case 1:
 8621			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
 8622			break;
 8623		case 2:
 8624			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
 8625			break;
 8626		default:
 8627			return;
 8628		}
 8629		reg_mem_engine = 0;
 8630	} else {
 8631		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
 8632		reg_mem_engine = 1; /* pfp */
 8633	}
 8634
 8635	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
 8636			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 8637			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 8638			       ref_and_mask, ref_and_mask, 0x20);
 8639}
 8640
 8641static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 8642				       struct amdgpu_job *job,
 8643				       struct amdgpu_ib *ib,
 8644				       uint32_t flags)
 8645{
 8646	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
 8647	u32 header, control = 0;
 8648
 8649	if (ib->flags & AMDGPU_IB_FLAG_CE)
 8650		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
 8651	else
 8652		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 8653
 8654	control |= ib->length_dw | (vmid << 24);
 8655
 8656	if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
 8657		control |= INDIRECT_BUFFER_PRE_ENB(1);
 8658
 8659		if (flags & AMDGPU_IB_PREEMPTED)
 8660			control |= INDIRECT_BUFFER_PRE_RESUME(1);
 8661
 8662		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
 8663			gfx_v10_0_ring_emit_de_meta(ring,
 8664				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
 8665	}
 8666
 8667	amdgpu_ring_write(ring, header);
 8668	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 8669	amdgpu_ring_write(ring,
 8670#ifdef __BIG_ENDIAN
 8671		(2 << 0) |
 8672#endif
 8673		lower_32_bits(ib->gpu_addr));
 8674	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 8675	amdgpu_ring_write(ring, control);
 8676}
 8677
 8678static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 8679					   struct amdgpu_job *job,
 8680					   struct amdgpu_ib *ib,
 8681					   uint32_t flags)
 8682{
 8683	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
 8684	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 8685
 8686	/* Currently, there is a high possibility to get wave ID mismatch
 8687	 * between ME and GDS, leading to a hw deadlock, because ME generates
 8688	 * different wave IDs than the GDS expects. This situation happens
 8689	 * randomly when at least 5 compute pipes use GDS ordered append.
 8690	 * The wave IDs generated by ME are also wrong after suspend/resume.
 8691	 * Those are probably bugs somewhere else in the kernel driver.
 8692	 *
 8693	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
 8694	 * GDS to 0 for this ring (me/pipe).
 8695	 */
 8696	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
 8697		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 8698		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
 8699		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
 8700	}
 8701
 8702	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 8703	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 8704	amdgpu_ring_write(ring,
 8705#ifdef __BIG_ENDIAN
 8706				(2 << 0) |
 8707#endif
 8708				lower_32_bits(ib->gpu_addr));
 8709	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 8710	amdgpu_ring_write(ring, control);
 8711}
 8712
 8713static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 8714				     u64 seq, unsigned int flags)
 8715{
 8716	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 8717	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
 8718
 8719	/* RELEASE_MEM - flush caches, send int */
 8720	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
 8721	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
 8722				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
 8723				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
 8724				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
 8725				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
 8726				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
 8727				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
 8728	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
 8729				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
 8730
 8731	/*
 8732	 * the address should be Qword aligned if 64bit write, Dword
 8733	 * aligned if only send 32bit data low (discard data high)
 8734	 */
 8735	if (write64bit)
 8736		BUG_ON(addr & 0x7);
 8737	else
 8738		BUG_ON(addr & 0x3);
 8739	amdgpu_ring_write(ring, lower_32_bits(addr));
 8740	amdgpu_ring_write(ring, upper_32_bits(addr));
 8741	amdgpu_ring_write(ring, lower_32_bits(seq));
 8742	amdgpu_ring_write(ring, upper_32_bits(seq));
 8743	amdgpu_ring_write(ring, 0);
 8744}
 8745
 8746static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 8747{
 8748	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 8749	uint32_t seq = ring->fence_drv.sync_seq;
 8750	uint64_t addr = ring->fence_drv.gpu_addr;
 8751
 8752	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
 8753			       upper_32_bits(addr), seq, 0xffffffff, 4);
 8754}
 8755
 8756static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 8757				   uint16_t pasid, uint32_t flush_type,
 8758				   bool all_hub, uint8_t dst_sel)
 8759{
 8760	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 8761	amdgpu_ring_write(ring,
 8762			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
 8763			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 8764			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 8765			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 8766}
 8767
 8768static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 8769					 unsigned int vmid, uint64_t pd_addr)
 8770{
 8771	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 8772
 8773	/* compute doesn't have PFP */
 8774	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
 8775		/* sync PFP to ME, otherwise we might get invalid PFP reads */
 8776		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
 8777		amdgpu_ring_write(ring, 0x0);
 8778	}
 8779}
 8780
 8781static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 8782					  u64 seq, unsigned int flags)
 8783{
 8784	struct amdgpu_device *adev = ring->adev;
 8785
 8786	/* we only allocate 32bit for each seq wb address */
 8787	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 8788
 8789	/* write fence seq to the "addr" */
 8790	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 8791	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
 8792				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
 8793	amdgpu_ring_write(ring, lower_32_bits(addr));
 8794	amdgpu_ring_write(ring, upper_32_bits(addr));
 8795	amdgpu_ring_write(ring, lower_32_bits(seq));
 8796
 8797	if (flags & AMDGPU_FENCE_FLAG_INT) {
 8798		/* set register to trigger INT */
 8799		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 8800		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
 8801					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
 8802		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
 8803		amdgpu_ring_write(ring, 0);
 8804		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
 8805	}
 8806}
 8807
 8808static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
 8809{
 8810	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
 8811	amdgpu_ring_write(ring, 0);
 8812}
 8813
 8814static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
 8815					 uint32_t flags)
 8816{
 8817	uint32_t dw2 = 0;
 8818
 8819	if (ring->adev->gfx.mcbp)
 8820		gfx_v10_0_ring_emit_ce_meta(ring,
 8821				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
 8822
 8823	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 8824	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
 8825		/* set load_global_config & load_global_uconfig */
 8826		dw2 |= 0x8001;
 8827		/* set load_cs_sh_regs */
 8828		dw2 |= 0x01000000;
 8829		/* set load_per_context_state & load_gfx_sh_regs for GFX */
 8830		dw2 |= 0x10002;
 8831
 8832		/* set load_ce_ram if preamble presented */
 8833		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
 8834			dw2 |= 0x10000000;
 8835	} else {
 8836		/* still load_ce_ram if this is the first time preamble presented
 8837		 * although there is no context switch happens.
 8838		 */
 8839		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
 8840			dw2 |= 0x10000000;
 8841	}
 8842
 8843	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 8844	amdgpu_ring_write(ring, dw2);
 8845	amdgpu_ring_write(ring, 0);
 8846}
 8847
 8848static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
 8849						       uint64_t addr)
 8850{
 8851	unsigned int ret;
 8852
 8853	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
 8854	amdgpu_ring_write(ring, lower_32_bits(addr));
 8855	amdgpu_ring_write(ring, upper_32_bits(addr));
 8856	/* discard following DWs if *cond_exec_gpu_addr==0 */
 8857	amdgpu_ring_write(ring, 0);
 8858	ret = ring->wptr & ring->buf_mask;
 8859	/* patch dummy value later */
 8860	amdgpu_ring_write(ring, 0);
 8861
 8862	return ret;
 8863}
 8864
 8865static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
 8866{
 8867	int i, r = 0;
 8868	struct amdgpu_device *adev = ring->adev;
 8869	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 8870	struct amdgpu_ring *kiq_ring = &kiq->ring;
 8871	unsigned long flags;
 8872
 8873	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 8874		return -EINVAL;
 8875
 8876	spin_lock_irqsave(&kiq->ring_lock, flags);
 8877
 8878	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
 8879		spin_unlock_irqrestore(&kiq->ring_lock, flags);
 8880		return -ENOMEM;
 8881	}
 8882
 8883	/* assert preemption condition */
 8884	amdgpu_ring_set_preempt_cond_exec(ring, false);
 8885
 8886	/* assert IB preemption, emit the trailing fence */
 8887	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
 8888				   ring->trail_fence_gpu_addr,
 8889				   ++ring->trail_seq);
 8890	amdgpu_ring_commit(kiq_ring);
 8891
 8892	spin_unlock_irqrestore(&kiq->ring_lock, flags);
 8893
 8894	/* poll the trailing fence */
 8895	for (i = 0; i < adev->usec_timeout; i++) {
 8896		if (ring->trail_seq ==
 8897		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
 8898			break;
 8899		udelay(1);
 8900	}
 8901
 8902	if (i >= adev->usec_timeout) {
 8903		r = -EINVAL;
 8904		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
 8905	}
 8906
 8907	/* deassert preemption condition */
 8908	amdgpu_ring_set_preempt_cond_exec(ring, true);
 8909	return r;
 8910}
 8911
 8912static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
 8913{
 8914	struct amdgpu_device *adev = ring->adev;
 8915	struct v10_ce_ib_state ce_payload = {0};
 8916	uint64_t offset, ce_payload_gpu_addr;
 8917	void *ce_payload_cpu_addr;
 8918	int cnt;
 8919
 8920	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
 8921
 8922	offset = offsetof(struct v10_gfx_meta_data, ce_payload);
 8923	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
 8924	ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
 8925
 8926	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
 8927	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
 8928				 WRITE_DATA_DST_SEL(8) |
 8929				 WR_CONFIRM) |
 8930				 WRITE_DATA_CACHE_POLICY(0));
 8931	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
 8932	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
 8933
 8934	if (resume)
 8935		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
 8936					   sizeof(ce_payload) >> 2);
 8937	else
 8938		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
 8939					   sizeof(ce_payload) >> 2);
 8940}
 8941
 8942static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
 8943{
 8944	struct amdgpu_device *adev = ring->adev;
 8945	struct v10_de_ib_state de_payload = {0};
 8946	uint64_t offset, gds_addr, de_payload_gpu_addr;
 8947	void *de_payload_cpu_addr;
 8948	int cnt;
 8949
 8950	offset = offsetof(struct v10_gfx_meta_data, de_payload);
 8951	de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
 8952	de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
 8953
 8954	gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
 8955			 AMDGPU_CSA_SIZE - adev->gds.gds_size,
 8956			 PAGE_SIZE);
 8957
 8958	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
 8959	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
 8960
 8961	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
 8962	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
 8963	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
 8964				 WRITE_DATA_DST_SEL(8) |
 8965				 WR_CONFIRM) |
 8966				 WRITE_DATA_CACHE_POLICY(0));
 8967	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
 8968	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
 8969
 8970	if (resume)
 8971		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
 8972					   sizeof(de_payload) >> 2);
 8973	else
 8974		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
 8975					   sizeof(de_payload) >> 2);
 8976}
 8977
 8978static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
 8979				    bool secure)
 8980{
 8981	uint32_t v = secure ? FRAME_TMZ : 0;
 8982
 8983	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
 8984	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
 8985}
 8986
 8987static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
 8988				     uint32_t reg_val_offs)
 8989{
 8990	struct amdgpu_device *adev = ring->adev;
 8991
 8992	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
 8993	amdgpu_ring_write(ring, 0 |	/* src: register*/
 8994				(5 << 8) |	/* dst: memory */
 8995				(1 << 20));	/* write confirm */
 8996	amdgpu_ring_write(ring, reg);
 8997	amdgpu_ring_write(ring, 0);
 8998	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
 8999				reg_val_offs * 4));
 9000	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
 9001				reg_val_offs * 4));
 9002}
 9003
 9004static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 9005				   uint32_t val)
 9006{
 9007	uint32_t cmd = 0;
 9008
 9009	switch (ring->funcs->type) {
 9010	case AMDGPU_RING_TYPE_GFX:
 9011		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
 9012		break;
 9013	case AMDGPU_RING_TYPE_KIQ:
 9014		cmd = (1 << 16); /* no inc addr */
 9015		break;
 9016	default:
 9017		cmd = WR_CONFIRM;
 9018		break;
 9019	}
 9020	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 9021	amdgpu_ring_write(ring, cmd);
 9022	amdgpu_ring_write(ring, reg);
 9023	amdgpu_ring_write(ring, 0);
 9024	amdgpu_ring_write(ring, val);
 9025}
 9026
 9027static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
 9028					uint32_t val, uint32_t mask)
 9029{
 9030	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
 9031}
 9032
 9033static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
 9034						   uint32_t reg0, uint32_t reg1,
 9035						   uint32_t ref, uint32_t mask)
 9036{
 9037	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 9038	struct amdgpu_device *adev = ring->adev;
 9039	bool fw_version_ok = false;
 9040
 9041	fw_version_ok = adev->gfx.cp_fw_write_wait;
 9042
 9043	if (fw_version_ok)
 9044		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
 9045				       ref, mask, 0x20);
 9046	else
 9047		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
 9048							   ref, mask);
 9049}
 9050
 9051static void
 9052gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
 9053				      uint32_t me, uint32_t pipe,
 9054				      enum amdgpu_interrupt_state state)
 9055{
 9056	uint32_t cp_int_cntl, cp_int_cntl_reg;
 9057
 9058	if (!me) {
 9059		switch (pipe) {
 9060		case 0:
 9061			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
 9062			break;
 9063		case 1:
 9064			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
 9065			break;
 9066		default:
 9067			DRM_DEBUG("invalid pipe %d\n", pipe);
 9068			return;
 9069		}
 9070	} else {
 9071		DRM_DEBUG("invalid me %d\n", me);
 9072		return;
 9073	}
 9074
 9075	switch (state) {
 9076	case AMDGPU_IRQ_STATE_DISABLE:
 9077		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9078		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 9079					    TIME_STAMP_INT_ENABLE, 0);
 9080		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9081		break;
 9082	case AMDGPU_IRQ_STATE_ENABLE:
 9083		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9084		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 9085					    TIME_STAMP_INT_ENABLE, 1);
 9086		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9087		break;
 9088	default:
 9089		break;
 9090	}
 9091}
 9092
 9093static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
 9094						     int me, int pipe,
 9095						     enum amdgpu_interrupt_state state)
 9096{
 9097	u32 mec_int_cntl, mec_int_cntl_reg;
 9098
 9099	/*
 9100	 * amdgpu controls only the first MEC. That's why this function only
 9101	 * handles the setting of interrupts for this specific MEC. All other
 9102	 * pipes' interrupts are set by amdkfd.
 9103	 */
 9104
 9105	if (me == 1) {
 9106		switch (pipe) {
 9107		case 0:
 9108			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
 9109			break;
 9110		case 1:
 9111			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
 9112			break;
 9113		case 2:
 9114			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
 9115			break;
 9116		case 3:
 9117			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
 9118			break;
 9119		default:
 9120			DRM_DEBUG("invalid pipe %d\n", pipe);
 9121			return;
 9122		}
 9123	} else {
 9124		DRM_DEBUG("invalid me %d\n", me);
 9125		return;
 9126	}
 9127
 9128	switch (state) {
 9129	case AMDGPU_IRQ_STATE_DISABLE:
 9130		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
 9131		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 9132					     TIME_STAMP_INT_ENABLE, 0);
 9133		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
 9134		break;
 9135	case AMDGPU_IRQ_STATE_ENABLE:
 9136		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
 9137		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 9138					     TIME_STAMP_INT_ENABLE, 1);
 9139		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
 9140		break;
 9141	default:
 9142		break;
 9143	}
 9144}
 9145
 9146static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 9147					    struct amdgpu_irq_src *src,
 9148					    unsigned int type,
 9149					    enum amdgpu_interrupt_state state)
 9150{
 9151	switch (type) {
 9152	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
 9153		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
 9154		break;
 9155	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
 9156		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
 9157		break;
 9158	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
 9159		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
 9160		break;
 9161	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
 9162		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
 9163		break;
 9164	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
 9165		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
 9166		break;
 9167	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
 9168		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
 9169		break;
 9170	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
 9171		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
 9172		break;
 9173	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
 9174		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
 9175		break;
 9176	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
 9177		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
 9178		break;
 9179	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
 9180		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
 9181		break;
 9182	default:
 9183		break;
 9184	}
 9185	return 0;
 9186}
 9187
 9188static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
 9189			     struct amdgpu_irq_src *source,
 9190			     struct amdgpu_iv_entry *entry)
 9191{
 9192	int i;
 9193	u8 me_id, pipe_id, queue_id;
 9194	struct amdgpu_ring *ring;
 9195
 9196	DRM_DEBUG("IH: CP EOP\n");
 9197
 9198	me_id = (entry->ring_id & 0x0c) >> 2;
 9199	pipe_id = (entry->ring_id & 0x03) >> 0;
 9200	queue_id = (entry->ring_id & 0x70) >> 4;
 9201
 9202	switch (me_id) {
 9203	case 0:
 9204		if (pipe_id == 0)
 9205			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
 9206		else
 9207			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
 9208		break;
 9209	case 1:
 9210	case 2:
 9211		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 9212			ring = &adev->gfx.compute_ring[i];
 9213			/* Per-queue interrupt is supported for MEC starting from VI.
 9214			 * The interrupt can only be enabled/disabled per pipe instead
 9215			 * of per queue.
 9216			 */
 9217			if ((ring->me == me_id) &&
 9218			    (ring->pipe == pipe_id) &&
 9219			    (ring->queue == queue_id))
 9220				amdgpu_fence_process(ring);
 9221		}
 9222		break;
 9223	}
 9224
 9225	return 0;
 9226}
 9227
 9228static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 9229					      struct amdgpu_irq_src *source,
 9230					      unsigned int type,
 9231					      enum amdgpu_interrupt_state state)
 9232{
 9233	u32 cp_int_cntl_reg, cp_int_cntl;
 9234	int i, j;
 9235
 9236	switch (state) {
 9237	case AMDGPU_IRQ_STATE_DISABLE:
 9238	case AMDGPU_IRQ_STATE_ENABLE:
 9239		for (i = 0; i < adev->gfx.me.num_me; i++) {
 9240			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 9241				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
 9242
 9243				if (cp_int_cntl_reg) {
 9244					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9245					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 9246								    PRIV_REG_INT_ENABLE,
 9247								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 9248					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9249				}
 9250			}
 9251		}
 9252		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
 9253			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
 9254				/* MECs start at 1 */
 9255				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
 9256
 9257				if (cp_int_cntl_reg) {
 9258					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9259					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 9260								    PRIV_REG_INT_ENABLE,
 9261								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 9262					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9263				}
 9264			}
 9265		}
 9266		break;
 9267	default:
 9268		break;
 9269	}
 9270
 9271	return 0;
 9272}
 9273
 9274static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 9275					    struct amdgpu_irq_src *source,
 9276					    unsigned type,
 9277					    enum amdgpu_interrupt_state state)
 9278{
 9279	u32 cp_int_cntl_reg, cp_int_cntl;
 9280	int i, j;
 9281
 9282	switch (state) {
 9283	case AMDGPU_IRQ_STATE_DISABLE:
 9284	case AMDGPU_IRQ_STATE_ENABLE:
 9285		for (i = 0; i < adev->gfx.me.num_me; i++) {
 9286			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 9287				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
 9288
 9289				if (cp_int_cntl_reg) {
 9290					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9291					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 9292								    OPCODE_ERROR_INT_ENABLE,
 9293								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 9294					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9295				}
 9296			}
 9297		}
 9298		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
 9299			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
 9300				/* MECs start at 1 */
 9301				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
 9302
 9303				if (cp_int_cntl_reg) {
 9304					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9305					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 9306								    OPCODE_ERROR_INT_ENABLE,
 9307								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 9308					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9309				}
 9310			}
 9311		}
 9312		break;
 9313	default:
 9314		break;
 9315	}
 9316	return 0;
 9317}
 9318
 9319static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 9320					       struct amdgpu_irq_src *source,
 9321					       unsigned int type,
 9322					       enum amdgpu_interrupt_state state)
 9323{
 9324	u32 cp_int_cntl_reg, cp_int_cntl;
 9325	int i, j;
 9326
 9327	switch (state) {
 9328	case AMDGPU_IRQ_STATE_DISABLE:
 9329	case AMDGPU_IRQ_STATE_ENABLE:
 9330		for (i = 0; i < adev->gfx.me.num_me; i++) {
 9331			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 9332				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
 9333
 9334				if (cp_int_cntl_reg) {
 9335					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 9336					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 9337								    PRIV_INSTR_INT_ENABLE,
 9338								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 9339					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 9340				}
 9341			}
 9342		}
 9343		break;
 9344	default:
 9345		break;
 9346	}
 9347
 9348	return 0;
 9349}
 9350
 9351static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
 9352					struct amdgpu_iv_entry *entry)
 9353{
 9354	u8 me_id, pipe_id, queue_id;
 9355	struct amdgpu_ring *ring;
 9356	int i;
 9357
 9358	me_id = (entry->ring_id & 0x0c) >> 2;
 9359	pipe_id = (entry->ring_id & 0x03) >> 0;
 9360	queue_id = (entry->ring_id & 0x70) >> 4;
 9361
 9362	switch (me_id) {
 9363	case 0:
 9364		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 9365			ring = &adev->gfx.gfx_ring[i];
 9366			if (ring->me == me_id && ring->pipe == pipe_id &&
 9367			    ring->queue == queue_id)
 9368				drm_sched_fault(&ring->sched);
 9369		}
 9370		break;
 9371	case 1:
 9372	case 2:
 9373		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 9374			ring = &adev->gfx.compute_ring[i];
 9375			if (ring->me == me_id && ring->pipe == pipe_id &&
 9376			    ring->queue == queue_id)
 9377				drm_sched_fault(&ring->sched);
 9378		}
 9379		break;
 9380	default:
 9381		BUG();
 9382	}
 9383}
 9384
 9385static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
 9386				  struct amdgpu_irq_src *source,
 9387				  struct amdgpu_iv_entry *entry)
 9388{
 9389	DRM_ERROR("Illegal register access in command stream\n");
 9390	gfx_v10_0_handle_priv_fault(adev, entry);
 9391	return 0;
 9392}
 9393
 9394static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
 9395				struct amdgpu_irq_src *source,
 9396				struct amdgpu_iv_entry *entry)
 9397{
 9398	DRM_ERROR("Illegal opcode in command stream \n");
 9399	gfx_v10_0_handle_priv_fault(adev, entry);
 9400	return 0;
 9401}
 9402
 9403static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
 9404				   struct amdgpu_irq_src *source,
 9405				   struct amdgpu_iv_entry *entry)
 9406{
 9407	DRM_ERROR("Illegal instruction in command stream\n");
 9408	gfx_v10_0_handle_priv_fault(adev, entry);
 9409	return 0;
 9410}
 9411
 9412static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
 9413					     struct amdgpu_irq_src *src,
 9414					     unsigned int type,
 9415					     enum amdgpu_interrupt_state state)
 9416{
 9417	uint32_t tmp, target;
 9418	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
 9419
 9420	if (ring->me == 1)
 9421		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
 9422	else
 9423		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
 9424	target += ring->pipe;
 9425
 9426	switch (type) {
 9427	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
 9428		if (state == AMDGPU_IRQ_STATE_DISABLE) {
 9429			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
 9430			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
 9431					    GENERIC2_INT_ENABLE, 0);
 9432			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 9433
 9434			tmp = RREG32_SOC15_IP(GC, target);
 9435			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
 9436					    GENERIC2_INT_ENABLE, 0);
 9437			WREG32_SOC15_IP(GC, target, tmp);
 9438		} else {
 9439			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
 9440			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
 9441					    GENERIC2_INT_ENABLE, 1);
 9442			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 9443
 9444			tmp = RREG32_SOC15_IP(GC, target);
 9445			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
 9446					    GENERIC2_INT_ENABLE, 1);
 9447			WREG32_SOC15_IP(GC, target, tmp);
 9448		}
 9449		break;
 9450	default:
 9451		BUG(); /* kiq only support GENERIC2_INT now */
 9452		break;
 9453	}
 9454	return 0;
 9455}
 9456
 9457static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
 9458			     struct amdgpu_irq_src *source,
 9459			     struct amdgpu_iv_entry *entry)
 9460{
 9461	u8 me_id, pipe_id, queue_id;
 9462	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
 9463
 9464	me_id = (entry->ring_id & 0x0c) >> 2;
 9465	pipe_id = (entry->ring_id & 0x03) >> 0;
 9466	queue_id = (entry->ring_id & 0x70) >> 4;
 9467	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
 9468		   me_id, pipe_id, queue_id);
 9469
 9470	amdgpu_fence_process(ring);
 9471	return 0;
 9472}
 9473
 9474static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
 9475{
 9476	const unsigned int gcr_cntl =
 9477			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
 9478			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
 9479			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
 9480			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
 9481			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
 9482			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
 9483			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
 9484			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
 9485
 9486	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
 9487	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
 9488	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
 9489	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
 9490	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
 9491	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
 9492	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
 9493	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
 9494	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 9495}
 9496
 9497static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
 9498{
 9499	/* Header itself is a NOP packet */
 9500	if (num_nop == 1) {
 9501		amdgpu_ring_write(ring, ring->funcs->nop);
 9502		return;
 9503	}
 9504
 9505	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
 9506	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
 9507
 9508	/* Header is at index 0, followed by num_nops - 1 NOP packet's */
 9509	amdgpu_ring_insert_nop(ring, num_nop - 1);
 9510}
 9511
 9512static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
 9513			       unsigned int vmid,
 9514			       struct amdgpu_fence *timedout_fence)
 9515{
 9516	struct amdgpu_device *adev = ring->adev;
 9517	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 9518	struct amdgpu_ring *kiq_ring = &kiq->ring;
 9519	unsigned long flags;
 9520	u32 tmp;
 9521	u64 addr;
 9522	int r;
 9523
 9524	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 9525		return -EINVAL;
 9526
 9527	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
 9528
 9529	spin_lock_irqsave(&kiq->ring_lock, flags);
 9530
 9531	if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {
 9532		spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9533		return -ENOMEM;
 9534	}
 9535
 9536	addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
 9537		offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
 9538	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
 9539	if (ring->pipe == 0)
 9540		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
 9541	else
 9542		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
 9543
 9544	gfx_v10_0_ring_emit_wreg(kiq_ring,
 9545				 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
 9546	gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
 9547			       lower_32_bits(addr), upper_32_bits(addr),
 9548			       0, 1, 0x20);
 9549	gfx_v10_0_ring_emit_reg_wait(kiq_ring,
 9550				     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
 9551	amdgpu_ring_commit(kiq_ring);
 9552	r = amdgpu_ring_test_ring(kiq_ring);
 9553	spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9554	if (r)
 9555		return r;
 9556
 9557	r = gfx_v10_0_kgq_init_queue(ring, true);
 9558	if (r) {
 9559		DRM_ERROR("fail to init kgq\n");
 9560		return r;
 9561	}
 9562
 9563	spin_lock_irqsave(&kiq->ring_lock, flags);
 9564
 9565	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
 9566		spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9567		return -ENOMEM;
 9568	}
 9569	kiq->pmf->kiq_map_queues(kiq_ring, ring);
 9570	amdgpu_ring_commit(kiq_ring);
 9571	r = amdgpu_ring_test_ring(kiq_ring);
 9572	spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9573	if (r)
 9574		return r;
 9575
 9576	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 9577}
 9578
 9579static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
 9580			       unsigned int vmid,
 9581			       struct amdgpu_fence *timedout_fence)
 9582{
 9583	struct amdgpu_device *adev = ring->adev;
 9584	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 9585	struct amdgpu_ring *kiq_ring = &kiq->ring;
 9586	unsigned long flags;
 9587	int i, r;
 9588
 9589	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 9590		return -EINVAL;
 9591
 9592	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
 9593
 9594	spin_lock_irqsave(&kiq->ring_lock, flags);
 9595
 9596	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
 9597		spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9598		return -ENOMEM;
 9599	}
 9600
 9601	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
 9602				   0, 0);
 9603	amdgpu_ring_commit(kiq_ring);
 9604	r = amdgpu_ring_test_ring(kiq_ring);
 9605	spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9606	if (r)
 9607		return r;
 9608
 9609	/* make sure dequeue is complete*/
 9610	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 9611	mutex_lock(&adev->srbm_mutex);
 9612	nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 9613	for (i = 0; i < adev->usec_timeout; i++) {
 9614		if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
 9615			break;
 9616		udelay(1);
 9617	}
 9618	if (i >= adev->usec_timeout)
 9619		r = -ETIMEDOUT;
 9620	nv_grbm_select(adev, 0, 0, 0, 0);
 9621	mutex_unlock(&adev->srbm_mutex);
 9622	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 9623	if (r) {
 9624		dev_err(adev->dev, "fail to wait on hqd deactivate\n");
 9625		return r;
 9626	}
 9627
 9628	r = gfx_v10_0_kcq_init_queue(ring, true);
 9629	if (r) {
 9630		dev_err(adev->dev, "fail to init kcq\n");
 9631		return r;
 9632	}
 9633
 9634	spin_lock_irqsave(&kiq->ring_lock, flags);
 9635	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
 9636		spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9637		return -ENOMEM;
 9638	}
 9639	kiq->pmf->kiq_map_queues(kiq_ring, ring);
 9640	amdgpu_ring_commit(kiq_ring);
 9641	r = amdgpu_ring_test_ring(kiq_ring);
 9642	spin_unlock_irqrestore(&kiq->ring_lock, flags);
 9643	if (r)
 9644		return r;
 9645
 9646	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 9647}
 9648
 9649static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
 9650{
 9651	struct amdgpu_device *adev = ip_block->adev;
 9652	uint32_t i, j, k, reg, index = 0;
 9653	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 9654
 9655	if (!adev->gfx.ip_dump_core)
 9656		return;
 9657
 9658	for (i = 0; i < reg_count; i++)
 9659		drm_printf(p, "%-50s \t 0x%08x\n",
 9660			   gc_reg_list_10_1[i].reg_name,
 9661			   adev->gfx.ip_dump_core[i]);
 9662
 9663	/* print compute queue registers for all instances */
 9664	if (!adev->gfx.ip_dump_compute_queues)
 9665		return;
 9666
 9667	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
 9668	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
 9669		   adev->gfx.mec.num_mec,
 9670		   adev->gfx.mec.num_pipe_per_mec,
 9671		   adev->gfx.mec.num_queue_per_pipe);
 9672
 9673	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
 9674		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
 9675			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
 9676				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
 9677				for (reg = 0; reg < reg_count; reg++) {
 9678					if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
 9679						drm_printf(p, "%-50s \t 0x%08x\n",
 9680							   "mmCP_MEC_ME2_HEADER_DUMP",
 9681							   adev->gfx.ip_dump_compute_queues[index + reg]);
 9682					else
 9683						drm_printf(p, "%-50s \t 0x%08x\n",
 9684							   gc_cp_reg_list_10[reg].reg_name,
 9685							   adev->gfx.ip_dump_compute_queues[index + reg]);
 9686				}
 9687				index += reg_count;
 9688			}
 9689		}
 9690	}
 9691
 9692	/* print gfx queue registers for all instances */
 9693	if (!adev->gfx.ip_dump_gfx_queues)
 9694		return;
 9695
 9696	index = 0;
 9697	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
 9698	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
 9699		   adev->gfx.me.num_me,
 9700		   adev->gfx.me.num_pipe_per_me,
 9701		   adev->gfx.me.num_queue_per_pipe);
 9702
 9703	for (i = 0; i < adev->gfx.me.num_me; i++) {
 9704		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 9705			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
 9706				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
 9707				for (reg = 0; reg < reg_count; reg++) {
 9708					drm_printf(p, "%-50s \t 0x%08x\n",
 9709						   gc_gfx_queue_reg_list_10[reg].reg_name,
 9710						   adev->gfx.ip_dump_gfx_queues[index + reg]);
 9711				}
 9712				index += reg_count;
 9713			}
 9714		}
 9715	}
 9716}
 9717
 9718static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
 9719{
 9720	struct amdgpu_device *adev = ip_block->adev;
 9721	uint32_t i, j, k, reg, index = 0;
 9722	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 9723
 9724	if (!adev->gfx.ip_dump_core)
 9725		return;
 9726
 9727	amdgpu_gfx_off_ctrl(adev, false);
 9728	for (i = 0; i < reg_count; i++)
 9729		adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
 9730	amdgpu_gfx_off_ctrl(adev, true);
 9731
 9732	/* dump compute queue registers for all instances */
 9733	if (!adev->gfx.ip_dump_compute_queues)
 9734		return;
 9735
 9736	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
 9737	amdgpu_gfx_off_ctrl(adev, false);
 9738	mutex_lock(&adev->srbm_mutex);
 9739	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
 9740		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
 9741			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
 9742				/* ME0 is for GFX so start from 1 for CP */
 9743				nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
 9744
 9745				for (reg = 0; reg < reg_count; reg++) {
 9746					if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
 9747						adev->gfx.ip_dump_compute_queues[index + reg] =
 9748							RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
 9749					else
 9750						adev->gfx.ip_dump_compute_queues[index + reg] =
 9751							RREG32(SOC15_REG_ENTRY_OFFSET(
 9752								       gc_cp_reg_list_10[reg]));
 9753				}
 9754				index += reg_count;
 9755			}
 9756		}
 9757	}
 9758	nv_grbm_select(adev, 0, 0, 0, 0);
 9759	mutex_unlock(&adev->srbm_mutex);
 9760	amdgpu_gfx_off_ctrl(adev, true);
 9761
 9762	/* dump gfx queue registers for all instances */
 9763	if (!adev->gfx.ip_dump_gfx_queues)
 9764		return;
 9765
 9766	index = 0;
 9767	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
 9768	amdgpu_gfx_off_ctrl(adev, false);
 9769	mutex_lock(&adev->srbm_mutex);
 9770	for (i = 0; i < adev->gfx.me.num_me; i++) {
 9771		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
 9772			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
 9773				nv_grbm_select(adev, i, j, k, 0);
 9774
 9775				for (reg = 0; reg < reg_count; reg++) {
 9776					adev->gfx.ip_dump_gfx_queues[index + reg] =
 9777						RREG32(SOC15_REG_ENTRY_OFFSET(
 9778							gc_gfx_queue_reg_list_10[reg]));
 9779				}
 9780				index += reg_count;
 9781			}
 9782		}
 9783	}
 9784	nv_grbm_select(adev, 0, 0, 0, 0);
 9785	mutex_unlock(&adev->srbm_mutex);
 9786	amdgpu_gfx_off_ctrl(adev, true);
 9787}
 9788
 9789static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
 9790{
 9791	/* Emit the cleaner shader */
 9792	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
 9793	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
 9794}
 9795
 9796static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
 9797{
 9798	amdgpu_gfx_profile_ring_begin_use(ring);
 9799
 9800	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
 9801}
 9802
 9803static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
 9804{
 9805	amdgpu_gfx_profile_ring_end_use(ring);
 9806
 9807	amdgpu_gfx_enforce_isolation_ring_end_use(ring);
 9808}
 9809
 9810static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
 9811	.name = "gfx_v10_0",
 9812	.early_init = gfx_v10_0_early_init,
 9813	.late_init = gfx_v10_0_late_init,
 9814	.sw_init = gfx_v10_0_sw_init,
 9815	.sw_fini = gfx_v10_0_sw_fini,
 9816	.hw_init = gfx_v10_0_hw_init,
 9817	.hw_fini = gfx_v10_0_hw_fini,
 9818	.suspend = gfx_v10_0_suspend,
 9819	.resume = gfx_v10_0_resume,
 9820	.is_idle = gfx_v10_0_is_idle,
 9821	.wait_for_idle = gfx_v10_0_wait_for_idle,
 9822	.soft_reset = gfx_v10_0_soft_reset,
 9823	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
 9824	.set_powergating_state = gfx_v10_0_set_powergating_state,
 9825	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
 9826	.dump_ip_state = gfx_v10_ip_dump,
 9827	.print_ip_state = gfx_v10_ip_print,
 9828};
 9829
 9830static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
 9831	.type = AMDGPU_RING_TYPE_GFX,
 9832	.align_mask = 0xff,
 9833	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 9834	.support_64bit_ptrs = true,
 9835	.secure_submission_supported = true,
 9836	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
 9837	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
 9838	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
 9839	.emit_frame_size = /* totally 242 maximum if 16 IBs */
 9840		5 + /* COND_EXEC */
 9841		7 + /* PIPELINE_SYNC */
 9842		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
 9843		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
 9844		4 + /* VM_FLUSH */
 9845		8 + /* FENCE for VM_FLUSH */
 9846		20 + /* GDS switch */
 9847		4 + /* double SWITCH_BUFFER,
 9848		     * the first COND_EXEC jump to the place
 9849		     * just prior to this double SWITCH_BUFFER
 9850		     */
 9851		5 + /* COND_EXEC */
 9852		7 + /* HDP_flush */
 9853		4 + /* VGT_flush */
 9854		14 + /*	CE_META */
 9855		31 + /*	DE_META */
 9856		3 + /* CNTX_CTRL */
 9857		5 + /* HDP_INVL */
 9858		8 + 8 + /* FENCE x2 */
 9859		2 + /* SWITCH_BUFFER */
 9860		8 + /* gfx_v10_0_emit_mem_sync */
 9861		2, /* gfx_v10_0_ring_emit_cleaner_shader */
 9862	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
 9863	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
 9864	.emit_fence = gfx_v10_0_ring_emit_fence,
 9865	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
 9866	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
 9867	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
 9868	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
 9869	.test_ring = gfx_v10_0_ring_test_ring,
 9870	.test_ib = gfx_v10_0_ring_test_ib,
 9871	.insert_nop = gfx_v10_ring_insert_nop,
 9872	.pad_ib = amdgpu_ring_generic_pad_ib,
 9873	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
 9874	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
 9875	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
 9876	.preempt_ib = gfx_v10_0_ring_preempt_ib,
 9877	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
 9878	.emit_wreg = gfx_v10_0_ring_emit_wreg,
 9879	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
 9880	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
 9881	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
 9882	.reset = gfx_v10_0_reset_kgq,
 9883	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
 9884	.begin_use = gfx_v10_0_ring_begin_use,
 9885	.end_use = gfx_v10_0_ring_end_use,
 9886};
 9887
 9888static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
 9889	.type = AMDGPU_RING_TYPE_COMPUTE,
 9890	.align_mask = 0xff,
 9891	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 9892	.support_64bit_ptrs = true,
 9893	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
 9894	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
 9895	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
 9896	.emit_frame_size =
 9897		20 + /* gfx_v10_0_ring_emit_gds_switch */
 9898		7 + /* gfx_v10_0_ring_emit_hdp_flush */
 9899		5 + /* hdp invalidate */
 9900		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
 9901		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
 9902		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
 9903		2 + /* gfx_v10_0_ring_emit_vm_flush */
 9904		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
 9905		8 + /* gfx_v10_0_emit_mem_sync */
 9906		2, /* gfx_v10_0_ring_emit_cleaner_shader */
 9907	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
 9908	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
 9909	.emit_fence = gfx_v10_0_ring_emit_fence,
 9910	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
 9911	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
 9912	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
 9913	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
 9914	.test_ring = gfx_v10_0_ring_test_ring,
 9915	.test_ib = gfx_v10_0_ring_test_ib,
 9916	.insert_nop = gfx_v10_ring_insert_nop,
 9917	.pad_ib = amdgpu_ring_generic_pad_ib,
 9918	.emit_wreg = gfx_v10_0_ring_emit_wreg,
 9919	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
 9920	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
 9921	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
 9922	.reset = gfx_v10_0_reset_kcq,
 9923	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
 9924	.begin_use = gfx_v10_0_ring_begin_use,
 9925	.end_use = gfx_v10_0_ring_end_use,
 9926};
 9927
 9928static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
 9929	.type = AMDGPU_RING_TYPE_KIQ,
 9930	.align_mask = 0xff,
 9931	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 9932	.support_64bit_ptrs = true,
 9933	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
 9934	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
 9935	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
 9936	.emit_frame_size =
 9937		20 + /* gfx_v10_0_ring_emit_gds_switch */
 9938		7 + /* gfx_v10_0_ring_emit_hdp_flush */
 9939		5 + /*hdp invalidate */
 9940		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
 9941		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
 9942		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
 9943		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
 9944	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
 9945	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
 9946	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
 9947	.test_ring = gfx_v10_0_ring_test_ring,
 9948	.test_ib = gfx_v10_0_ring_test_ib,
 9949	.insert_nop = amdgpu_ring_insert_nop,
 9950	.pad_ib = amdgpu_ring_generic_pad_ib,
 9951	.emit_rreg = gfx_v10_0_ring_emit_rreg,
 9952	.emit_wreg = gfx_v10_0_ring_emit_wreg,
 9953	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
 9954	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
 9955	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
 9956};
 9957
 9958static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
 9959{
 9960	int i;
 9961
 9962	adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
 9963
 9964	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 9965		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
 9966
 9967	for (i = 0; i < adev->gfx.num_compute_rings; i++)
 9968		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
 9969}
 9970
 9971static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
 9972	.set = gfx_v10_0_set_eop_interrupt_state,
 9973	.process = gfx_v10_0_eop_irq,
 9974};
 9975
 9976static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
 9977	.set = gfx_v10_0_set_priv_reg_fault_state,
 9978	.process = gfx_v10_0_priv_reg_irq,
 9979};
 9980
 9981static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
 9982	.set = gfx_v10_0_set_bad_op_fault_state,
 9983	.process = gfx_v10_0_bad_op_irq,
 9984};
 9985
 9986static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
 9987	.set = gfx_v10_0_set_priv_inst_fault_state,
 9988	.process = gfx_v10_0_priv_inst_irq,
 9989};
 9990
 9991static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
 9992	.set = gfx_v10_0_kiq_set_interrupt_state,
 9993	.process = gfx_v10_0_kiq_irq,
 9994};
 9995
 9996static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 9997{
 9998	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
 9999	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
10000
10001	adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
10002	adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
10003
10004	adev->gfx.priv_reg_irq.num_types = 1;
10005	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
10006
10007	adev->gfx.bad_op_irq.num_types = 1;
10008	adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
10009
10010	adev->gfx.priv_inst_irq.num_types = 1;
10011	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
10012}
10013
10014static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
10015{
10016	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
10017	case IP_VERSION(10, 1, 10):
10018	case IP_VERSION(10, 1, 1):
10019	case IP_VERSION(10, 1, 3):
10020	case IP_VERSION(10, 1, 4):
10021	case IP_VERSION(10, 3, 2):
10022	case IP_VERSION(10, 3, 1):
10023	case IP_VERSION(10, 3, 4):
10024	case IP_VERSION(10, 3, 5):
10025	case IP_VERSION(10, 3, 6):
10026	case IP_VERSION(10, 3, 3):
10027	case IP_VERSION(10, 3, 7):
10028		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
10029		break;
10030	case IP_VERSION(10, 1, 2):
10031	case IP_VERSION(10, 3, 0):
10032		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
10033		break;
10034	default:
10035		break;
10036	}
10037}
10038
10039static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
10040{
10041	unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
10042			    adev->gfx.config.max_sh_per_se *
10043			    adev->gfx.config.max_shader_engines;
10044
10045	adev->gds.gds_size = 0x10000;
10046	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
10047	adev->gds.gws_size = 64;
10048	adev->gds.oa_size = 16;
10049}
10050
10051static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
10052{
10053	/* set gfx eng mqd */
10054	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
10055		sizeof(struct v10_gfx_mqd);
10056	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
10057		gfx_v10_0_gfx_mqd_init;
10058	/* set compute eng mqd */
10059	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10060		sizeof(struct v10_compute_mqd);
10061	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10062		gfx_v10_0_compute_mqd_init;
10063}
10064
10065static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10066							  u32 bitmap)
10067{
10068	u32 data;
10069
10070	if (!bitmap)
10071		return;
10072
10073	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10074	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10075
10076	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10077}
10078
10079static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10080{
10081	u32 disabled_mask =
10082		~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10083	u32 efuse_setting = 0;
10084	u32 vbios_setting = 0;
10085
10086	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10087	efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10088	efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10089
10090	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10091	vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10092	vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10093
10094	disabled_mask |= efuse_setting | vbios_setting;
10095
10096	return (~disabled_mask);
10097}
10098
10099static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10100{
10101	u32 wgp_idx, wgp_active_bitmap;
10102	u32 cu_bitmap_per_wgp, cu_active_bitmap;
10103
10104	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10105	cu_active_bitmap = 0;
10106
10107	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10108		/* if there is one WGP enabled, it means 2 CUs will be enabled */
10109		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10110		if (wgp_active_bitmap & (1 << wgp_idx))
10111			cu_active_bitmap |= cu_bitmap_per_wgp;
10112	}
10113
10114	return cu_active_bitmap;
10115}
10116
10117static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10118				 struct amdgpu_cu_info *cu_info)
10119{
10120	int i, j, k, counter, active_cu_number = 0;
10121	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10122	unsigned int disable_masks[4 * 2];
10123
10124	if (!adev || !cu_info)
10125		return -EINVAL;
10126
10127	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10128
10129	mutex_lock(&adev->grbm_idx_mutex);
10130	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10131		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10132			bitmap = i * adev->gfx.config.max_sh_per_se + j;
10133			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10134			      IP_VERSION(10, 3, 0)) ||
10135			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10136			      IP_VERSION(10, 3, 3)) ||
10137			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10138			      IP_VERSION(10, 3, 6)) ||
10139			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10140			      IP_VERSION(10, 3, 7))) &&
10141			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10142				continue;
10143			mask = 1;
10144			ao_bitmap = 0;
10145			counter = 0;
10146			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10147			if (i < 4 && j < 2)
10148				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10149					adev, disable_masks[i * 2 + j]);
10150			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10151			cu_info->bitmap[0][i][j] = bitmap;
10152
10153			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10154				if (bitmap & mask) {
10155					if (counter < adev->gfx.config.max_cu_per_sh)
10156						ao_bitmap |= mask;
10157					counter++;
10158				}
10159				mask <<= 1;
10160			}
10161			active_cu_number += counter;
10162			if (i < 2 && j < 2)
10163				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10164			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10165		}
10166	}
10167	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10168	mutex_unlock(&adev->grbm_idx_mutex);
10169
10170	cu_info->number = active_cu_number;
10171	cu_info->ao_cu_mask = ao_cu_mask;
10172	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10173
10174	return 0;
10175}
10176
10177static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10178{
10179	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10180
10181	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10182	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10183	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10184
10185	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10186	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10187	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10188
10189	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10190						adev->gfx.config.max_shader_engines);
10191	disabled_sa = efuse_setting | vbios_setting;
10192	disabled_sa &= max_sa_mask;
10193
10194	return disabled_sa;
10195}
10196
10197static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10198{
10199	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10200	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10201
10202	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10203
10204	max_sa_per_se = adev->gfx.config.max_sh_per_se;
10205	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10206	max_shader_engines = adev->gfx.config.max_shader_engines;
10207
10208	for (se_index = 0; max_shader_engines > se_index; se_index++) {
10209		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10210		disabled_sa_per_se &= max_sa_per_se_mask;
10211		if (disabled_sa_per_se == max_sa_per_se_mask) {
10212			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10213			break;
10214		}
10215	}
10216}
10217
10218static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10219{
10220	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10221		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10222		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10223		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10224
10225	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10226	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10227		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10228		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10229		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10230		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10231
10232	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10233		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10234		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10235		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10236
10237	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10238
10239	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10240		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10241}
10242
10243const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10244	.type = AMD_IP_BLOCK_TYPE_GFX,
10245	.major = 10,
10246	.minor = 0,
10247	.rev = 0,
10248	.funcs = &gfx_v10_0_ip_funcs,
10249};
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