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cikd.h
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/cikd.h
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef CIK_H 25#define CIK_H 26 27#define MC_SEQ_MISC0__MT__MASK 0xf0000000 28#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 29#define MC_SEQ_MISC0__MT__DDR2 0x20000000 30#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 31#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 32#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 33#define MC_SEQ_MISC0__MT__HBM 0x60000000 34#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 35 36#define CP_ME_TABLE_SIZE 96 37 38/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 39#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 40#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 41#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 42#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 43#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45 46/* hpd instance offsets */ 47#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 48#define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 49#define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 50#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 51#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 52#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 53 54/* audio endpt instance offsets */ 55#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 56#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 57#define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 58#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 59#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 60#define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 61#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 62 63#define PIPEID(x) ((x) << 0) 64#define MEID(x) ((x) << 2) 65#define VMID(x) ((x) << 4) 66#define QUEUEID(x) ((x) << 8) 67 68#define mmCC_DRM_ID_STRAPS 0x1559 69#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 70 71#define mmCHUB_CONTROL 0x619 72#define BYPASS_VM (1 << 0) 73 74#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 75 76#define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 77#define LUT_10BIT_BYPASS_EN (1 << 8) 78 79# define CURSOR_MONO 0 80# define CURSOR_24_1 1 81# define CURSOR_24_8_PRE_MULT 2 82# define CURSOR_24_8_UNPRE_MULT 3 83# define CURSOR_URGENT_ALWAYS 0 84# define CURSOR_URGENT_1_8 1 85# define CURSOR_URGENT_1_4 2 86# define CURSOR_URGENT_3_8 3 87# define CURSOR_URGENT_1_2 4 88 89# define GRPH_DEPTH_8BPP 0 90# define GRPH_DEPTH_16BPP 1 91# define GRPH_DEPTH_32BPP 2 92/* 8 BPP */ 93# define GRPH_FORMAT_INDEXED 0 94/* 16 BPP */ 95# define GRPH_FORMAT_ARGB1555 0 96# define GRPH_FORMAT_ARGB565 1 97# define GRPH_FORMAT_ARGB4444 2 98# define GRPH_FORMAT_AI88 3 99# define GRPH_FORMAT_MONO16 4 100# define GRPH_FORMAT_BGRA5551 5 101/* 32 BPP */ 102# define GRPH_FORMAT_ARGB8888 0 103# define GRPH_FORMAT_ARGB2101010 1 104# define GRPH_FORMAT_32BPP_DIG 2 105# define GRPH_FORMAT_8B_ARGB2101010 3 106# define GRPH_FORMAT_BGRA1010102 4 107# define GRPH_FORMAT_8B_BGRA1010102 5 108# define GRPH_FORMAT_RGB111110 6 109# define GRPH_FORMAT_BGR101111 7 110# define ADDR_SURF_MACRO_TILE_ASPECT_1 0 111# define ADDR_SURF_MACRO_TILE_ASPECT_2 1 112# define ADDR_SURF_MACRO_TILE_ASPECT_4 2 113# define ADDR_SURF_MACRO_TILE_ASPECT_8 3 114# define GRPH_ARRAY_LINEAR_GENERAL 0 115# define GRPH_ARRAY_LINEAR_ALIGNED 1 116# define GRPH_ARRAY_1D_TILED_THIN1 2 117# define GRPH_ARRAY_2D_TILED_THIN1 4 118# define DISPLAY_MICRO_TILING 0 119# define THIN_MICRO_TILING 1 120# define DEPTH_MICRO_TILING 2 121# define ROTATED_MICRO_TILING 4 122# define GRPH_ENDIAN_NONE 0 123# define GRPH_ENDIAN_8IN16 1 124# define GRPH_ENDIAN_8IN32 2 125# define GRPH_ENDIAN_8IN64 3 126# define GRPH_RED_SEL_R 0 127# define GRPH_RED_SEL_G 1 128# define GRPH_RED_SEL_B 2 129# define GRPH_RED_SEL_A 3 130# define GRPH_GREEN_SEL_G 0 131# define GRPH_GREEN_SEL_B 1 132# define GRPH_GREEN_SEL_A 2 133# define GRPH_GREEN_SEL_R 3 134# define GRPH_BLUE_SEL_B 0 135# define GRPH_BLUE_SEL_A 1 136# define GRPH_BLUE_SEL_R 2 137# define GRPH_BLUE_SEL_G 3 138# define GRPH_ALPHA_SEL_A 0 139# define GRPH_ALPHA_SEL_R 1 140# define GRPH_ALPHA_SEL_G 2 141# define GRPH_ALPHA_SEL_B 3 142# define INPUT_GAMMA_USE_LUT 0 143# define INPUT_GAMMA_BYPASS 1 144# define INPUT_GAMMA_SRGB_24 2 145# define INPUT_GAMMA_XVYCC_222 3 146 147# define INPUT_CSC_BYPASS 0 148# define INPUT_CSC_PROG_COEFF 1 149# define INPUT_CSC_PROG_SHARED_MATRIXA 2 150 151# define OUTPUT_CSC_BYPASS 0 152# define OUTPUT_CSC_TV_RGB 1 153# define OUTPUT_CSC_YCBCR_601 2 154# define OUTPUT_CSC_YCBCR_709 3 155# define OUTPUT_CSC_PROG_COEFF 4 156# define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 157 158# define DEGAMMA_BYPASS 0 159# define DEGAMMA_SRGB_24 1 160# define DEGAMMA_XVYCC_222 2 161# define GAMUT_REMAP_BYPASS 0 162# define GAMUT_REMAP_PROG_COEFF 1 163# define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 164# define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 165 166# define REGAMMA_BYPASS 0 167# define REGAMMA_SRGB_24 1 168# define REGAMMA_XVYCC_222 2 169# define REGAMMA_PROG_A 3 170# define REGAMMA_PROG_B 4 171 172# define FMT_CLAMP_6BPC 0 173# define FMT_CLAMP_8BPC 1 174# define FMT_CLAMP_10BPC 2 175 176# define HDMI_24BIT_DEEP_COLOR 0 177# define HDMI_30BIT_DEEP_COLOR 1 178# define HDMI_36BIT_DEEP_COLOR 2 179# define HDMI_ACR_HW 0 180# define HDMI_ACR_32 1 181# define HDMI_ACR_44 2 182# define HDMI_ACR_48 3 183# define HDMI_ACR_X1 1 184# define HDMI_ACR_X2 2 185# define HDMI_ACR_X4 4 186# define AFMT_AVI_INFO_Y_RGB 0 187# define AFMT_AVI_INFO_Y_YCBCR422 1 188# define AFMT_AVI_INFO_Y_YCBCR444 2 189 190#define NO_AUTO 0 191#define ES_AUTO 1 192#define GS_AUTO 2 193#define ES_AND_GS_AUTO 3 194 195# define ARRAY_MODE(x) ((x) << 2) 196# define PIPE_CONFIG(x) ((x) << 6) 197# define TILE_SPLIT(x) ((x) << 11) 198# define MICRO_TILE_MODE_NEW(x) ((x) << 22) 199# define SAMPLE_SPLIT(x) ((x) << 25) 200# define BANK_WIDTH(x) ((x) << 0) 201# define BANK_HEIGHT(x) ((x) << 2) 202# define MACRO_TILE_ASPECT(x) ((x) << 4) 203# define NUM_BANKS(x) ((x) << 6) 204 205#define MSG_ENTER_RLC_SAFE_MODE 1 206#define MSG_EXIT_RLC_SAFE_MODE 0 207 208/* 209 * PM4 210 */ 211#define PACKET_TYPE0 0 212#define PACKET_TYPE1 1 213#define PACKET_TYPE2 2 214#define PACKET_TYPE3 3 215 216#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 217#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 218#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 219#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 220#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 221 ((reg) & 0xFFFF) | \ 222 ((n) & 0x3FFF) << 16) 223#define CP_PACKET2 0x80000000 224#define PACKET2_PAD_SHIFT 0 225#define PACKET2_PAD_MASK (0x3fffffff << 0) 226 227#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 228 229#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 230 (((op) & 0xFF) << 8) | \ 231 ((n) & 0x3FFF) << 16) 232 233#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 234 235/* Packet 3 types */ 236#define PACKET3_NOP 0x10 237#define PACKET3_SET_BASE 0x11 238#define PACKET3_BASE_INDEX(x) ((x) << 0) 239#define CE_PARTITION_BASE 3 240#define PACKET3_CLEAR_STATE 0x12 241#define PACKET3_INDEX_BUFFER_SIZE 0x13 242#define PACKET3_DISPATCH_DIRECT 0x15 243#define PACKET3_DISPATCH_INDIRECT 0x16 244#define PACKET3_ATOMIC_GDS 0x1D 245#define PACKET3_ATOMIC_MEM 0x1E 246#define PACKET3_OCCLUSION_QUERY 0x1F 247#define PACKET3_SET_PREDICATION 0x20 248#define PACKET3_REG_RMW 0x21 249#define PACKET3_COND_EXEC 0x22 250#define PACKET3_PRED_EXEC 0x23 251#define PACKET3_DRAW_INDIRECT 0x24 252#define PACKET3_DRAW_INDEX_INDIRECT 0x25 253#define PACKET3_INDEX_BASE 0x26 254#define PACKET3_DRAW_INDEX_2 0x27 255#define PACKET3_CONTEXT_CONTROL 0x28 256#define PACKET3_INDEX_TYPE 0x2A 257#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 258#define PACKET3_DRAW_INDEX_AUTO 0x2D 259#define PACKET3_NUM_INSTANCES 0x2F 260#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 261#define PACKET3_INDIRECT_BUFFER_CONST 0x33 262#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 263#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 264#define PACKET3_DRAW_PREAMBLE 0x36 265#define PACKET3_WRITE_DATA 0x37 266#define WRITE_DATA_DST_SEL(x) ((x) << 8) 267 /* 0 - register 268 * 1 - memory (sync - via GRBM) 269 * 2 - gl2 270 * 3 - gds 271 * 4 - reserved 272 * 5 - memory (async - direct) 273 */ 274#define WR_ONE_ADDR (1 << 16) 275#define WR_CONFIRM (1 << 20) 276#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 277 /* 0 - LRU 278 * 1 - Stream 279 */ 280#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 281 /* 0 - me 282 * 1 - pfp 283 * 2 - ce 284 */ 285#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 286#define PACKET3_MEM_SEMAPHORE 0x39 287# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 288# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 289# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 290# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 291# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 292#define PACKET3_COPY_DW 0x3B 293#define PACKET3_WAIT_REG_MEM 0x3C 294#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 295 /* 0 - always 296 * 1 - < 297 * 2 - <= 298 * 3 - == 299 * 4 - != 300 * 5 - >= 301 * 6 - > 302 */ 303#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 304 /* 0 - reg 305 * 1 - mem 306 */ 307#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 308 /* 0 - wait_reg_mem 309 * 1 - wr_wait_wr_reg 310 */ 311#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 312 /* 0 - me 313 * 1 - pfp 314 */ 315#define PACKET3_INDIRECT_BUFFER 0x3F 316#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 317#define INDIRECT_BUFFER_VALID (1 << 23) 318#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 319 /* 0 - LRU 320 * 1 - Stream 321 * 2 - Bypass 322 */ 323#define PACKET3_COPY_DATA 0x40 324#define PACKET3_PFP_SYNC_ME 0x42 325#define PACKET3_SURFACE_SYNC 0x43 326# define PACKET3_DEST_BASE_0_ENA (1 << 0) 327# define PACKET3_DEST_BASE_1_ENA (1 << 1) 328# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 329# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 330# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 331# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 332# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 333# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 334# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 335# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 336# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 337# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 338# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 339# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 340# define PACKET3_DEST_BASE_2_ENA (1 << 19) 341# define PACKET3_DEST_BASE_3_ENA (1 << 21) 342# define PACKET3_TCL1_ACTION_ENA (1 << 22) 343# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 344# define PACKET3_CB_ACTION_ENA (1 << 25) 345# define PACKET3_DB_ACTION_ENA (1 << 26) 346# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 347# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 348# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 349#define PACKET3_COND_WRITE 0x45 350#define PACKET3_EVENT_WRITE 0x46 351#define EVENT_TYPE(x) ((x) << 0) 352#define EVENT_INDEX(x) ((x) << 8) 353 /* 0 - any non-TS event 354 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 355 * 2 - SAMPLE_PIPELINESTAT 356 * 3 - SAMPLE_STREAMOUTSTAT* 357 * 4 - *S_PARTIAL_FLUSH 358 * 5 - EOP events 359 * 6 - EOS events 360 */ 361#define PACKET3_EVENT_WRITE_EOP 0x47 362#define EOP_TCL1_VOL_ACTION_EN (1 << 12) 363#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 364#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 365#define EOP_TCL1_ACTION_EN (1 << 16) 366#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 367#define EOP_TCL2_VOLATILE (1 << 24) 368#define EOP_CACHE_POLICY(x) ((x) << 25) 369 /* 0 - LRU 370 * 1 - Stream 371 * 2 - Bypass 372 */ 373#define EOP_EXEC (1 << 28) /* For Trailing Fence */ 374#define DATA_SEL(x) ((x) << 29) 375 /* 0 - discard 376 * 1 - send low 32bit data 377 * 2 - send 64bit data 378 * 3 - send 64bit GPU counter value 379 * 4 - send 64bit sys counter value 380 */ 381#define INT_SEL(x) ((x) << 24) 382 /* 0 - none 383 * 1 - interrupt only (DATA_SEL = 0) 384 * 2 - interrupt when data write is confirmed 385 */ 386#define DST_SEL(x) ((x) << 16) 387 /* 0 - MC 388 * 1 - TC/L2 389 */ 390#define PACKET3_EVENT_WRITE_EOS 0x48 391#define PACKET3_RELEASE_MEM 0x49 392#define PACKET3_PREAMBLE_CNTL 0x4A 393# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 394# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 395#define PACKET3_DMA_DATA 0x50 396/* 1. header 397 * 2. CONTROL 398 * 3. SRC_ADDR_LO or DATA [31:0] 399 * 4. SRC_ADDR_HI [31:0] 400 * 5. DST_ADDR_LO [31:0] 401 * 6. DST_ADDR_HI [7:0] 402 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 403 */ 404/* CONTROL */ 405# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 406 /* 0 - ME 407 * 1 - PFP 408 */ 409# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 410 /* 0 - LRU 411 * 1 - Stream 412 * 2 - Bypass 413 */ 414# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 415# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 416 /* 0 - DST_ADDR using DAS 417 * 1 - GDS 418 * 3 - DST_ADDR using L2 419 */ 420# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 421 /* 0 - LRU 422 * 1 - Stream 423 * 2 - Bypass 424 */ 425# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 426# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 427 /* 0 - SRC_ADDR using SAS 428 * 1 - GDS 429 * 2 - DATA 430 * 3 - SRC_ADDR using L2 431 */ 432# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 433/* COMMAND */ 434# define PACKET3_DMA_DATA_DIS_WC (1 << 21) 435# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 436 /* 0 - none 437 * 1 - 8 in 16 438 * 2 - 8 in 32 439 * 3 - 8 in 64 440 */ 441# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 442 /* 0 - none 443 * 1 - 8 in 16 444 * 2 - 8 in 32 445 * 3 - 8 in 64 446 */ 447# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 448 /* 0 - memory 449 * 1 - register 450 */ 451# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 452 /* 0 - memory 453 * 1 - register 454 */ 455# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 456# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 457# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 458#define PACKET3_ACQUIRE_MEM 0x58 459#define PACKET3_REWIND 0x59 460#define PACKET3_LOAD_UCONFIG_REG 0x5E 461#define PACKET3_LOAD_SH_REG 0x5F 462#define PACKET3_LOAD_CONFIG_REG 0x60 463#define PACKET3_LOAD_CONTEXT_REG 0x61 464#define PACKET3_SET_CONFIG_REG 0x68 465#define PACKET3_SET_CONFIG_REG_START 0x00002000 466#define PACKET3_SET_CONFIG_REG_END 0x00002c00 467#define PACKET3_SET_CONTEXT_REG 0x69 468#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 469#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 470#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 471#define PACKET3_SET_SH_REG 0x76 472#define PACKET3_SET_SH_REG_START 0x00002c00 473#define PACKET3_SET_SH_REG_END 0x00003000 474#define PACKET3_SET_SH_REG_OFFSET 0x77 475#define PACKET3_SET_QUEUE_REG 0x78 476#define PACKET3_SET_UCONFIG_REG 0x79 477#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 478#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 479#define PACKET3_SCRATCH_RAM_WRITE 0x7D 480#define PACKET3_SCRATCH_RAM_READ 0x7E 481#define PACKET3_LOAD_CONST_RAM 0x80 482#define PACKET3_WRITE_CONST_RAM 0x81 483#define PACKET3_DUMP_CONST_RAM 0x83 484#define PACKET3_INCREMENT_CE_COUNTER 0x84 485#define PACKET3_INCREMENT_DE_COUNTER 0x85 486#define PACKET3_WAIT_ON_CE_COUNTER 0x86 487#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 488#define PACKET3_SWITCH_BUFFER 0x8B 489 490/* SDMA - first instance at 0xd000, second at 0xd800 */ 491#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 492#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 493#define SDMA_MAX_INSTANCE 2 494 495#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 496 (((sub_op) & 0xFF) << 8) | \ 497 (((op) & 0xFF) << 0)) 498/* sDMA opcodes */ 499#define SDMA_OPCODE_NOP 0 500# define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 501#define SDMA_OPCODE_COPY 1 502# define SDMA_COPY_SUB_OPCODE_LINEAR 0 503# define SDMA_COPY_SUB_OPCODE_TILED 1 504# define SDMA_COPY_SUB_OPCODE_SOA 3 505# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 506# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 507# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 508#define SDMA_OPCODE_WRITE 2 509# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 510# define SDMA_WRITE_SUB_OPCODE_TILED 1 511#define SDMA_OPCODE_INDIRECT_BUFFER 4 512#define SDMA_OPCODE_FENCE 5 513#define SDMA_OPCODE_TRAP 6 514#define SDMA_OPCODE_SEMAPHORE 7 515# define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 516 /* 0 - increment 517 * 1 - write 1 518 */ 519# define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 520 /* 0 - wait 521 * 1 - signal 522 */ 523# define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 524 /* mailbox */ 525#define SDMA_OPCODE_POLL_REG_MEM 8 526# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 527 /* 0 - wait_reg_mem 528 * 1 - wr_wait_wr_reg 529 */ 530# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 531 /* 0 - always 532 * 1 - < 533 * 2 - <= 534 * 3 - == 535 * 4 - != 536 * 5 - >= 537 * 6 - > 538 */ 539# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 540 /* 0 = register 541 * 1 = memory 542 */ 543#define SDMA_OPCODE_COND_EXEC 9 544#define SDMA_OPCODE_CONSTANT_FILL 11 545# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 546 /* 0 = byte fill 547 * 2 = DW fill 548 */ 549#define SDMA_OPCODE_GENERATE_PTE_PDE 12 550#define SDMA_OPCODE_TIMESTAMP 13 551# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 552# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 553# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 554#define SDMA_OPCODE_SRBM_WRITE 14 555# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 556 /* byte mask */ 557 558#define VCE_CMD_NO_OP 0x00000000 559#define VCE_CMD_END 0x00000001 560#define VCE_CMD_IB 0x00000002 561#define VCE_CMD_FENCE 0x00000003 562#define VCE_CMD_TRAP 0x00000004 563#define VCE_CMD_IB_AUTO 0x00000005 564#define VCE_CMD_SEMAPHORE 0x00000006 565 566/* if PTR32, these are the bases for scratch and lds */ 567#define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 568#define SHARED_BASE(x) ((x) << 16) /* LDS */ 569 570#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) 571 572/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 573enum { 574 MTYPE_CACHED = 0, 575 MTYPE_NONCACHED = 3 576}; 577 578/* mmPA_SC_RASTER_CONFIG mask */ 579#define RB_MAP_PKR0(x) ((x) << 0) 580#define RB_MAP_PKR0_MASK (0x3 << 0) 581#define RB_MAP_PKR1(x) ((x) << 2) 582#define RB_MAP_PKR1_MASK (0x3 << 2) 583#define RB_XSEL2(x) ((x) << 4) 584#define RB_XSEL2_MASK (0x3 << 4) 585#define RB_XSEL (1 << 6) 586#define RB_YSEL (1 << 7) 587#define PKR_MAP(x) ((x) << 8) 588#define PKR_MAP_MASK (0x3 << 8) 589#define PKR_XSEL(x) ((x) << 10) 590#define PKR_XSEL_MASK (0x3 << 10) 591#define PKR_YSEL(x) ((x) << 12) 592#define PKR_YSEL_MASK (0x3 << 12) 593#define SC_MAP(x) ((x) << 16) 594#define SC_MAP_MASK (0x3 << 16) 595#define SC_XSEL(x) ((x) << 18) 596#define SC_XSEL_MASK (0x3 << 18) 597#define SC_YSEL(x) ((x) << 20) 598#define SC_YSEL_MASK (0x3 << 20) 599#define SE_MAP(x) ((x) << 24) 600#define SE_MAP_MASK (0x3 << 24) 601#define SE_XSEL(x) ((x) << 26) 602#define SE_XSEL_MASK (0x3 << 26) 603#define SE_YSEL(x) ((x) << 28) 604#define SE_YSEL_MASK (0x3 << 28) 605 606/* mmPA_SC_RASTER_CONFIG_1 mask */ 607#define SE_PAIR_MAP(x) ((x) << 0) 608#define SE_PAIR_MAP_MASK (0x3 << 0) 609#define SE_PAIR_XSEL(x) ((x) << 2) 610#define SE_PAIR_XSEL_MASK (0x3 << 2) 611#define SE_PAIR_YSEL(x) ((x) << 4) 612#define SE_PAIR_YSEL_MASK (0x3 << 4) 613 614#endif
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