amdgpu_userq_fence.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright 2023 Advanced Micro Devices, Inc.
 4 *
 5 * Permission is hereby granted, free of charge, to any person obtaining a
 6 * copy of this software and associated documentation files (the "Software"),
 7 * to deal in the Software without restriction, including without limitation
 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef __AMDGPU_USERQ_FENCE_H__
26#define __AMDGPU_USERQ_FENCE_H__
27
28#include <linux/types.h>
29
30#include "amdgpu_userq.h"
31
32struct amdgpu_userq_fence {
33	struct dma_fence base;
34	/*
35	 * This lock is necessary to synchronize the
36	 * userqueue dma fence operations.
37	 */
38	spinlock_t lock;
39	struct list_head link;
40	unsigned long fence_drv_array_count;
41	struct amdgpu_userq_fence_driver *fence_drv;
42	struct amdgpu_userq_fence_driver **fence_drv_array;
43};
44
45struct amdgpu_userq_fence_driver {
46	struct kref refcount;
47	u64 va;
48	u64 gpu_addr;
49	u64 *cpu_addr;
50	u64 context;
51	/*
52	 * This lock is necesaary to synchronize the access
53	 * to the fences list by the fence driver.
54	 */
55	spinlock_t fence_list_lock;
56	struct list_head fences;
57	struct amdgpu_device *adev;
58	char timeline_name[TASK_COMM_LEN];
59};
60
61int amdgpu_userq_fence_slab_init(void);
62void amdgpu_userq_fence_slab_fini(void);
63
64void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv);
65void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv);
66int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev,
67				    struct amdgpu_usermode_queue *userq);
68void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq);
69void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv);
70void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq);
71void amdgpu_userq_fence_driver_destroy(struct kref *ref);
72int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
73			      struct drm_file *filp);
74int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
75			    struct drm_file *filp);
76
77#endif