amdgpu_ttm.h

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef __AMDGPU_TTM_H__
 25#define __AMDGPU_TTM_H__
 26
 27#include <linux/dma-direction.h>
 28#include <drm/gpu_scheduler.h>
 29#include <drm/ttm/ttm_placement.h>
 30#include "amdgpu_vram_mgr.h"
 31#include "amdgpu_hmm.h"
 32
 33#define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
 34#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
 35#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)
 36#define AMDGPU_PL_PREEMPT	(TTM_PL_PRIV + 3)
 37#define AMDGPU_PL_DOORBELL	(TTM_PL_PRIV + 4)
 38#define AMDGPU_PL_MMIO_REMAP	(TTM_PL_PRIV + 5)
 39#define __AMDGPU_PL_NUM	(TTM_PL_PRIV + 6)
 40
 41#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
 42#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2
 43
 44extern const struct attribute_group amdgpu_vram_mgr_attr_group;
 45extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
 46
 47struct hmm_range;
 48
 49struct amdgpu_gtt_mgr {
 50	struct ttm_resource_manager manager;
 51	struct drm_mm mm;
 52	spinlock_t lock;
 53};
 54
 55struct amdgpu_mman {
 56	struct ttm_device		bdev;
 57	struct ttm_pool			*ttm_pools;
 58	bool				initialized;
 59	void __iomem			*aper_base_kaddr;
 60
 61	/* buffer handling */
 62	const struct amdgpu_buffer_funcs	*buffer_funcs;
 63	struct amdgpu_ring			*buffer_funcs_ring;
 64	bool					buffer_funcs_enabled;
 65
 66	struct mutex				gtt_window_lock;
 67	/* High priority scheduler entity for buffer moves */
 68	struct drm_sched_entity			high_pr;
 69	/* Low priority scheduler entity for VRAM clearing */
 70	struct drm_sched_entity			low_pr;
 71
 72	struct amdgpu_vram_mgr vram_mgr;
 73	struct amdgpu_gtt_mgr gtt_mgr;
 74	struct ttm_resource_manager preempt_mgr;
 75
 76	uint64_t		stolen_vga_size;
 77	struct amdgpu_bo	*stolen_vga_memory;
 78	uint64_t		stolen_extended_size;
 79	struct amdgpu_bo	*stolen_extended_memory;
 80	bool			keep_stolen_vga_memory;
 81
 82	struct amdgpu_bo	*stolen_reserved_memory;
 83	uint64_t		stolen_reserved_offset;
 84	uint64_t		stolen_reserved_size;
 85
 86	/* fw reserved memory */
 87	struct amdgpu_bo		*fw_reserved_memory;
 88	struct amdgpu_bo		*fw_reserved_memory_extend;
 89
 90	/* firmware VRAM reservation */
 91	u64		fw_vram_usage_start_offset;
 92	u64		fw_vram_usage_size;
 93	struct amdgpu_bo	*fw_vram_usage_reserved_bo;
 94	void		*fw_vram_usage_va;
 95
 96	/* driver VRAM reservation */
 97	u64		drv_vram_usage_start_offset;
 98	u64		drv_vram_usage_size;
 99	struct amdgpu_bo	*drv_vram_usage_reserved_bo;
100	void		*drv_vram_usage_va;
101
102	/* PAGE_SIZE'd BO for process memory r/w over SDMA. */
103	struct amdgpu_bo	*sdma_access_bo;
104	void			*sdma_access_ptr;
105};
106
107struct amdgpu_copy_mem {
108	struct ttm_buffer_object	*bo;
109	struct ttm_resource		*mem;
110	unsigned long			offset;
111};
112
113#define AMDGPU_COPY_FLAGS_TMZ		(1 << 0)
114#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED	(1 << 1)
115#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED	(1 << 2)
116#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT		3
117#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK		0x03
118#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT		5
119#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK		0x07
120#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT		8
121#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK		0x3f
122#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT	14
123#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK	0x1
124
125#define AMDGPU_COPY_FLAGS_SET(field, value) \
126	(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)
127#define AMDGPU_COPY_FLAGS_GET(value, field) \
128	(((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)
129
130int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
131void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
132int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
133void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
134int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
135void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
136
137bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
138void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
139
140uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
141
142u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
143int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
144			      struct ttm_resource *mem,
145			      u64 offset, u64 size,
146			      struct device *dev,
147			      enum dma_data_direction dir,
148			      struct sg_table **sgt);
149void amdgpu_vram_mgr_free_sgt(struct device *dev,
150			      enum dma_data_direction dir,
151			      struct sg_table *sgt);
152uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
153int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
154				  uint64_t start, uint64_t size);
155int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
156				      uint64_t start);
157void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev);
158
159bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
160			    struct ttm_resource *res);
161
162int amdgpu_ttm_init(struct amdgpu_device *adev);
163void amdgpu_ttm_fini(struct amdgpu_device *adev);
164void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
165					bool enable);
166int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
167		       uint64_t dst_offset, uint32_t byte_count,
168		       struct dma_resv *resv,
169		       struct dma_fence **fence, bool direct_submit,
170		       bool vm_needs_flush, uint32_t copy_flags);
171int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
172			    struct dma_resv *resv,
173			    struct dma_fence **fence);
174int amdgpu_fill_buffer(struct amdgpu_bo *bo,
175			uint32_t src_data,
176			struct dma_resv *resv,
177			struct dma_fence **fence,
178			bool delayed,
179			u64 k_job_id);
180
181int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
182void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
183uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
184
185#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
186int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
187				 struct amdgpu_hmm_range *range);
188#else
189static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
190					       struct amdgpu_hmm_range *range)
191{
192	return -EPERM;
193}
194#endif
195
196void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range);
197int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
198			      uint64_t *user_addr);
199int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
200			      uint64_t addr, uint32_t flags);
201bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
202struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
203bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
204				  unsigned long end, unsigned long *userptr);
205bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
206				       int *last_invalidated);
207bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
208bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
209uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
210uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
211				 struct ttm_resource *mem);
212int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
213
214void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
215
216#endif