amdgpu_ttm.c

   1/*
   2 * Copyright 2009 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26/*
  27 * Authors:
  28 *    Jerome Glisse <glisse@freedesktop.org>
  29 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30 *    Dave Airlie
  31 */
  32
  33#include <linux/dma-mapping.h>
  34#include <linux/iommu.h>
  35#include <linux/pagemap.h>
  36#include <linux/sched/task.h>
  37#include <linux/sched/mm.h>
  38#include <linux/seq_file.h>
  39#include <linux/slab.h>
  40#include <linux/swap.h>
  41#include <linux/dma-buf.h>
  42#include <linux/sizes.h>
  43#include <linux/module.h>
  44
  45#include <drm/drm_drv.h>
  46#include <drm/ttm/ttm_bo.h>
  47#include <drm/ttm/ttm_placement.h>
  48#include <drm/ttm/ttm_range_manager.h>
  49#include <drm/ttm/ttm_tt.h>
  50
  51#include <drm/amdgpu_drm.h>
  52
  53#include "amdgpu.h"
  54#include "amdgpu_object.h"
  55#include "amdgpu_trace.h"
  56#include "amdgpu_amdkfd.h"
  57#include "amdgpu_sdma.h"
  58#include "amdgpu_ras.h"
  59#include "amdgpu_hmm.h"
  60#include "amdgpu_atomfirmware.h"
  61#include "amdgpu_res_cursor.h"
  62#include "bif/bif_4_1_d.h"
  63
  64MODULE_IMPORT_NS("DMA_BUF");
  65
  66#define AMDGPU_TTM_VRAM_MAX_DW_READ	((size_t)128)
  67
  68static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  69				   struct ttm_tt *ttm,
  70				   struct ttm_resource *bo_mem);
  71static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  72				      struct ttm_tt *ttm);
  73
  74static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  75				    unsigned int type,
  76				    uint64_t size_in_page)
  77{
  78	return ttm_range_man_init(&adev->mman.bdev, type,
  79				  false, size_in_page);
  80}
  81
  82/**
  83 * amdgpu_evict_flags - Compute placement flags
  84 *
  85 * @bo: The buffer object to evict
  86 * @placement: Possible destination(s) for evicted BO
  87 *
  88 * Fill in placement data when ttm_bo_evict() is called
  89 */
  90static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  91				struct ttm_placement *placement)
  92{
  93	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  94	struct amdgpu_bo *abo;
  95	static const struct ttm_place placements = {
  96		.fpfn = 0,
  97		.lpfn = 0,
  98		.mem_type = TTM_PL_SYSTEM,
  99		.flags = 0
 100	};
 101
 102	/* Don't handle scatter gather BOs */
 103	if (bo->type == ttm_bo_type_sg) {
 104		placement->num_placement = 0;
 105		return;
 106	}
 107
 108	/* Object isn't an AMDGPU object so ignore */
 109	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 110		placement->placement = &placements;
 111		placement->num_placement = 1;
 112		return;
 113	}
 114
 115	abo = ttm_to_amdgpu_bo(bo);
 116	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
 117		placement->num_placement = 0;
 118		return;
 119	}
 120
 121	switch (bo->resource->mem_type) {
 122	case AMDGPU_PL_GDS:
 123	case AMDGPU_PL_GWS:
 124	case AMDGPU_PL_OA:
 125	case AMDGPU_PL_DOORBELL:
 126	case AMDGPU_PL_MMIO_REMAP:
 127		placement->num_placement = 0;
 128		return;
 129
 130	case TTM_PL_VRAM:
 131		if (!adev->mman.buffer_funcs_enabled) {
 132			/* Move to system memory */
 133			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 134
 135		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 136			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 137			   amdgpu_res_cpu_visible(adev, bo->resource)) {
 138
 139			/* Try evicting to the CPU inaccessible part of VRAM
 140			 * first, but only set GTT as busy placement, so this
 141			 * BO will be evicted to GTT rather than causing other
 142			 * BOs to be evicted from VRAM
 143			 */
 144			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 145							AMDGPU_GEM_DOMAIN_GTT |
 146							AMDGPU_GEM_DOMAIN_CPU);
 147			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 148			abo->placements[0].lpfn = 0;
 149			abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
 150		} else {
 151			/* Move to GTT memory */
 152			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
 153							AMDGPU_GEM_DOMAIN_CPU);
 154		}
 155		break;
 156	case TTM_PL_TT:
 157	case AMDGPU_PL_PREEMPT:
 158	default:
 159		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 160		break;
 161	}
 162	*placement = abo->placement;
 163}
 164
 165/**
 166 * amdgpu_ttm_map_buffer - Map memory into the GART windows
 167 * @bo: buffer object to map
 168 * @mem: memory object to map
 169 * @mm_cur: range to map
 170 * @window: which GART window to use
 171 * @ring: DMA ring to use for the copy
 172 * @tmz: if we should setup a TMZ enabled mapping
 173 * @size: in number of bytes to map, out number of bytes mapped
 174 * @addr: resulting address inside the MC address space
 175 *
 176 * Setup one of the GART windows to access a specific piece of memory or return
 177 * the physical address for local memory.
 178 */
 179static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 180				 struct ttm_resource *mem,
 181				 struct amdgpu_res_cursor *mm_cur,
 182				 unsigned int window, struct amdgpu_ring *ring,
 183				 bool tmz, uint64_t *size, uint64_t *addr)
 184{
 185	struct amdgpu_device *adev = ring->adev;
 186	unsigned int offset, num_pages, num_dw, num_bytes;
 187	uint64_t src_addr, dst_addr;
 188	struct amdgpu_job *job;
 189	void *cpu_addr;
 190	uint64_t flags;
 191	int r;
 192
 193	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 194	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 195
 196	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
 197		return -EINVAL;
 198
 199	/* Map only what can't be accessed directly */
 200	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 201		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 202			mm_cur->start;
 203		return 0;
 204	}
 205
 206
 207	/*
 208	 * If start begins at an offset inside the page, then adjust the size
 209	 * and addr accordingly
 210	 */
 211	offset = mm_cur->start & ~PAGE_MASK;
 212
 213	num_pages = PFN_UP(*size + offset);
 214	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
 215
 216	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
 217
 218	*addr = adev->gmc.gart_start;
 219	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 220		AMDGPU_GPU_PAGE_SIZE;
 221	*addr += offset;
 222
 223	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 224	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 225
 226	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
 227				     AMDGPU_FENCE_OWNER_UNDEFINED,
 228				     num_dw * 4 + num_bytes,
 229				     AMDGPU_IB_POOL_DELAYED, &job,
 230				     AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER);
 231	if (r)
 232		return r;
 233
 234	src_addr = num_dw * 4;
 235	src_addr += job->ibs[0].gpu_addr;
 236
 237	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 238	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 239	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 240				dst_addr, num_bytes, 0);
 241
 242	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 243	WARN_ON(job->ibs[0].length_dw > num_dw);
 244
 245	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 246	if (tmz)
 247		flags |= AMDGPU_PTE_TMZ;
 248
 249	cpu_addr = &job->ibs[0].ptr[num_dw];
 250
 251	if (mem->mem_type == TTM_PL_TT) {
 252		dma_addr_t *dma_addr;
 253
 254		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 255		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
 256	} else {
 257		u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset;
 258
 259		amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr);
 260	}
 261
 262	dma_fence_put(amdgpu_job_submit(job));
 263	return 0;
 264}
 265
 266/**
 267 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 268 * @adev: amdgpu device
 269 * @src: buffer/address where to read from
 270 * @dst: buffer/address where to write to
 271 * @size: number of bytes to copy
 272 * @tmz: if a secure copy should be used
 273 * @resv: resv object to sync to
 274 * @f: Returns the last fence if multiple jobs are submitted.
 275 *
 276 * The function copies @size bytes from {src->mem + src->offset} to
 277 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 278 * move and different for a BO to BO copy.
 279 *
 280 */
 281__attribute__((nonnull))
 282static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 283				      const struct amdgpu_copy_mem *src,
 284				      const struct amdgpu_copy_mem *dst,
 285				      uint64_t size, bool tmz,
 286				      struct dma_resv *resv,
 287				      struct dma_fence **f)
 288{
 289	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 290	struct amdgpu_res_cursor src_mm, dst_mm;
 291	struct dma_fence *fence = NULL;
 292	int r = 0;
 293	uint32_t copy_flags = 0;
 294	struct amdgpu_bo *abo_src, *abo_dst;
 295
 296	if (!adev->mman.buffer_funcs_enabled) {
 297		dev_err(adev->dev,
 298			"Trying to move memory with ring turned off.\n");
 299		return -EINVAL;
 300	}
 301
 302	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 303	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 304
 305	mutex_lock(&adev->mman.gtt_window_lock);
 306	while (src_mm.remaining) {
 307		uint64_t from, to, cur_size, tiling_flags;
 308		uint32_t num_type, data_format, max_com, write_compress_disable;
 309		struct dma_fence *next;
 310
 311		/* Never copy more than 256MiB at once to avoid a timeout */
 312		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
 313
 314		/* Map src to window 0 and dst to window 1. */
 315		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 316					  0, ring, tmz, &cur_size, &from);
 317		if (r)
 318			goto error;
 319
 320		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 321					  1, ring, tmz, &cur_size, &to);
 322		if (r)
 323			goto error;
 324
 325		abo_src = ttm_to_amdgpu_bo(src->bo);
 326		abo_dst = ttm_to_amdgpu_bo(dst->bo);
 327		if (tmz)
 328			copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
 329		if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
 330		    (abo_src->tbo.resource->mem_type == TTM_PL_VRAM))
 331			copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
 332		if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
 333		    (dst->mem->mem_type == TTM_PL_VRAM)) {
 334			copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
 335			amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags);
 336			max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
 337			num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
 338			data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
 339			write_compress_disable =
 340				AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
 341			copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
 342				       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
 343				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
 344				       AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
 345							     write_compress_disable));
 346		}
 347
 348		r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
 349				       &next, false, true, copy_flags);
 350		if (r)
 351			goto error;
 352
 353		dma_fence_put(fence);
 354		fence = next;
 355
 356		amdgpu_res_next(&src_mm, cur_size);
 357		amdgpu_res_next(&dst_mm, cur_size);
 358	}
 359error:
 360	mutex_unlock(&adev->mman.gtt_window_lock);
 361	*f = fence;
 362	return r;
 363}
 364
 365/*
 366 * amdgpu_move_blit - Copy an entire buffer to another buffer
 367 *
 368 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 369 * help move buffers to and from VRAM.
 370 */
 371static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 372			    bool evict,
 373			    struct ttm_resource *new_mem,
 374			    struct ttm_resource *old_mem)
 375{
 376	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 377	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 378	struct amdgpu_copy_mem src, dst;
 379	struct dma_fence *fence = NULL;
 380	int r;
 381
 382	src.bo = bo;
 383	dst.bo = bo;
 384	src.mem = old_mem;
 385	dst.mem = new_mem;
 386	src.offset = 0;
 387	dst.offset = 0;
 388
 389	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 390				       new_mem->size,
 391				       amdgpu_bo_encrypted(abo),
 392				       bo->base.resv, &fence);
 393	if (r)
 394		goto error;
 395
 396	/* clear the space being freed */
 397	if (old_mem->mem_type == TTM_PL_VRAM &&
 398	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 399		struct dma_fence *wipe_fence = NULL;
 400
 401		r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence,
 402				       false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
 403		if (r) {
 404			goto error;
 405		} else if (wipe_fence) {
 406			amdgpu_vram_mgr_set_cleared(bo->resource);
 407			dma_fence_put(fence);
 408			fence = wipe_fence;
 409		}
 410	}
 411
 412	/* Always block for VM page tables before committing the new location */
 413	if (bo->type == ttm_bo_type_kernel)
 414		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 415	else
 416		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 417	dma_fence_put(fence);
 418	return r;
 419
 420error:
 421	if (fence)
 422		dma_fence_wait(fence, false);
 423	dma_fence_put(fence);
 424	return r;
 425}
 426
 427/**
 428 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU
 429 * @adev: amdgpu device
 430 * @res: the resource to check
 431 *
 432 * Returns: true if the full resource is CPU visible, false otherwise.
 433 */
 434bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
 435			    struct ttm_resource *res)
 436{
 437	struct amdgpu_res_cursor cursor;
 438
 439	if (!res)
 440		return false;
 441
 442	if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||
 443	    res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL ||
 444	    res->mem_type == AMDGPU_PL_MMIO_REMAP)
 445		return true;
 446
 447	if (res->mem_type != TTM_PL_VRAM)
 448		return false;
 449
 450	amdgpu_res_first(res, 0, res->size, &cursor);
 451	while (cursor.remaining) {
 452		if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
 453			return false;
 454		amdgpu_res_next(&cursor, cursor.size);
 455	}
 456
 457	return true;
 458}
 459
 460/*
 461 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy
 462 *
 463 * Called by amdgpu_bo_move()
 464 */
 465static bool amdgpu_res_copyable(struct amdgpu_device *adev,
 466				struct ttm_resource *mem)
 467{
 468	if (!amdgpu_res_cpu_visible(adev, mem))
 469		return false;
 470
 471	/* ttm_resource_ioremap only supports contiguous memory */
 472	if (mem->mem_type == TTM_PL_VRAM &&
 473	    !(mem->placement & TTM_PL_FLAG_CONTIGUOUS))
 474		return false;
 475
 476	return true;
 477}
 478
 479/*
 480 * amdgpu_bo_move - Move a buffer object to a new memory location
 481 *
 482 * Called by ttm_bo_handle_move_mem()
 483 */
 484static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 485			  struct ttm_operation_ctx *ctx,
 486			  struct ttm_resource *new_mem,
 487			  struct ttm_place *hop)
 488{
 489	struct amdgpu_device *adev;
 490	struct amdgpu_bo *abo;
 491	struct ttm_resource *old_mem = bo->resource;
 492	int r;
 493
 494	if (new_mem->mem_type == TTM_PL_TT ||
 495	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 496		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 497		if (r)
 498			return r;
 499	}
 500
 501	abo = ttm_to_amdgpu_bo(bo);
 502	adev = amdgpu_ttm_adev(bo->bdev);
 503
 504	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 505			 bo->ttm == NULL)) {
 506		amdgpu_bo_move_notify(bo, evict, new_mem);
 507		ttm_bo_move_null(bo, new_mem);
 508		return 0;
 509	}
 510	if (old_mem->mem_type == TTM_PL_SYSTEM &&
 511	    (new_mem->mem_type == TTM_PL_TT ||
 512	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 513		amdgpu_bo_move_notify(bo, evict, new_mem);
 514		ttm_bo_move_null(bo, new_mem);
 515		return 0;
 516	}
 517	if ((old_mem->mem_type == TTM_PL_TT ||
 518	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 519	    new_mem->mem_type == TTM_PL_SYSTEM) {
 520		r = ttm_bo_wait_ctx(bo, ctx);
 521		if (r)
 522			return r;
 523
 524		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 525		amdgpu_bo_move_notify(bo, evict, new_mem);
 526		ttm_resource_free(bo, &bo->resource);
 527		ttm_bo_assign_mem(bo, new_mem);
 528		return 0;
 529	}
 530
 531	if (old_mem->mem_type == AMDGPU_PL_GDS ||
 532	    old_mem->mem_type == AMDGPU_PL_GWS ||
 533	    old_mem->mem_type == AMDGPU_PL_OA ||
 534	    old_mem->mem_type == AMDGPU_PL_DOORBELL ||
 535	    old_mem->mem_type == AMDGPU_PL_MMIO_REMAP ||
 536	    new_mem->mem_type == AMDGPU_PL_GDS ||
 537	    new_mem->mem_type == AMDGPU_PL_GWS ||
 538	    new_mem->mem_type == AMDGPU_PL_OA ||
 539	    new_mem->mem_type == AMDGPU_PL_DOORBELL ||
 540	    new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) {
 541		/* Nothing to save here */
 542		amdgpu_bo_move_notify(bo, evict, new_mem);
 543		ttm_bo_move_null(bo, new_mem);
 544		return 0;
 545	}
 546
 547	if (bo->type == ttm_bo_type_device &&
 548	    new_mem->mem_type == TTM_PL_VRAM &&
 549	    old_mem->mem_type != TTM_PL_VRAM) {
 550		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 551		 * accesses the BO after it's moved.
 552		 */
 553		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 554	}
 555
 556	if (adev->mman.buffer_funcs_enabled &&
 557	    ((old_mem->mem_type == TTM_PL_SYSTEM &&
 558	      new_mem->mem_type == TTM_PL_VRAM) ||
 559	     (old_mem->mem_type == TTM_PL_VRAM &&
 560	      new_mem->mem_type == TTM_PL_SYSTEM))) {
 561		hop->fpfn = 0;
 562		hop->lpfn = 0;
 563		hop->mem_type = TTM_PL_TT;
 564		hop->flags = TTM_PL_FLAG_TEMPORARY;
 565		return -EMULTIHOP;
 566	}
 567
 568	amdgpu_bo_move_notify(bo, evict, new_mem);
 569	if (adev->mman.buffer_funcs_enabled)
 570		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 571	else
 572		r = -ENODEV;
 573
 574	if (r) {
 575		/* Check that all memory is CPU accessible */
 576		if (!amdgpu_res_copyable(adev, old_mem) ||
 577		    !amdgpu_res_copyable(adev, new_mem)) {
 578			pr_err("Move buffer fallback to memcpy unavailable\n");
 579			return r;
 580		}
 581
 582		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 583		if (r)
 584			return r;
 585	}
 586
 587	/* update statistics after the move */
 588	if (evict)
 589		atomic64_inc(&adev->num_evictions);
 590	atomic64_add(bo->base.size, &adev->num_bytes_moved);
 591	return 0;
 592}
 593
 594/*
 595 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 596 *
 597 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 598 */
 599static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 600				     struct ttm_resource *mem)
 601{
 602	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 603
 604	switch (mem->mem_type) {
 605	case TTM_PL_SYSTEM:
 606		/* system memory */
 607		return 0;
 608	case TTM_PL_TT:
 609	case AMDGPU_PL_PREEMPT:
 610		break;
 611	case TTM_PL_VRAM:
 612		mem->bus.offset = mem->start << PAGE_SHIFT;
 613
 614		if (adev->mman.aper_base_kaddr &&
 615		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 616			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 617					mem->bus.offset;
 618
 619		mem->bus.offset += adev->gmc.aper_base;
 620		mem->bus.is_iomem = true;
 621		break;
 622	case AMDGPU_PL_DOORBELL:
 623		mem->bus.offset = mem->start << PAGE_SHIFT;
 624		mem->bus.offset += adev->doorbell.base;
 625		mem->bus.is_iomem = true;
 626		mem->bus.caching = ttm_uncached;
 627		break;
 628	case AMDGPU_PL_MMIO_REMAP:
 629		mem->bus.offset = mem->start << PAGE_SHIFT;
 630		mem->bus.offset += adev->rmmio_remap.bus_addr;
 631		mem->bus.is_iomem = true;
 632		mem->bus.caching = ttm_uncached;
 633		break;
 634	default:
 635		return -EINVAL;
 636	}
 637	return 0;
 638}
 639
 640static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 641					   unsigned long page_offset)
 642{
 643	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 644	struct amdgpu_res_cursor cursor;
 645
 646	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 647			 &cursor);
 648
 649	if (bo->resource->mem_type == AMDGPU_PL_DOORBELL)
 650		return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT;
 651	else if (bo->resource->mem_type == AMDGPU_PL_MMIO_REMAP)
 652		return ((uint64_t)(adev->rmmio_remap.bus_addr + cursor.start)) >> PAGE_SHIFT;
 653
 654	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 655}
 656
 657/**
 658 * amdgpu_ttm_domain_start - Returns GPU start address
 659 * @adev: amdgpu device object
 660 * @type: type of the memory
 661 *
 662 * Returns:
 663 * GPU start address of a memory domain
 664 */
 665
 666uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 667{
 668	switch (type) {
 669	case TTM_PL_TT:
 670		return adev->gmc.gart_start;
 671	case TTM_PL_VRAM:
 672		return adev->gmc.vram_start;
 673	}
 674
 675	return 0;
 676}
 677
 678/*
 679 * TTM backend functions.
 680 */
 681struct amdgpu_ttm_tt {
 682	struct ttm_tt	ttm;
 683	struct drm_gem_object	*gobj;
 684	u64			offset;
 685	uint64_t		userptr;
 686	struct task_struct	*usertask;
 687	uint32_t		userflags;
 688	bool			bound;
 689	int32_t			pool_id;
 690};
 691
 692#define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
 693
 694#ifdef CONFIG_DRM_AMDGPU_USERPTR
 695/*
 696 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 697 * memory and start HMM tracking CPU page table update
 698 *
 699 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 700 * once afterwards to stop HMM tracking. Its the caller responsibility to ensure
 701 * that range is a valid memory and it is freed too.
 702 */
 703int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
 704				 struct amdgpu_hmm_range *range)
 705{
 706	struct ttm_tt *ttm = bo->tbo.ttm;
 707	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 708	unsigned long start = gtt->userptr;
 709	struct vm_area_struct *vma;
 710	struct mm_struct *mm;
 711	bool readonly;
 712	int r = 0;
 713
 714	mm = bo->notifier.mm;
 715	if (unlikely(!mm)) {
 716		DRM_DEBUG_DRIVER("BO is not registered?\n");
 717		return -EFAULT;
 718	}
 719
 720	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 721		return -ESRCH;
 722
 723	mmap_read_lock(mm);
 724	vma = vma_lookup(mm, start);
 725	if (unlikely(!vma)) {
 726		r = -EFAULT;
 727		goto out_unlock;
 728	}
 729	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 730		vma->vm_file)) {
 731		r = -EPERM;
 732		goto out_unlock;
 733	}
 734
 735	readonly = amdgpu_ttm_tt_is_readonly(ttm);
 736	r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
 737				       readonly, NULL, range);
 738out_unlock:
 739	mmap_read_unlock(mm);
 740	if (r)
 741		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
 742
 743	mmput(mm);
 744
 745	return r;
 746}
 747
 748#endif
 749
 750/*
 751 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 752 *
 753 * Called by amdgpu_cs_list_validate(). This creates the page list
 754 * that backs user memory and will ultimately be mapped into the device
 755 * address space.
 756 */
 757void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range)
 758{
 759	unsigned long i;
 760
 761	for (i = 0; i < ttm->num_pages; ++i)
 762		ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL;
 763}
 764
 765/*
 766 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 767 *
 768 * Called by amdgpu_ttm_backend_bind()
 769 **/
 770static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 771				     struct ttm_tt *ttm)
 772{
 773	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 774	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 775	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 776	enum dma_data_direction direction = write ?
 777		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 778	int r;
 779
 780	/* Allocate an SG array and squash pages into it */
 781	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 782				      (u64)ttm->num_pages << PAGE_SHIFT,
 783				      GFP_KERNEL);
 784	if (r)
 785		goto release_sg;
 786
 787	/* Map SG to device */
 788	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 789	if (r)
 790		goto release_sg_table;
 791
 792	/* convert SG to linear array of pages and dma addresses */
 793	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 794				       ttm->num_pages);
 795
 796	return 0;
 797
 798release_sg_table:
 799	sg_free_table(ttm->sg);
 800release_sg:
 801	kfree(ttm->sg);
 802	ttm->sg = NULL;
 803	return r;
 804}
 805
 806/*
 807 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 808 */
 809static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 810					struct ttm_tt *ttm)
 811{
 812	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 813	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 814	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 815	enum dma_data_direction direction = write ?
 816		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 817
 818	/* double check that we don't free the table twice */
 819	if (!ttm->sg || !ttm->sg->sgl)
 820		return;
 821
 822	/* unmap the pages mapped to the device */
 823	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 824	sg_free_table(ttm->sg);
 825}
 826
 827/*
 828 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ...
 829 * MQDn+CtrlStackn where n is the number of XCCs per partition.
 830 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD
 831 * and uses memory type default, UC. The rest of pages_per_xcc are
 832 * Ctrl stack and modify their memory type to NC.
 833 */
 834static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
 835				struct ttm_tt *ttm, uint64_t flags)
 836{
 837	struct amdgpu_ttm_tt *gtt = (void *)ttm;
 838	uint64_t total_pages = ttm->num_pages;
 839	int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
 840	uint64_t page_idx, pages_per_xcc;
 841	int i;
 842	uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
 843
 844	pages_per_xcc = total_pages;
 845	do_div(pages_per_xcc, num_xcc);
 846
 847	for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
 848		/* MQD page: use default flags */
 849		amdgpu_gart_bind(adev,
 850				gtt->offset + (page_idx << PAGE_SHIFT),
 851				1, &gtt->ttm.dma_address[page_idx], flags);
 852		/*
 853		 * Ctrl pages - modify the memory type to NC (ctrl_flags) from
 854		 * the second page of the BO onward.
 855		 */
 856		amdgpu_gart_bind(adev,
 857				gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
 858				pages_per_xcc - 1,
 859				&gtt->ttm.dma_address[page_idx + 1],
 860				ctrl_flags);
 861	}
 862}
 863
 864static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 865				 struct ttm_buffer_object *tbo,
 866				 uint64_t flags)
 867{
 868	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 869	struct ttm_tt *ttm = tbo->ttm;
 870	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 871
 872	if (amdgpu_bo_encrypted(abo))
 873		flags |= AMDGPU_PTE_TMZ;
 874
 875	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 876		amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
 877	} else {
 878		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 879				 gtt->ttm.dma_address, flags);
 880	}
 881	gtt->bound = true;
 882}
 883
 884/*
 885 * amdgpu_ttm_backend_bind - Bind GTT memory
 886 *
 887 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 888 * This handles binding GTT memory to the device address space.
 889 */
 890static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 891				   struct ttm_tt *ttm,
 892				   struct ttm_resource *bo_mem)
 893{
 894	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 895	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 896	uint64_t flags;
 897	int r;
 898
 899	if (!bo_mem)
 900		return -EINVAL;
 901
 902	if (gtt->bound)
 903		return 0;
 904
 905	if (gtt->userptr) {
 906		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 907		if (r) {
 908			dev_err(adev->dev, "failed to pin userptr\n");
 909			return r;
 910		}
 911	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
 912		if (!ttm->sg) {
 913			struct dma_buf_attachment *attach;
 914			struct sg_table *sgt;
 915
 916			attach = gtt->gobj->import_attach;
 917			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 918			if (IS_ERR(sgt))
 919				return PTR_ERR(sgt);
 920
 921			ttm->sg = sgt;
 922		}
 923
 924		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 925					       ttm->num_pages);
 926	}
 927
 928	if (!ttm->num_pages) {
 929		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 930		     ttm->num_pages, bo_mem, ttm);
 931	}
 932
 933	if (bo_mem->mem_type != TTM_PL_TT ||
 934	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 935		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 936		return 0;
 937	}
 938
 939	/* compute PTE flags relevant to this BO memory */
 940	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 941
 942	/* bind pages into GART page tables */
 943	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 944	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 945			 gtt->ttm.dma_address, flags);
 946	gtt->bound = true;
 947	return 0;
 948}
 949
 950/*
 951 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 952 * through AGP or GART aperture.
 953 *
 954 * If bo is accessible through AGP aperture, then use AGP aperture
 955 * to access bo; otherwise allocate logical space in GART aperture
 956 * and map bo to GART aperture.
 957 */
 958int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 959{
 960	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 961	struct ttm_operation_ctx ctx = { false, false };
 962	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
 963	struct ttm_placement placement;
 964	struct ttm_place placements;
 965	struct ttm_resource *tmp;
 966	uint64_t addr, flags;
 967	int r;
 968
 969	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 970		return 0;
 971
 972	addr = amdgpu_gmc_agp_addr(bo);
 973	if (addr != AMDGPU_BO_INVALID_OFFSET)
 974		return 0;
 975
 976	/* allocate GART space */
 977	placement.num_placement = 1;
 978	placement.placement = &placements;
 979	placements.fpfn = 0;
 980	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 981	placements.mem_type = TTM_PL_TT;
 982	placements.flags = bo->resource->placement;
 983
 984	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 985	if (unlikely(r))
 986		return r;
 987
 988	/* compute PTE flags for this buffer object */
 989	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 990
 991	/* Bind pages */
 992	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 993	amdgpu_ttm_gart_bind(adev, bo, flags);
 994	amdgpu_gart_invalidate_tlb(adev);
 995	ttm_resource_free(bo, &bo->resource);
 996	ttm_bo_assign_mem(bo, tmp);
 997
 998	return 0;
 999}
1000
1001/*
1002 * amdgpu_ttm_recover_gart - Rebind GTT pages
1003 *
1004 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1005 * rebind GTT pages during a GPU reset.
1006 */
1007void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1008{
1009	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1010	uint64_t flags;
1011
1012	if (!tbo->ttm)
1013		return;
1014
1015	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1016	amdgpu_ttm_gart_bind(adev, tbo, flags);
1017}
1018
1019/*
1020 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1021 *
1022 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1023 * ttm_tt_destroy().
1024 */
1025static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1026				      struct ttm_tt *ttm)
1027{
1028	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1029	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1030
1031	/* if the pages have userptr pinning then clear that first */
1032	if (gtt->userptr) {
1033		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1034	} else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) {
1035		struct dma_buf_attachment *attach;
1036
1037		attach = gtt->gobj->import_attach;
1038		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1039		ttm->sg = NULL;
1040	}
1041
1042	if (!gtt->bound)
1043		return;
1044
1045	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1046		return;
1047
1048	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1049	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1050	gtt->bound = false;
1051}
1052
1053static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1054				       struct ttm_tt *ttm)
1055{
1056	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1057
1058	if (gtt->usertask)
1059		put_task_struct(gtt->usertask);
1060
1061	ttm_tt_fini(&gtt->ttm);
1062	kfree(gtt);
1063}
1064
1065/**
1066 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1067 *
1068 * @bo: The buffer object to create a GTT ttm_tt object around
1069 * @page_flags: Page flags to be added to the ttm_tt object
1070 *
1071 * Called by ttm_tt_create().
1072 */
1073static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1074					   uint32_t page_flags)
1075{
1076	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1077	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1078	struct amdgpu_ttm_tt *gtt;
1079	enum ttm_caching caching;
1080
1081	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1082	if (!gtt)
1083		return NULL;
1084
1085	gtt->gobj = &bo->base;
1086	if (adev->gmc.mem_partitions && abo->xcp_id >= 0)
1087		gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
1088	else
1089		gtt->pool_id = abo->xcp_id;
1090
1091	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1092		caching = ttm_write_combined;
1093	else
1094		caching = ttm_cached;
1095
1096	/* allocate space for the uninitialized page entries */
1097	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1098		kfree(gtt);
1099		return NULL;
1100	}
1101	return &gtt->ttm;
1102}
1103
1104/*
1105 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1106 *
1107 * Map the pages of a ttm_tt object to an address space visible
1108 * to the underlying device.
1109 */
1110static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1111				  struct ttm_tt *ttm,
1112				  struct ttm_operation_ctx *ctx)
1113{
1114	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1115	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1116	struct ttm_pool *pool;
1117	pgoff_t i;
1118	int ret;
1119
1120	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1121	if (gtt->userptr) {
1122		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1123		if (!ttm->sg)
1124			return -ENOMEM;
1125		return 0;
1126	}
1127
1128	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1129		return 0;
1130
1131	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1132		pool = &adev->mman.ttm_pools[gtt->pool_id];
1133	else
1134		pool = &adev->mman.bdev.pool;
1135	ret = ttm_pool_alloc(pool, ttm, ctx);
1136	if (ret)
1137		return ret;
1138
1139	for (i = 0; i < ttm->num_pages; ++i)
1140		ttm->pages[i]->mapping = bdev->dev_mapping;
1141
1142	return 0;
1143}
1144
1145/*
1146 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1147 *
1148 * Unmaps pages of a ttm_tt object from the device address space and
1149 * unpopulates the page array backing it.
1150 */
1151static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1152				     struct ttm_tt *ttm)
1153{
1154	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1155	struct amdgpu_device *adev;
1156	struct ttm_pool *pool;
1157	pgoff_t i;
1158
1159	amdgpu_ttm_backend_unbind(bdev, ttm);
1160
1161	if (gtt->userptr) {
1162		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1163		kfree(ttm->sg);
1164		ttm->sg = NULL;
1165		return;
1166	}
1167
1168	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1169		return;
1170
1171	for (i = 0; i < ttm->num_pages; ++i)
1172		ttm->pages[i]->mapping = NULL;
1173
1174	adev = amdgpu_ttm_adev(bdev);
1175
1176	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1177		pool = &adev->mman.ttm_pools[gtt->pool_id];
1178	else
1179		pool = &adev->mman.bdev.pool;
1180
1181	return ttm_pool_free(pool, ttm);
1182}
1183
1184/**
1185 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1186 * task
1187 *
1188 * @tbo: The ttm_buffer_object that contains the userptr
1189 * @user_addr:  The returned value
1190 */
1191int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1192			      uint64_t *user_addr)
1193{
1194	struct amdgpu_ttm_tt *gtt;
1195
1196	if (!tbo->ttm)
1197		return -EINVAL;
1198
1199	gtt = (void *)tbo->ttm;
1200	*user_addr = gtt->userptr;
1201	return 0;
1202}
1203
1204/**
1205 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1206 * task
1207 *
1208 * @bo: The ttm_buffer_object to bind this userptr to
1209 * @addr:  The address in the current tasks VM space to use
1210 * @flags: Requirements of userptr object.
1211 *
1212 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1213 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1214 * initialize GPU VM for a KFD process.
1215 */
1216int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1217			      uint64_t addr, uint32_t flags)
1218{
1219	struct amdgpu_ttm_tt *gtt;
1220
1221	if (!bo->ttm) {
1222		/* TODO: We want a separate TTM object type for userptrs */
1223		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1224		if (bo->ttm == NULL)
1225			return -ENOMEM;
1226	}
1227
1228	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1229	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1230
1231	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1232	gtt->userptr = addr;
1233	gtt->userflags = flags;
1234
1235	if (gtt->usertask)
1236		put_task_struct(gtt->usertask);
1237	gtt->usertask = current->group_leader;
1238	get_task_struct(gtt->usertask);
1239
1240	return 0;
1241}
1242
1243/*
1244 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1245 */
1246struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1247{
1248	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1249
1250	if (gtt == NULL)
1251		return NULL;
1252
1253	if (gtt->usertask == NULL)
1254		return NULL;
1255
1256	return gtt->usertask->mm;
1257}
1258
1259/*
1260 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1261 * address range for the current task.
1262 *
1263 */
1264bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1265				  unsigned long end, unsigned long *userptr)
1266{
1267	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1268	unsigned long size;
1269
1270	if (gtt == NULL || !gtt->userptr)
1271		return false;
1272
1273	/* Return false if no part of the ttm_tt object lies within
1274	 * the range
1275	 */
1276	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1277	if (gtt->userptr > end || gtt->userptr + size <= start)
1278		return false;
1279
1280	if (userptr)
1281		*userptr = gtt->userptr;
1282	return true;
1283}
1284
1285/*
1286 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1287 */
1288bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1289{
1290	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1291
1292	if (gtt == NULL || !gtt->userptr)
1293		return false;
1294
1295	return true;
1296}
1297
1298/*
1299 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1300 */
1301bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1302{
1303	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1304
1305	if (gtt == NULL)
1306		return false;
1307
1308	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1309}
1310
1311/**
1312 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1313 *
1314 * @ttm: The ttm_tt object to compute the flags for
1315 * @mem: The memory registry backing this ttm_tt object
1316 *
1317 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1318 */
1319uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1320{
1321	uint64_t flags = 0;
1322
1323	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1324		flags |= AMDGPU_PTE_VALID;
1325
1326	if (mem && (mem->mem_type == TTM_PL_TT ||
1327		    mem->mem_type == AMDGPU_PL_DOORBELL ||
1328		    mem->mem_type == AMDGPU_PL_PREEMPT ||
1329		    mem->mem_type == AMDGPU_PL_MMIO_REMAP)) {
1330		flags |= AMDGPU_PTE_SYSTEM;
1331
1332		if (ttm && ttm->caching == ttm_cached)
1333			flags |= AMDGPU_PTE_SNOOPED;
1334	}
1335
1336	if (mem && mem->mem_type == TTM_PL_VRAM &&
1337			mem->bus.caching == ttm_cached)
1338		flags |= AMDGPU_PTE_SNOOPED;
1339
1340	return flags;
1341}
1342
1343/**
1344 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1345 *
1346 * @adev: amdgpu_device pointer
1347 * @ttm: The ttm_tt object to compute the flags for
1348 * @mem: The memory registry backing this ttm_tt object
1349 *
1350 * Figure out the flags to use for a VM PTE (Page Table Entry).
1351 */
1352uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1353				 struct ttm_resource *mem)
1354{
1355	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1356
1357	flags |= adev->gart.gart_pte_flags;
1358	flags |= AMDGPU_PTE_READABLE;
1359
1360	if (!amdgpu_ttm_tt_is_readonly(ttm))
1361		flags |= AMDGPU_PTE_WRITEABLE;
1362
1363	return flags;
1364}
1365
1366/*
1367 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1368 * object.
1369 *
1370 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1371 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1372 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1373 * used to clean out a memory space.
1374 */
1375static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1376					    const struct ttm_place *place)
1377{
1378	struct dma_resv_iter resv_cursor;
1379	struct dma_fence *f;
1380
1381	if (!amdgpu_bo_is_amdgpu_bo(bo))
1382		return ttm_bo_eviction_valuable(bo, place);
1383
1384	/* Swapout? */
1385	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1386		return true;
1387
1388	if (bo->type == ttm_bo_type_kernel &&
1389	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1390		return false;
1391
1392	/* If bo is a KFD BO, check if the bo belongs to the current process.
1393	 * If true, then return false as any KFD process needs all its BOs to
1394	 * be resident to run successfully
1395	 */
1396	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1397				DMA_RESV_USAGE_BOOKKEEP, f) {
1398		if (amdkfd_fence_check_mm(f, current->mm) &&
1399		    !(place->flags & TTM_PL_FLAG_CONTIGUOUS))
1400			return false;
1401	}
1402
1403	/* Preemptible BOs don't own system resources managed by the
1404	 * driver (pages, VRAM, GART space). They point to resources
1405	 * owned by someone else (e.g. pageable memory in user mode
1406	 * or a DMABuf). They are used in a preemptible context so we
1407	 * can guarantee no deadlocks and good QoS in case of MMU
1408	 * notifiers or DMABuf move notifiers from the resource owner.
1409	 */
1410	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1411		return false;
1412
1413	if (bo->resource->mem_type == TTM_PL_TT &&
1414	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1415		return false;
1416
1417	return ttm_bo_eviction_valuable(bo, place);
1418}
1419
1420static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1421				      void *buf, size_t size, bool write)
1422{
1423	while (size) {
1424		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1425		uint64_t bytes = 4 - (pos & 0x3);
1426		uint32_t shift = (pos & 0x3) * 8;
1427		uint32_t mask = 0xffffffff << shift;
1428		uint32_t value = 0;
1429
1430		if (size < bytes) {
1431			mask &= 0xffffffff >> (bytes - size) * 8;
1432			bytes = size;
1433		}
1434
1435		if (mask != 0xffffffff) {
1436			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1437			if (write) {
1438				value &= ~mask;
1439				value |= (*(uint32_t *)buf << shift) & mask;
1440				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1441			} else {
1442				value = (value & mask) >> shift;
1443				memcpy(buf, &value, bytes);
1444			}
1445		} else {
1446			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1447		}
1448
1449		pos += bytes;
1450		buf += bytes;
1451		size -= bytes;
1452	}
1453}
1454
1455static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1456					unsigned long offset, void *buf,
1457					int len, int write)
1458{
1459	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1460	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1461	struct amdgpu_res_cursor src_mm;
1462	struct amdgpu_job *job;
1463	struct dma_fence *fence;
1464	uint64_t src_addr, dst_addr;
1465	unsigned int num_dw;
1466	int r, idx;
1467
1468	if (len != PAGE_SIZE)
1469		return -EINVAL;
1470
1471	if (!adev->mman.sdma_access_ptr)
1472		return -EACCES;
1473
1474	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1475		return -ENODEV;
1476
1477	if (write)
1478		memcpy(adev->mman.sdma_access_ptr, buf, len);
1479
1480	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1481	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
1482				     AMDGPU_FENCE_OWNER_UNDEFINED,
1483				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1484				     &job,
1485				     AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA);
1486	if (r)
1487		goto out;
1488
1489	mutex_lock(&adev->mman.gtt_window_lock);
1490	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1491	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1492		src_mm.start;
1493	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1494	if (write)
1495		swap(src_addr, dst_addr);
1496
1497	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1498				PAGE_SIZE, 0);
1499
1500	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1501	WARN_ON(job->ibs[0].length_dw > num_dw);
1502
1503	fence = amdgpu_job_submit(job);
1504	mutex_unlock(&adev->mman.gtt_window_lock);
1505
1506	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1507		r = -ETIMEDOUT;
1508	dma_fence_put(fence);
1509
1510	if (!(r || write))
1511		memcpy(buf, adev->mman.sdma_access_ptr, len);
1512out:
1513	drm_dev_exit(idx);
1514	return r;
1515}
1516
1517/**
1518 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1519 *
1520 * @bo:  The buffer object to read/write
1521 * @offset:  Offset into buffer object
1522 * @buf:  Secondary buffer to write/read from
1523 * @len: Length in bytes of access
1524 * @write:  true if writing
1525 *
1526 * This is used to access VRAM that backs a buffer object via MMIO
1527 * access for debugging purposes.
1528 */
1529static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1530				    unsigned long offset, void *buf, int len,
1531				    int write)
1532{
1533	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1534	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1535	struct amdgpu_res_cursor cursor;
1536	int ret = 0;
1537
1538	if (bo->resource->mem_type != TTM_PL_VRAM)
1539		return -EIO;
1540
1541	if (amdgpu_device_has_timeouts_enabled(adev) &&
1542			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1543		return len;
1544
1545	amdgpu_res_first(bo->resource, offset, len, &cursor);
1546	while (cursor.remaining) {
1547		size_t count, size = cursor.size;
1548		loff_t pos = cursor.start;
1549
1550		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1551		size -= count;
1552		if (size) {
1553			/* using MM to access rest vram and handle un-aligned address */
1554			pos += count;
1555			buf += count;
1556			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1557		}
1558
1559		ret += cursor.size;
1560		buf += cursor.size;
1561		amdgpu_res_next(&cursor, cursor.size);
1562	}
1563
1564	return ret;
1565}
1566
1567static void
1568amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1569{
1570	amdgpu_bo_move_notify(bo, false, NULL);
1571}
1572
1573static struct ttm_device_funcs amdgpu_bo_driver = {
1574	.ttm_tt_create = &amdgpu_ttm_tt_create,
1575	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1576	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1577	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1578	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1579	.evict_flags = &amdgpu_evict_flags,
1580	.move = &amdgpu_bo_move,
1581	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1582	.release_notify = &amdgpu_bo_release_notify,
1583	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1584	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1585	.access_memory = &amdgpu_ttm_access_memory,
1586};
1587
1588/*
1589 * Firmware Reservation functions
1590 */
1591/**
1592 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1593 *
1594 * @adev: amdgpu_device pointer
1595 *
1596 * free fw reserved vram if it has been reserved.
1597 */
1598static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1599{
1600	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1601		NULL, &adev->mman.fw_vram_usage_va);
1602}
1603
1604/*
1605 * Driver Reservation functions
1606 */
1607/**
1608 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1609 *
1610 * @adev: amdgpu_device pointer
1611 *
1612 * free drv reserved vram if it has been reserved.
1613 */
1614static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1615{
1616	amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1617						  NULL,
1618						  &adev->mman.drv_vram_usage_va);
1619}
1620
1621/**
1622 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1623 *
1624 * @adev: amdgpu_device pointer
1625 *
1626 * create bo vram reservation from fw.
1627 */
1628static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1629{
1630	uint64_t vram_size = adev->gmc.visible_vram_size;
1631
1632	adev->mman.fw_vram_usage_va = NULL;
1633	adev->mman.fw_vram_usage_reserved_bo = NULL;
1634
1635	if (adev->mman.fw_vram_usage_size == 0 ||
1636	    adev->mman.fw_vram_usage_size > vram_size)
1637		return 0;
1638
1639	return amdgpu_bo_create_kernel_at(adev,
1640					  adev->mman.fw_vram_usage_start_offset,
1641					  adev->mman.fw_vram_usage_size,
1642					  &adev->mman.fw_vram_usage_reserved_bo,
1643					  &adev->mman.fw_vram_usage_va);
1644}
1645
1646/**
1647 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1648 *
1649 * @adev: amdgpu_device pointer
1650 *
1651 * create bo vram reservation from drv.
1652 */
1653static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1654{
1655	u64 vram_size = adev->gmc.visible_vram_size;
1656
1657	adev->mman.drv_vram_usage_va = NULL;
1658	adev->mman.drv_vram_usage_reserved_bo = NULL;
1659
1660	if (adev->mman.drv_vram_usage_size == 0 ||
1661	    adev->mman.drv_vram_usage_size > vram_size)
1662		return 0;
1663
1664	return amdgpu_bo_create_kernel_at(adev,
1665					  adev->mman.drv_vram_usage_start_offset,
1666					  adev->mman.drv_vram_usage_size,
1667					  &adev->mman.drv_vram_usage_reserved_bo,
1668					  &adev->mman.drv_vram_usage_va);
1669}
1670
1671/*
1672 * Memoy training reservation functions
1673 */
1674
1675/**
1676 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1677 *
1678 * @adev: amdgpu_device pointer
1679 *
1680 * free memory training reserved vram if it has been reserved.
1681 */
1682static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1683{
1684	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1685
1686	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1687	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1688	ctx->c2p_bo = NULL;
1689
1690	return 0;
1691}
1692
1693static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev,
1694						uint32_t reserve_size)
1695{
1696	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1697
1698	memset(ctx, 0, sizeof(*ctx));
1699
1700	ctx->c2p_train_data_offset =
1701		ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M);
1702	ctx->p2c_train_data_offset =
1703		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1704	ctx->train_data_size =
1705		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1706
1707	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1708			ctx->train_data_size,
1709			ctx->p2c_train_data_offset,
1710			ctx->c2p_train_data_offset);
1711}
1712
1713/*
1714 * reserve TMR memory at the top of VRAM which holds
1715 * IP Discovery data and is protected by PSP.
1716 */
1717static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1718{
1719	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1720	bool mem_train_support = false;
1721	uint32_t reserve_size = 0;
1722	int ret;
1723
1724	if (adev->bios && !amdgpu_sriov_vf(adev)) {
1725		if (amdgpu_atomfirmware_mem_training_supported(adev))
1726			mem_train_support = true;
1727		else
1728			DRM_DEBUG("memory training does not support!\n");
1729	}
1730
1731	/*
1732	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1733	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1734	 *
1735	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1736	 * discovery data and G6 memory training data respectively
1737	 */
1738	if (adev->bios)
1739		reserve_size =
1740			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1741
1742	if (!adev->bios &&
1743	    (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1744	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
1745	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)))
1746		reserve_size = max(reserve_size, (uint32_t)280 << 20);
1747	else if (!reserve_size)
1748		reserve_size = DISCOVERY_TMR_OFFSET;
1749
1750	if (mem_train_support) {
1751		/* reserve vram for mem train according to TMR location */
1752		amdgpu_ttm_training_data_block_init(adev, reserve_size);
1753		ret = amdgpu_bo_create_kernel_at(adev,
1754						 ctx->c2p_train_data_offset,
1755						 ctx->train_data_size,
1756						 &ctx->c2p_bo,
1757						 NULL);
1758		if (ret) {
1759			dev_err(adev->dev, "alloc c2p_bo failed(%d)!\n", ret);
1760			amdgpu_ttm_training_reserve_vram_fini(adev);
1761			return ret;
1762		}
1763		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1764	}
1765
1766	ret = amdgpu_bo_create_kernel_at(
1767		adev, adev->gmc.real_vram_size - reserve_size, reserve_size,
1768		&adev->mman.fw_reserved_memory, NULL);
1769	if (ret) {
1770		dev_err(adev->dev, "alloc tmr failed(%d)!\n", ret);
1771		amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
1772				      NULL);
1773		return ret;
1774	}
1775
1776	return 0;
1777}
1778
1779static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
1780{
1781	int i;
1782
1783	if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
1784		return 0;
1785
1786	adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
1787				       sizeof(*adev->mman.ttm_pools),
1788				       GFP_KERNEL);
1789	if (!adev->mman.ttm_pools)
1790		return -ENOMEM;
1791
1792	for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
1793		ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
1794			      adev->gmc.mem_partitions[i].numa.node,
1795			      TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));
1796	}
1797	return 0;
1798}
1799
1800static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
1801{
1802	int i;
1803
1804	if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
1805		return;
1806
1807	for (i = 0; i < adev->gmc.num_mem_partitions; i++)
1808		ttm_pool_fini(&adev->mman.ttm_pools[i]);
1809
1810	kfree(adev->mman.ttm_pools);
1811	adev->mman.ttm_pools = NULL;
1812}
1813
1814/**
1815 * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton MMIO_REMAP BO
1816 * @adev: amdgpu device
1817 *
1818 * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the
1819 * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host
1820 * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular
1821 * GEM object (amdgpu_bo_create).
1822 *
1823 * Return:
1824 *  * 0 on success or intentional skip (feature not present/unsupported)
1825 *  * negative errno on allocation failure
1826 */
1827static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev)
1828{
1829	struct ttm_operation_ctx ctx = { false, false };
1830	struct ttm_placement placement;
1831	struct ttm_buffer_object *tbo;
1832	struct ttm_place placements;
1833	struct amdgpu_bo_param bp;
1834	struct ttm_resource *tmp;
1835	int r;
1836
1837	/* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */
1838	if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE)
1839		return 0;
1840
1841	/*
1842	 * Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP.
1843	 * The initial TTM resource assigned by amdgpu_bo_create() is
1844	 * replaced below with a fixed MMIO_REMAP placement.
1845	 */
1846	memset(&bp, 0, sizeof(bp));
1847	bp.type        = ttm_bo_type_device;
1848	bp.size        = AMDGPU_GPU_PAGE_SIZE;
1849	bp.byte_align  = AMDGPU_GPU_PAGE_SIZE;
1850	bp.domain      = 0;
1851	bp.flags       = 0;
1852	bp.resv        = NULL;
1853	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
1854	r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo);
1855	if (r)
1856		return r;
1857
1858	r = amdgpu_bo_reserve(adev->rmmio_remap.bo, true);
1859	if (r)
1860		goto err_unref;
1861
1862	tbo = &adev->rmmio_remap.bo->tbo;
1863
1864	/*
1865	 * MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP).
1866	 */
1867	placement.num_placement = 1;
1868	placement.placement = &placements;
1869	placements.fpfn = 0;
1870	placements.lpfn = 0;
1871	placements.mem_type = AMDGPU_PL_MMIO_REMAP;
1872	placements.flags = 0;
1873	/* Force the BO into the fixed MMIO_REMAP placement */
1874	r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx);
1875	if (unlikely(r))
1876		goto err_unlock;
1877
1878	ttm_resource_free(tbo, &tbo->resource);
1879	ttm_bo_assign_mem(tbo, tmp);
1880	ttm_bo_pin(tbo);
1881
1882	amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1883	return 0;
1884
1885err_unlock:
1886	amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1887
1888err_unref:
1889	amdgpu_bo_unref(&adev->rmmio_remap.bo);
1890	adev->rmmio_remap.bo = NULL;
1891	return r;
1892}
1893
1894/**
1895 * amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO
1896 * @adev: amdgpu device
1897 *
1898 * Frees the kernel-owned MMIO_REMAP BO if it was allocated by
1899 * amdgpu_ttm_mmio_remap_bo_init().
1900 */
1901static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev)
1902{
1903	if (!adev->rmmio_remap.bo)
1904		return;
1905
1906	if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) {
1907		ttm_bo_unpin(&adev->rmmio_remap.bo->tbo);
1908		amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1909	}
1910
1911    /*
1912     * At this point we rely on normal DRM teardown ordering:
1913     * no new user ioctls can access the global MMIO_REMAP BO
1914     * once TTM teardown begins.
1915     */
1916	amdgpu_bo_unref(&adev->rmmio_remap.bo);
1917	adev->rmmio_remap.bo = NULL;
1918}
1919
1920/*
1921 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1922 * gtt/vram related fields.
1923 *
1924 * This initializes all of the memory space pools that the TTM layer
1925 * will need such as the GTT space (system memory mapped to the device),
1926 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1927 * can be mapped per VMID.
1928 */
1929int amdgpu_ttm_init(struct amdgpu_device *adev)
1930{
1931	uint64_t gtt_size;
1932	int r;
1933
1934	mutex_init(&adev->mman.gtt_window_lock);
1935
1936	dma_set_max_seg_size(adev->dev, UINT_MAX);
1937	/* No others user of address space so set it to 0 */
1938	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1939			       adev_to_drm(adev)->anon_inode->i_mapping,
1940			       adev_to_drm(adev)->vma_offset_manager,
1941			       (adev->need_swiotlb ?
1942				TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) |
1943			       (dma_addressing_limited(adev->dev) ?
1944				TTM_ALLOCATION_POOL_USE_DMA32 : 0) |
1945			       TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));
1946	if (r) {
1947		dev_err(adev->dev,
1948			"failed initializing buffer object driver(%d).\n", r);
1949		return r;
1950	}
1951
1952	r = amdgpu_ttm_pools_init(adev);
1953	if (r) {
1954		dev_err(adev->dev, "failed to init ttm pools(%d).\n", r);
1955		return r;
1956	}
1957	adev->mman.initialized = true;
1958
1959	if (!adev->gmc.is_app_apu) {
1960		/* Initialize VRAM pool with all of VRAM divided into pages */
1961		r = amdgpu_vram_mgr_init(adev);
1962		if (r) {
1963			dev_err(adev->dev, "Failed initializing VRAM heap.\n");
1964			return r;
1965		}
1966	}
1967
1968	/* Change the size here instead of the init above so only lpfn is affected */
1969	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1970#ifdef CONFIG_64BIT
1971#ifdef CONFIG_X86
1972	if (adev->gmc.xgmi.connected_to_cpu)
1973		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1974				adev->gmc.visible_vram_size);
1975
1976	else if (adev->gmc.is_app_apu)
1977		DRM_DEBUG_DRIVER(
1978			"No need to ioremap when real vram size is 0\n");
1979	else
1980#endif
1981		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1982				adev->gmc.visible_vram_size);
1983#endif
1984
1985	/*
1986	 *The reserved vram for firmware must be pinned to the specified
1987	 *place on the VRAM, so reserve it early.
1988	 */
1989	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1990	if (r)
1991		return r;
1992
1993	/*
1994	 * The reserved VRAM for the driver must be pinned to a specific
1995	 * location in VRAM, so reserve it early.
1996	 */
1997	r = amdgpu_ttm_drv_reserve_vram_init(adev);
1998	if (r)
1999		return r;
2000
2001	/*
2002	 * only NAVI10 and later ASICs support IP discovery.
2003	 * If IP discovery is enabled, a block of memory should be
2004	 * reserved for it.
2005	 */
2006	if (adev->discovery.reserve_tmr) {
2007		r = amdgpu_ttm_reserve_tmr(adev);
2008		if (r)
2009			return r;
2010	}
2011
2012	/* allocate memory as required for VGA
2013	 * This is used for VGA emulation and pre-OS scanout buffers to
2014	 * avoid display artifacts while transitioning between pre-OS
2015	 * and driver.
2016	 */
2017	if (!adev->gmc.is_app_apu) {
2018		r = amdgpu_bo_create_kernel_at(adev, 0,
2019					       adev->mman.stolen_vga_size,
2020					       &adev->mman.stolen_vga_memory,
2021					       NULL);
2022		if (r)
2023			return r;
2024
2025		r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
2026					       adev->mman.stolen_extended_size,
2027					       &adev->mman.stolen_extended_memory,
2028					       NULL);
2029
2030		if (r)
2031			return r;
2032
2033		r = amdgpu_bo_create_kernel_at(adev,
2034					       adev->mman.stolen_reserved_offset,
2035					       adev->mman.stolen_reserved_size,
2036					       &adev->mman.stolen_reserved_memory,
2037					       NULL);
2038		if (r)
2039			return r;
2040	} else {
2041		DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");
2042	}
2043
2044	dev_info(adev->dev, "amdgpu: %uM of VRAM memory ready\n",
2045		 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024)));
2046
2047	/* Compute GTT size, either based on TTM limit
2048	 * or whatever the user passed on module init.
2049	 */
2050	gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT;
2051	if (amdgpu_gtt_size != -1) {
2052		uint64_t configured_size = (uint64_t)amdgpu_gtt_size << 20;
2053
2054		drm_warn(&adev->ddev,
2055			"Configuring gttsize via module parameter is deprecated, please use ttm.pages_limit\n");
2056		if (gtt_size != configured_size)
2057			drm_warn(&adev->ddev,
2058				"GTT size has been set as %llu but TTM size has been set as %llu, this is unusual\n",
2059				configured_size, gtt_size);
2060
2061		gtt_size = configured_size;
2062	}
2063
2064	/* Initialize GTT memory pool */
2065	r = amdgpu_gtt_mgr_init(adev, gtt_size);
2066	if (r) {
2067		dev_err(adev->dev, "Failed initializing GTT heap.\n");
2068		return r;
2069	}
2070	dev_info(adev->dev, "amdgpu: %uM of GTT memory ready.\n",
2071		 (unsigned int)(gtt_size / (1024 * 1024)));
2072
2073	if (adev->flags & AMD_IS_APU) {
2074		if (adev->gmc.real_vram_size < gtt_size)
2075			adev->apu_prefer_gtt = true;
2076	}
2077
2078	/* Initialize doorbell pool on PCI BAR */
2079	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE);
2080	if (r) {
2081		dev_err(adev->dev, "Failed initializing doorbell heap.\n");
2082		return r;
2083	}
2084
2085	/* Create a boorbell page for kernel usages */
2086	r = amdgpu_doorbell_create_kernel_doorbells(adev);
2087	if (r) {
2088		dev_err(adev->dev, "Failed to initialize kernel doorbells.\n");
2089		return r;
2090	}
2091
2092	/* Initialize MMIO-remap pool (single page 4K) */
2093	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_MMIO_REMAP, 1);
2094	if (r) {
2095		dev_err(adev->dev, "Failed initializing MMIO-remap heap.\n");
2096		return r;
2097	}
2098
2099	/* Allocate the singleton MMIO_REMAP BO if supported */
2100	r = amdgpu_ttm_alloc_mmio_remap_bo(adev);
2101	if (r)
2102		return r;
2103
2104	/* Initialize preemptible memory pool */
2105	r = amdgpu_preempt_mgr_init(adev);
2106	if (r) {
2107		dev_err(adev->dev, "Failed initializing PREEMPT heap.\n");
2108		return r;
2109	}
2110
2111	/* Initialize various on-chip memory pools */
2112	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2113	if (r) {
2114		dev_err(adev->dev, "Failed initializing GDS heap.\n");
2115		return r;
2116	}
2117
2118	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2119	if (r) {
2120		dev_err(adev->dev, "Failed initializing gws heap.\n");
2121		return r;
2122	}
2123
2124	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2125	if (r) {
2126		dev_err(adev->dev, "Failed initializing oa heap.\n");
2127		return r;
2128	}
2129	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
2130				AMDGPU_GEM_DOMAIN_GTT,
2131				&adev->mman.sdma_access_bo, NULL,
2132				&adev->mman.sdma_access_ptr))
2133		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
2134
2135	return 0;
2136}
2137
2138/*
2139 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2140 */
2141void amdgpu_ttm_fini(struct amdgpu_device *adev)
2142{
2143	int idx;
2144
2145	if (!adev->mman.initialized)
2146		return;
2147
2148	amdgpu_ttm_pools_fini(adev);
2149
2150	amdgpu_ttm_training_reserve_vram_fini(adev);
2151	/* return the stolen vga memory back to VRAM */
2152	if (!adev->gmc.is_app_apu) {
2153		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2154		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2155		/* return the FW reserved memory back to VRAM */
2156		amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
2157				      NULL);
2158		amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory_extend, NULL,
2159				      NULL);
2160		if (adev->mman.stolen_reserved_size)
2161			amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
2162					      NULL, NULL);
2163	}
2164	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
2165					&adev->mman.sdma_access_ptr);
2166
2167	amdgpu_ttm_free_mmio_remap_bo(adev);
2168	amdgpu_ttm_fw_reserve_vram_fini(adev);
2169	amdgpu_ttm_drv_reserve_vram_fini(adev);
2170
2171	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
2172
2173		if (adev->mman.aper_base_kaddr)
2174			iounmap(adev->mman.aper_base_kaddr);
2175		adev->mman.aper_base_kaddr = NULL;
2176
2177		drm_dev_exit(idx);
2178	}
2179
2180	if (!adev->gmc.is_app_apu)
2181		amdgpu_vram_mgr_fini(adev);
2182	amdgpu_gtt_mgr_fini(adev);
2183	amdgpu_preempt_mgr_fini(adev);
2184	amdgpu_doorbell_fini(adev);
2185
2186	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2187	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2188	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2189	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL);
2190	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP);
2191	ttm_device_fini(&adev->mman.bdev);
2192	adev->mman.initialized = false;
2193	dev_info(adev->dev, "amdgpu: ttm finalized\n");
2194}
2195
2196/**
2197 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2198 *
2199 * @adev: amdgpu_device pointer
2200 * @enable: true when we can use buffer functions.
2201 *
2202 * Enable/disable use of buffer functions during suspend/resume. This should
2203 * only be called at bootup or when userspace isn't running.
2204 */
2205void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2206{
2207	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2208	uint64_t size;
2209	int r;
2210
2211	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2212	    adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
2213		return;
2214
2215	if (enable) {
2216		struct amdgpu_ring *ring;
2217		struct drm_gpu_scheduler *sched;
2218
2219		ring = adev->mman.buffer_funcs_ring;
2220		sched = &ring->sched;
2221		r = drm_sched_entity_init(&adev->mman.high_pr,
2222					  DRM_SCHED_PRIORITY_KERNEL, &sched,
2223					  1, NULL);
2224		if (r) {
2225			dev_err(adev->dev,
2226				"Failed setting up TTM BO move entity (%d)\n",
2227				r);
2228			return;
2229		}
2230
2231		r = drm_sched_entity_init(&adev->mman.low_pr,
2232					  DRM_SCHED_PRIORITY_NORMAL, &sched,
2233					  1, NULL);
2234		if (r) {
2235			dev_err(adev->dev,
2236				"Failed setting up TTM BO move entity (%d)\n",
2237				r);
2238			goto error_free_entity;
2239		}
2240	} else {
2241		drm_sched_entity_destroy(&adev->mman.high_pr);
2242		drm_sched_entity_destroy(&adev->mman.low_pr);
2243		/* Drop all the old fences since re-creating the scheduler entities
2244		 * will allocate new contexts.
2245		 */
2246		ttm_resource_manager_cleanup(man);
2247	}
2248
2249	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
2250	if (enable)
2251		size = adev->gmc.real_vram_size;
2252	else
2253		size = adev->gmc.visible_vram_size;
2254	man->size = size;
2255	adev->mman.buffer_funcs_enabled = enable;
2256
2257	return;
2258
2259error_free_entity:
2260	drm_sched_entity_destroy(&adev->mman.high_pr);
2261}
2262
2263static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
2264				  bool direct_submit,
2265				  unsigned int num_dw,
2266				  struct dma_resv *resv,
2267				  bool vm_needs_flush,
2268				  struct amdgpu_job **job,
2269				  bool delayed, u64 k_job_id)
2270{
2271	enum amdgpu_ib_pool_type pool = direct_submit ?
2272		AMDGPU_IB_POOL_DIRECT :
2273		AMDGPU_IB_POOL_DELAYED;
2274	int r;
2275	struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2276						    &adev->mman.high_pr;
2277	r = amdgpu_job_alloc_with_ib(adev, entity,
2278				     AMDGPU_FENCE_OWNER_UNDEFINED,
2279				     num_dw * 4, pool, job, k_job_id);
2280	if (r)
2281		return r;
2282
2283	if (vm_needs_flush) {
2284		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2285							adev->gmc.pdb0_bo :
2286							adev->gart.bo);
2287		(*job)->vm_needs_flush = true;
2288	}
2289	if (!resv)
2290		return 0;
2291
2292	return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2293						   DMA_RESV_USAGE_BOOKKEEP);
2294}
2295
2296int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2297		       uint64_t dst_offset, uint32_t byte_count,
2298		       struct dma_resv *resv,
2299		       struct dma_fence **fence, bool direct_submit,
2300		       bool vm_needs_flush, uint32_t copy_flags)
2301{
2302	struct amdgpu_device *adev = ring->adev;
2303	unsigned int num_loops, num_dw;
2304	struct amdgpu_job *job;
2305	uint32_t max_bytes;
2306	unsigned int i;
2307	int r;
2308
2309	if (!direct_submit && !ring->sched.ready) {
2310		dev_err(adev->dev,
2311			"Trying to move memory with ring turned off.\n");
2312		return -EINVAL;
2313	}
2314
2315	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2316	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2317	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2318	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2319				   resv, vm_needs_flush, &job, false,
2320				   AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
2321	if (r)
2322		return r;
2323
2324	for (i = 0; i < num_loops; i++) {
2325		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2326
2327		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2328					dst_offset, cur_size_in_bytes, copy_flags);
2329		src_offset += cur_size_in_bytes;
2330		dst_offset += cur_size_in_bytes;
2331		byte_count -= cur_size_in_bytes;
2332	}
2333
2334	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2335	WARN_ON(job->ibs[0].length_dw > num_dw);
2336	if (direct_submit)
2337		r = amdgpu_job_submit_direct(job, ring, fence);
2338	else
2339		*fence = amdgpu_job_submit(job);
2340	if (r)
2341		goto error_free;
2342
2343	return r;
2344
2345error_free:
2346	amdgpu_job_free(job);
2347	dev_err(adev->dev, "Error scheduling IBs (%d)\n", r);
2348	return r;
2349}
2350
2351static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2352			       uint64_t dst_addr, uint32_t byte_count,
2353			       struct dma_resv *resv,
2354			       struct dma_fence **fence,
2355			       bool vm_needs_flush, bool delayed,
2356			       u64 k_job_id)
2357{
2358	struct amdgpu_device *adev = ring->adev;
2359	unsigned int num_loops, num_dw;
2360	struct amdgpu_job *job;
2361	uint32_t max_bytes;
2362	unsigned int i;
2363	int r;
2364
2365	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2366	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2367	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2368	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2369				   &job, delayed, k_job_id);
2370	if (r)
2371		return r;
2372
2373	for (i = 0; i < num_loops; i++) {
2374		uint32_t cur_size = min(byte_count, max_bytes);
2375
2376		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2377					cur_size);
2378
2379		dst_addr += cur_size;
2380		byte_count -= cur_size;
2381	}
2382
2383	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2384	WARN_ON(job->ibs[0].length_dw > num_dw);
2385	*fence = amdgpu_job_submit(job);
2386	return 0;
2387}
2388
2389/**
2390 * amdgpu_ttm_clear_buffer - clear memory buffers
2391 * @bo: amdgpu buffer object
2392 * @resv: reservation object
2393 * @fence: dma_fence associated with the operation
2394 *
2395 * Clear the memory buffer resource.
2396 *
2397 * Returns:
2398 * 0 for success or a negative error code on failure.
2399 */
2400int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
2401			    struct dma_resv *resv,
2402			    struct dma_fence **fence)
2403{
2404	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2405	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2406	struct amdgpu_res_cursor cursor;
2407	u64 addr;
2408	int r = 0;
2409
2410	if (!adev->mman.buffer_funcs_enabled)
2411		return -EINVAL;
2412
2413	if (!fence)
2414		return -EINVAL;
2415
2416	*fence = dma_fence_get_stub();
2417
2418	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
2419
2420	mutex_lock(&adev->mman.gtt_window_lock);
2421	while (cursor.remaining) {
2422		struct dma_fence *next = NULL;
2423		u64 size;
2424
2425		if (amdgpu_res_cleared(&cursor)) {
2426			amdgpu_res_next(&cursor, cursor.size);
2427			continue;
2428		}
2429
2430		/* Never clear more than 256MiB at once to avoid timeouts */
2431		size = min(cursor.size, 256ULL << 20);
2432
2433		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &cursor,
2434					  1, ring, false, &size, &addr);
2435		if (r)
2436			goto err;
2437
2438		r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,
2439					&next, true, true,
2440					AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
2441		if (r)
2442			goto err;
2443
2444		dma_fence_put(*fence);
2445		*fence = next;
2446
2447		amdgpu_res_next(&cursor, size);
2448	}
2449err:
2450	mutex_unlock(&adev->mman.gtt_window_lock);
2451
2452	return r;
2453}
2454
2455int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2456			uint32_t src_data,
2457			struct dma_resv *resv,
2458			struct dma_fence **f,
2459			bool delayed,
2460			u64 k_job_id)
2461{
2462	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2463	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2464	struct dma_fence *fence = NULL;
2465	struct amdgpu_res_cursor dst;
2466	int r;
2467
2468	if (!adev->mman.buffer_funcs_enabled) {
2469		dev_err(adev->dev,
2470			"Trying to clear memory with ring turned off.\n");
2471		return -EINVAL;
2472	}
2473
2474	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2475
2476	mutex_lock(&adev->mman.gtt_window_lock);
2477	while (dst.remaining) {
2478		struct dma_fence *next;
2479		uint64_t cur_size, to;
2480
2481		/* Never fill more than 256MiB at once to avoid timeouts */
2482		cur_size = min(dst.size, 256ULL << 20);
2483
2484		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2485					  1, ring, false, &cur_size, &to);
2486		if (r)
2487			goto error;
2488
2489		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2490					&next, true, delayed, k_job_id);
2491		if (r)
2492			goto error;
2493
2494		dma_fence_put(fence);
2495		fence = next;
2496
2497		amdgpu_res_next(&dst, cur_size);
2498	}
2499error:
2500	mutex_unlock(&adev->mman.gtt_window_lock);
2501	if (f)
2502		*f = dma_fence_get(fence);
2503	dma_fence_put(fence);
2504	return r;
2505}
2506
2507/**
2508 * amdgpu_ttm_evict_resources - evict memory buffers
2509 * @adev: amdgpu device object
2510 * @mem_type: evicted BO's memory type
2511 *
2512 * Evicts all @mem_type buffers on the lru list of the memory type.
2513 *
2514 * Returns:
2515 * 0 for success or a negative error code on failure.
2516 */
2517int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2518{
2519	struct ttm_resource_manager *man;
2520
2521	switch (mem_type) {
2522	case TTM_PL_VRAM:
2523	case TTM_PL_TT:
2524	case AMDGPU_PL_GWS:
2525	case AMDGPU_PL_GDS:
2526	case AMDGPU_PL_OA:
2527		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2528		break;
2529	default:
2530		dev_err(adev->dev, "Trying to evict invalid memory type\n");
2531		return -EINVAL;
2532	}
2533
2534	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2535}
2536
2537#if defined(CONFIG_DEBUG_FS)
2538
2539static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2540{
2541	struct amdgpu_device *adev = m->private;
2542
2543	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2544}
2545
2546DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2547
2548/*
2549 * amdgpu_ttm_vram_read - Linear read access to VRAM
2550 *
2551 * Accesses VRAM via MMIO for debugging purposes.
2552 */
2553static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2554				    size_t size, loff_t *pos)
2555{
2556	struct amdgpu_device *adev = file_inode(f)->i_private;
2557	ssize_t result = 0;
2558
2559	if (size & 0x3 || *pos & 0x3)
2560		return -EINVAL;
2561
2562	if (*pos >= adev->gmc.mc_vram_size)
2563		return -ENXIO;
2564
2565	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2566	while (size) {
2567		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2568		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2569
2570		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2571		if (copy_to_user(buf, value, bytes))
2572			return -EFAULT;
2573
2574		result += bytes;
2575		buf += bytes;
2576		*pos += bytes;
2577		size -= bytes;
2578	}
2579
2580	return result;
2581}
2582
2583/*
2584 * amdgpu_ttm_vram_write - Linear write access to VRAM
2585 *
2586 * Accesses VRAM via MMIO for debugging purposes.
2587 */
2588static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2589				    size_t size, loff_t *pos)
2590{
2591	struct amdgpu_device *adev = file_inode(f)->i_private;
2592	ssize_t result = 0;
2593	int r;
2594
2595	if (size & 0x3 || *pos & 0x3)
2596		return -EINVAL;
2597
2598	if (*pos >= adev->gmc.mc_vram_size)
2599		return -ENXIO;
2600
2601	while (size) {
2602		uint32_t value;
2603
2604		if (*pos >= adev->gmc.mc_vram_size)
2605			return result;
2606
2607		r = get_user(value, (uint32_t *)buf);
2608		if (r)
2609			return r;
2610
2611		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2612
2613		result += 4;
2614		buf += 4;
2615		*pos += 4;
2616		size -= 4;
2617	}
2618
2619	return result;
2620}
2621
2622static const struct file_operations amdgpu_ttm_vram_fops = {
2623	.owner = THIS_MODULE,
2624	.read = amdgpu_ttm_vram_read,
2625	.write = amdgpu_ttm_vram_write,
2626	.llseek = default_llseek,
2627};
2628
2629/*
2630 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2631 *
2632 * This function is used to read memory that has been mapped to the
2633 * GPU and the known addresses are not physical addresses but instead
2634 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2635 */
2636static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2637				 size_t size, loff_t *pos)
2638{
2639	struct amdgpu_device *adev = file_inode(f)->i_private;
2640	struct iommu_domain *dom;
2641	ssize_t result = 0;
2642	int r;
2643
2644	/* retrieve the IOMMU domain if any for this device */
2645	dom = iommu_get_domain_for_dev(adev->dev);
2646
2647	while (size) {
2648		phys_addr_t addr = *pos & PAGE_MASK;
2649		loff_t off = *pos & ~PAGE_MASK;
2650		size_t bytes = PAGE_SIZE - off;
2651		unsigned long pfn;
2652		struct page *p;
2653		void *ptr;
2654
2655		bytes = min(bytes, size);
2656
2657		/* Translate the bus address to a physical address.  If
2658		 * the domain is NULL it means there is no IOMMU active
2659		 * and the address translation is the identity
2660		 */
2661		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2662
2663		pfn = addr >> PAGE_SHIFT;
2664		if (!pfn_valid(pfn))
2665			return -EPERM;
2666
2667		p = pfn_to_page(pfn);
2668		if (p->mapping != adev->mman.bdev.dev_mapping)
2669			return -EPERM;
2670
2671		ptr = kmap_local_page(p);
2672		r = copy_to_user(buf, ptr + off, bytes);
2673		kunmap_local(ptr);
2674		if (r)
2675			return -EFAULT;
2676
2677		size -= bytes;
2678		*pos += bytes;
2679		result += bytes;
2680	}
2681
2682	return result;
2683}
2684
2685/*
2686 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2687 *
2688 * This function is used to write memory that has been mapped to the
2689 * GPU and the known addresses are not physical addresses but instead
2690 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2691 */
2692static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2693				 size_t size, loff_t *pos)
2694{
2695	struct amdgpu_device *adev = file_inode(f)->i_private;
2696	struct iommu_domain *dom;
2697	ssize_t result = 0;
2698	int r;
2699
2700	dom = iommu_get_domain_for_dev(adev->dev);
2701
2702	while (size) {
2703		phys_addr_t addr = *pos & PAGE_MASK;
2704		loff_t off = *pos & ~PAGE_MASK;
2705		size_t bytes = PAGE_SIZE - off;
2706		unsigned long pfn;
2707		struct page *p;
2708		void *ptr;
2709
2710		bytes = min(bytes, size);
2711
2712		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2713
2714		pfn = addr >> PAGE_SHIFT;
2715		if (!pfn_valid(pfn))
2716			return -EPERM;
2717
2718		p = pfn_to_page(pfn);
2719		if (p->mapping != adev->mman.bdev.dev_mapping)
2720			return -EPERM;
2721
2722		ptr = kmap_local_page(p);
2723		r = copy_from_user(ptr + off, buf, bytes);
2724		kunmap_local(ptr);
2725		if (r)
2726			return -EFAULT;
2727
2728		size -= bytes;
2729		*pos += bytes;
2730		result += bytes;
2731	}
2732
2733	return result;
2734}
2735
2736static const struct file_operations amdgpu_ttm_iomem_fops = {
2737	.owner = THIS_MODULE,
2738	.read = amdgpu_iomem_read,
2739	.write = amdgpu_iomem_write,
2740	.llseek = default_llseek
2741};
2742
2743#endif
2744
2745void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2746{
2747#if defined(CONFIG_DEBUG_FS)
2748	struct drm_minor *minor = adev_to_drm(adev)->primary;
2749	struct dentry *root = minor->debugfs_root;
2750
2751	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2752				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2753	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2754			    &amdgpu_ttm_iomem_fops);
2755	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2756			    &amdgpu_ttm_page_pool_fops);
2757	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2758							     TTM_PL_VRAM),
2759					    root, "amdgpu_vram_mm");
2760	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2761							     TTM_PL_TT),
2762					    root, "amdgpu_gtt_mm");
2763	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2764							     AMDGPU_PL_GDS),
2765					    root, "amdgpu_gds_mm");
2766	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2767							     AMDGPU_PL_GWS),
2768					    root, "amdgpu_gws_mm");
2769	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2770							     AMDGPU_PL_OA),
2771					    root, "amdgpu_oa_mm");
2772
2773#endif
2774}