amdgpu_ring.h

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Christian König
 23 */
 24#ifndef __AMDGPU_RING_H__
 25#define __AMDGPU_RING_H__
 26
 27#include <drm/amdgpu_drm.h>
 28#include <drm/gpu_scheduler.h>
 29#include <drm/drm_print.h>
 30#include <drm/drm_suballoc.h>
 31
 32struct amdgpu_device;
 33struct amdgpu_ring;
 34struct amdgpu_ib;
 35struct amdgpu_cs_parser;
 36struct amdgpu_job;
 37struct amdgpu_vm;
 38
 39/* max number of rings */
 40#define AMDGPU_MAX_RINGS		149
 41#define AMDGPU_MAX_HWIP_RINGS		64
 42#define AMDGPU_MAX_GFX_RINGS		2
 43#define AMDGPU_MAX_SW_GFX_RINGS         2
 44#define AMDGPU_MAX_COMPUTE_RINGS	8
 45#define AMDGPU_MAX_VCE_RINGS		3
 46#define AMDGPU_MAX_UVD_ENC_RINGS	2
 47#define AMDGPU_MAX_VPE_RINGS		2
 48
 49enum amdgpu_ring_priority_level {
 50	AMDGPU_RING_PRIO_0,
 51	AMDGPU_RING_PRIO_1,
 52	AMDGPU_RING_PRIO_DEFAULT = 1,
 53	AMDGPU_RING_PRIO_2,
 54	AMDGPU_RING_PRIO_MAX
 55};
 56
 57/* some special values for the owner field */
 58#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
 59#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
 60#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)
 61
 62#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 63#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
 64#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
 65#define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
 66
 67#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
 68
 69#define AMDGPU_IB_POOL_SIZE	(1024 * 1024)
 70
 71enum amdgpu_ring_type {
 72	AMDGPU_RING_TYPE_GFX		= AMDGPU_HW_IP_GFX,
 73	AMDGPU_RING_TYPE_COMPUTE	= AMDGPU_HW_IP_COMPUTE,
 74	AMDGPU_RING_TYPE_SDMA		= AMDGPU_HW_IP_DMA,
 75	AMDGPU_RING_TYPE_UVD		= AMDGPU_HW_IP_UVD,
 76	AMDGPU_RING_TYPE_VCE		= AMDGPU_HW_IP_VCE,
 77	AMDGPU_RING_TYPE_UVD_ENC	= AMDGPU_HW_IP_UVD_ENC,
 78	AMDGPU_RING_TYPE_VCN_DEC	= AMDGPU_HW_IP_VCN_DEC,
 79	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
 80	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
 81	AMDGPU_RING_TYPE_VPE		= AMDGPU_HW_IP_VPE,
 82	AMDGPU_RING_TYPE_KIQ,
 83	AMDGPU_RING_TYPE_MES,
 84	AMDGPU_RING_TYPE_UMSCH_MM,
 85	AMDGPU_RING_TYPE_CPER,
 86	AMDGPU_RING_TYPE_MAX,
 87};
 88
 89enum amdgpu_ib_pool_type {
 90	/* Normal submissions to the top of the pipeline. */
 91	AMDGPU_IB_POOL_DELAYED,
 92	/* Immediate submissions to the bottom of the pipeline. */
 93	AMDGPU_IB_POOL_IMMEDIATE,
 94	/* Direct submission to the ring buffer during init and reset. */
 95	AMDGPU_IB_POOL_DIRECT,
 96
 97	AMDGPU_IB_POOL_MAX
 98};
 99
100struct amdgpu_ib {
101	struct drm_suballoc		*sa_bo;
102	uint32_t			length_dw;
103	uint64_t			gpu_addr;
104	uint32_t			*ptr;
105	uint32_t			flags;
106};
107
108struct amdgpu_sched {
109	u32				num_scheds;
110	struct drm_gpu_scheduler	*sched[AMDGPU_MAX_HWIP_RINGS];
111};
112
113/*
114 * Fences.
115 */
116struct amdgpu_fence_driver {
117	uint64_t			gpu_addr;
118	uint32_t			*cpu_addr;
119	/* sync_seq is protected by ring emission lock */
120	uint32_t			sync_seq;
121	atomic_t			last_seq;
122	u64				signalled_wptr;
123	bool				initialized;
124	struct amdgpu_irq_src		*irq_src;
125	unsigned			irq_type;
126	struct timer_list		fallback_timer;
127	unsigned			num_fences_mask;
128	spinlock_t			lock;
129	struct dma_fence		**fences;
130};
131
132/*
133 * Fences mark an event in the GPUs pipeline and are used
134 * for GPU/CPU synchronization.  When the fence is written,
135 * it is expected that all buffers associated with that fence
136 * are no longer in use by the associated ring on the GPU and
137 * that the relevant GPU caches have been flushed.
138 */
139
140struct amdgpu_fence {
141	struct dma_fence base;
142
143	/* RB, DMA, etc. */
144	struct amdgpu_ring		*ring;
145	ktime_t				start_timestamp;
146
147	/* wptr for the total submission for resets */
148	u64				wptr;
149	/* fence context for resets */
150	u64				context;
151	/* has this fence been reemitted */
152	unsigned int			reemitted;
153	/* wptr for the fence for the submission */
154	u64				fence_wptr_start;
155	u64				fence_wptr_end;
156};
157
158extern const struct drm_sched_backend_ops amdgpu_sched_ops;
159
160void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
161void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
162void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af);
163void amdgpu_fence_save_wptr(struct amdgpu_fence *af);
164
165int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
166int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
167				   struct amdgpu_irq_src *irq_src,
168				   unsigned irq_type);
169void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
170void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
171int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
172void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
173int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
174		      unsigned int flags);
175int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
176			      uint32_t timeout);
177bool amdgpu_fence_process(struct amdgpu_ring *ring);
178int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
179signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
180				      uint32_t wait_seq,
181				      signed long timeout);
182unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
183
184void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
185
186u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
187void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
188					 ktime_t timestamp);
189
190/*
191 * Rings.
192 */
193
194/* provided by hw blocks that expose a ring buffer for commands */
195struct amdgpu_ring_funcs {
196	/**
197	 * @type:
198	 *
199	 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER
200	 * use ring buffers. The type field just identifies which component the
201	 * ring buffer is associated with.
202	 */
203	enum amdgpu_ring_type	type;
204	uint32_t		align_mask;
205
206	/**
207	 * @nop:
208	 *
209	 * Every block in the amdgpu has no-op instructions (e.g., GFX 10
210	 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP,
211	 * etc). This field receives the specific no-op for the component
212	 * that initializes the ring.
213	 */
214	u32			nop;
215	bool			support_64bit_ptrs;
216	bool			no_user_fence;
217	bool			secure_submission_supported;
218
219	/**
220	 * @extra_bytes:
221	 *
222	 * Optional extra space in bytes that is added to the ring size
223	 * when allocating the BO that holds the contents of the ring.
224	 * This space isn't used for command submission to the ring,
225	 * but is just there to satisfy some hardware requirements or
226	 * implement workarounds. It's up to the implementation of each
227	 * specific ring to initialize this space.
228	 */
229	unsigned		extra_bytes;
230
231	/* ring read/write ptr handling */
232	u64 (*get_rptr)(struct amdgpu_ring *ring);
233	u64 (*get_wptr)(struct amdgpu_ring *ring);
234	void (*set_wptr)(struct amdgpu_ring *ring);
235	/* validating and patching of IBs */
236	int (*parse_cs)(struct amdgpu_cs_parser *p,
237			struct amdgpu_job *job,
238			struct amdgpu_ib *ib);
239	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
240				 struct amdgpu_job *job,
241				 struct amdgpu_ib *ib);
242	/* constants to calculate how many DW are needed for an emit */
243	unsigned emit_frame_size;
244	unsigned emit_ib_size;
245	/* command emit functions */
246	void (*emit_ib)(struct amdgpu_ring *ring,
247			struct amdgpu_job *job,
248			struct amdgpu_ib *ib,
249			uint32_t flags);
250	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
251			   uint64_t seq, unsigned flags);
252	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
253	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
254			      uint64_t pd_addr);
255	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
256	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
257				uint32_t gds_base, uint32_t gds_size,
258				uint32_t gws_base, uint32_t gws_size,
259				uint32_t oa_base, uint32_t oa_size);
260	/* testing functions */
261	int (*test_ring)(struct amdgpu_ring *ring);
262	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
263	/* insert NOP packets */
264	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
265	void (*insert_start)(struct amdgpu_ring *ring);
266	void (*insert_end)(struct amdgpu_ring *ring);
267	/* pad the indirect buffer to the necessary number of dw */
268	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
269	unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr);
270	/* note usage for clock and power gating */
271	void (*begin_use)(struct amdgpu_ring *ring);
272	void (*end_use)(struct amdgpu_ring *ring);
273	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
274	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
275	void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
276				u64 gds_va, bool init_shadow, int vmid);
277	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
278			  uint32_t reg_val_offs);
279	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
280	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
281			      uint32_t val, uint32_t mask);
282	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
283					uint32_t reg0, uint32_t reg1,
284					uint32_t ref, uint32_t mask);
285	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
286				bool secure);
287	/* Try to soft recover the ring to make the fence signal */
288	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
289	int (*preempt_ib)(struct amdgpu_ring *ring);
290	void (*emit_mem_sync)(struct amdgpu_ring *ring);
291	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
292	void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
293	void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
294	void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
295	int (*reset)(struct amdgpu_ring *ring, unsigned int vmid,
296		     struct amdgpu_fence *timedout_fence);
297	void (*emit_cleaner_shader)(struct amdgpu_ring *ring);
298};
299
300/**
301 * amdgpu_ring - Holds ring information
302 */
303struct amdgpu_ring {
304	struct amdgpu_device		*adev;
305	const struct amdgpu_ring_funcs	*funcs;
306	struct amdgpu_fence_driver	fence_drv;
307	struct drm_gpu_scheduler	sched;
308
309	struct amdgpu_bo	*ring_obj;
310	uint32_t		*ring;
311	/* backups for resets */
312	uint32_t		*ring_backup;
313	unsigned int		ring_backup_entries_to_copy;
314	unsigned		rptr_offs;
315	u64			rptr_gpu_addr;
316	u32			*rptr_cpu_addr;
317
318	/**
319	 * @wptr:
320	 *
321	 * This is part of the Ring buffer implementation and represents the
322	 * write pointer. The wptr determines where the host has written.
323	 */
324	u64			wptr;
325
326	/**
327	 * @wptr_old:
328	 *
329	 * Before update wptr with the new value, usually the old value is
330	 * stored in the wptr_old.
331	 */
332	u64			wptr_old;
333	unsigned		ring_size;
334
335	/**
336	 * @max_dw:
337	 *
338	 * Maximum number of DWords for ring allocation. This information is
339	 * provided at the ring initialization time, and each IP block can
340	 * specify a specific value. Check places that invoke
341	 * amdgpu_ring_init() to see the maximum size per block.
342	 */
343	unsigned		max_dw;
344
345	/**
346	 * @count_dw:
347	 *
348	 * This value starts with the maximum amount of DWords supported by the
349	 * ring. This value is updated based on the ring manipulation.
350	 */
351	int			count_dw;
352	uint64_t		gpu_addr;
353
354	/**
355	 * @ptr_mask:
356	 *
357	 * Some IPs provide support for 64-bit pointers and others for 32-bit
358	 * only; this behavior is component-specific and defined by the field
359	 * support_64bit_ptr. If the IP block supports 64-bits, the mask
360	 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask.
361	 * Notice that this field is used to keep wptr under a valid range.
362	 */
363	uint64_t		ptr_mask;
364
365	/**
366	 * @buf_mask:
367	 *
368	 * Buffer mask is a value used to keep wptr count under its
369	 * thresholding. Buffer mask initialized during the ring buffer
370	 * initialization time, and it is defined as (ring_size / 4) -1.
371	 */
372	uint32_t		buf_mask;
373	u32			idx;
374	u32			xcc_id;
375	u32			xcp_id;
376	u32			me;
377	u32			pipe;
378	u32			queue;
379	struct amdgpu_bo	*mqd_obj;
380	uint64_t                mqd_gpu_addr;
381	void                    *mqd_ptr;
382	unsigned                mqd_size;
383	uint64_t                eop_gpu_addr;
384	u32			doorbell_index;
385	bool			use_doorbell;
386	bool			use_pollmem;
387	unsigned		wptr_offs;
388	u64			wptr_gpu_addr;
389
390	/**
391	 * @wptr_cpu_addr:
392	 *
393	 * This is the CPU address pointer in the writeback slot. This is used
394	 * to commit changes to the GPU.
395	 */
396	u32			*wptr_cpu_addr;
397	unsigned		fence_offs;
398	u64			fence_gpu_addr;
399	u32			*fence_cpu_addr;
400	uint64_t		current_ctx;
401	char			name[16];
402	u32                     trail_seq;
403	unsigned		trail_fence_offs;
404	u64			trail_fence_gpu_addr;
405	u32			*trail_fence_cpu_addr;
406	unsigned		cond_exe_offs;
407	u64			cond_exe_gpu_addr;
408	u32			*cond_exe_cpu_addr;
409	unsigned int		set_q_mode_offs;
410	u32			*set_q_mode_ptr;
411	u64			set_q_mode_token;
412	unsigned		vm_hub;
413	unsigned		vm_inv_eng;
414	struct dma_fence	*vmid_wait;
415	bool			has_compute_vm_bug;
416	bool			no_scheduler;
417	bool			no_user_submission;
418	int			hw_prio;
419	unsigned 		num_hw_submission;
420	atomic_t		*sched_score;
421
422	bool            is_sw_ring;
423	unsigned int    entry_index;
424	/* store the cached rptr to restore after reset */
425	uint64_t cached_rptr;
426};
427
428#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
429#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
430#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
431#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
432#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
433#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
434#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
435#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
436#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
437#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
438#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
439#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
440#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
441#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
442#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
443#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
444#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
445#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
446#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
447#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
448#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
449#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
450#define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
451#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
452#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
453#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
454#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
455#define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))
456
457unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
458int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
459void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
460void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
461void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
462void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
463void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
464
465void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
466void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
467void amdgpu_ring_commit(struct amdgpu_ring *ring);
468void amdgpu_ring_undo(struct amdgpu_ring *ring);
469int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
470		     unsigned int max_dw, struct amdgpu_irq_src *irq_src,
471		     unsigned int irq_type, unsigned int hw_prio,
472		     atomic_t *sched_score);
473void amdgpu_ring_fini(struct amdgpu_ring *ring);
474void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
475						uint32_t reg0, uint32_t val0,
476						uint32_t reg1, uint32_t val1);
477bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
478			       struct dma_fence *fence);
479
480static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
481							bool cond_exec)
482{
483	*ring->cond_exe_cpu_addr = cond_exec;
484}
485
486static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
487{
488	memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1);
489}
490
491static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
492{
493	ring->ring[ring->wptr++ & ring->buf_mask] = v;
494	ring->wptr &= ring->ptr_mask;
495	ring->count_dw--;
496}
497
498static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
499					      void *src, int count_dw)
500{
501	unsigned occupied, chunk1, chunk2;
502
503	occupied = ring->wptr & ring->buf_mask;
504	chunk1 = ring->buf_mask + 1 - occupied;
505	chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1;
506	chunk2 = count_dw - chunk1;
507	chunk1 <<= 2;
508	chunk2 <<= 2;
509
510	if (chunk1)
511		memcpy(&ring->ring[occupied], src, chunk1);
512
513	if (chunk2) {
514		src += chunk1;
515		memcpy(ring->ring, src, chunk2);
516	}
517
518	ring->wptr += count_dw;
519	ring->wptr &= ring->ptr_mask;
520	ring->count_dw -= count_dw;
521}
522
523/**
524 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
525 * @ring: amdgpu_ring structure
526 * @offset: offset returned by amdgpu_ring_init_cond_exec
527 *
528 * Calculate the dw count and patch it into a cond_exec command.
529 */
530static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring,
531					       unsigned int offset)
532{
533	unsigned cur;
534
535	if (!ring->funcs->init_cond_exec)
536		return;
537
538	WARN_ON(offset > ring->buf_mask);
539	WARN_ON(ring->ring[offset] != 0);
540
541	cur = (ring->wptr - 1) & ring->buf_mask;
542	if (cur < offset)
543		cur += ring->ring_size >> 2;
544	ring->ring[offset] = cur - offset;
545}
546
547int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
548
549void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
550			      struct amdgpu_ring *ring);
551
552int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
553
554static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
555{
556	return ib->ptr[idx];
557}
558
559static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
560				       uint32_t value)
561{
562	ib->ptr[idx] = value;
563}
564
565int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
566		  unsigned size,
567		  enum amdgpu_ib_pool_type pool,
568		  struct amdgpu_ib *ib);
569void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f);
570int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
571		       struct amdgpu_ib *ibs, struct amdgpu_job *job,
572		       struct dma_fence **f);
573int amdgpu_ib_pool_init(struct amdgpu_device *adev);
574void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
575int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
576bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
577void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
578					     struct amdgpu_fence *guilty_fence);
579void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
580				    struct amdgpu_fence *guilty_fence);
581int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
582				 struct amdgpu_fence *guilty_fence);
583bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
584					 u32 reset_type);
585#endif