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amdgpu_ras.h
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24#ifndef _AMDGPU_RAS_H 25#define _AMDGPU_RAS_H 26 27#include <linux/debugfs.h> 28#include <linux/list.h> 29#include <linux/kfifo.h> 30#include <linux/radix-tree.h> 31#include "ta_ras_if.h" 32#include "amdgpu_ras_eeprom.h" 33#include "amdgpu_smuio.h" 34#include "amdgpu_aca.h" 35 36struct amdgpu_iv_entry; 37 38#define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 39#define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 40#define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 41#define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 42#define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 43#define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 44#define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 45#define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 46#define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 47#define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 48#define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 49#define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x) AMDGPU_GET_REG_FIELD(x, 29, 29) 50#define AMDGPU_RAS_GPU_ERR_GENERIC(x) AMDGPU_GET_REG_FIELD(x, 30, 30) 51 52#define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100 53#define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 54#define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 55 56#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 57/* position of instance value in sub_block_index of 58 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 59 */ 60#define AMDGPU_RAS_INST_MASK 0xfffff000 61#define AMDGPU_RAS_INST_SHIFT 0xc 62 63#define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 64#define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 65 66/* Reserve 8 physical dram row for possible retirement. 67 * In worst cases, it will lose 8 * 2MB memory in vram domain */ 68#define AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT (16ULL << 20) 69/* The high three bits indicates socketid */ 70#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 71 72#define RAS_EVENT_INVALID_ID (BIT_ULL(63)) 73#define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63))) 74 75#define RAS_EVENT_LOG(adev, id, fmt, ...) \ 76 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__) 77 78#define amdgpu_ras_mark_ras_event(adev, type) \ 79 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0))) 80 81enum amdgpu_ras_block { 82 AMDGPU_RAS_BLOCK__UMC = 0, 83 AMDGPU_RAS_BLOCK__SDMA, 84 AMDGPU_RAS_BLOCK__GFX, 85 AMDGPU_RAS_BLOCK__MMHUB, 86 AMDGPU_RAS_BLOCK__ATHUB, 87 AMDGPU_RAS_BLOCK__PCIE_BIF, 88 AMDGPU_RAS_BLOCK__HDP, 89 AMDGPU_RAS_BLOCK__XGMI_WAFL, 90 AMDGPU_RAS_BLOCK__DF, 91 AMDGPU_RAS_BLOCK__SMN, 92 AMDGPU_RAS_BLOCK__SEM, 93 AMDGPU_RAS_BLOCK__MP0, 94 AMDGPU_RAS_BLOCK__MP1, 95 AMDGPU_RAS_BLOCK__FUSE, 96 AMDGPU_RAS_BLOCK__MCA, 97 AMDGPU_RAS_BLOCK__VCN, 98 AMDGPU_RAS_BLOCK__JPEG, 99 AMDGPU_RAS_BLOCK__IH, 100 AMDGPU_RAS_BLOCK__MPIO, 101 AMDGPU_RAS_BLOCK__MMSCH, 102 103 AMDGPU_RAS_BLOCK__LAST, 104 AMDGPU_RAS_BLOCK__ANY = -1 105}; 106 107enum amdgpu_ras_mca_block { 108 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 109 AMDGPU_RAS_MCA_BLOCK__MP1, 110 AMDGPU_RAS_MCA_BLOCK__MPIO, 111 AMDGPU_RAS_MCA_BLOCK__IOHC, 112 113 AMDGPU_RAS_MCA_BLOCK__LAST 114}; 115 116#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 117#define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 118#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 119 120enum amdgpu_ras_gfx_subblock { 121 /* CPC */ 122 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 123 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 124 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 125 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 126 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 127 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 128 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 129 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 130 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 131 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 132 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 133 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 134 /* CPF */ 135 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 136 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 137 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 138 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 139 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 140 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 141 /* CPG */ 142 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 143 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 144 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 145 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 146 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 147 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 148 /* GDS */ 149 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 150 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 151 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 153 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 154 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 155 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 156 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 157 /* SPI */ 158 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 159 /* SQ */ 160 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 161 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 162 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 163 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 164 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 165 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 166 /* SQC (3 ranges) */ 167 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 168 /* SQC range 0 */ 169 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 170 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 171 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 172 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 175 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 177 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 178 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 179 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 180 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 181 /* SQC range 1 */ 182 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 183 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 184 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 185 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 186 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 187 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 189 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 191 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 192 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 193 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 194 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 195 /* SQC range 2 */ 196 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 197 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 198 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 199 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 200 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 201 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 203 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 205 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 206 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 207 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 208 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 209 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 210 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 211 /* TA */ 212 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 213 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 214 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 215 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 216 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 217 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 218 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 219 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 220 /* TCA */ 221 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 222 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 223 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 224 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 225 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 226 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 227 /* TCC (5 sub-ranges) */ 228 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 229 /* TCC range 0 */ 230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 231 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 232 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 233 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 235 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 236 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 237 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 238 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 239 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 240 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 241 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 242 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 243 /* TCC range 1 */ 244 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 245 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 246 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 247 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 248 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 249 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 250 /* TCC range 2 */ 251 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 252 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 253 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 254 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 255 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 256 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 257 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 258 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 259 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 260 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 261 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 262 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 263 /* TCC range 3 */ 264 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 265 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 266 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 267 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 268 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 269 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 270 /* TCC range 4 */ 271 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 272 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 273 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 274 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 275 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 276 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 277 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 278 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 279 /* TCI */ 280 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 281 /* TCP */ 282 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 283 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 284 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 285 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 286 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 287 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 288 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 289 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 290 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 291 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 292 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 293 /* TD */ 294 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 295 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 296 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 297 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 298 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 299 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 300 /* EA (3 sub-ranges) */ 301 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 302 /* EA range 0 */ 303 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 304 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 305 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 306 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 307 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 308 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 309 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 310 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 311 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 312 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 313 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 314 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 315 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 316 /* EA range 1 */ 317 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 318 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 319 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 320 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 321 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 322 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 323 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 324 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 325 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 326 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 327 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 328 /* EA range 2 */ 329 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 330 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 331 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 333 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 334 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 335 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 336 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 337 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 338 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 339 /* UTC VM L2 bank */ 340 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 341 /* UTC VM walker */ 342 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 343 /* UTC ATC L2 2MB cache */ 344 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 345 /* UTC ATC L2 4KB cache */ 346 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 347 AMDGPU_RAS_BLOCK__GFX_MAX 348}; 349 350enum amdgpu_ras_error_type { 351 AMDGPU_RAS_ERROR__NONE = 0, 352 AMDGPU_RAS_ERROR__PARITY = 1, 353 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 354 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 355 AMDGPU_RAS_ERROR__POISON = 8, 356}; 357 358enum amdgpu_ras_ret { 359 AMDGPU_RAS_SUCCESS = 0, 360 AMDGPU_RAS_FAIL, 361 AMDGPU_RAS_UE, 362 AMDGPU_RAS_CE, 363 AMDGPU_RAS_PT, 364}; 365 366enum amdgpu_ras_error_query_mode { 367 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 368 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 369 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 370 AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3, 371}; 372 373/* ras error status reisger fields */ 374#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 375#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 376#define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 377#define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 378#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 379#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 380#define ERR_STATUS__ERR_CNT__SHIFT 0x17 381#define ERR_STATUS__ERR_CNT_MASK 0x03800000L 382 383#define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 384 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 385 386#define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 387 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 388 389#define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 390#define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 391#define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 392 393#define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 394#define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 395 396struct amdgpu_ras_err_status_reg_entry { 397 uint32_t hwip; 398 uint32_t ip_inst; 399 uint32_t seg_lo; 400 uint32_t reg_lo; 401 uint32_t seg_hi; 402 uint32_t reg_hi; 403 uint32_t reg_inst; 404 uint32_t flags; 405 const char *block_name; 406}; 407 408struct amdgpu_ras_memory_id_entry { 409 uint32_t memory_id; 410 const char *name; 411}; 412 413struct ras_common_if { 414 enum amdgpu_ras_block block; 415 enum amdgpu_ras_error_type type; 416 uint32_t sub_block_index; 417 char name[32]; 418}; 419 420#define MAX_UMC_CHANNEL_NUM 32 421 422struct ecc_info_per_ch { 423 uint16_t ce_count_lo_chip; 424 uint16_t ce_count_hi_chip; 425 uint64_t mca_umc_status; 426 uint64_t mca_umc_addr; 427 uint64_t mca_ceumc_addr; 428}; 429 430struct umc_ecc_info { 431 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 432 433 /* Determine smu ecctable whether support 434 * record correctable error address 435 */ 436 int record_ce_addr_supported; 437}; 438 439enum ras_event_type { 440 RAS_EVENT_TYPE_INVALID = 0, 441 RAS_EVENT_TYPE_FATAL, 442 RAS_EVENT_TYPE_POISON_CREATION, 443 RAS_EVENT_TYPE_POISON_CONSUMPTION, 444 RAS_EVENT_TYPE_COUNT, 445}; 446 447struct ras_event_state { 448 u64 last_seqno; 449 atomic64_t count; 450}; 451 452struct ras_event_manager { 453 atomic64_t seqno; 454 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT]; 455}; 456 457struct ras_event_id { 458 enum ras_event_type type; 459 u64 event_id; 460}; 461 462struct ras_query_context { 463 struct ras_event_id evid; 464}; 465 466typedef int (*pasid_notify)(struct amdgpu_device *adev, 467 uint16_t pasid, void *data); 468 469struct ras_poison_msg { 470 enum amdgpu_ras_block block; 471 uint16_t pasid; 472 uint32_t reset; 473 pasid_notify pasid_fn; 474 void *data; 475}; 476 477struct ras_err_pages { 478 uint32_t count; 479 uint64_t *pfn; 480}; 481 482struct ras_ecc_err { 483 uint64_t status; 484 uint64_t ipid; 485 uint64_t addr; 486 uint64_t pa_pfn; 487 /* save global channel index across all UMC instances */ 488 uint32_t channel_idx; 489 struct ras_err_pages err_pages; 490}; 491 492struct ras_ecc_log_info { 493 struct mutex lock; 494 struct radix_tree_root de_page_tree; 495 uint64_t de_queried_count; 496 uint64_t consumption_q_count; 497}; 498 499struct ras_critical_region { 500 struct list_head node; 501 struct amdgpu_bo *bo; 502 uint64_t start; 503 uint64_t size; 504}; 505 506struct ras_eeprom_table_version { 507 uint32_t minor : 16; 508 uint32_t major : 16; 509}; 510 511struct ras_eeprom_smu_funcs { 512 int (*get_ras_table_version)(struct amdgpu_device *adev, 513 uint32_t *table_version); 514 int (*get_badpage_count)(struct amdgpu_device *adev, uint32_t *count, uint32_t timeout); 515 int (*get_badpage_mca_addr)(struct amdgpu_device *adev, uint16_t index, uint64_t *mca_addr); 516 int (*set_timestamp)(struct amdgpu_device *adev, uint64_t timestamp); 517 int (*get_timestamp)(struct amdgpu_device *adev, 518 uint16_t index, uint64_t *timestamp); 519 int (*get_badpage_ipid)(struct amdgpu_device *adev, uint16_t index, uint64_t *ipid); 520 int (*erase_ras_table)(struct amdgpu_device *adev, uint32_t *result); 521}; 522 523enum ras_smu_feature_flags { 524 RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), 525}; 526 527struct ras_smu_drv { 528 const struct ras_eeprom_smu_funcs *smu_eeprom_funcs; 529 void (*ras_smu_feature_flags)(struct amdgpu_device *adev, uint64_t *flags); 530}; 531 532struct amdgpu_ras { 533 void *ras_mgr; 534 /* ras infrastructure */ 535 /* for ras itself. */ 536 uint32_t features; 537 uint32_t schema; 538 struct list_head head; 539 /* sysfs */ 540 struct device_attribute features_attr; 541 struct device_attribute version_attr; 542 struct device_attribute schema_attr; 543 struct device_attribute event_state_attr; 544 struct bin_attribute badpages_attr; 545 struct dentry *de_ras_eeprom_table; 546 /* block array */ 547 struct ras_manager *objs; 548 549 /* gpu recovery */ 550 struct work_struct recovery_work; 551 atomic_t in_recovery; 552 atomic_t rma_in_recovery; 553 struct amdgpu_device *adev; 554 /* error handler data */ 555 struct ras_err_handler_data *eh_data; 556 struct mutex recovery_lock; 557 558 uint32_t flags; 559 bool reboot; 560 struct amdgpu_ras_eeprom_control eeprom_control; 561 562 bool error_query_ready; 563 564 /* bad page count threshold */ 565 uint32_t bad_page_cnt_threshold; 566 567 /* disable ras error count harvest in recovery */ 568 bool disable_ras_err_cnt_harvest; 569 570 /* is poison mode supported */ 571 bool poison_supported; 572 573 /* RAS count errors delayed work */ 574 struct delayed_work ras_counte_delay_work; 575 atomic_t ras_ue_count; 576 atomic_t ras_ce_count; 577 578 /* record umc error info queried from smu */ 579 struct umc_ecc_info umc_ecc; 580 581 /* Indicates smu whether need update bad channel info */ 582 bool update_channel_flag; 583 /* Record status of smu mca debug mode */ 584 bool is_aca_debug_mode; 585 bool is_rma; 586 587 /* Record special requirements of gpu reset caller */ 588 uint32_t gpu_reset_flags; 589 590 struct task_struct *page_retirement_thread; 591 wait_queue_head_t page_retirement_wq; 592 struct mutex page_retirement_lock; 593 atomic_t page_retirement_req_cnt; 594 atomic_t poison_creation_count; 595 atomic_t poison_consumption_count; 596 struct mutex page_rsv_lock; 597 DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128); 598 struct ras_ecc_log_info umc_ecc_log; 599 struct delayed_work page_retirement_dwork; 600 601 /* ras errors detected */ 602 unsigned long ras_err_state; 603 604 /* RAS event manager */ 605 struct ras_event_manager __event_mgr; 606 struct ras_event_manager *event_mgr; 607 608 uint64_t reserved_pages_in_bytes; 609 610 pid_t init_task_pid; 611 char init_task_comm[TASK_COMM_LEN]; 612 613 int bad_page_num; 614 615 struct list_head critical_region_head; 616 struct mutex critical_region_lock; 617 618 /* Protect poison injection */ 619 struct mutex poison_lock; 620 621 /* Disable/Enable uniras switch */ 622 bool uniras_enabled; 623 const struct ras_smu_drv *ras_smu_drv; 624}; 625 626struct ras_fs_data { 627 char sysfs_name[48]; 628 char debugfs_name[32]; 629}; 630 631struct ras_err_info { 632 struct amdgpu_smuio_mcm_config_info mcm_info; 633 u64 ce_count; 634 u64 ue_count; 635 u64 de_count; 636}; 637 638struct ras_err_node { 639 struct list_head node; 640 struct ras_err_info err_info; 641}; 642 643struct ras_err_data { 644 unsigned long ue_count; 645 unsigned long ce_count; 646 unsigned long de_count; 647 unsigned long err_addr_cnt; 648 struct eeprom_table_record *err_addr; 649 unsigned long err_addr_len; 650 u32 err_list_count; 651 struct list_head err_node_list; 652}; 653 654#define for_each_ras_error(err_node, err_data) \ 655 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 656 657struct ras_err_handler_data { 658 /* point to bad page records array */ 659 struct eeprom_table_record *bps; 660 /* the count of entries */ 661 int count; 662 int count_saved; 663 /* the space can place new entries */ 664 int space_left; 665}; 666 667typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 668 void *err_data, 669 struct amdgpu_iv_entry *entry); 670 671struct ras_ih_data { 672 /* interrupt bottom half */ 673 struct work_struct ih_work; 674 int inuse; 675 /* IP callback */ 676 ras_ih_cb cb; 677 /* full of entries */ 678 unsigned char *ring; 679 unsigned int ring_size; 680 unsigned int element_size; 681 unsigned int aligned_element_size; 682 unsigned int rptr; 683 unsigned int wptr; 684}; 685 686struct ras_manager { 687 struct ras_common_if head; 688 /* reference count */ 689 int use; 690 /* ras block link */ 691 struct list_head node; 692 /* the device */ 693 struct amdgpu_device *adev; 694 /* sysfs */ 695 struct device_attribute sysfs_attr; 696 int attr_inuse; 697 698 /* fs node name */ 699 struct ras_fs_data fs_data; 700 701 /* IH data */ 702 struct ras_ih_data ih_data; 703 704 struct ras_err_data err_data; 705 706 struct aca_handle aca_handle; 707}; 708 709struct ras_badpage { 710 unsigned int bp; 711 unsigned int size; 712 unsigned int flags; 713}; 714 715/* interfaces for IP */ 716struct ras_fs_if { 717 struct ras_common_if head; 718 const char* sysfs_name; 719 char debugfs_name[32]; 720}; 721 722struct ras_query_if { 723 struct ras_common_if head; 724 unsigned long ue_count; 725 unsigned long ce_count; 726 unsigned long de_count; 727}; 728 729struct ras_inject_if { 730 struct ras_common_if head; 731 uint64_t address; 732 uint64_t value; 733 uint32_t instance_mask; 734}; 735 736struct ras_cure_if { 737 struct ras_common_if head; 738 uint64_t address; 739}; 740 741struct ras_ih_if { 742 struct ras_common_if head; 743 ras_ih_cb cb; 744}; 745 746struct ras_dispatch_if { 747 struct ras_common_if head; 748 struct amdgpu_iv_entry *entry; 749}; 750 751struct ras_debug_if { 752 union { 753 struct ras_common_if head; 754 struct ras_inject_if inject; 755 }; 756 int op; 757}; 758 759struct amdgpu_ras_block_object { 760 struct ras_common_if ras_comm; 761 762 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 763 enum amdgpu_ras_block block, uint32_t sub_block_index); 764 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 765 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 766 ras_ih_cb ras_cb; 767 const struct amdgpu_ras_block_hw_ops *hw_ops; 768}; 769 770struct amdgpu_ras_block_hw_ops { 771 int (*ras_error_inject)(struct amdgpu_device *adev, 772 void *inject_if, uint32_t instance_mask); 773 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 774 void (*query_ras_error_status)(struct amdgpu_device *adev); 775 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 776 void (*reset_ras_error_count)(struct amdgpu_device *adev); 777 void (*reset_ras_error_status)(struct amdgpu_device *adev); 778 bool (*query_poison_status)(struct amdgpu_device *adev); 779 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 780}; 781 782/* work flow 783 * vbios 784 * 1: ras feature enable (enabled by default) 785 * psp 786 * 2: ras framework init (in ip_init) 787 * IP 788 * 3: IH add 789 * 4: debugfs/sysfs create 790 * 5: query/inject 791 * 6: debugfs/sysfs remove 792 * 7: IH remove 793 * 8: feature disable 794 */ 795 796int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev); 797int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info); 798 799void amdgpu_ras_resume(struct amdgpu_device *adev); 800void amdgpu_ras_suspend(struct amdgpu_device *adev); 801 802int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 803 unsigned long *ce_count, 804 unsigned long *ue_count, 805 struct ras_query_if *query_info); 806 807/* error handling functions */ 808int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 809 struct eeprom_table_record *bps, int pages, bool from_rom); 810 811int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 812 unsigned long *new_cnt); 813 814static inline enum ta_ras_block 815amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 816 switch (block) { 817 case AMDGPU_RAS_BLOCK__UMC: 818 return TA_RAS_BLOCK__UMC; 819 case AMDGPU_RAS_BLOCK__SDMA: 820 return TA_RAS_BLOCK__SDMA; 821 case AMDGPU_RAS_BLOCK__GFX: 822 return TA_RAS_BLOCK__GFX; 823 case AMDGPU_RAS_BLOCK__MMHUB: 824 return TA_RAS_BLOCK__MMHUB; 825 case AMDGPU_RAS_BLOCK__ATHUB: 826 return TA_RAS_BLOCK__ATHUB; 827 case AMDGPU_RAS_BLOCK__PCIE_BIF: 828 return TA_RAS_BLOCK__PCIE_BIF; 829 case AMDGPU_RAS_BLOCK__HDP: 830 return TA_RAS_BLOCK__HDP; 831 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 832 return TA_RAS_BLOCK__XGMI_WAFL; 833 case AMDGPU_RAS_BLOCK__DF: 834 return TA_RAS_BLOCK__DF; 835 case AMDGPU_RAS_BLOCK__SMN: 836 return TA_RAS_BLOCK__SMN; 837 case AMDGPU_RAS_BLOCK__SEM: 838 return TA_RAS_BLOCK__SEM; 839 case AMDGPU_RAS_BLOCK__MP0: 840 return TA_RAS_BLOCK__MP0; 841 case AMDGPU_RAS_BLOCK__MP1: 842 return TA_RAS_BLOCK__MP1; 843 case AMDGPU_RAS_BLOCK__FUSE: 844 return TA_RAS_BLOCK__FUSE; 845 case AMDGPU_RAS_BLOCK__MCA: 846 return TA_RAS_BLOCK__MCA; 847 case AMDGPU_RAS_BLOCK__VCN: 848 return TA_RAS_BLOCK__VCN; 849 case AMDGPU_RAS_BLOCK__JPEG: 850 return TA_RAS_BLOCK__JPEG; 851 case AMDGPU_RAS_BLOCK__IH: 852 return TA_RAS_BLOCK__IH; 853 case AMDGPU_RAS_BLOCK__MPIO: 854 return TA_RAS_BLOCK__MPIO; 855 case AMDGPU_RAS_BLOCK__MMSCH: 856 return TA_RAS_BLOCK__MMSCH; 857 default: 858 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 859 return TA_RAS_BLOCK__UMC; 860 } 861} 862 863static inline enum ta_ras_error_type 864amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 865 switch (error) { 866 case AMDGPU_RAS_ERROR__NONE: 867 return TA_RAS_ERROR__NONE; 868 case AMDGPU_RAS_ERROR__PARITY: 869 return TA_RAS_ERROR__PARITY; 870 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 871 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 872 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 873 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 874 case AMDGPU_RAS_ERROR__POISON: 875 return TA_RAS_ERROR__POISON; 876 default: 877 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 878 return TA_RAS_ERROR__NONE; 879 } 880} 881 882/* called in ip_init and ip_fini */ 883int amdgpu_ras_init(struct amdgpu_device *adev); 884int amdgpu_ras_late_init(struct amdgpu_device *adev); 885int amdgpu_ras_fini(struct amdgpu_device *adev); 886int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 887 888int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 889 struct ras_common_if *ras_block); 890 891void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 892 struct ras_common_if *ras_block); 893 894int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 895 struct ras_common_if *head, bool enable); 896 897int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 898 struct ras_common_if *head, bool enable); 899 900int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 901 struct ras_common_if *head); 902 903int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 904 struct ras_common_if *head); 905 906void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 907 908int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 909 struct ras_query_if *info); 910 911int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 912 enum amdgpu_ras_block block); 913int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 914 enum amdgpu_ras_block block); 915 916int amdgpu_ras_error_inject(struct amdgpu_device *adev, 917 struct ras_inject_if *info); 918 919int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 920 struct ras_common_if *head); 921 922int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 923 struct ras_common_if *head); 924 925int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 926 struct ras_dispatch_if *info); 927 928struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 929 struct ras_common_if *head); 930 931extern atomic_t amdgpu_ras_in_intr; 932 933static inline bool amdgpu_ras_intr_triggered(void) 934{ 935 return !!atomic_read(&amdgpu_ras_in_intr); 936} 937 938static inline void amdgpu_ras_intr_cleared(void) 939{ 940 atomic_set(&amdgpu_ras_in_intr, 0); 941} 942 943int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 944 945void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 946 947bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 948 949void amdgpu_release_ras_context(struct amdgpu_device *adev); 950 951int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 952 953const char *get_ras_block_str(struct ras_common_if *ras_block); 954 955bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 956 957int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 958 959int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 960 961struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 962 963int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 964 965int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 966int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 967bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 968bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 969 unsigned int *mode); 970 971int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 972 struct amdgpu_ras_block_object *ras_block_obj); 973void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 974void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 975bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 976 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 977 uint32_t instance, 978 uint32_t *memory_id); 979bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 980 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 981 uint32_t instance, 982 unsigned long *err_cnt); 983void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 984 const struct amdgpu_ras_err_status_reg_entry *reg_list, 985 uint32_t reg_list_size, 986 const struct amdgpu_ras_memory_id_entry *mem_list, 987 uint32_t mem_list_size, 988 uint32_t instance, 989 uint32_t err_type, 990 unsigned long *err_count); 991void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 992 const struct amdgpu_ras_err_status_reg_entry *reg_list, 993 uint32_t reg_list_size, 994 uint32_t instance); 995 996int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 997void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 998int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 999 struct amdgpu_smuio_mcm_config_info *mcm_info, 1000 u64 count); 1001int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 1002 struct amdgpu_smuio_mcm_config_info *mcm_info, 1003 u64 count); 1004int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 1005 struct amdgpu_smuio_mcm_config_info *mcm_info, 1006 u64 count); 1007void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 1008int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 1009 const struct aca_info *aca_info, void *data); 1010int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 1011 1012ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 1013 struct aca_handle *handle, char *buf, void *data); 1014 1015void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 1016bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 1017void amdgpu_ras_set_err_poison(struct amdgpu_device *adev, 1018 enum amdgpu_ras_block block); 1019void amdgpu_ras_clear_err_state(struct amdgpu_device *adev); 1020bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block); 1021 1022u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 1023int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, 1024 const void *caller); 1025 1026int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); 1027 1028int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, struct amdgpu_bo *bo); 1029bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr); 1030 1031int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, 1032 enum amdgpu_ras_block block, uint16_t pasid, 1033 pasid_notify pasid_fn, void *data, uint32_t reset); 1034 1035bool amdgpu_ras_in_recovery(struct amdgpu_device *adev); 1036 1037__printf(3, 4) 1038void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 1039 const char *fmt, ...); 1040 1041bool amdgpu_ras_is_rma(struct amdgpu_device *adev); 1042 1043void amdgpu_ras_pre_reset(struct amdgpu_device *adev, 1044 struct list_head *device_list); 1045void amdgpu_ras_post_reset(struct amdgpu_device *adev, 1046 struct list_head *device_list); 1047#endif
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