amdgpu_object.h

  1/*
  2 * Copyright 2008 Advanced Micro Devices, Inc.
  3 * Copyright 2008 Red Hat Inc.
  4 * Copyright 2009 Jerome Glisse.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 22 * OTHER DEALINGS IN THE SOFTWARE.
 23 *
 24 * Authors: Dave Airlie
 25 *          Alex Deucher
 26 *          Jerome Glisse
 27 */
 28#ifndef __AMDGPU_OBJECT_H__
 29#define __AMDGPU_OBJECT_H__
 30
 31#include <drm/amdgpu_drm.h>
 32#include "amdgpu.h"
 33#include "amdgpu_res_cursor.h"
 34
 35#ifdef CONFIG_MMU_NOTIFIER
 36#include <linux/mmu_notifier.h>
 37#endif
 38
 39#define AMDGPU_BO_INVALID_OFFSET	LONG_MAX
 40#define AMDGPU_BO_MAX_PLACEMENTS	3
 41
 42/* BO flag to indicate a KFD userptr BO */
 43#define AMDGPU_AMDKFD_CREATE_USERPTR_BO	(1ULL << 63)
 44
 45#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
 46#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
 47
 48struct amdgpu_bo_param {
 49	unsigned long			size;
 50	int				byte_align;
 51	u32				bo_ptr_size;
 52	u32				domain;
 53	u32				preferred_domain;
 54	u64				flags;
 55	enum ttm_bo_type		type;
 56	bool				no_wait_gpu;
 57	struct dma_resv			*resv;
 58	void				(*destroy)(struct ttm_buffer_object *bo);
 59	/* xcp partition number plus 1, 0 means any partition */
 60	int8_t				xcp_id_plus1;
 61};
 62
 63/* bo virtual addresses in a vm */
 64struct amdgpu_bo_va_mapping {
 65	struct amdgpu_bo_va		*bo_va;
 66	struct list_head		list;
 67	struct rb_node			rb;
 68	uint64_t			start;
 69	uint64_t			last;
 70	uint64_t			__subtree_last;
 71	uint64_t			offset;
 72	uint32_t			flags;
 73};
 74
 75/* User space allocated BO in a VM */
 76struct amdgpu_bo_va {
 77	struct amdgpu_vm_bo_base	base;
 78
 79	/* protected by bo being reserved */
 80	unsigned			ref_count;
 81
 82	/* all other members protected by the VM PD being reserved */
 83	struct dma_fence	        *last_pt_update;
 84
 85	/* mappings for this bo_va */
 86	struct list_head		invalids;
 87	struct list_head		valids;
 88
 89	/* If the mappings are cleared or filled */
 90	bool				cleared;
 91
 92	bool				is_xgmi;
 93
 94	/*
 95	 * protected by vm reservation lock
 96	 * if non-zero, cannot unmap from GPU because user queues may still access it
 97	 */
 98	unsigned int			queue_refcount;
 99	atomic_t			userq_va_mapped;
100};
101
102struct amdgpu_bo {
103	/* Protected by tbo.reserved */
104	u32				preferred_domains;
105	u32				allowed_domains;
106	struct ttm_place		placements[AMDGPU_BO_MAX_PLACEMENTS];
107	struct ttm_placement		placement;
108	struct ttm_buffer_object	tbo;
109	struct ttm_bo_kmap_obj		kmap;
110	u64				flags;
111	/* per VM structure for page tables and with virtual addresses */
112	struct amdgpu_vm_bo_base	*vm_bo;
113	/* Constant after initialization */
114	struct amdgpu_bo		*parent;
115
116#ifdef CONFIG_MMU_NOTIFIER
117	struct mmu_interval_notifier	notifier;
118#endif
119	struct kgd_mem                  *kfd_bo;
120
121	/*
122	 * For GPUs with spatial partitioning, xcp partition number, -1 means
123	 * any partition. For other ASICs without spatial partition, always 0
124	 * for memory accounting.
125	 */
126	int8_t				xcp_id;
127};
128
129struct amdgpu_bo_user {
130	struct amdgpu_bo		bo;
131	u64				tiling_flags;
132	u64				metadata_flags;
133	void				*metadata;
134	u32				metadata_size;
135
136};
137
138struct amdgpu_bo_vm {
139	struct amdgpu_bo		bo;
140	struct amdgpu_vm_bo_base        entries[];
141};
142
143static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
144{
145	return container_of(tbo, struct amdgpu_bo, tbo);
146}
147
148/**
149 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
150 * @mem_type:	ttm memory type
151 *
152 * Returns corresponding domain of the ttm mem_type
153 */
154static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
155{
156	switch (mem_type) {
157	case TTM_PL_VRAM:
158		return AMDGPU_GEM_DOMAIN_VRAM;
159	case TTM_PL_TT:
160		return AMDGPU_GEM_DOMAIN_GTT;
161	case TTM_PL_SYSTEM:
162		return AMDGPU_GEM_DOMAIN_CPU;
163	case AMDGPU_PL_GDS:
164		return AMDGPU_GEM_DOMAIN_GDS;
165	case AMDGPU_PL_GWS:
166		return AMDGPU_GEM_DOMAIN_GWS;
167	case AMDGPU_PL_OA:
168		return AMDGPU_GEM_DOMAIN_OA;
169	case AMDGPU_PL_DOORBELL:
170		return AMDGPU_GEM_DOMAIN_DOORBELL;
171	default:
172		break;
173	}
174	return 0;
175}
176
177/**
178 * amdgpu_bo_reserve - reserve bo
179 * @bo:		bo structure
180 * @no_intr:	don't return -ERESTARTSYS on pending signal
181 *
182 * Returns:
183 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
184 * a signal. Release all buffer reservations and return to user-space.
185 */
186static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
187{
188	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
189	int r;
190
191	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
192	if (unlikely(r != 0)) {
193		if (r != -ERESTARTSYS)
194			dev_err(adev->dev, "%p reserve failed\n", bo);
195		return r;
196	}
197	return 0;
198}
199
200static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
201{
202	ttm_bo_unreserve(&bo->tbo);
203}
204
205static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
206{
207	return bo->tbo.base.size;
208}
209
210static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
211{
212	return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
213}
214
215static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
216{
217	return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
218}
219
220/**
221 * amdgpu_bo_mmap_offset - return mmap offset of bo
222 * @bo:	amdgpu object for which we query the offset
223 *
224 * Returns mmap offset of the object.
225 */
226static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
227{
228	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
229}
230
231/**
232 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
233 */
234static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
235{
236	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
237}
238
239/**
240 * amdgpu_bo_encrypted - test if the BO is encrypted
241 * @bo: pointer to a buffer object
242 *
243 * Return true if the buffer object is encrypted, false otherwise.
244 */
245static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
246{
247	return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
248}
249
250bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
251void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
252
253int amdgpu_bo_create(struct amdgpu_device *adev,
254		     struct amdgpu_bo_param *bp,
255		     struct amdgpu_bo **bo_ptr);
256int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
257			      unsigned long size, int align,
258			      u32 domain, struct amdgpu_bo **bo_ptr,
259			      u64 *gpu_addr, void **cpu_addr);
260int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
261			    unsigned long size, int align,
262			    u32 domain, struct amdgpu_bo **bo_ptr,
263			    u64 *gpu_addr, void **cpu_addr);
264int amdgpu_bo_create_isp_user(struct amdgpu_device *adev,
265			   struct dma_buf *dbuf, u32 domain,
266			   struct amdgpu_bo **bo,
267			   u64 *gpu_addr);
268int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
269			       uint64_t offset, uint64_t size,
270			       struct amdgpu_bo **bo_ptr, void **cpu_addr);
271int amdgpu_bo_create_user(struct amdgpu_device *adev,
272			  struct amdgpu_bo_param *bp,
273			  struct amdgpu_bo_user **ubo_ptr);
274int amdgpu_bo_create_vm(struct amdgpu_device *adev,
275			struct amdgpu_bo_param *bp,
276			struct amdgpu_bo_vm **ubo_ptr);
277void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
278			   void **cpu_addr);
279void amdgpu_bo_free_isp_user(struct amdgpu_bo *bo);
280int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
281void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
282void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
283struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
284void amdgpu_bo_unref(struct amdgpu_bo **bo);
285int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
286void amdgpu_bo_unpin(struct amdgpu_bo *bo);
287int amdgpu_bo_init(struct amdgpu_device *adev);
288void amdgpu_bo_fini(struct amdgpu_device *adev);
289int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
290void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
291int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
292			    uint32_t metadata_size, uint64_t flags);
293int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
294			   size_t buffer_size, uint32_t *metadata_size,
295			   uint64_t *flags);
296void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
297			   bool evict,
298			   struct ttm_resource *new_mem);
299void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
300vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
301void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
302		     bool shared);
303int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
304			     enum amdgpu_sync_mode sync_mode, void *owner,
305			     bool intr);
306int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
307u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
308u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo);
309u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
310uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo);
311uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
312					    uint32_t domain);
313
314/*
315 * sub allocation
316 */
317static inline struct amdgpu_sa_manager *
318to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
319{
320	return container_of(manager, struct amdgpu_sa_manager, base);
321}
322
323static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
324{
325	return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
326		drm_suballoc_soffset(sa_bo);
327}
328
329static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
330{
331	return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
332		drm_suballoc_soffset(sa_bo);
333}
334
335int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
336				     struct amdgpu_sa_manager *sa_manager,
337				     unsigned size, u32 align, u32 domain);
338void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
339				      struct amdgpu_sa_manager *sa_manager);
340int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
341				      struct amdgpu_sa_manager *sa_manager);
342int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
343		     struct drm_suballoc **sa_bo,
344		     unsigned int size);
345void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo,
346		       struct dma_fence *fence);
347#if defined(CONFIG_DEBUG_FS)
348void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
349					 struct seq_file *m);
350u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
351#endif
352void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
353
354bool amdgpu_bo_support_uswc(u64 bo_flags);
355
356
357#endif