amdgpu_job.h

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#ifndef __AMDGPU_JOB_H__
 24#define __AMDGPU_JOB_H__
 25
 26#include <drm/gpu_scheduler.h>
 27#include "amdgpu_sync.h"
 28#include "amdgpu_ring.h"
 29
 30/* bit set means command submit involves a preamble IB */
 31#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0)
 32/* bit set means preamble IB is first presented in belonging context */
 33#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1)
 34/* bit set means context switch occured */
 35#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2)
 36/* bit set means IB is preempted */
 37#define AMDGPU_IB_PREEMPTED                 (1 << 3)
 38
 39#define to_amdgpu_job(sched_job)		\
 40		container_of((sched_job), struct amdgpu_job, base)
 41
 42#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
 43
 44struct amdgpu_fence;
 45enum amdgpu_ib_pool_type;
 46
 47/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */
 48#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE              (18446744073709551615ULL)
 49#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES         (18446744073709551614ULL)
 50#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE        (18446744073709551613ULL)
 51#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR            (18446744073709551612ULL)
 52#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER         (18446744073709551611ULL)
 53#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)
 54#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER        (18446744073709551609ULL)
 55#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE       (18446744073709551608ULL)
 56#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT              (18446744073709551607ULL)
 57#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER       (18446744073709551606ULL)
 58#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER         (18446744073709551605ULL)
 59#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB          (18446744073709551604ULL)
 60#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP           (18446744073709551603ULL)
 61#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST          (18446744073709551602ULL)
 62
 63struct amdgpu_job {
 64	struct drm_sched_job    base;
 65	struct amdgpu_vm	*vm;
 66	struct amdgpu_sync	explicit_sync;
 67	struct amdgpu_fence	*hw_fence;
 68	struct amdgpu_fence	*hw_vm_fence;
 69	struct dma_fence	*gang_submit;
 70	uint32_t		preamble_status;
 71	uint32_t                preemption_status;
 72	bool                    vm_needs_flush;
 73	bool			gds_switch_needed;
 74	bool			spm_update_needed;
 75	uint64_t		vm_pd_addr;
 76	unsigned		vmid;
 77	unsigned		pasid;
 78	uint32_t		gds_base, gds_size;
 79	uint32_t		gws_base, gws_size;
 80	uint32_t		oa_base, oa_size;
 81	uint64_t		generation;
 82
 83	/* user fence handling */
 84	uint64_t		uf_addr;
 85	uint64_t		uf_sequence;
 86
 87	/* virtual addresses for shadow/GDS/CSA */
 88	uint64_t		shadow_va;
 89	uint64_t		csa_va;
 90	uint64_t		gds_va;
 91	bool			init_shadow;
 92
 93	/* job_run_counter >= 1 means a resubmit job */
 94	uint32_t		job_run_counter;
 95
 96	/* enforce isolation */
 97	bool			enforce_isolation;
 98	bool			run_cleaner_shader;
 99
100	uint32_t		num_ibs;
101	struct amdgpu_ib	ibs[];
102};
103
104static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)
105{
106	return to_amdgpu_ring(job->base.entity->rq->sched);
107}
108
109int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
110		     struct drm_sched_entity *entity, void *owner,
111		     unsigned int num_ibs, struct amdgpu_job **job,
112		     u64 drm_client_id);
113int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
114			     struct drm_sched_entity *entity, void *owner,
115			     size_t size, enum amdgpu_ib_pool_type pool_type,
116			     struct amdgpu_job **job,
117			     u64 k_job_id);
118void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
119			      struct amdgpu_bo *gws, struct amdgpu_bo *oa);
120void amdgpu_job_free_resources(struct amdgpu_job *job);
121void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
122				struct amdgpu_job *leader);
123void amdgpu_job_free(struct amdgpu_job *job);
124struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job);
125int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
126			     struct dma_fence **fence);
127
128void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
129
130#endif