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amdgpu_drv.c
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linux-6.19.14/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
1/* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#include <drm/amdgpu_drm.h> 26#include <drm/clients/drm_client_setup.h> 27#include <drm/drm_drv.h> 28#include <drm/drm_fbdev_ttm.h> 29#include <drm/drm_gem.h> 30#include <drm/drm_managed.h> 31#include <drm/drm_pciids.h> 32#include <drm/drm_probe_helper.h> 33#include <drm/drm_vblank.h> 34 35#include <linux/cc_platform.h> 36#include <linux/console.h> 37#include <linux/dynamic_debug.h> 38#include <linux/module.h> 39#include <linux/mmu_notifier.h> 40#include <linux/pm_runtime.h> 41#include <linux/suspend.h> 42#include <linux/vga_switcheroo.h> 43 44#include "amdgpu.h" 45#include "amdgpu_amdkfd.h" 46#include "amdgpu_dma_buf.h" 47#include "amdgpu_drv.h" 48#include "amdgpu_fdinfo.h" 49#include "amdgpu_irq.h" 50#include "amdgpu_psp.h" 51#include "amdgpu_ras.h" 52#include "amdgpu_reset.h" 53#include "amdgpu_sched.h" 54#include "amdgpu_xgmi.h" 55#include "amdgpu_userq.h" 56#include "amdgpu_userq_fence.h" 57#include "../amdxcp/amdgpu_xcp_drv.h" 58 59/* 60 * KMS wrapper. 61 * - 3.0.0 - initial driver 62 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 63 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 64 * at the end of IBs. 65 * - 3.3.0 - Add VM support for UVD on supported hardware. 66 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 67 * - 3.5.0 - Add support for new UVD_NO_OP register. 68 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 69 * - 3.7.0 - Add support for VCE clock list packet 70 * - 3.8.0 - Add support raster config init in the kernel 71 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 72 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 73 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 74 * - 3.12.0 - Add query for double offchip LDS buffers 75 * - 3.13.0 - Add PRT support 76 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 77 * - 3.15.0 - Export more gpu info for gfx9 78 * - 3.16.0 - Add reserved vmid support 79 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 80 * - 3.18.0 - Export gpu always on cu bitmap 81 * - 3.19.0 - Add support for UVD MJPEG decode 82 * - 3.20.0 - Add support for local BOs 83 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 84 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 85 * - 3.23.0 - Add query for VRAM lost counter 86 * - 3.24.0 - Add high priority compute support for gfx9 87 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 88 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 89 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 90 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 91 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 92 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 93 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 94 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 95 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 96 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 97 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 98 * - 3.36.0 - Allow reading more status registers on si/cik 99 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 100 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 101 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 102 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 103 * - 3.41.0 - Add video codec query 104 * - 3.42.0 - Add 16bpc fixed point display support 105 * - 3.43.0 - Add device hot plug/unplug support 106 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 107 * - 3.45.0 - Add context ioctl stable pstate interface 108 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 109 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 110 * - 3.48.0 - Add IP discovery version info to HW INFO 111 * - 3.49.0 - Add gang submit into CS IOCTL 112 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 113 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 114 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 115 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 116 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 117 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 118 * 3.53.0 - Support for GFX11 CP GFX shadowing 119 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 120 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 121 * - 3.56.0 - Update IB start address and size alignment for decode and encode 122 * - 3.57.0 - Compute tunneling on GFX10+ 123 * - 3.58.0 - Add GFX12 DCC support 124 * - 3.59.0 - Cleared VRAM 125 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 126 * - 3.61.0 - Contains fix for RV/PCO compute queues 127 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 128 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 129 * - 3.64.0 - Userq IP support query 130 */ 131#define KMS_DRIVER_MAJOR 3 132#define KMS_DRIVER_MINOR 64 133#define KMS_DRIVER_PATCHLEVEL 0 134 135/* 136 * amdgpu.debug module options. Are all disabled by default 137 */ 138enum AMDGPU_DEBUG_MASK { 139 AMDGPU_DEBUG_VM = BIT(0), 140 AMDGPU_DEBUG_LARGEBAR = BIT(1), 141 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 142 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 143 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 144 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 145 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 146 AMDGPU_DEBUG_SMU_POOL = BIT(7), 147 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 148 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 149 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10) 150}; 151 152unsigned int amdgpu_vram_limit = UINT_MAX; 153int amdgpu_vis_vram_limit; 154int amdgpu_gart_size = -1; /* auto */ 155int amdgpu_gtt_size = -1; /* auto */ 156int amdgpu_moverate = -1; /* auto */ 157int amdgpu_audio = -1; 158int amdgpu_disp_priority; 159int amdgpu_hw_i2c; 160int amdgpu_pcie_gen2 = -1; 161int amdgpu_msi = -1; 162char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163int amdgpu_dpm = -1; 164int amdgpu_fw_load_type = -1; 165int amdgpu_aspm = -1; 166int amdgpu_runtime_pm = -1; 167uint amdgpu_ip_block_mask = 0xffffffff; 168int amdgpu_bapm = -1; 169int amdgpu_deep_color; 170int amdgpu_vm_size = -1; 171int amdgpu_vm_fragment_size = -1; 172int amdgpu_vm_block_size = -1; 173int amdgpu_vm_fault_stop; 174int amdgpu_vm_update_mode = -1; 175int amdgpu_exp_hw_support; 176int amdgpu_dc = -1; 177int amdgpu_sched_jobs = 32; 178int amdgpu_sched_hw_submission = 2; 179uint amdgpu_pcie_gen_cap; 180uint amdgpu_pcie_lane_cap; 181u64 amdgpu_cg_mask = 0xffffffffffffffff; 182uint amdgpu_pg_mask = 0xffffffff; 183uint amdgpu_sdma_phase_quantum = 32; 184char *amdgpu_disable_cu; 185char *amdgpu_virtual_display; 186int amdgpu_enforce_isolation = -1; 187int amdgpu_modeset = -1; 188 189/* Specifies the default granularity for SVM, used in buffer 190 * migration and restoration of backing memory when handling 191 * recoverable page faults. 192 * 193 * The value is given as log(numPages(buffer)); for a 2 MiB 194 * buffer it computes to be 9 195 */ 196uint amdgpu_svm_default_granularity = 9; 197 198/* 199 * OverDrive(bit 14) disabled by default 200 * GFX DCS(bit 19) disabled by default 201 */ 202uint amdgpu_pp_feature_mask = 0xfff7bfff; 203uint amdgpu_force_long_training; 204int amdgpu_lbpw = -1; 205int amdgpu_compute_multipipe = -1; 206int amdgpu_gpu_recovery = -1; /* auto */ 207int amdgpu_emu_mode; 208uint amdgpu_smu_memory_pool_size; 209int amdgpu_smu_pptable_id = -1; 210/* 211 * FBC (bit 0) disabled by default 212 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 213 * - With this, for multiple monitors in sync(e.g. with the same model), 214 * mclk switching will be allowed. And the mclk will be not foced to the 215 * highest. That helps saving some idle power. 216 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 217 * PSR (bit 3) disabled by default 218 * EDP NO POWER SEQUENCING (bit 4) disabled by default 219 */ 220uint amdgpu_dc_feature_mask = 2; 221uint amdgpu_dc_debug_mask; 222uint amdgpu_dc_visual_confirm; 223int amdgpu_async_gfx_ring = 1; 224int amdgpu_mcbp = -1; 225int amdgpu_discovery = -1; 226int amdgpu_mes; 227int amdgpu_mes_log_enable = 0; 228int amdgpu_mes_kiq; 229int amdgpu_uni_mes = 1; 230int amdgpu_noretry = -1; 231int amdgpu_force_asic_type = -1; 232int amdgpu_tmz = -1; /* auto */ 233uint amdgpu_freesync_vid_mode; 234int amdgpu_reset_method = -1; /* auto */ 235int amdgpu_num_kcq = -1; 236int amdgpu_smartshift_bias; 237int amdgpu_use_xgmi_p2p = 1; 238int amdgpu_vcnfw_log; 239int amdgpu_sg_display = -1; /* auto */ 240int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 241int amdgpu_umsch_mm; 242int amdgpu_seamless = -1; /* auto */ 243uint amdgpu_debug_mask; 244int amdgpu_agp = -1; /* auto */ 245int amdgpu_wbrf = -1; 246int amdgpu_damage_clips = -1; /* auto */ 247int amdgpu_umsch_mm_fwlog; 248int amdgpu_rebar = -1; /* auto */ 249int amdgpu_user_queue = -1; 250uint amdgpu_hdmi_hpd_debounce_delay_ms; 251 252DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 253 "DRM_UT_CORE", 254 "DRM_UT_DRIVER", 255 "DRM_UT_KMS", 256 "DRM_UT_PRIME", 257 "DRM_UT_ATOMIC", 258 "DRM_UT_VBL", 259 "DRM_UT_STATE", 260 "DRM_UT_LEASE", 261 "DRM_UT_DP", 262 "DRM_UT_DRMRES"); 263 264struct amdgpu_mgpu_info mgpu_info = { 265 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 266}; 267int amdgpu_ras_enable = -1; 268uint amdgpu_ras_mask = 0xffffffff; 269int amdgpu_bad_page_threshold = -1; 270struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 271 .timeout_fatal_disable = false, 272 .period = 0x0, /* default to 0x0 (timeout disable) */ 273}; 274 275/** 276 * DOC: vramlimit (int) 277 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 278 */ 279MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 280module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 281 282/** 283 * DOC: vis_vramlimit (int) 284 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 285 */ 286MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 287module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 288 289/** 290 * DOC: gartsize (uint) 291 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 292 * The default is -1 (The size depends on asic). 293 */ 294MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 295module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 296 297/** 298 * DOC: gttsize (int) 299 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 300 * The default is -1 (Use value specified by TTM). 301 * This parameter is deprecated and will be removed in the future. 302 */ 303MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 304module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 305 306/** 307 * DOC: moverate (int) 308 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 309 */ 310MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 311module_param_named(moverate, amdgpu_moverate, int, 0600); 312 313/** 314 * DOC: audio (int) 315 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 316 */ 317MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 318module_param_named(audio, amdgpu_audio, int, 0444); 319 320/** 321 * DOC: disp_priority (int) 322 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 323 */ 324MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 325module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 326 327/** 328 * DOC: hw_i2c (int) 329 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 330 */ 331MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 332module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 333 334/** 335 * DOC: pcie_gen2 (int) 336 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 337 */ 338MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 339module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 340 341/** 342 * DOC: msi (int) 343 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 344 */ 345MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 346module_param_named(msi, amdgpu_msi, int, 0444); 347 348/** 349 * DOC: svm_default_granularity (uint) 350 * Used in buffer migration and handling of recoverable page faults 351 */ 352MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 353module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 354 355/** 356 * DOC: lockup_timeout (string) 357 * Set GPU scheduler timeout value in ms. 358 * 359 * The format can be [single value] for setting all timeouts at once or 360 * [GFX,Compute,SDMA,Video] to set individual timeouts. 361 * Negative values mean infinity. 362 * 363 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 364 */ 365MODULE_PARM_DESC(lockup_timeout, 366 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 367module_param_string(lockup_timeout, amdgpu_lockup_timeout, 368 sizeof(amdgpu_lockup_timeout), 0444); 369 370/** 371 * DOC: dpm (int) 372 * Override for dynamic power management setting 373 * (0 = disable, 1 = enable) 374 * The default is -1 (auto). 375 */ 376MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 377module_param_named(dpm, amdgpu_dpm, int, 0444); 378 379/** 380 * DOC: fw_load_type (int) 381 * Set different firmware loading type for debugging, if supported. 382 * Set to 0 to force direct loading if supported by the ASIC. Set 383 * to -1 to select the default loading mode for the ASIC, as defined 384 * by the driver. The default is -1 (auto). 385 */ 386MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 387module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 388 389/** 390 * DOC: aspm (int) 391 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 392 */ 393MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 394module_param_named(aspm, amdgpu_aspm, int, 0444); 395 396/** 397 * DOC: runpm (int) 398 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 399 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 400 * Setting the value to 0 disables this functionality. 401 * Setting the value to -2 is auto enabled with power down when displays are attached. 402 */ 403MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 404module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 405 406/** 407 * DOC: ip_block_mask (uint) 408 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 409 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 410 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 411 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 412 */ 413MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 414module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 415 416/** 417 * DOC: bapm (int) 418 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 419 * The default -1 (auto, enabled) 420 */ 421MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 422module_param_named(bapm, amdgpu_bapm, int, 0444); 423 424/** 425 * DOC: deep_color (int) 426 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 427 */ 428MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 429module_param_named(deep_color, amdgpu_deep_color, int, 0444); 430 431/** 432 * DOC: vm_size (int) 433 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 434 */ 435MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 436module_param_named(vm_size, amdgpu_vm_size, int, 0444); 437 438/** 439 * DOC: vm_fragment_size (int) 440 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 441 */ 442MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 443module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 444 445/** 446 * DOC: vm_block_size (int) 447 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 448 */ 449MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 450module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 451 452/** 453 * DOC: vm_fault_stop (int) 454 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 455 */ 456MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 457module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 458 459/** 460 * DOC: vm_update_mode (int) 461 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 462 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 463 */ 464MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 465module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 466 467/** 468 * DOC: exp_hw_support (int) 469 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 470 */ 471MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 472module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 473 474/** 475 * DOC: dc (int) 476 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 477 */ 478MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 479module_param_named(dc, amdgpu_dc, int, 0444); 480 481/** 482 * DOC: sched_jobs (int) 483 * Override the max number of jobs supported in the sw queue. The default is 32. 484 */ 485MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 486module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 487 488/** 489 * DOC: sched_hw_submission (int) 490 * Override the max number of HW submissions. The default is 2. 491 */ 492MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 493module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 494 495/** 496 * DOC: ppfeaturemask (hexint) 497 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 498 * The default is the current set of stable power features. 499 */ 500MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 501module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 502 503/** 504 * DOC: forcelongtraining (uint) 505 * Force long memory training in resume. 506 * The default is zero, indicates short training in resume. 507 */ 508MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 509module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 510 511/** 512 * DOC: pcie_gen_cap (uint) 513 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 514 * The default is 0 (automatic for each asic). 515 */ 516MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 517module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 518 519/** 520 * DOC: pcie_lane_cap (uint) 521 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 522 * The default is 0 (automatic for each asic). 523 */ 524MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 525module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 526 527/** 528 * DOC: cg_mask (ullong) 529 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 530 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 531 */ 532MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 533module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 534 535/** 536 * DOC: pg_mask (uint) 537 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 538 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 539 */ 540MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 541module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 542 543/** 544 * DOC: sdma_phase_quantum (uint) 545 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 546 */ 547MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 548module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 549 550/** 551 * DOC: disable_cu (charp) 552 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 553 */ 554MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 555module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 556 557/** 558 * DOC: virtual_display (charp) 559 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 560 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 561 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 562 * device at 26:00.0. The default is NULL. 563 */ 564MODULE_PARM_DESC(virtual_display, 565 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 566module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 567 568/** 569 * DOC: lbpw (int) 570 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 571 */ 572MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 573module_param_named(lbpw, amdgpu_lbpw, int, 0444); 574 575MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 576module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 577 578/** 579 * DOC: gpu_recovery (int) 580 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 581 */ 582MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 583module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 584 585/** 586 * DOC: emu_mode (int) 587 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 588 */ 589MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 590module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 591 592/** 593 * DOC: ras_enable (int) 594 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 595 */ 596MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 597module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 598 599/** 600 * DOC: ras_mask (uint) 601 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 602 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 603 */ 604MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 605module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 606 607/** 608 * DOC: timeout_fatal_disable (bool) 609 * Disable Watchdog timeout fatal error event 610 */ 611MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 612module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 613 614/** 615 * DOC: timeout_period (uint) 616 * Modify the watchdog timeout max_cycles as (1 << period) 617 */ 618MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 619module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 620 621/** 622 * DOC: si_support (int) 623 * 1 = enabled, 0 = disabled, -1 = default 624 * 625 * SI (Southern Islands) are first generation GCN GPUs, supported by both 626 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 627 * amdgpu should support SI. 628 * By default, SI dedicated GPUs are supported by amdgpu. 629 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 630 * See also radeon.si_support which should be disabled when amdgpu.si_support is 631 * enabled, and vice versa. 632 */ 633int amdgpu_si_support = -1; 634#ifdef CONFIG_DRM_AMDGPU_SI 635MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 636module_param_named(si_support, amdgpu_si_support, int, 0444); 637#endif 638 639/** 640 * DOC: cik_support (int) 641 * 1 = enabled, 0 = disabled, -1 = default 642 * 643 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 644 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 645 * amdgpu should support CIK. 646 * By default: 647 * - CIK dedicated GPUs are supported by amdgpu. 648 * - CIK APUs are supported by radeon (except when radeon is not built). 649 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 650 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 651 * enabled, and vice versa. 652 */ 653int amdgpu_cik_support = -1; 654#ifdef CONFIG_DRM_AMDGPU_CIK 655MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 656module_param_named(cik_support, amdgpu_cik_support, int, 0444); 657#endif 658 659/** 660 * DOC: smu_memory_pool_size (uint) 661 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 662 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 663 */ 664MODULE_PARM_DESC(smu_memory_pool_size, 665 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 666module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 667 668/** 669 * DOC: async_gfx_ring (int) 670 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 671 */ 672MODULE_PARM_DESC(async_gfx_ring, 673 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 674module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 675 676/** 677 * DOC: mcbp (int) 678 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 679 */ 680MODULE_PARM_DESC(mcbp, 681 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 682module_param_named(mcbp, amdgpu_mcbp, int, 0444); 683 684/** 685 * DOC: discovery (int) 686 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 687 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 688 */ 689MODULE_PARM_DESC(discovery, 690 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 691module_param_named(discovery, amdgpu_discovery, int, 0444); 692 693/** 694 * DOC: mes (int) 695 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 696 * (0 = disabled (default), 1 = enabled) 697 */ 698MODULE_PARM_DESC(mes, 699 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 700module_param_named(mes, amdgpu_mes, int, 0444); 701 702/** 703 * DOC: mes_log_enable (int) 704 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 705 * (0 = disabled (default), 1 = enabled) 706 */ 707MODULE_PARM_DESC(mes_log_enable, 708 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 709module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 710 711/** 712 * DOC: mes_kiq (int) 713 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 714 * (0 = disabled (default), 1 = enabled) 715 */ 716MODULE_PARM_DESC(mes_kiq, 717 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 718module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 719 720/** 721 * DOC: uni_mes (int) 722 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 723 * (0 = disabled (default), 1 = enabled) 724 */ 725MODULE_PARM_DESC(uni_mes, 726 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 727module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 728 729/** 730 * DOC: noretry (int) 731 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 732 * do not support per-process XNACK this also disables retry page faults. 733 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 734 */ 735MODULE_PARM_DESC(noretry, 736 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 737module_param_named(noretry, amdgpu_noretry, int, 0644); 738 739/** 740 * DOC: force_asic_type (int) 741 * A non negative value used to specify the asic type for all supported GPUs. 742 */ 743MODULE_PARM_DESC(force_asic_type, 744 "A non negative value used to specify the asic type for all supported GPUs"); 745module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 746 747/** 748 * DOC: use_xgmi_p2p (int) 749 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 750 */ 751MODULE_PARM_DESC(use_xgmi_p2p, 752 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 753module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 754 755 756#ifdef CONFIG_HSA_AMD 757/** 758 * DOC: sched_policy (int) 759 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 760 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 761 * assigns queues to HQDs. 762 */ 763int sched_policy = KFD_SCHED_POLICY_HWS; 764module_param_unsafe(sched_policy, int, 0444); 765MODULE_PARM_DESC(sched_policy, 766 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 767 768/** 769 * DOC: hws_max_conc_proc (int) 770 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 771 * number of VMIDs assigned to the HWS, which is also the default. 772 */ 773int hws_max_conc_proc = -1; 774module_param(hws_max_conc_proc, int, 0444); 775MODULE_PARM_DESC(hws_max_conc_proc, 776 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 777 778/** 779 * DOC: cwsr_enable (int) 780 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 781 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 782 * disables it. 783 */ 784int cwsr_enable = 1; 785module_param(cwsr_enable, int, 0444); 786MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 787 788/** 789 * DOC: max_num_of_queues_per_device (int) 790 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 791 * is 4096. 792 */ 793int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 794module_param(max_num_of_queues_per_device, int, 0444); 795MODULE_PARM_DESC(max_num_of_queues_per_device, 796 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 797 798/** 799 * DOC: send_sigterm (int) 800 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 801 * but just print errors on dmesg. Setting 1 enables sending sigterm. 802 */ 803int send_sigterm; 804module_param(send_sigterm, int, 0444); 805MODULE_PARM_DESC(send_sigterm, 806 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 807 808/** 809 * DOC: halt_if_hws_hang (int) 810 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 811 * Setting 1 enables halt on hang. 812 */ 813int halt_if_hws_hang; 814module_param_unsafe(halt_if_hws_hang, int, 0644); 815MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 816 817/** 818 * DOC: hws_gws_support(bool) 819 * Assume that HWS supports GWS barriers regardless of what firmware version 820 * check says. Default value: false (rely on MEC2 firmware version check). 821 */ 822bool hws_gws_support; 823module_param_unsafe(hws_gws_support, bool, 0444); 824MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 825 826/** 827 * DOC: queue_preemption_timeout_ms (int) 828 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 829 */ 830int queue_preemption_timeout_ms = 9000; 831module_param(queue_preemption_timeout_ms, int, 0644); 832MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 833 834/** 835 * DOC: debug_evictions(bool) 836 * Enable extra debug messages to help determine the cause of evictions 837 */ 838bool debug_evictions; 839module_param(debug_evictions, bool, 0644); 840MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 841 842/** 843 * DOC: no_system_mem_limit(bool) 844 * Disable system memory limit, to support multiple process shared memory 845 */ 846bool no_system_mem_limit; 847module_param(no_system_mem_limit, bool, 0644); 848MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 849 850/** 851 * DOC: no_queue_eviction_on_vm_fault (int) 852 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 853 */ 854int amdgpu_no_queue_eviction_on_vm_fault; 855MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 856module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 857#endif 858 859/** 860 * DOC: mtype_local (int) 861 */ 862int amdgpu_mtype_local; 863MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 864module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 865 866/** 867 * DOC: pcie_p2p (bool) 868 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 869 */ 870#ifdef CONFIG_HSA_AMD_P2P 871bool pcie_p2p = true; 872module_param(pcie_p2p, bool, 0444); 873MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 874#endif 875 876/** 877 * DOC: dcfeaturemask (uint) 878 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 879 * The default is the current set of stable display features. 880 */ 881MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 882module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 883 884/** 885 * DOC: dcdebugmask (uint) 886 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 887 */ 888MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 889module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 890 891MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 892module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 893 894/** 895 * DOC: abmlevel (uint) 896 * Override the default ABM (Adaptive Backlight Management) level used for DC 897 * enabled hardware. Requires DMCU to be supported and loaded. 898 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 899 * default. Values 1-4 control the maximum allowable brightness reduction via 900 * the ABM algorithm, with 1 being the least reduction and 4 being the most 901 * reduction. 902 * 903 * Defaults to -1, or auto. Userspace can only override this level after 904 * boot if it's set to auto. 905 */ 906int amdgpu_dm_abm_level = -1; 907MODULE_PARM_DESC(abmlevel, 908 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 909module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 910 911int amdgpu_backlight = -1; 912MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 913module_param_named(backlight, amdgpu_backlight, bint, 0444); 914 915/** 916 * DOC: damageclips (int) 917 * Enable or disable damage clips support. If damage clips support is disabled, 918 * we will force full frame updates, irrespective of what user space sends to 919 * us. 920 * 921 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 922 */ 923MODULE_PARM_DESC(damageclips, 924 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 925module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 926 927/** 928 * DOC: tmz (int) 929 * Trusted Memory Zone (TMZ) is a method to protect data being written 930 * to or read from memory. 931 * 932 * The default value: 0 (off). TODO: change to auto till it is completed. 933 */ 934MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 935module_param_named(tmz, amdgpu_tmz, int, 0444); 936 937/** 938 * DOC: freesync_video (uint) 939 * Enable the optimization to adjust front porch timing to achieve seamless 940 * mode change experience when setting a freesync supported mode for which full 941 * modeset is not needed. 942 * 943 * The Display Core will add a set of modes derived from the base FreeSync 944 * video mode into the corresponding connector's mode list based on commonly 945 * used refresh rates and VRR range of the connected display, when users enable 946 * this feature. From the userspace perspective, they can see a seamless mode 947 * change experience when the change between different refresh rates under the 948 * same resolution. Additionally, userspace applications such as Video playback 949 * can read this modeset list and change the refresh rate based on the video 950 * frame rate. Finally, the userspace can also derive an appropriate mode for a 951 * particular refresh rate based on the FreeSync Mode and add it to the 952 * connector's mode list. 953 * 954 * Note: This is an experimental feature. 955 * 956 * The default value: 0 (off). 957 */ 958MODULE_PARM_DESC( 959 freesync_video, 960 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 961module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 962 963/** 964 * DOC: reset_method (int) 965 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 966 */ 967MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 968module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 969 970/** 971 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 972 * threshold value of faulty pages detected by RAS ECC, which may 973 * result in the GPU entering bad status when the number of total 974 * faulty pages by ECC exceeds the threshold value. 975 */ 976MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 977module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 978 979MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 980module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 981 982/** 983 * DOC: vcnfw_log (int) 984 * Enable vcnfw log output for debugging, the default is disabled. 985 */ 986MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 987module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 988 989/** 990 * DOC: sg_display (int) 991 * Disable S/G (scatter/gather) display (i.e., display from system memory). 992 * This option is only relevant on APUs. Set this option to 0 to disable 993 * S/G display if you experience flickering or other issues under memory 994 * pressure and report the issue. 995 */ 996MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 997module_param_named(sg_display, amdgpu_sg_display, int, 0444); 998 999/** 1000 * DOC: umsch_mm (int) 1001 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1002 * (0 = disabled (default), 1 = enabled) 1003 */ 1004MODULE_PARM_DESC(umsch_mm, 1005 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1006module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1007 1008/** 1009 * DOC: umsch_mm_fwlog (int) 1010 * Enable umschfw log output for debugging, the default is disabled. 1011 */ 1012MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1013module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1014 1015/** 1016 * DOC: smu_pptable_id (int) 1017 * Used to override pptable id. id = 0 use VBIOS pptable. 1018 * id > 0 use the soft pptable with specicfied id. 1019 */ 1020MODULE_PARM_DESC(smu_pptable_id, 1021 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1022module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1023 1024/** 1025 * DOC: partition_mode (int) 1026 * Used to override the default SPX mode. 1027 */ 1028MODULE_PARM_DESC( 1029 user_partt_mode, 1030 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1031 0 = AMDGPU_SPX_PARTITION_MODE, \ 1032 1 = AMDGPU_DPX_PARTITION_MODE, \ 1033 2 = AMDGPU_TPX_PARTITION_MODE, \ 1034 3 = AMDGPU_QPX_PARTITION_MODE, \ 1035 4 = AMDGPU_CPX_PARTITION_MODE)"); 1036module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1037 1038 1039/** 1040 * DOC: enforce_isolation (int) 1041 * enforce process isolation between graphics and compute. 1042 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1043 */ 1044module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1045MODULE_PARM_DESC(enforce_isolation, 1046"enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1047 1048/** 1049 * DOC: modeset (int) 1050 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1051 */ 1052MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1053module_param_named(modeset, amdgpu_modeset, int, 0444); 1054 1055/** 1056 * DOC: seamless (int) 1057 * Seamless boot will keep the image on the screen during the boot process. 1058 */ 1059MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1060module_param_named(seamless, amdgpu_seamless, int, 0444); 1061 1062/** 1063 * DOC: debug_mask (uint) 1064 * Debug options for amdgpu, work as a binary mask with the following options: 1065 * 1066 * - 0x1: Debug VM handling 1067 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1068 * limits the VRAM size reported to ROCm applications to the visible 1069 * size, usually 256MB. 1070 * - 0x4: Disable GPU soft recovery, always do a full reset 1071 * - 0x8: Use VRAM for firmware loading 1072 * - 0x10: Enable ACA based RAS logging 1073 * - 0x20: Enable experimental resets 1074 * - 0x40: Disable ring resets 1075 * - 0x80: Use VRAM for SMU pool 1076 */ 1077MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1078module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1079 1080/** 1081 * DOC: agp (int) 1082 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1083 * address space for direct access to system memory. Note that these accesses 1084 * are non-snooped, so they are only used for access to uncached memory. 1085 */ 1086MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1087module_param_named(agp, amdgpu_agp, int, 0444); 1088 1089/** 1090 * DOC: wbrf (int) 1091 * Enable Wifi RFI interference mitigation feature. 1092 * Due to electrical and mechanical constraints there may be likely interference of 1093 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1094 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1095 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1096 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1097 * P-state transition. However, there may be potential performance impact with this 1098 * feature enabled. 1099 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1100 */ 1101MODULE_PARM_DESC(wbrf, 1102 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1103module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1104 1105/** 1106 * DOC: rebar (int) 1107 * Allow BAR resizing. Disable this to prevent the driver from attempting 1108 * to resize the BAR if the GPU supports it and there is available MMIO space. 1109 * Note that this just prevents the driver from resizing the BAR. The BIOS 1110 * may have already resized the BAR at boot time. 1111 */ 1112MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1113module_param_named(rebar, amdgpu_rebar, int, 0444); 1114 1115/** 1116 * DOC: user_queue (int) 1117 * Enable user queues on systems that support user queues. Possible values: 1118 * 1119 * - -1 = auto (ASIC specific default) 1120 * - 0 = user queues disabled 1121 * - 1 = user queues enabled and kernel queues enabled (if supported) 1122 * - 2 = user queues enabled and kernel queues disabled 1123 */ 1124MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1125module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1126 1127/* 1128 * DOC: hdmi_hpd_debounce_delay_ms (uint) 1129 * HDMI HPD disconnect debounce delay in milliseconds. 1130 * 1131 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1132 * generate while entering/leaving power save. Set to 0 to disable by default. 1133 */ 1134MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1135module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1136 1137/* These devices are not supported by amdgpu. 1138 * They are supported by the mach64, r128, radeon drivers 1139 */ 1140static const u16 amdgpu_unsupported_pciidlist[] = { 1141 /* mach64 */ 1142 0x4354, 1143 0x4358, 1144 0x4554, 1145 0x4742, 1146 0x4744, 1147 0x4749, 1148 0x474C, 1149 0x474D, 1150 0x474E, 1151 0x474F, 1152 0x4750, 1153 0x4751, 1154 0x4752, 1155 0x4753, 1156 0x4754, 1157 0x4755, 1158 0x4756, 1159 0x4757, 1160 0x4758, 1161 0x4759, 1162 0x475A, 1163 0x4C42, 1164 0x4C44, 1165 0x4C47, 1166 0x4C49, 1167 0x4C4D, 1168 0x4C4E, 1169 0x4C50, 1170 0x4C51, 1171 0x4C52, 1172 0x4C53, 1173 0x5654, 1174 0x5655, 1175 0x5656, 1176 /* r128 */ 1177 0x4c45, 1178 0x4c46, 1179 0x4d46, 1180 0x4d4c, 1181 0x5041, 1182 0x5042, 1183 0x5043, 1184 0x5044, 1185 0x5045, 1186 0x5046, 1187 0x5047, 1188 0x5048, 1189 0x5049, 1190 0x504A, 1191 0x504B, 1192 0x504C, 1193 0x504D, 1194 0x504E, 1195 0x504F, 1196 0x5050, 1197 0x5051, 1198 0x5052, 1199 0x5053, 1200 0x5054, 1201 0x5055, 1202 0x5056, 1203 0x5057, 1204 0x5058, 1205 0x5245, 1206 0x5246, 1207 0x5247, 1208 0x524b, 1209 0x524c, 1210 0x534d, 1211 0x5446, 1212 0x544C, 1213 0x5452, 1214 /* radeon */ 1215 0x3150, 1216 0x3151, 1217 0x3152, 1218 0x3154, 1219 0x3155, 1220 0x3E50, 1221 0x3E54, 1222 0x4136, 1223 0x4137, 1224 0x4144, 1225 0x4145, 1226 0x4146, 1227 0x4147, 1228 0x4148, 1229 0x4149, 1230 0x414A, 1231 0x414B, 1232 0x4150, 1233 0x4151, 1234 0x4152, 1235 0x4153, 1236 0x4154, 1237 0x4155, 1238 0x4156, 1239 0x4237, 1240 0x4242, 1241 0x4336, 1242 0x4337, 1243 0x4437, 1244 0x4966, 1245 0x4967, 1246 0x4A48, 1247 0x4A49, 1248 0x4A4A, 1249 0x4A4B, 1250 0x4A4C, 1251 0x4A4D, 1252 0x4A4E, 1253 0x4A4F, 1254 0x4A50, 1255 0x4A54, 1256 0x4B48, 1257 0x4B49, 1258 0x4B4A, 1259 0x4B4B, 1260 0x4B4C, 1261 0x4C57, 1262 0x4C58, 1263 0x4C59, 1264 0x4C5A, 1265 0x4C64, 1266 0x4C66, 1267 0x4C67, 1268 0x4E44, 1269 0x4E45, 1270 0x4E46, 1271 0x4E47, 1272 0x4E48, 1273 0x4E49, 1274 0x4E4A, 1275 0x4E4B, 1276 0x4E50, 1277 0x4E51, 1278 0x4E52, 1279 0x4E53, 1280 0x4E54, 1281 0x4E56, 1282 0x5144, 1283 0x5145, 1284 0x5146, 1285 0x5147, 1286 0x5148, 1287 0x514C, 1288 0x514D, 1289 0x5157, 1290 0x5158, 1291 0x5159, 1292 0x515A, 1293 0x515E, 1294 0x5460, 1295 0x5462, 1296 0x5464, 1297 0x5548, 1298 0x5549, 1299 0x554A, 1300 0x554B, 1301 0x554C, 1302 0x554D, 1303 0x554E, 1304 0x554F, 1305 0x5550, 1306 0x5551, 1307 0x5552, 1308 0x5554, 1309 0x564A, 1310 0x564B, 1311 0x564F, 1312 0x5652, 1313 0x5653, 1314 0x5657, 1315 0x5834, 1316 0x5835, 1317 0x5954, 1318 0x5955, 1319 0x5974, 1320 0x5975, 1321 0x5960, 1322 0x5961, 1323 0x5962, 1324 0x5964, 1325 0x5965, 1326 0x5969, 1327 0x5a41, 1328 0x5a42, 1329 0x5a61, 1330 0x5a62, 1331 0x5b60, 1332 0x5b62, 1333 0x5b63, 1334 0x5b64, 1335 0x5b65, 1336 0x5c61, 1337 0x5c63, 1338 0x5d48, 1339 0x5d49, 1340 0x5d4a, 1341 0x5d4c, 1342 0x5d4d, 1343 0x5d4e, 1344 0x5d4f, 1345 0x5d50, 1346 0x5d52, 1347 0x5d57, 1348 0x5e48, 1349 0x5e4a, 1350 0x5e4b, 1351 0x5e4c, 1352 0x5e4d, 1353 0x5e4f, 1354 0x6700, 1355 0x6701, 1356 0x6702, 1357 0x6703, 1358 0x6704, 1359 0x6705, 1360 0x6706, 1361 0x6707, 1362 0x6708, 1363 0x6709, 1364 0x6718, 1365 0x6719, 1366 0x671c, 1367 0x671d, 1368 0x671f, 1369 0x6720, 1370 0x6721, 1371 0x6722, 1372 0x6723, 1373 0x6724, 1374 0x6725, 1375 0x6726, 1376 0x6727, 1377 0x6728, 1378 0x6729, 1379 0x6738, 1380 0x6739, 1381 0x673e, 1382 0x6740, 1383 0x6741, 1384 0x6742, 1385 0x6743, 1386 0x6744, 1387 0x6745, 1388 0x6746, 1389 0x6747, 1390 0x6748, 1391 0x6749, 1392 0x674A, 1393 0x6750, 1394 0x6751, 1395 0x6758, 1396 0x6759, 1397 0x675B, 1398 0x675D, 1399 0x675F, 1400 0x6760, 1401 0x6761, 1402 0x6762, 1403 0x6763, 1404 0x6764, 1405 0x6765, 1406 0x6766, 1407 0x6767, 1408 0x6768, 1409 0x6770, 1410 0x6771, 1411 0x6772, 1412 0x6778, 1413 0x6779, 1414 0x677B, 1415 0x6840, 1416 0x6841, 1417 0x6842, 1418 0x6843, 1419 0x6849, 1420 0x684C, 1421 0x6850, 1422 0x6858, 1423 0x6859, 1424 0x6880, 1425 0x6888, 1426 0x6889, 1427 0x688A, 1428 0x688C, 1429 0x688D, 1430 0x6898, 1431 0x6899, 1432 0x689b, 1433 0x689c, 1434 0x689d, 1435 0x689e, 1436 0x68a0, 1437 0x68a1, 1438 0x68a8, 1439 0x68a9, 1440 0x68b0, 1441 0x68b8, 1442 0x68b9, 1443 0x68ba, 1444 0x68be, 1445 0x68bf, 1446 0x68c0, 1447 0x68c1, 1448 0x68c7, 1449 0x68c8, 1450 0x68c9, 1451 0x68d8, 1452 0x68d9, 1453 0x68da, 1454 0x68de, 1455 0x68e0, 1456 0x68e1, 1457 0x68e4, 1458 0x68e5, 1459 0x68e8, 1460 0x68e9, 1461 0x68f1, 1462 0x68f2, 1463 0x68f8, 1464 0x68f9, 1465 0x68fa, 1466 0x68fe, 1467 0x7100, 1468 0x7101, 1469 0x7102, 1470 0x7103, 1471 0x7104, 1472 0x7105, 1473 0x7106, 1474 0x7108, 1475 0x7109, 1476 0x710A, 1477 0x710B, 1478 0x710C, 1479 0x710E, 1480 0x710F, 1481 0x7140, 1482 0x7141, 1483 0x7142, 1484 0x7143, 1485 0x7144, 1486 0x7145, 1487 0x7146, 1488 0x7147, 1489 0x7149, 1490 0x714A, 1491 0x714B, 1492 0x714C, 1493 0x714D, 1494 0x714E, 1495 0x714F, 1496 0x7151, 1497 0x7152, 1498 0x7153, 1499 0x715E, 1500 0x715F, 1501 0x7180, 1502 0x7181, 1503 0x7183, 1504 0x7186, 1505 0x7187, 1506 0x7188, 1507 0x718A, 1508 0x718B, 1509 0x718C, 1510 0x718D, 1511 0x718F, 1512 0x7193, 1513 0x7196, 1514 0x719B, 1515 0x719F, 1516 0x71C0, 1517 0x71C1, 1518 0x71C2, 1519 0x71C3, 1520 0x71C4, 1521 0x71C5, 1522 0x71C6, 1523 0x71C7, 1524 0x71CD, 1525 0x71CE, 1526 0x71D2, 1527 0x71D4, 1528 0x71D5, 1529 0x71D6, 1530 0x71DA, 1531 0x71DE, 1532 0x7200, 1533 0x7210, 1534 0x7211, 1535 0x7240, 1536 0x7243, 1537 0x7244, 1538 0x7245, 1539 0x7246, 1540 0x7247, 1541 0x7248, 1542 0x7249, 1543 0x724A, 1544 0x724B, 1545 0x724C, 1546 0x724D, 1547 0x724E, 1548 0x724F, 1549 0x7280, 1550 0x7281, 1551 0x7283, 1552 0x7284, 1553 0x7287, 1554 0x7288, 1555 0x7289, 1556 0x728B, 1557 0x728C, 1558 0x7290, 1559 0x7291, 1560 0x7293, 1561 0x7297, 1562 0x7834, 1563 0x7835, 1564 0x791e, 1565 0x791f, 1566 0x793f, 1567 0x7941, 1568 0x7942, 1569 0x796c, 1570 0x796d, 1571 0x796e, 1572 0x796f, 1573 0x9400, 1574 0x9401, 1575 0x9402, 1576 0x9403, 1577 0x9405, 1578 0x940A, 1579 0x940B, 1580 0x940F, 1581 0x94A0, 1582 0x94A1, 1583 0x94A3, 1584 0x94B1, 1585 0x94B3, 1586 0x94B4, 1587 0x94B5, 1588 0x94B9, 1589 0x9440, 1590 0x9441, 1591 0x9442, 1592 0x9443, 1593 0x9444, 1594 0x9446, 1595 0x944A, 1596 0x944B, 1597 0x944C, 1598 0x944E, 1599 0x9450, 1600 0x9452, 1601 0x9456, 1602 0x945A, 1603 0x945B, 1604 0x945E, 1605 0x9460, 1606 0x9462, 1607 0x946A, 1608 0x946B, 1609 0x947A, 1610 0x947B, 1611 0x9480, 1612 0x9487, 1613 0x9488, 1614 0x9489, 1615 0x948A, 1616 0x948F, 1617 0x9490, 1618 0x9491, 1619 0x9495, 1620 0x9498, 1621 0x949C, 1622 0x949E, 1623 0x949F, 1624 0x94C0, 1625 0x94C1, 1626 0x94C3, 1627 0x94C4, 1628 0x94C5, 1629 0x94C6, 1630 0x94C7, 1631 0x94C8, 1632 0x94C9, 1633 0x94CB, 1634 0x94CC, 1635 0x94CD, 1636 0x9500, 1637 0x9501, 1638 0x9504, 1639 0x9505, 1640 0x9506, 1641 0x9507, 1642 0x9508, 1643 0x9509, 1644 0x950F, 1645 0x9511, 1646 0x9515, 1647 0x9517, 1648 0x9519, 1649 0x9540, 1650 0x9541, 1651 0x9542, 1652 0x954E, 1653 0x954F, 1654 0x9552, 1655 0x9553, 1656 0x9555, 1657 0x9557, 1658 0x955f, 1659 0x9580, 1660 0x9581, 1661 0x9583, 1662 0x9586, 1663 0x9587, 1664 0x9588, 1665 0x9589, 1666 0x958A, 1667 0x958B, 1668 0x958C, 1669 0x958D, 1670 0x958E, 1671 0x958F, 1672 0x9590, 1673 0x9591, 1674 0x9593, 1675 0x9595, 1676 0x9596, 1677 0x9597, 1678 0x9598, 1679 0x9599, 1680 0x959B, 1681 0x95C0, 1682 0x95C2, 1683 0x95C4, 1684 0x95C5, 1685 0x95C6, 1686 0x95C7, 1687 0x95C9, 1688 0x95CC, 1689 0x95CD, 1690 0x95CE, 1691 0x95CF, 1692 0x9610, 1693 0x9611, 1694 0x9612, 1695 0x9613, 1696 0x9614, 1697 0x9615, 1698 0x9616, 1699 0x9640, 1700 0x9641, 1701 0x9642, 1702 0x9643, 1703 0x9644, 1704 0x9645, 1705 0x9647, 1706 0x9648, 1707 0x9649, 1708 0x964a, 1709 0x964b, 1710 0x964c, 1711 0x964e, 1712 0x964f, 1713 0x9710, 1714 0x9711, 1715 0x9712, 1716 0x9713, 1717 0x9714, 1718 0x9715, 1719 0x9802, 1720 0x9803, 1721 0x9804, 1722 0x9805, 1723 0x9806, 1724 0x9807, 1725 0x9808, 1726 0x9809, 1727 0x980A, 1728 0x9900, 1729 0x9901, 1730 0x9903, 1731 0x9904, 1732 0x9905, 1733 0x9906, 1734 0x9907, 1735 0x9908, 1736 0x9909, 1737 0x990A, 1738 0x990B, 1739 0x990C, 1740 0x990D, 1741 0x990E, 1742 0x990F, 1743 0x9910, 1744 0x9913, 1745 0x9917, 1746 0x9918, 1747 0x9919, 1748 0x9990, 1749 0x9991, 1750 0x9992, 1751 0x9993, 1752 0x9994, 1753 0x9995, 1754 0x9996, 1755 0x9997, 1756 0x9998, 1757 0x9999, 1758 0x999A, 1759 0x999B, 1760 0x999C, 1761 0x999D, 1762 0x99A0, 1763 0x99A2, 1764 0x99A4, 1765 /* radeon secondary ids */ 1766 0x3171, 1767 0x3e70, 1768 0x4164, 1769 0x4165, 1770 0x4166, 1771 0x4168, 1772 0x4170, 1773 0x4171, 1774 0x4172, 1775 0x4173, 1776 0x496e, 1777 0x4a69, 1778 0x4a6a, 1779 0x4a6b, 1780 0x4a70, 1781 0x4a74, 1782 0x4b69, 1783 0x4b6b, 1784 0x4b6c, 1785 0x4c6e, 1786 0x4e64, 1787 0x4e65, 1788 0x4e66, 1789 0x4e67, 1790 0x4e68, 1791 0x4e69, 1792 0x4e6a, 1793 0x4e71, 1794 0x4f73, 1795 0x5569, 1796 0x556b, 1797 0x556d, 1798 0x556f, 1799 0x5571, 1800 0x5854, 1801 0x5874, 1802 0x5940, 1803 0x5941, 1804 0x5b70, 1805 0x5b72, 1806 0x5b73, 1807 0x5b74, 1808 0x5b75, 1809 0x5d44, 1810 0x5d45, 1811 0x5d6d, 1812 0x5d6f, 1813 0x5d72, 1814 0x5d77, 1815 0x5e6b, 1816 0x5e6d, 1817 0x7120, 1818 0x7124, 1819 0x7129, 1820 0x712e, 1821 0x712f, 1822 0x7162, 1823 0x7163, 1824 0x7166, 1825 0x7167, 1826 0x7172, 1827 0x7173, 1828 0x71a0, 1829 0x71a1, 1830 0x71a3, 1831 0x71a7, 1832 0x71bb, 1833 0x71e0, 1834 0x71e1, 1835 0x71e2, 1836 0x71e6, 1837 0x71e7, 1838 0x71f2, 1839 0x7269, 1840 0x726b, 1841 0x726e, 1842 0x72a0, 1843 0x72a8, 1844 0x72b1, 1845 0x72b3, 1846 0x793f, 1847}; 1848 1849static const struct pci_device_id pciidlist[] = { 1850 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1851 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1852 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1853 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1854 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1855 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1856 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1857 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1858 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1859 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1860 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1861 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1862 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1863 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1867 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1868 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1869 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1870 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1871 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1872 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1873 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1874 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1875 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1879 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1884 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1885 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1886 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1887 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1888 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1889 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1890 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1891 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1892 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1894 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1899 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1900 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1901 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1902 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1903 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1904 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1905 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1906 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1907 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1908 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1909 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1910 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1911 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1912 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1913 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1914 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1915 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1916 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1917 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1918 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1919 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1920 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1921 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1922 /* Kaveri */ 1923 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1925 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1934 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1935 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1936 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1937 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1938 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1939 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1940 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1943 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1944 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1945 /* Bonaire */ 1946 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1947 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1948 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1949 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1950 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1951 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1952 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1953 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1954 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1955 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1956 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1957 /* Hawaii */ 1958 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1959 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1960 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1961 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1962 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1963 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1964 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1965 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1966 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1967 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1968 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1969 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1970 /* Kabini */ 1971 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1972 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1973 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1974 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1975 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1976 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1977 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1978 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1979 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1980 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1981 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1982 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1984 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1985 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1986 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1987 /* mullins */ 1988 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1992 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1993 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1994 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1995 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1996 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1997 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1998 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1999 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 2000 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 2001 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 2002 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 2003 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 2004 /* topaz */ 2005 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2006 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2007 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2008 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2009 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2010 /* tonga */ 2011 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2012 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2013 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2014 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2015 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2016 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2017 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2018 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2019 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2020 /* fiji */ 2021 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2022 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2023 /* carrizo */ 2024 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2025 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2026 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2027 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2028 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2029 /* stoney */ 2030 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2031 /* Polaris11 */ 2032 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2033 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2034 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2035 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2036 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2037 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2038 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2039 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2040 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2041 /* Polaris10 */ 2042 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2043 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2044 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2045 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2046 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2047 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2048 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2049 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2050 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2051 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2052 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2053 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2054 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2055 /* Polaris12 */ 2056 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2057 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2058 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2059 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2060 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2061 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2062 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2063 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2064 /* VEGAM */ 2065 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2066 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2067 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2068 /* Vega 10 */ 2069 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2072 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2073 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2074 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2075 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2076 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2077 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2078 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2079 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2080 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2081 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2082 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2083 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2084 /* Vega 12 */ 2085 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2086 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2087 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2088 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2089 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2090 /* Vega 20 */ 2091 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2092 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2093 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2094 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2095 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2096 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2097 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2098 /* Raven */ 2099 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2100 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2101 /* Arcturus */ 2102 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2103 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2104 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2105 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2106 /* Navi10 */ 2107 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2108 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2109 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2110 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2111 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2112 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2113 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2114 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2115 /* Navi14 */ 2116 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2117 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2118 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2119 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2120 2121 /* Renoir */ 2122 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2123 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2124 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2125 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2126 2127 /* Navi12 */ 2128 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2129 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2130 2131 /* Sienna_Cichlid */ 2132 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2133 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2134 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2135 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2136 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2137 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2138 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2139 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2140 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2141 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2142 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2143 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2144 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2145 2146 /* Yellow Carp */ 2147 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2148 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2149 2150 /* Navy_Flounder */ 2151 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2152 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2153 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2154 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2155 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2156 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2157 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2158 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2159 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2160 2161 /* DIMGREY_CAVEFISH */ 2162 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2163 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2164 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2165 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2166 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2167 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2168 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2169 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2170 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2171 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2172 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2173 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2174 2175 /* Aldebaran */ 2176 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2177 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2178 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2179 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2180 2181 /* CYAN_SKILLFISH */ 2182 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2183 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2184 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2185 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2186 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2187 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2188 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2189 2190 /* BEIGE_GOBY */ 2191 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2192 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2193 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2194 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2195 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2196 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2197 2198 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2199 .class = PCI_CLASS_DISPLAY_VGA << 8, 2200 .class_mask = 0xffffff, 2201 .driver_data = CHIP_IP_DISCOVERY }, 2202 2203 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2204 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2205 .class_mask = 0xffffff, 2206 .driver_data = CHIP_IP_DISCOVERY }, 2207 2208 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2209 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2210 .class_mask = 0xffffff, 2211 .driver_data = CHIP_IP_DISCOVERY }, 2212 2213 {0, 0, 0} 2214}; 2215 2216MODULE_DEVICE_TABLE(pci, pciidlist); 2217 2218static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2219 /* differentiate between P10 and P11 asics with the same DID */ 2220 {0x67FF, 0xE3, CHIP_POLARIS10}, 2221 {0x67FF, 0xE7, CHIP_POLARIS10}, 2222 {0x67FF, 0xF3, CHIP_POLARIS10}, 2223 {0x67FF, 0xF7, CHIP_POLARIS10}, 2224}; 2225 2226static const struct drm_driver amdgpu_kms_driver; 2227 2228static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2229{ 2230 struct pci_dev *p = NULL; 2231 int i; 2232 2233 /* 0 - GPU 2234 * 1 - audio 2235 * 2 - USB 2236 * 3 - UCSI 2237 */ 2238 for (i = 1; i < 4; i++) { 2239 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2240 adev->pdev->bus->number, i); 2241 if (p) { 2242 pm_runtime_get_sync(&p->dev); 2243 pm_runtime_put_autosuspend(&p->dev); 2244 pci_dev_put(p); 2245 } 2246 } 2247} 2248 2249static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2250{ 2251 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2252 pr_info("debug: VM handling debug enabled\n"); 2253 adev->debug_vm = true; 2254 } 2255 2256 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2257 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2258 adev->debug_largebar = true; 2259 } 2260 2261 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2262 pr_info("debug: soft reset for GPU recovery disabled\n"); 2263 adev->debug_disable_soft_recovery = true; 2264 } 2265 2266 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2267 pr_info("debug: place fw in vram for frontdoor loading\n"); 2268 adev->debug_use_vram_fw_buf = true; 2269 } 2270 2271 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2272 pr_info("debug: enable RAS ACA\n"); 2273 adev->debug_enable_ras_aca = true; 2274 } 2275 2276 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2277 pr_info("debug: enable experimental reset features\n"); 2278 adev->debug_exp_resets = true; 2279 } 2280 2281 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2282 pr_info("debug: ring reset disabled\n"); 2283 adev->debug_disable_gpu_ring_reset = true; 2284 } 2285 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2286 pr_info("debug: use vram for smu pool\n"); 2287 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2288 } 2289 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2290 pr_info("debug: VM mode debug for userptr is enabled\n"); 2291 adev->debug_vm_userptr = true; 2292 } 2293 2294 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2295 pr_info("debug: disable kernel logs of correctable errors\n"); 2296 adev->debug_disable_ce_logs = true; 2297 } 2298 2299 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2300 pr_info("debug: allowing command submission to CE engine\n"); 2301 adev->debug_enable_ce_cs = true; 2302 } 2303} 2304 2305static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2306{ 2307 int i; 2308 2309 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2310 if (pdev->device == asic_type_quirks[i].device && 2311 pdev->revision == asic_type_quirks[i].revision) { 2312 flags &= ~AMD_ASIC_MASK; 2313 flags |= asic_type_quirks[i].type; 2314 break; 2315 } 2316 } 2317 2318 return flags; 2319} 2320 2321static bool amdgpu_support_enabled(struct device *dev, 2322 const enum amd_asic_type family) 2323{ 2324 const char *gen; 2325 const char *param; 2326 int module_param = -1; 2327 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2328 bool amdgpu_support_built = false; 2329 bool support_by_default = false; 2330 2331 switch (family) { 2332 case CHIP_TAHITI: 2333 case CHIP_PITCAIRN: 2334 case CHIP_VERDE: 2335 case CHIP_OLAND: 2336 case CHIP_HAINAN: 2337 gen = "SI"; 2338 param = "si_support"; 2339 module_param = amdgpu_si_support; 2340 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2341 support_by_default = true; 2342 break; 2343 2344 case CHIP_BONAIRE: 2345 case CHIP_HAWAII: 2346 support_by_default = true; 2347 fallthrough; 2348 case CHIP_KAVERI: 2349 case CHIP_KABINI: 2350 case CHIP_MULLINS: 2351 gen = "CIK"; 2352 param = "cik_support"; 2353 module_param = amdgpu_cik_support; 2354 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2355 break; 2356 2357 default: 2358 /* All other chips are supported by amdgpu only */ 2359 return true; 2360 } 2361 2362 if (!amdgpu_support_built) { 2363 dev_info(dev, "amdgpu built without %s support\n", gen); 2364 return false; 2365 } 2366 2367 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2368 module_param == 1) { 2369 if (radeon_support_built) 2370 dev_info(dev, "%s support provided by amdgpu.\n" 2371 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2372 gen, param, param); 2373 2374 return true; 2375 } 2376 2377 if (radeon_support_built) 2378 dev_info(dev, "%s support provided by radeon.\n" 2379 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2380 gen, param, param); 2381 else if (module_param == 0) 2382 dev_info(dev, "%s support disabled by module param\n", gen); 2383 2384 return false; 2385} 2386 2387static int amdgpu_pci_probe(struct pci_dev *pdev, 2388 const struct pci_device_id *ent) 2389{ 2390 struct drm_device *ddev; 2391 struct amdgpu_device *adev; 2392 unsigned long flags = ent->driver_data; 2393 int ret, retry = 0, i; 2394 bool supports_atomic = false; 2395 2396 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2397 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2398 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2399 return -EINVAL; 2400 } 2401 2402 /* skip devices which are owned by radeon */ 2403 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2404 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2405 return -ENODEV; 2406 } 2407 2408 if (amdgpu_virtual_display || 2409 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2410 supports_atomic = true; 2411 2412 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2413 DRM_INFO("This hardware requires experimental hardware support.\n" 2414 "See modparam exp_hw_support\n"); 2415 return -ENODEV; 2416 } 2417 2418 flags = amdgpu_fix_asic_type(pdev, flags); 2419 2420 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2421 * however, SME requires an indirect IOMMU mapping because the encryption 2422 * bit is beyond the DMA mask of the chip. 2423 */ 2424 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2425 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2426 dev_info(&pdev->dev, 2427 "SME is not compatible with RAVEN\n"); 2428 return -ENOTSUPP; 2429 } 2430 2431 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2432 return -ENODEV; 2433 2434 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2435 if (IS_ERR(adev)) 2436 return PTR_ERR(adev); 2437 2438 adev->dev = &pdev->dev; 2439 adev->pdev = pdev; 2440 ddev = adev_to_drm(adev); 2441 2442 if (!supports_atomic) 2443 ddev->driver_features &= ~DRIVER_ATOMIC; 2444 2445 ret = pci_enable_device(pdev); 2446 if (ret) 2447 return ret; 2448 2449 pci_set_drvdata(pdev, ddev); 2450 2451 amdgpu_init_debug_options(adev); 2452 2453 ret = amdgpu_driver_load_kms(adev, flags); 2454 if (ret) 2455 goto err_pci; 2456 2457retry_init: 2458 ret = drm_dev_register(ddev, flags); 2459 if (ret == -EAGAIN && ++retry <= 3) { 2460 DRM_INFO("retry init %d\n", retry); 2461 /* Don't request EX mode too frequently which is attacking */ 2462 msleep(5000); 2463 goto retry_init; 2464 } else if (ret) { 2465 goto err_pci; 2466 } 2467 2468 ret = amdgpu_xcp_dev_register(adev, ent); 2469 if (ret) 2470 goto err_pci; 2471 2472 ret = amdgpu_amdkfd_drm_client_create(adev); 2473 if (ret) 2474 goto err_pci; 2475 2476 /* 2477 * 1. don't init fbdev on hw without DCE 2478 * 2. don't init fbdev if there are no connectors 2479 */ 2480 if (adev->mode_info.mode_config_initialized && 2481 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2482 const struct drm_format_info *format; 2483 2484 /* select 8 bpp console on low vram cards */ 2485 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2486 format = drm_format_info(DRM_FORMAT_C8); 2487 else 2488 format = NULL; 2489 2490 drm_client_setup(adev_to_drm(adev), format); 2491 } 2492 2493 ret = amdgpu_debugfs_init(adev); 2494 if (ret) 2495 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2496 2497 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2498 /* only need to skip on ATPX */ 2499 if (amdgpu_device_supports_px(adev)) 2500 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2501 /* we want direct complete for BOCO */ 2502 if (amdgpu_device_supports_boco(adev)) 2503 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2504 DPM_FLAG_SMART_SUSPEND | 2505 DPM_FLAG_MAY_SKIP_RESUME); 2506 pm_runtime_use_autosuspend(ddev->dev); 2507 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2508 2509 pm_runtime_allow(ddev->dev); 2510 2511 pm_runtime_put_autosuspend(ddev->dev); 2512 2513 pci_wake_from_d3(pdev, TRUE); 2514 2515 /* 2516 * For runpm implemented via BACO, PMFW will handle the 2517 * timing for BACO in and out: 2518 * - put ASIC into BACO state only when both video and 2519 * audio functions are in D3 state. 2520 * - pull ASIC out of BACO state when either video or 2521 * audio function is in D0 state. 2522 * Also, at startup, PMFW assumes both functions are in 2523 * D0 state. 2524 * 2525 * So if snd driver was loaded prior to amdgpu driver 2526 * and audio function was put into D3 state, there will 2527 * be no PMFW-aware D-state transition(D0->D3) on runpm 2528 * suspend. Thus the BACO will be not correctly kicked in. 2529 * 2530 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2531 * into D0 state. Then there will be a PMFW-aware D-state 2532 * transition(D0->D3) on runpm suspend. 2533 */ 2534 if (amdgpu_device_supports_baco(adev) && 2535 !(adev->flags & AMD_IS_APU) && 2536 adev->asic_type >= CHIP_NAVI10) 2537 amdgpu_get_secondary_funcs(adev); 2538 } 2539 2540 return 0; 2541 2542err_pci: 2543 pci_disable_device(pdev); 2544 return ret; 2545} 2546 2547static void 2548amdgpu_pci_remove(struct pci_dev *pdev) 2549{ 2550 struct drm_device *dev = pci_get_drvdata(pdev); 2551 struct amdgpu_device *adev = drm_to_adev(dev); 2552 2553 amdgpu_ras_eeprom_check_and_recover(adev); 2554 amdgpu_xcp_dev_unplug(adev); 2555 amdgpu_gmc_prepare_nps_mode_change(adev); 2556 drm_dev_unplug(dev); 2557 2558 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2559 pm_runtime_get_sync(dev->dev); 2560 pm_runtime_forbid(dev->dev); 2561 } 2562 2563 amdgpu_driver_unload_kms(dev); 2564 2565 /* 2566 * Flush any in flight DMA operations from device. 2567 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2568 * StatusTransactions Pending bit. 2569 */ 2570 pci_disable_device(pdev); 2571 pci_wait_for_pending_transaction(pdev); 2572} 2573 2574static void 2575amdgpu_pci_shutdown(struct pci_dev *pdev) 2576{ 2577 struct drm_device *dev = pci_get_drvdata(pdev); 2578 struct amdgpu_device *adev = drm_to_adev(dev); 2579 2580 if (amdgpu_ras_intr_triggered()) 2581 return; 2582 2583 /* device maybe not resumed here, return immediately in this case */ 2584 if (adev->in_s4 && adev->in_suspend) 2585 return; 2586 2587 /* if we are running in a VM, make sure the device 2588 * torn down properly on reboot/shutdown. 2589 * unfortunately we can't detect certain 2590 * hypervisors so just do this all the time. 2591 */ 2592 if (!amdgpu_passthrough(adev)) 2593 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2594 amdgpu_device_prepare(dev); 2595 amdgpu_device_suspend(dev, true); 2596 adev->mp1_state = PP_MP1_STATE_NONE; 2597} 2598 2599static int amdgpu_pmops_prepare(struct device *dev) 2600{ 2601 struct drm_device *drm_dev = dev_get_drvdata(dev); 2602 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2603 2604 /* device maybe not resumed here, return immediately in this case */ 2605 if (adev->in_s4 && adev->in_suspend) 2606 return 0; 2607 2608 /* Return a positive number here so 2609 * DPM_FLAG_SMART_SUSPEND works properly 2610 */ 2611 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2612 return 1; 2613 2614 /* if we will not support s3 or s2i for the device 2615 * then skip suspend 2616 */ 2617 if (!amdgpu_acpi_is_s0ix_active(adev) && 2618 !amdgpu_acpi_is_s3_active(adev)) 2619 return 1; 2620 2621 return amdgpu_device_prepare(drm_dev); 2622} 2623 2624static void amdgpu_pmops_complete(struct device *dev) 2625{ 2626 amdgpu_device_complete(dev_get_drvdata(dev)); 2627} 2628 2629static int amdgpu_pmops_suspend(struct device *dev) 2630{ 2631 struct drm_device *drm_dev = dev_get_drvdata(dev); 2632 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2633 2634 if (amdgpu_acpi_is_s0ix_active(adev)) 2635 adev->in_s0ix = true; 2636 else if (amdgpu_acpi_is_s3_active(adev)) 2637 adev->in_s3 = true; 2638 if (!adev->in_s0ix && !adev->in_s3) { 2639#if IS_ENABLED(CONFIG_SUSPEND) 2640 /* don't allow going deep first time followed by s2idle the next time */ 2641 if (adev->last_suspend_state != PM_SUSPEND_ON && 2642 adev->last_suspend_state != pm_suspend_target_state) { 2643 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2644 pm_suspend_target_state); 2645 return -EINVAL; 2646 } 2647#endif 2648 return 0; 2649 } 2650 2651#if IS_ENABLED(CONFIG_SUSPEND) 2652 /* cache the state last used for suspend */ 2653 adev->last_suspend_state = pm_suspend_target_state; 2654#endif 2655 2656 return amdgpu_device_suspend(drm_dev, true); 2657} 2658 2659static int amdgpu_pmops_suspend_noirq(struct device *dev) 2660{ 2661 struct drm_device *drm_dev = dev_get_drvdata(dev); 2662 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2663 int r; 2664 2665 if (amdgpu_acpi_should_gpu_reset(adev)) { 2666 amdgpu_device_lock_reset_domain(adev->reset_domain); 2667 r = amdgpu_asic_reset(adev); 2668 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2669 return r; 2670 } 2671 2672 return 0; 2673} 2674 2675static int amdgpu_pmops_resume(struct device *dev) 2676{ 2677 struct drm_device *drm_dev = dev_get_drvdata(dev); 2678 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2679 int r; 2680 2681 if (!adev->in_s0ix && !adev->in_s3) 2682 return 0; 2683 2684 /* Avoids registers access if device is physically gone */ 2685 if (!pci_device_is_present(adev->pdev)) 2686 adev->no_hw_access = true; 2687 2688 r = amdgpu_device_resume(drm_dev, true); 2689 if (amdgpu_acpi_is_s0ix_active(adev)) 2690 adev->in_s0ix = false; 2691 else 2692 adev->in_s3 = false; 2693 return r; 2694} 2695 2696static int amdgpu_pmops_freeze(struct device *dev) 2697{ 2698 struct drm_device *drm_dev = dev_get_drvdata(dev); 2699 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2700 int r; 2701 2702 r = amdgpu_device_suspend(drm_dev, true); 2703 if (r) 2704 return r; 2705 2706 if (amdgpu_acpi_should_gpu_reset(adev)) { 2707 amdgpu_device_lock_reset_domain(adev->reset_domain); 2708 r = amdgpu_asic_reset(adev); 2709 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2710 return r; 2711 } 2712 return 0; 2713} 2714 2715static int amdgpu_pmops_thaw(struct device *dev) 2716{ 2717 struct drm_device *drm_dev = dev_get_drvdata(dev); 2718 2719 /* do not resume device if it's normal hibernation */ 2720 if (console_suspend_enabled && 2721 !pm_hibernate_is_recovering() && 2722 !pm_hibernation_mode_is_suspend()) 2723 return 0; 2724 2725 return amdgpu_device_resume(drm_dev, true); 2726} 2727 2728static int amdgpu_pmops_poweroff(struct device *dev) 2729{ 2730 struct drm_device *drm_dev = dev_get_drvdata(dev); 2731 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2732 2733 /* device maybe not resumed here, return immediately in this case */ 2734 if (adev->in_s4 && adev->in_suspend) 2735 return 0; 2736 2737 return amdgpu_device_suspend(drm_dev, true); 2738} 2739 2740static int amdgpu_pmops_restore(struct device *dev) 2741{ 2742 struct drm_device *drm_dev = dev_get_drvdata(dev); 2743 2744 return amdgpu_device_resume(drm_dev, true); 2745} 2746 2747static int amdgpu_runtime_idle_check_display(struct device *dev) 2748{ 2749 struct pci_dev *pdev = to_pci_dev(dev); 2750 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2751 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2752 2753 if (adev->mode_info.num_crtc) { 2754 struct drm_connector *list_connector; 2755 struct drm_connector_list_iter iter; 2756 int ret = 0; 2757 2758 if (amdgpu_runtime_pm != -2) { 2759 /* XXX: Return busy if any displays are connected to avoid 2760 * possible display wakeups after runtime resume due to 2761 * hotplug events in case any displays were connected while 2762 * the GPU was in suspend. Remove this once that is fixed. 2763 */ 2764 mutex_lock(&drm_dev->mode_config.mutex); 2765 drm_connector_list_iter_begin(drm_dev, &iter); 2766 drm_for_each_connector_iter(list_connector, &iter) { 2767 if (list_connector->status == connector_status_connected) { 2768 ret = -EBUSY; 2769 break; 2770 } 2771 } 2772 drm_connector_list_iter_end(&iter); 2773 mutex_unlock(&drm_dev->mode_config.mutex); 2774 2775 if (ret) 2776 return ret; 2777 } 2778 2779 if (adev->dc_enabled) { 2780 struct drm_crtc *crtc; 2781 2782 drm_for_each_crtc(crtc, drm_dev) { 2783 drm_modeset_lock(&crtc->mutex, NULL); 2784 if (crtc->state->active) 2785 ret = -EBUSY; 2786 drm_modeset_unlock(&crtc->mutex); 2787 if (ret < 0) 2788 break; 2789 } 2790 } else { 2791 mutex_lock(&drm_dev->mode_config.mutex); 2792 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2793 2794 drm_connector_list_iter_begin(drm_dev, &iter); 2795 drm_for_each_connector_iter(list_connector, &iter) { 2796 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2797 ret = -EBUSY; 2798 break; 2799 } 2800 } 2801 2802 drm_connector_list_iter_end(&iter); 2803 2804 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2805 mutex_unlock(&drm_dev->mode_config.mutex); 2806 } 2807 if (ret) 2808 return ret; 2809 } 2810 2811 return 0; 2812} 2813 2814static int amdgpu_runtime_idle_check_userq(struct device *dev) 2815{ 2816 struct pci_dev *pdev = to_pci_dev(dev); 2817 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2818 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2819 2820 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2821} 2822 2823static int amdgpu_pmops_runtime_suspend(struct device *dev) 2824{ 2825 struct pci_dev *pdev = to_pci_dev(dev); 2826 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2827 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2828 int ret, i; 2829 2830 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2831 pm_runtime_forbid(dev); 2832 return -EBUSY; 2833 } 2834 2835 ret = amdgpu_runtime_idle_check_display(dev); 2836 if (ret) 2837 return ret; 2838 ret = amdgpu_runtime_idle_check_userq(dev); 2839 if (ret) 2840 return ret; 2841 2842 /* wait for all rings to drain before suspending */ 2843 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2844 struct amdgpu_ring *ring = adev->rings[i]; 2845 2846 if (ring && ring->sched.ready) { 2847 ret = amdgpu_fence_wait_empty(ring); 2848 if (ret) 2849 return -EBUSY; 2850 } 2851 } 2852 2853 adev->in_runpm = true; 2854 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2855 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2856 2857 /* 2858 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2859 * proper cleanups and put itself into a state ready for PNP. That 2860 * can address some random resuming failure observed on BOCO capable 2861 * platforms. 2862 * TODO: this may be also needed for PX capable platform. 2863 */ 2864 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2865 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2866 2867 ret = amdgpu_device_prepare(drm_dev); 2868 if (ret) 2869 return ret; 2870 ret = amdgpu_device_suspend(drm_dev, false); 2871 if (ret) { 2872 adev->in_runpm = false; 2873 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2874 adev->mp1_state = PP_MP1_STATE_NONE; 2875 return ret; 2876 } 2877 2878 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2879 adev->mp1_state = PP_MP1_STATE_NONE; 2880 2881 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2882 /* Only need to handle PCI state in the driver for ATPX 2883 * PCI core handles it for _PR3. 2884 */ 2885 amdgpu_device_cache_pci_state(pdev); 2886 pci_disable_device(pdev); 2887 pci_ignore_hotplug(pdev); 2888 pci_set_power_state(pdev, PCI_D3cold); 2889 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2890 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2891 /* nothing to do */ 2892 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2893 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2894 amdgpu_device_baco_enter(adev); 2895 } 2896 2897 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2898 2899 return 0; 2900} 2901 2902static int amdgpu_pmops_runtime_resume(struct device *dev) 2903{ 2904 struct pci_dev *pdev = to_pci_dev(dev); 2905 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2906 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2907 int ret; 2908 2909 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2910 return -EINVAL; 2911 2912 /* Avoids registers access if device is physically gone */ 2913 if (!pci_device_is_present(adev->pdev)) 2914 adev->no_hw_access = true; 2915 2916 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2917 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2918 2919 /* Only need to handle PCI state in the driver for ATPX 2920 * PCI core handles it for _PR3. 2921 */ 2922 pci_set_power_state(pdev, PCI_D0); 2923 amdgpu_device_load_pci_state(pdev); 2924 ret = pci_enable_device(pdev); 2925 if (ret) 2926 return ret; 2927 pci_set_master(pdev); 2928 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2929 /* Only need to handle PCI state in the driver for ATPX 2930 * PCI core handles it for _PR3. 2931 */ 2932 pci_set_master(pdev); 2933 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2934 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2935 amdgpu_device_baco_exit(adev); 2936 } 2937 ret = amdgpu_device_resume(drm_dev, false); 2938 if (ret) { 2939 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2940 pci_disable_device(pdev); 2941 return ret; 2942 } 2943 2944 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2945 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2946 adev->in_runpm = false; 2947 return 0; 2948} 2949 2950static int amdgpu_pmops_runtime_idle(struct device *dev) 2951{ 2952 struct drm_device *drm_dev = dev_get_drvdata(dev); 2953 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2954 int ret; 2955 2956 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2957 pm_runtime_forbid(dev); 2958 return -EBUSY; 2959 } 2960 2961 ret = amdgpu_runtime_idle_check_display(dev); 2962 if (ret) 2963 goto done; 2964 2965 ret = amdgpu_runtime_idle_check_userq(dev); 2966done: 2967 pm_runtime_autosuspend(dev); 2968 return ret; 2969} 2970 2971static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2972{ 2973 struct drm_file *file_priv = filp->private_data; 2974 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2975 struct drm_device *dev = file_priv->minor->dev; 2976 int idx; 2977 2978 if (fpriv && drm_dev_enter(dev, &idx)) { 2979 fpriv->evf_mgr.fd_closing = true; 2980 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); 2981 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2982 drm_dev_exit(idx); 2983 } 2984 2985 return drm_release(inode, filp); 2986} 2987 2988long amdgpu_drm_ioctl(struct file *filp, 2989 unsigned int cmd, unsigned long arg) 2990{ 2991 struct drm_file *file_priv = filp->private_data; 2992 struct drm_device *dev; 2993 long ret; 2994 2995 dev = file_priv->minor->dev; 2996 ret = pm_runtime_get_sync(dev->dev); 2997 if (ret < 0) 2998 goto out; 2999 3000 ret = drm_ioctl(filp, cmd, arg); 3001 3002out: 3003 pm_runtime_put_autosuspend(dev->dev); 3004 return ret; 3005} 3006 3007static const struct dev_pm_ops amdgpu_pm_ops = { 3008 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 3009 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 3010 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 3011 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3012 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3013 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3014 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3015 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3016 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3017 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3018 .runtime_resume = amdgpu_pmops_runtime_resume, 3019 .runtime_idle = amdgpu_pmops_runtime_idle, 3020}; 3021 3022static int amdgpu_flush(struct file *f, fl_owner_t id) 3023{ 3024 struct drm_file *file_priv = f->private_data; 3025 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3026 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3027 3028 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3029 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3030 3031 return timeout >= 0 ? 0 : timeout; 3032} 3033 3034static const struct file_operations amdgpu_driver_kms_fops = { 3035 .owner = THIS_MODULE, 3036 .open = drm_open, 3037 .flush = amdgpu_flush, 3038 .release = amdgpu_drm_release, 3039 .unlocked_ioctl = amdgpu_drm_ioctl, 3040 .mmap = drm_gem_mmap, 3041 .poll = drm_poll, 3042 .read = drm_read, 3043#ifdef CONFIG_COMPAT 3044 .compat_ioctl = amdgpu_kms_compat_ioctl, 3045#endif 3046#ifdef CONFIG_PROC_FS 3047 .show_fdinfo = drm_show_fdinfo, 3048#endif 3049 .fop_flags = FOP_UNSIGNED_OFFSET, 3050}; 3051 3052int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3053{ 3054 struct drm_file *file; 3055 3056 if (!filp) 3057 return -EINVAL; 3058 3059 if (filp->f_op != &amdgpu_driver_kms_fops) 3060 return -EINVAL; 3061 3062 file = filp->private_data; 3063 *fpriv = file->driver_priv; 3064 return 0; 3065} 3066 3067const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3068 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3069 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3070 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3071 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3072 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3073 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3074 /* KMS */ 3075 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3076 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3077 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3078 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3079 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3080 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3081 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3082 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3083 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3084 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3085 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3086 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3087 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3088 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3089}; 3090 3091static const struct drm_driver amdgpu_kms_driver = { 3092 .driver_features = 3093 DRIVER_ATOMIC | 3094 DRIVER_GEM | 3095 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3096 DRIVER_SYNCOBJ_TIMELINE, 3097 .open = amdgpu_driver_open_kms, 3098 .postclose = amdgpu_driver_postclose_kms, 3099 .ioctls = amdgpu_ioctls_kms, 3100 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3101 .dumb_create = amdgpu_mode_dumb_create, 3102 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3103 DRM_FBDEV_TTM_DRIVER_OPS, 3104 .fops = &amdgpu_driver_kms_fops, 3105 .release = &amdgpu_driver_release_kms, 3106#ifdef CONFIG_PROC_FS 3107 .show_fdinfo = amdgpu_show_fdinfo, 3108#endif 3109 3110 .gem_prime_import = amdgpu_gem_prime_import, 3111 3112 .name = DRIVER_NAME, 3113 .desc = DRIVER_DESC, 3114 .major = KMS_DRIVER_MAJOR, 3115 .minor = KMS_DRIVER_MINOR, 3116 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3117}; 3118 3119const struct drm_driver amdgpu_partition_driver = { 3120 .driver_features = 3121 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3122 DRIVER_SYNCOBJ_TIMELINE, 3123 .open = amdgpu_driver_open_kms, 3124 .postclose = amdgpu_driver_postclose_kms, 3125 .ioctls = amdgpu_ioctls_kms, 3126 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3127 .dumb_create = amdgpu_mode_dumb_create, 3128 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3129 DRM_FBDEV_TTM_DRIVER_OPS, 3130 .fops = &amdgpu_driver_kms_fops, 3131 .release = &amdgpu_driver_release_kms, 3132 3133 .gem_prime_import = amdgpu_gem_prime_import, 3134 3135 .name = DRIVER_NAME, 3136 .desc = DRIVER_DESC, 3137 .major = KMS_DRIVER_MAJOR, 3138 .minor = KMS_DRIVER_MINOR, 3139 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3140}; 3141 3142static struct pci_error_handlers amdgpu_pci_err_handler = { 3143 .error_detected = amdgpu_pci_error_detected, 3144 .mmio_enabled = amdgpu_pci_mmio_enabled, 3145 .slot_reset = amdgpu_pci_slot_reset, 3146 .resume = amdgpu_pci_resume, 3147}; 3148 3149static const struct attribute_group *amdgpu_sysfs_groups[] = { 3150 &amdgpu_vram_mgr_attr_group, 3151 &amdgpu_gtt_mgr_attr_group, 3152 &amdgpu_flash_attr_group, 3153 NULL, 3154}; 3155 3156static struct pci_driver amdgpu_kms_pci_driver = { 3157 .name = DRIVER_NAME, 3158 .id_table = pciidlist, 3159 .probe = amdgpu_pci_probe, 3160 .remove = amdgpu_pci_remove, 3161 .shutdown = amdgpu_pci_shutdown, 3162 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3163 .err_handler = &amdgpu_pci_err_handler, 3164 .dev_groups = amdgpu_sysfs_groups, 3165}; 3166 3167static int __init amdgpu_init(void) 3168{ 3169 int r; 3170 3171 r = amdgpu_sync_init(); 3172 if (r) 3173 goto error_sync; 3174 3175 r = amdgpu_userq_fence_slab_init(); 3176 if (r) 3177 goto error_fence; 3178 3179 amdgpu_register_atpx_handler(); 3180 amdgpu_acpi_detect(); 3181 3182 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3183 amdgpu_amdkfd_init(); 3184 3185 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3186 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3187 pr_crit("Overdrive is enabled, please disable it before " 3188 "reporting any bugs unrelated to overdrive.\n"); 3189 } 3190 3191 /* let modprobe override vga console setting */ 3192 return pci_register_driver(&amdgpu_kms_pci_driver); 3193 3194error_fence: 3195 amdgpu_sync_fini(); 3196 3197error_sync: 3198 return r; 3199} 3200 3201static void __exit amdgpu_exit(void) 3202{ 3203 amdgpu_amdkfd_fini(); 3204 pci_unregister_driver(&amdgpu_kms_pci_driver); 3205 amdgpu_unregister_atpx_handler(); 3206 amdgpu_acpi_release(); 3207 amdgpu_sync_fini(); 3208 amdgpu_userq_fence_slab_fini(); 3209 mmu_notifier_synchronize(); 3210 amdgpu_xcp_drv_release(); 3211} 3212 3213module_init(amdgpu_init); 3214module_exit(amdgpu_exit); 3215 3216MODULE_AUTHOR(DRIVER_AUTHOR); 3217MODULE_DESCRIPTION(DRIVER_DESC); 3218MODULE_LICENSE("GPL and additional rights");
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