gpio-xgene-sb.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * AppliedMicro X-Gene SoC GPIO-Standby Driver
  4 *
  5 * Copyright (c) 2014, Applied Micro Circuits Corporation
  6 * Author:	Tin Huynh <tnhuynh@apm.com>.
  7 *		Y Vo <yvo@apm.com>.
  8 *		Quan Nguyen <qnguyen@apm.com>.
  9 */
 10
 11#include <linux/device.h>
 12#include <linux/err.h>
 13#include <linux/io.h>
 14#include <linux/irq.h>
 15#include <linux/irqdomain.h>
 16#include <linux/mod_devicetable.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/platform_device.h>
 20#include <linux/property.h>
 21#include <linux/types.h>
 22
 23#include <linux/gpio/driver.h>
 24#include <linux/gpio/generic.h>
 25
 26#include "gpiolib-acpi.h"
 27
 28#define XGENE_DFLT_MAX_NGPIO		22
 29#define XGENE_DFLT_MAX_NIRQ		6
 30#define XGENE_DFLT_IRQ_START_PIN	8
 31#define GPIO_MASK(x)			(1U << ((x) % 32))
 32
 33#define MPA_GPIO_INT_LVL		0x0290
 34#define MPA_GPIO_OE_ADDR		0x029c
 35#define MPA_GPIO_OUT_ADDR		0x02a0
 36#define MPA_GPIO_IN_ADDR 		0x02a4
 37#define MPA_GPIO_SEL_LO 		0x0294
 38
 39#define GPIO_INT_LEVEL_H	0x000001
 40#define GPIO_INT_LEVEL_L	0x000000
 41
 42/**
 43 * struct xgene_gpio_sb - GPIO-Standby private data structure.
 44 * @chip:			Generic GPIO chip data
 45 * @regs:			GPIO register base offset
 46 * @irq_domain:			GPIO interrupt domain
 47 * @irq_start:			GPIO pin that start support interrupt
 48 * @nirq:			Number of GPIO pins that supports interrupt
 49 * @parent_irq_base:		Start parent HWIRQ
 50 */
 51struct xgene_gpio_sb {
 52	struct gpio_generic_chip chip;
 53	void __iomem		*regs;
 54	struct irq_domain	*irq_domain;
 55	u16			irq_start;
 56	u16			nirq;
 57	u16			parent_irq_base;
 58};
 59
 60#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
 61#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
 62
 63static void xgene_gpio_set_bit(struct gpio_chip *gc,
 64				void __iomem *reg, u32 gpio, int val)
 65{
 66	struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
 67	u32 data;
 68
 69	data = gpio_generic_read_reg(chip, reg);
 70	if (val)
 71		data |= GPIO_MASK(gpio);
 72	else
 73		data &= ~GPIO_MASK(gpio);
 74	gpio_generic_write_reg(chip, reg, data);
 75}
 76
 77static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
 78{
 79	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
 80	int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
 81	int lvl_type = GPIO_INT_LEVEL_H;
 82
 83	switch (type & IRQ_TYPE_SENSE_MASK) {
 84	case IRQ_TYPE_EDGE_RISING:
 85	case IRQ_TYPE_LEVEL_HIGH:
 86		lvl_type = GPIO_INT_LEVEL_H;
 87		break;
 88	case IRQ_TYPE_EDGE_FALLING:
 89	case IRQ_TYPE_LEVEL_LOW:
 90		lvl_type = GPIO_INT_LEVEL_L;
 91		break;
 92	default:
 93		break;
 94	}
 95
 96	xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
 97			gpio * 2, 1);
 98	xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_INT_LVL,
 99			d->hwirq, lvl_type);
100
101	/* Propagate IRQ type setting to parent */
102	if (type & IRQ_TYPE_EDGE_BOTH)
103		return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
104	else
105		return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
106}
107
108static void xgene_gpio_sb_irq_mask(struct irq_data *d)
109{
110	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
111
112	irq_chip_mask_parent(d);
113
114	gpiochip_disable_irq(&priv->chip.gc, d->hwirq);
115}
116
117static void xgene_gpio_sb_irq_unmask(struct irq_data *d)
118{
119	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
120
121	gpiochip_enable_irq(&priv->chip.gc, d->hwirq);
122
123	irq_chip_unmask_parent(d);
124}
125
126static const struct irq_chip xgene_gpio_sb_irq_chip = {
127	.name           = "sbgpio",
128	.irq_eoi	= irq_chip_eoi_parent,
129	.irq_mask       = xgene_gpio_sb_irq_mask,
130	.irq_unmask     = xgene_gpio_sb_irq_unmask,
131	.irq_set_type   = xgene_gpio_sb_irq_set_type,
132	.flags = IRQCHIP_IMMUTABLE,
133	GPIOCHIP_IRQ_RESOURCE_HELPERS,
134};
135
136static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
137{
138	struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
139	struct irq_fwspec fwspec;
140
141	if ((gpio < priv->irq_start) ||
142			(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
143		return -ENXIO;
144
145	fwspec.fwnode = gc->parent->fwnode;
146	fwspec.param_count = 2;
147	fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
148	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
149	return irq_create_fwspec_mapping(&fwspec);
150}
151
152static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
153					 struct irq_data *irq_data,
154					 bool reserve)
155{
156	struct xgene_gpio_sb *priv = d->host_data;
157	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
158	int ret;
159
160	ret = gpiochip_lock_as_irq(&priv->chip.gc, gpio);
161	if (ret) {
162		dev_err(priv->chip.gc.parent,
163		"Unable to configure XGene GPIO standby pin %d as IRQ\n",
164				gpio);
165		return ret;
166	}
167
168	xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
169			gpio * 2, 1);
170	return 0;
171}
172
173static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
174		struct irq_data *irq_data)
175{
176	struct xgene_gpio_sb *priv = d->host_data;
177	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
178
179	gpiochip_unlock_as_irq(&priv->chip.gc, gpio);
180	xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
181			gpio * 2, 0);
182}
183
184static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
185		struct irq_fwspec *fwspec,
186		unsigned long *hwirq,
187		unsigned int *type)
188{
189	struct xgene_gpio_sb *priv = d->host_data;
190
191	if ((fwspec->param_count != 2) ||
192		(fwspec->param[0] >= priv->nirq))
193		return -EINVAL;
194	*hwirq = fwspec->param[0];
195	*type = fwspec->param[1];
196	return 0;
197}
198
199static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
200					unsigned int virq,
201					unsigned int nr_irqs, void *data)
202{
203	struct irq_fwspec *fwspec = data;
204	struct irq_fwspec parent_fwspec;
205	struct xgene_gpio_sb *priv = domain->host_data;
206	irq_hw_number_t hwirq;
207	unsigned int i;
208
209	hwirq = fwspec->param[0];
210	for (i = 0; i < nr_irqs; i++)
211		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
212				&xgene_gpio_sb_irq_chip, priv);
213
214	parent_fwspec.fwnode = domain->parent->fwnode;
215	if (is_of_node(parent_fwspec.fwnode)) {
216		parent_fwspec.param_count = 3;
217		parent_fwspec.param[0] = 0;/* SPI */
218		/* Skip SGIs and PPIs*/
219		parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
220		parent_fwspec.param[2] = fwspec->param[1];
221	} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
222		parent_fwspec.param_count = 2;
223		parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
224		parent_fwspec.param[1] = fwspec->param[1];
225	} else
226		return -EINVAL;
227
228	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
229			&parent_fwspec);
230}
231
232static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
233	.translate      = xgene_gpio_sb_domain_translate,
234	.alloc          = xgene_gpio_sb_domain_alloc,
235	.free           = irq_domain_free_irqs_common,
236	.activate	= xgene_gpio_sb_domain_activate,
237	.deactivate	= xgene_gpio_sb_domain_deactivate,
238};
239
240static int xgene_gpio_sb_probe(struct platform_device *pdev)
241{
242	struct gpio_generic_chip_config config;
243	struct xgene_gpio_sb *priv;
244	int ret;
245	void __iomem *regs;
246	struct irq_domain *parent_domain = NULL;
247	u32 val32;
248
249	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
250	if (!priv)
251		return -ENOMEM;
252
253	regs = devm_platform_ioremap_resource(pdev, 0);
254	if (IS_ERR(regs))
255		return PTR_ERR(regs);
256
257	priv->regs = regs;
258
259	ret = platform_get_irq(pdev, 0);
260	if (ret > 0) {
261		priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
262		parent_domain = irq_get_irq_data(ret)->domain;
263	}
264	if (!parent_domain) {
265		dev_err(&pdev->dev, "unable to obtain parent domain\n");
266		return -ENODEV;
267	}
268
269	config = (struct gpio_generic_chip_config) {
270		.dev = &pdev->dev,
271		.sz = 4,
272		.dat = regs + MPA_GPIO_IN_ADDR,
273		.set = regs + MPA_GPIO_OUT_ADDR,
274		.dirout = regs + MPA_GPIO_OE_ADDR,
275	};
276
277	ret = gpio_generic_chip_init(&priv->chip, &config);
278        if (ret)
279                return ret;
280
281	priv->chip.gc.to_irq = xgene_gpio_sb_to_irq;
282
283	/* Retrieve start irq pin, use default if property not found */
284	priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
285	if (!device_property_read_u32(&pdev->dev, "apm,irq-start", &val32))
286		priv->irq_start = val32;
287
288	/* Retrieve number irqs, use default if property not found */
289	priv->nirq = XGENE_DFLT_MAX_NIRQ;
290	if (!device_property_read_u32(&pdev->dev, "apm,nr-irqs", &val32))
291		priv->nirq = val32;
292
293	/* Retrieve number gpio, use default if property not found */
294	priv->chip.gc.ngpio = XGENE_DFLT_MAX_NGPIO;
295	if (!device_property_read_u32(&pdev->dev, "apm,nr-gpios", &val32))
296		priv->chip.gc.ngpio = val32;
297
298	dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
299			priv->chip.gc.ngpio, priv->nirq, priv->irq_start);
300
301	platform_set_drvdata(pdev, priv);
302
303	priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
304					0, priv->nirq, pdev->dev.fwnode,
305					&xgene_gpio_sb_domain_ops, priv);
306	if (!priv->irq_domain)
307		return -ENODEV;
308
309	priv->chip.gc.irq.domain = priv->irq_domain;
310
311	ret = devm_gpiochip_add_data(&pdev->dev, &priv->chip.gc, priv);
312	if (ret) {
313		dev_err(&pdev->dev,
314			"failed to register X-Gene GPIO Standby driver\n");
315		irq_domain_remove(priv->irq_domain);
316		return ret;
317	}
318
319	dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
320
321	/* Register interrupt handlers for GPIO signaled ACPI Events */
322	acpi_gpiochip_request_interrupts(&priv->chip.gc);
323
324	return ret;
325}
326
327static void xgene_gpio_sb_remove(struct platform_device *pdev)
328{
329	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
330
331	acpi_gpiochip_free_interrupts(&priv->chip.gc);
332
333	irq_domain_remove(priv->irq_domain);
334}
335
336static const struct of_device_id xgene_gpio_sb_of_match[] = {
337	{ .compatible = "apm,xgene-gpio-sb" },
338	{}
339};
340MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
341
342static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
343	{ "APMC0D15" },
344	{}
345};
346MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
347
348static struct platform_driver xgene_gpio_sb_driver = {
349	.driver = {
350		   .name = "xgene-gpio-sb",
351		   .of_match_table = xgene_gpio_sb_of_match,
352		   .acpi_match_table = xgene_gpio_sb_acpi_match,
353	},
354	.probe = xgene_gpio_sb_probe,
355	.remove = xgene_gpio_sb_remove,
356};
357module_platform_driver(xgene_gpio_sb_driver);
358
359MODULE_AUTHOR("AppliedMicro");
360MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
361MODULE_LICENSE("GPL");